]>
Commit | Line | Data |
---|---|---|
32a1795f JS |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ | |
4 | * Author: Jyri Sarha <jsarha@ti.com> | |
5 | */ | |
6 | ||
7 | #ifndef __TIDSS_DISPC_REGS_H | |
8 | #define __TIDSS_DISPC_REGS_H | |
9 | ||
10 | enum dispc_common_regs { | |
11 | NOT_APPLICABLE_OFF = 0, | |
12 | DSS_REVISION_OFF, | |
13 | DSS_SYSCONFIG_OFF, | |
14 | DSS_SYSSTATUS_OFF, | |
15 | DISPC_IRQ_EOI_OFF, | |
16 | DISPC_IRQSTATUS_RAW_OFF, | |
17 | DISPC_IRQSTATUS_OFF, | |
18 | DISPC_IRQENABLE_SET_OFF, | |
19 | DISPC_IRQENABLE_CLR_OFF, | |
20 | DISPC_VID_IRQENABLE_OFF, | |
21 | DISPC_VID_IRQSTATUS_OFF, | |
22 | DISPC_VP_IRQENABLE_OFF, | |
23 | DISPC_VP_IRQSTATUS_OFF, | |
24 | WB_IRQENABLE_OFF, | |
25 | WB_IRQSTATUS_OFF, | |
26 | DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF, | |
27 | DISPC_GLOBAL_OUTPUT_ENABLE_OFF, | |
28 | DISPC_GLOBAL_BUFFER_OFF, | |
29 | DSS_CBA_CFG_OFF, | |
30 | DISPC_DBG_CONTROL_OFF, | |
31 | DISPC_DBG_STATUS_OFF, | |
32 | DISPC_CLKGATING_DISABLE_OFF, | |
33 | DISPC_SECURE_DISABLE_OFF, | |
34 | FBDC_REVISION_1_OFF, | |
35 | FBDC_REVISION_2_OFF, | |
36 | FBDC_REVISION_3_OFF, | |
37 | FBDC_REVISION_4_OFF, | |
38 | FBDC_REVISION_5_OFF, | |
39 | FBDC_REVISION_6_OFF, | |
40 | FBDC_COMMON_CONTROL_OFF, | |
41 | FBDC_CONSTANT_COLOR_0_OFF, | |
42 | FBDC_CONSTANT_COLOR_1_OFF, | |
43 | DISPC_CONNECTIONS_OFF, | |
44 | DISPC_MSS_VP1_OFF, | |
45 | DISPC_MSS_VP3_OFF, | |
46 | DISPC_COMMON_REG_TABLE_LEN, | |
47 | }; | |
48 | ||
49 | /* | |
50 | * dispc_common_regmap should be defined as const u16 * and pointing | |
51 | * to a valid dss common register map for the platform, before the | |
52 | * macros bellow can be used. | |
53 | */ | |
54 | ||
55 | #define REG(r) (dispc_common_regmap[r ## _OFF]) | |
56 | ||
57 | #define DSS_REVISION REG(DSS_REVISION) | |
58 | #define DSS_SYSCONFIG REG(DSS_SYSCONFIG) | |
59 | #define DSS_SYSSTATUS REG(DSS_SYSSTATUS) | |
60 | #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) | |
61 | #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) | |
62 | #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) | |
63 | #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) | |
64 | #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) | |
65 | #define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4) | |
66 | #define DISPC_VID_IRQSTATUS(n) (REG(DISPC_VID_IRQSTATUS) + (n) * 4) | |
67 | #define DISPC_VP_IRQENABLE(n) (REG(DISPC_VP_IRQENABLE) + (n) * 4) | |
68 | #define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) | |
69 | #define WB_IRQENABLE REG(WB_IRQENABLE) | |
70 | #define WB_IRQSTATUS REG(WB_IRQSTATUS) | |
71 | ||
72 | #define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) | |
73 | #define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) | |
74 | #define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) | |
75 | #define DSS_CBA_CFG REG(DSS_CBA_CFG) | |
76 | #define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) | |
77 | #define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) | |
78 | #define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) | |
79 | #define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) | |
80 | ||
81 | #define FBDC_REVISION_1 REG(FBDC_REVISION_1) | |
82 | #define FBDC_REVISION_2 REG(FBDC_REVISION_2) | |
83 | #define FBDC_REVISION_3 REG(FBDC_REVISION_3) | |
84 | #define FBDC_REVISION_4 REG(FBDC_REVISION_4) | |
85 | #define FBDC_REVISION_5 REG(FBDC_REVISION_5) | |
86 | #define FBDC_REVISION_6 REG(FBDC_REVISION_6) | |
87 | #define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) | |
88 | #define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) | |
89 | #define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) | |
90 | #define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) | |
91 | #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) | |
92 | #define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) | |
93 | ||
94 | /* VID */ | |
95 | ||
96 | #define DISPC_VID_ACCUH_0 0x0 | |
97 | #define DISPC_VID_ACCUH_1 0x4 | |
98 | #define DISPC_VID_ACCUH2_0 0x8 | |
99 | #define DISPC_VID_ACCUH2_1 0xc | |
100 | #define DISPC_VID_ACCUV_0 0x10 | |
101 | #define DISPC_VID_ACCUV_1 0x14 | |
102 | #define DISPC_VID_ACCUV2_0 0x18 | |
103 | #define DISPC_VID_ACCUV2_1 0x1c | |
104 | #define DISPC_VID_ATTRIBUTES 0x20 | |
105 | #define DISPC_VID_ATTRIBUTES2 0x24 | |
106 | #define DISPC_VID_BA_0 0x28 | |
107 | #define DISPC_VID_BA_1 0x2c | |
108 | #define DISPC_VID_BA_UV_0 0x30 | |
109 | #define DISPC_VID_BA_UV_1 0x34 | |
110 | #define DISPC_VID_BUF_SIZE_STATUS 0x38 | |
111 | #define DISPC_VID_BUF_THRESHOLD 0x3c | |
112 | #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) | |
113 | ||
114 | #define DISPC_VID_FIRH 0x5c | |
115 | #define DISPC_VID_FIRH2 0x60 | |
116 | #define DISPC_VID_FIRV 0x64 | |
117 | #define DISPC_VID_FIRV2 0x68 | |
118 | ||
119 | #define DISPC_VID_FIR_COEFS_H0 0x6c | |
120 | #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) | |
121 | #define DISPC_VID_FIR_COEFS_H0_C 0x90 | |
122 | #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) | |
123 | ||
124 | #define DISPC_VID_FIR_COEFS_H12 0xb4 | |
125 | #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) | |
126 | #define DISPC_VID_FIR_COEFS_H12_C 0xf4 | |
127 | #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) | |
128 | ||
129 | #define DISPC_VID_FIR_COEFS_V0 0x134 | |
130 | #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) | |
131 | #define DISPC_VID_FIR_COEFS_V0_C 0x158 | |
132 | #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) | |
133 | ||
134 | #define DISPC_VID_FIR_COEFS_V12 0x17c | |
135 | #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) | |
136 | #define DISPC_VID_FIR_COEFS_V12_C 0x1bc | |
137 | #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) | |
138 | ||
139 | #define DISPC_VID_GLOBAL_ALPHA 0x1fc | |
140 | #define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ | |
141 | #define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ | |
142 | #define DISPC_VID_MFLAG_THRESHOLD 0x208 | |
143 | #define DISPC_VID_PICTURE_SIZE 0x20c | |
144 | #define DISPC_VID_PIXEL_INC 0x210 | |
145 | #define DISPC_VID_K2G_POSITION 0x214 /* K2G */ | |
146 | #define DISPC_VID_PRELOAD 0x218 | |
147 | #define DISPC_VID_ROW_INC 0x21c | |
148 | #define DISPC_VID_SIZE 0x220 | |
149 | #define DISPC_VID_BA_EXT_0 0x22c | |
150 | #define DISPC_VID_BA_EXT_1 0x230 | |
151 | #define DISPC_VID_BA_UV_EXT_0 0x234 | |
152 | #define DISPC_VID_BA_UV_EXT_1 0x238 | |
153 | #define DISPC_VID_CSC_COEF7 0x23c | |
154 | #define DISPC_VID_ROW_INC_UV 0x248 | |
155 | #define DISPC_VID_CLUT 0x260 | |
156 | #define DISPC_VID_SAFETY_ATTRIBUTES 0x2a0 | |
157 | #define DISPC_VID_SAFETY_CAPT_SIGNATURE 0x2a4 | |
158 | #define DISPC_VID_SAFETY_POSITION 0x2a8 | |
159 | #define DISPC_VID_SAFETY_REF_SIGNATURE 0x2ac | |
160 | #define DISPC_VID_SAFETY_SIZE 0x2b0 | |
161 | #define DISPC_VID_SAFETY_LFSR_SEED 0x2b4 | |
162 | #define DISPC_VID_LUMAKEY 0x2b8 | |
163 | #define DISPC_VID_DMA_BUFSIZE 0x2bc /* J721E */ | |
164 | ||
165 | /* OVR */ | |
166 | ||
167 | #define DISPC_OVR_CONFIG 0x0 | |
168 | #define DISPC_OVR_VIRTVP 0x4 /* J721E */ | |
169 | #define DISPC_OVR_DEFAULT_COLOR 0x8 | |
170 | #define DISPC_OVR_DEFAULT_COLOR2 0xc | |
171 | #define DISPC_OVR_TRANS_COLOR_MAX 0x10 | |
172 | #define DISPC_OVR_TRANS_COLOR_MAX2 0x14 | |
173 | #define DISPC_OVR_TRANS_COLOR_MIN 0x18 | |
174 | #define DISPC_OVR_TRANS_COLOR_MIN2 0x1c | |
175 | #define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) | |
176 | #define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ | |
177 | /* VP */ | |
178 | ||
179 | #define DISPC_VP_CONFIG 0x0 | |
180 | #define DISPC_VP_CONTROL 0x4 | |
181 | #define DISPC_VP_CSC_COEF0 0x8 | |
182 | #define DISPC_VP_CSC_COEF1 0xc | |
183 | #define DISPC_VP_CSC_COEF2 0x10 | |
184 | #define DISPC_VP_DATA_CYCLE_0 0x14 | |
185 | #define DISPC_VP_DATA_CYCLE_1 0x18 | |
186 | #define DISPC_VP_K2G_GAMMA_TABLE 0x20 /* K2G */ | |
187 | #define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ | |
188 | #define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ | |
189 | #define DISPC_VP_DATA_CYCLE_2 0x1c | |
190 | #define DISPC_VP_LINE_NUMBER 0x44 | |
191 | #define DISPC_VP_POL_FREQ 0x4c | |
192 | #define DISPC_VP_SIZE_SCREEN 0x50 | |
193 | #define DISPC_VP_TIMING_H 0x54 | |
194 | #define DISPC_VP_TIMING_V 0x58 | |
195 | #define DISPC_VP_CSC_COEF3 0x5c | |
196 | #define DISPC_VP_CSC_COEF4 0x60 | |
197 | #define DISPC_VP_CSC_COEF5 0x64 | |
198 | #define DISPC_VP_CSC_COEF6 0x68 | |
199 | #define DISPC_VP_CSC_COEF7 0x6c | |
200 | #define DISPC_VP_SAFETY_ATTRIBUTES_0 0x70 | |
201 | #define DISPC_VP_SAFETY_ATTRIBUTES_1 0x74 | |
202 | #define DISPC_VP_SAFETY_ATTRIBUTES_2 0x78 | |
203 | #define DISPC_VP_SAFETY_ATTRIBUTES_3 0x7c | |
204 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 0x90 | |
205 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 0x94 | |
206 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 0x98 | |
207 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 0x9c | |
208 | #define DISPC_VP_SAFETY_POSITION_0 0xb0 | |
209 | #define DISPC_VP_SAFETY_POSITION_1 0xb4 | |
210 | #define DISPC_VP_SAFETY_POSITION_2 0xb8 | |
211 | #define DISPC_VP_SAFETY_POSITION_3 0xbc | |
212 | #define DISPC_VP_SAFETY_REF_SIGNATURE_0 0xd0 | |
213 | #define DISPC_VP_SAFETY_REF_SIGNATURE_1 0xd4 | |
214 | #define DISPC_VP_SAFETY_REF_SIGNATURE_2 0xd8 | |
215 | #define DISPC_VP_SAFETY_REF_SIGNATURE_3 0xdc | |
216 | #define DISPC_VP_SAFETY_SIZE_0 0xf0 | |
217 | #define DISPC_VP_SAFETY_SIZE_1 0xf4 | |
218 | #define DISPC_VP_SAFETY_SIZE_2 0xf8 | |
219 | #define DISPC_VP_SAFETY_SIZE_3 0xfc | |
220 | #define DISPC_VP_SAFETY_LFSR_SEED 0x110 | |
221 | #define DISPC_VP_GAMMA_TABLE 0x120 | |
222 | #define DISPC_VP_DSS_OLDI_CFG 0x160 | |
223 | #define DISPC_VP_DSS_OLDI_STATUS 0x164 | |
224 | #define DISPC_VP_DSS_OLDI_LB 0x168 | |
225 | #define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ | |
226 | #define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ | |
227 | #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ | |
228 | ||
229 | /* | |
230 | * OLDI IO_CTRL register offsets. On AM654 the registers are found | |
231 | * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from | |
232 | * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL | |
233 | * register range. | |
234 | */ | |
235 | #define OLDI_DAT0_IO_CTRL 0x00 | |
236 | #define OLDI_DAT1_IO_CTRL 0x04 | |
237 | #define OLDI_DAT2_IO_CTRL 0x08 | |
238 | #define OLDI_DAT3_IO_CTRL 0x0C | |
239 | #define OLDI_CLK_IO_CTRL 0x10 | |
240 | ||
241 | #define OLDI_PWRDN_TX BIT(8) | |
242 | ||
243 | #endif /* __TIDSS_DISPC_REGS_H */ |