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Commit | Line | Data |
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16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
ce2f2c3f | 18 | #include <drm/drm_atomic.h> |
305198de | 19 | #include <drm/drm_atomic_helper.h> |
ce2f2c3f SP |
20 | #include <drm/drm_crtc.h> |
21 | #include <drm/drm_flip_work.h> | |
22 | #include <drm/drm_plane_helper.h> | |
4e910c7a | 23 | #include <linux/workqueue.h> |
16ea975e RC |
24 | |
25 | #include "tilcdc_drv.h" | |
26 | #include "tilcdc_regs.h" | |
27 | ||
2b3a8cd7 TV |
28 | #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 |
29 | ||
16ea975e RC |
30 | struct tilcdc_crtc { |
31 | struct drm_crtc base; | |
32 | ||
47f571c6 | 33 | struct drm_plane primary; |
16ea975e | 34 | const struct tilcdc_panel_info *info; |
16ea975e | 35 | struct drm_pending_vblank_event *event; |
2d53a180 | 36 | struct mutex enable_lock; |
47bfd6c0 | 37 | bool enabled; |
2d53a180 | 38 | bool shutdown; |
16ea975e RC |
39 | wait_queue_head_t frame_done_wq; |
40 | bool frame_done; | |
2b3a8cd7 TV |
41 | spinlock_t irq_lock; |
42 | ||
642e5167 JS |
43 | unsigned int lcd_fck_rate; |
44 | ||
2b3a8cd7 | 45 | ktime_t last_vblank; |
16ea975e | 46 | |
2b2080d7 | 47 | struct drm_framebuffer *curr_fb; |
2b3a8cd7 | 48 | struct drm_framebuffer *next_fb; |
16ea975e RC |
49 | |
50 | /* for deferred fb unref's: */ | |
a464d618 | 51 | struct drm_flip_work unref_work; |
103cd8bc JS |
52 | |
53 | /* Only set if an external encoder is connected */ | |
54 | bool simulate_vesa_sync; | |
5895d08f JS |
55 | |
56 | int sync_lost_count; | |
57 | bool frame_intact; | |
13b3d727 | 58 | struct work_struct recover_work; |
16ea975e RC |
59 | }; |
60 | #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) | |
61 | ||
a464d618 | 62 | static void unref_worker(struct drm_flip_work *work, void *val) |
16ea975e | 63 | { |
f7b45756 | 64 | struct tilcdc_crtc *tilcdc_crtc = |
a464d618 | 65 | container_of(work, struct tilcdc_crtc, unref_work); |
16ea975e | 66 | struct drm_device *dev = tilcdc_crtc->base.dev; |
16ea975e RC |
67 | |
68 | mutex_lock(&dev->mode_config.mutex); | |
a464d618 | 69 | drm_framebuffer_unreference(val); |
16ea975e RC |
70 | mutex_unlock(&dev->mode_config.mutex); |
71 | } | |
72 | ||
2b2080d7 | 73 | static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) |
16ea975e RC |
74 | { |
75 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
76 | struct drm_device *dev = crtc->dev; | |
4c268d63 | 77 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e | 78 | struct drm_gem_cma_object *gem; |
2b2080d7 | 79 | dma_addr_t start, end; |
7eb9f069 | 80 | u64 dma_base_and_ceiling; |
16ea975e | 81 | |
16ea975e RC |
82 | gem = drm_fb_cma_get_gem_obj(fb, 0); |
83 | ||
2b2080d7 TV |
84 | start = gem->paddr + fb->offsets[0] + |
85 | crtc->y * fb->pitches[0] + | |
59f11a43 | 86 | crtc->x * drm_format_plane_cpp(fb->pixel_format, 0); |
16ea975e | 87 | |
2b2080d7 | 88 | end = start + (crtc->mode.vdisplay * fb->pitches[0]); |
16ea975e | 89 | |
7eb9f069 JS |
90 | /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG |
91 | * with a single insruction, if available. This should make it more | |
92 | * unlikely that LCDC would fetch the DMA addresses in the middle of | |
93 | * an update. | |
94 | */ | |
4c268d63 DS |
95 | if (priv->rev == 1) |
96 | end -= 1; | |
97 | ||
98 | dma_base_and_ceiling = (u64)end << 32 | start; | |
7eb9f069 | 99 | tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); |
2b2080d7 TV |
100 | |
101 | if (tilcdc_crtc->curr_fb) | |
102 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
103 | tilcdc_crtc->curr_fb); | |
104 | ||
105 | tilcdc_crtc->curr_fb = fb; | |
16ea975e RC |
106 | } |
107 | ||
afaf833d JS |
108 | static void tilcdc_crtc_enable_irqs(struct drm_device *dev) |
109 | { | |
110 | struct tilcdc_drm_private *priv = dev->dev_private; | |
111 | ||
112 | tilcdc_clear_irqstatus(dev, 0xffffffff); | |
113 | ||
114 | if (priv->rev == 1) { | |
115 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, | |
116 | LCDC_V1_UNDERFLOW_INT_ENA); | |
8d6c3f7d KB |
117 | tilcdc_set(dev, LCDC_DMA_CTRL_REG, |
118 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
afaf833d JS |
119 | } else { |
120 | tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, | |
121 | LCDC_V2_UNDERFLOW_INT_ENA | | |
122 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
123 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
124 | } | |
125 | } | |
126 | ||
127 | static void tilcdc_crtc_disable_irqs(struct drm_device *dev) | |
128 | { | |
129 | struct tilcdc_drm_private *priv = dev->dev_private; | |
130 | ||
131 | /* disable irqs that we might have enabled: */ | |
132 | if (priv->rev == 1) { | |
133 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, | |
134 | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); | |
135 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, | |
136 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
137 | } else { | |
138 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
139 | LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | | |
140 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
141 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
142 | } | |
143 | } | |
144 | ||
2efec4f3 | 145 | static void reset(struct drm_crtc *crtc) |
16ea975e RC |
146 | { |
147 | struct drm_device *dev = crtc->dev; | |
148 | struct tilcdc_drm_private *priv = dev->dev_private; | |
149 | ||
2efec4f3 TV |
150 | if (priv->rev != 2) |
151 | return; | |
152 | ||
153 | tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
154 | usleep_range(250, 1000); | |
155 | tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
156 | } | |
157 | ||
47bfd6c0 | 158 | static void tilcdc_crtc_enable(struct drm_crtc *crtc) |
2efec4f3 TV |
159 | { |
160 | struct drm_device *dev = crtc->dev; | |
47bfd6c0 JS |
161 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
162 | ||
2e0965b0 | 163 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
2d53a180 JS |
164 | mutex_lock(&tilcdc_crtc->enable_lock); |
165 | if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) { | |
166 | mutex_unlock(&tilcdc_crtc->enable_lock); | |
47bfd6c0 | 167 | return; |
2d53a180 | 168 | } |
47bfd6c0 JS |
169 | |
170 | pm_runtime_get_sync(dev->dev); | |
2efec4f3 TV |
171 | |
172 | reset(crtc); | |
16ea975e | 173 | |
afaf833d JS |
174 | tilcdc_crtc_enable_irqs(dev); |
175 | ||
2b2080d7 | 176 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); |
16ea975e RC |
177 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); |
178 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); | |
d85f850e JS |
179 | |
180 | drm_crtc_vblank_on(crtc); | |
47bfd6c0 JS |
181 | |
182 | tilcdc_crtc->enabled = true; | |
2d53a180 | 183 | mutex_unlock(&tilcdc_crtc->enable_lock); |
16ea975e RC |
184 | } |
185 | ||
2d53a180 | 186 | static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) |
16ea975e | 187 | { |
2d5be882 | 188 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 189 | struct drm_device *dev = crtc->dev; |
2d5be882 | 190 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e | 191 | |
2d53a180 JS |
192 | mutex_lock(&tilcdc_crtc->enable_lock); |
193 | if (shutdown) | |
194 | tilcdc_crtc->shutdown = true; | |
195 | if (!tilcdc_crtc->enabled) { | |
196 | mutex_unlock(&tilcdc_crtc->enable_lock); | |
47bfd6c0 | 197 | return; |
2d53a180 | 198 | } |
2d5be882 | 199 | tilcdc_crtc->frame_done = false; |
16ea975e | 200 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); |
2d5be882 JS |
201 | |
202 | /* | |
203 | * if necessary wait for framedone irq which will still come | |
204 | * before putting things to sleep.. | |
205 | */ | |
206 | if (priv->rev == 2) { | |
207 | int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, | |
208 | tilcdc_crtc->frame_done, | |
437c7d94 | 209 | msecs_to_jiffies(500)); |
2d5be882 JS |
210 | if (ret == 0) |
211 | dev_err(dev->dev, "%s: timeout waiting for framedone\n", | |
212 | __func__); | |
213 | } | |
d85f850e JS |
214 | |
215 | drm_crtc_vblank_off(crtc); | |
afaf833d JS |
216 | |
217 | tilcdc_crtc_disable_irqs(dev); | |
47bfd6c0 JS |
218 | |
219 | pm_runtime_put_sync(dev->dev); | |
220 | ||
221 | if (tilcdc_crtc->next_fb) { | |
222 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
223 | tilcdc_crtc->next_fb); | |
224 | tilcdc_crtc->next_fb = NULL; | |
225 | } | |
226 | ||
227 | if (tilcdc_crtc->curr_fb) { | |
228 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
229 | tilcdc_crtc->curr_fb); | |
230 | tilcdc_crtc->curr_fb = NULL; | |
231 | } | |
232 | ||
233 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); | |
234 | tilcdc_crtc->last_vblank = ktime_set(0, 0); | |
235 | ||
236 | tilcdc_crtc->enabled = false; | |
2d53a180 | 237 | mutex_unlock(&tilcdc_crtc->enable_lock); |
47bfd6c0 JS |
238 | } |
239 | ||
9e79e062 JS |
240 | static void tilcdc_crtc_disable(struct drm_crtc *crtc) |
241 | { | |
242 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
2d53a180 JS |
243 | tilcdc_crtc_off(crtc, false); |
244 | } | |
245 | ||
246 | void tilcdc_crtc_shutdown(struct drm_crtc *crtc) | |
247 | { | |
248 | tilcdc_crtc_off(crtc, true); | |
9e79e062 JS |
249 | } |
250 | ||
47bfd6c0 JS |
251 | static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) |
252 | { | |
253 | return crtc->state && crtc->state->enable && crtc->state->active; | |
16ea975e RC |
254 | } |
255 | ||
13b3d727 JS |
256 | static void tilcdc_crtc_recover_work(struct work_struct *work) |
257 | { | |
258 | struct tilcdc_crtc *tilcdc_crtc = | |
259 | container_of(work, struct tilcdc_crtc, recover_work); | |
260 | struct drm_crtc *crtc = &tilcdc_crtc->base; | |
261 | ||
262 | dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__); | |
263 | ||
264 | drm_modeset_lock_crtc(crtc, NULL); | |
265 | ||
266 | if (!tilcdc_crtc_is_on(crtc)) | |
267 | goto out; | |
268 | ||
269 | tilcdc_crtc_disable(crtc); | |
270 | tilcdc_crtc_enable(crtc); | |
271 | out: | |
272 | drm_modeset_unlock_crtc(crtc); | |
273 | } | |
274 | ||
16ea975e RC |
275 | static void tilcdc_crtc_destroy(struct drm_crtc *crtc) |
276 | { | |
277 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
4e910c7a | 278 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; |
16ea975e | 279 | |
6c94c714 | 280 | drm_modeset_lock_crtc(crtc, NULL); |
47bfd6c0 | 281 | tilcdc_crtc_disable(crtc); |
6c94c714 | 282 | drm_modeset_unlock_crtc(crtc); |
16ea975e | 283 | |
4e910c7a | 284 | flush_workqueue(priv->wq); |
16ea975e | 285 | |
d66284fb | 286 | of_node_put(crtc->port); |
16ea975e | 287 | drm_crtc_cleanup(crtc); |
a464d618 | 288 | drm_flip_work_cleanup(&tilcdc_crtc->unref_work); |
16ea975e RC |
289 | } |
290 | ||
e0e344e6 | 291 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
16ea975e | 292 | struct drm_framebuffer *fb, |
e0e344e6 | 293 | struct drm_pending_vblank_event *event) |
16ea975e RC |
294 | { |
295 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
296 | struct drm_device *dev = crtc->dev; | |
2b2080d7 | 297 | unsigned long flags; |
6f206e9d | 298 | |
2e0965b0 JS |
299 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
300 | ||
16ea975e RC |
301 | if (tilcdc_crtc->event) { |
302 | dev_err(dev->dev, "already pending page flip!\n"); | |
303 | return -EBUSY; | |
304 | } | |
305 | ||
2b2080d7 TV |
306 | drm_framebuffer_reference(fb); |
307 | ||
f4510a27 | 308 | crtc->primary->fb = fb; |
65734a26 | 309 | |
2b3a8cd7 TV |
310 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
311 | ||
0a1fe1b7 JS |
312 | if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { |
313 | ktime_t next_vblank; | |
314 | s64 tdiff; | |
2b2080d7 | 315 | |
0a1fe1b7 JS |
316 | next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, |
317 | 1000000 / crtc->hwmode.vrefresh); | |
2b3a8cd7 | 318 | |
0a1fe1b7 JS |
319 | tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); |
320 | ||
321 | if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) | |
322 | tilcdc_crtc->next_fb = fb; | |
323 | } | |
324 | ||
325 | if (tilcdc_crtc->next_fb != fb) | |
2b3a8cd7 | 326 | set_scanout(crtc, fb); |
2b2080d7 | 327 | |
2b2080d7 | 328 | tilcdc_crtc->event = event; |
2b3a8cd7 TV |
329 | |
330 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
16ea975e RC |
331 | |
332 | return 0; | |
333 | } | |
334 | ||
16ea975e RC |
335 | static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, |
336 | const struct drm_display_mode *mode, | |
337 | struct drm_display_mode *adjusted_mode) | |
338 | { | |
103cd8bc JS |
339 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
340 | ||
341 | if (!tilcdc_crtc->simulate_vesa_sync) | |
342 | return true; | |
343 | ||
344 | /* | |
345 | * tilcdc does not generate VESA-compliant sync but aligns | |
346 | * VS on the second edge of HS instead of first edge. | |
347 | * We use adjusted_mode, to fixup sync by aligning both rising | |
348 | * edges and add HSKEW offset to fix the sync. | |
349 | */ | |
350 | adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; | |
351 | adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; | |
352 | ||
353 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) { | |
354 | adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
355 | adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; | |
356 | } else { | |
357 | adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
358 | adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; | |
359 | } | |
360 | ||
16ea975e RC |
361 | return true; |
362 | } | |
363 | ||
cb42e20e BG |
364 | /* |
365 | * Calculate the percentage difference between the requested pixel clock rate | |
366 | * and the effective rate resulting from calculating the clock divider value. | |
367 | */ | |
368 | static unsigned int tilcdc_pclk_diff(unsigned long rate, | |
369 | unsigned long real_rate) | |
370 | { | |
371 | int r = rate / 100, rr = real_rate / 100; | |
372 | ||
373 | return (unsigned int)(abs(((rr - r) * 100) / r)); | |
374 | } | |
375 | ||
642e5167 JS |
376 | static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) |
377 | { | |
378 | struct drm_device *dev = crtc->dev; | |
379 | struct tilcdc_drm_private *priv = dev->dev_private; | |
380 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
cb42e20e BG |
381 | unsigned long clk_rate, real_rate, req_rate; |
382 | unsigned int clkdiv; | |
642e5167 JS |
383 | int ret; |
384 | ||
cb42e20e BG |
385 | clkdiv = 2; /* first try using a standard divider of 2 */ |
386 | ||
642e5167 | 387 | /* mode.clock is in KHz, set_rate wants parameter in Hz */ |
cb42e20e BG |
388 | req_rate = crtc->mode.clock * 1000; |
389 | ||
390 | ret = clk_set_rate(priv->clk, req_rate * clkdiv); | |
391 | clk_rate = clk_get_rate(priv->clk); | |
642e5167 | 392 | if (ret < 0) { |
cb42e20e BG |
393 | /* |
394 | * If we fail to set the clock rate (some architectures don't | |
395 | * use the common clock framework yet and may not implement | |
396 | * all the clk API calls for every clock), try the next best | |
397 | * thing: adjusting the clock divider, unless clk_get_rate() | |
398 | * failed as well. | |
399 | */ | |
400 | if (!clk_rate) { | |
401 | /* Nothing more we can do. Just bail out. */ | |
402 | dev_err(dev->dev, | |
403 | "failed to set the pixel clock - unable to read current lcdc clock rate\n"); | |
404 | return; | |
405 | } | |
406 | ||
407 | clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); | |
408 | ||
409 | /* | |
410 | * Emit a warning if the real clock rate resulting from the | |
411 | * calculated divider differs much from the requested rate. | |
412 | * | |
413 | * 5% is an arbitrary value - LCDs are usually quite tolerant | |
414 | * about pixel clock rates. | |
415 | */ | |
416 | real_rate = clkdiv * req_rate; | |
417 | ||
418 | if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { | |
419 | dev_warn(dev->dev, | |
420 | "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n", | |
421 | clk_rate, real_rate); | |
422 | } | |
642e5167 JS |
423 | } |
424 | ||
cb42e20e | 425 | tilcdc_crtc->lcd_fck_rate = clk_rate; |
642e5167 JS |
426 | |
427 | DBG("lcd_clk=%u, mode clock=%d, div=%u", | |
428 | tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); | |
429 | ||
430 | /* Configure the LCD clock divisor. */ | |
431 | tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | | |
432 | LCDC_RASTER_MODE); | |
433 | ||
434 | if (priv->rev == 2) | |
435 | tilcdc_set(dev, LCDC_CLK_ENABLE_REG, | |
436 | LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | | |
437 | LCDC_V2_CORE_CLK_EN); | |
438 | } | |
439 | ||
f6382f18 JS |
440 | static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) |
441 | { | |
442 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
443 | struct drm_device *dev = crtc->dev; | |
444 | struct tilcdc_drm_private *priv = dev->dev_private; | |
445 | const struct tilcdc_panel_info *info = tilcdc_crtc->info; | |
446 | uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; | |
447 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; | |
448 | struct drm_framebuffer *fb = crtc->primary->state->fb; | |
449 | ||
2e0965b0 JS |
450 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
451 | ||
f6382f18 JS |
452 | if (WARN_ON(!info)) |
453 | return; | |
454 | ||
455 | if (WARN_ON(!fb)) | |
456 | return; | |
457 | ||
f6382f18 JS |
458 | /* Configure the Burst Size and fifo threshold of DMA: */ |
459 | reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; | |
460 | switch (info->dma_burst_sz) { | |
461 | case 1: | |
462 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); | |
463 | break; | |
464 | case 2: | |
465 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); | |
466 | break; | |
467 | case 4: | |
468 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); | |
469 | break; | |
470 | case 8: | |
471 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); | |
472 | break; | |
473 | case 16: | |
474 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); | |
475 | break; | |
476 | default: | |
477 | dev_err(dev->dev, "invalid burst size\n"); | |
478 | return; | |
479 | } | |
480 | reg |= (info->fifo_th << 8); | |
481 | tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); | |
482 | ||
483 | /* Configure timings: */ | |
484 | hbp = mode->htotal - mode->hsync_end; | |
485 | hfp = mode->hsync_start - mode->hdisplay; | |
486 | hsw = mode->hsync_end - mode->hsync_start; | |
487 | vbp = mode->vtotal - mode->vsync_end; | |
488 | vfp = mode->vsync_start - mode->vdisplay; | |
489 | vsw = mode->vsync_end - mode->vsync_start; | |
490 | ||
491 | DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", | |
492 | mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); | |
493 | ||
494 | /* Set AC Bias Period and Number of Transitions per Interrupt: */ | |
495 | reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; | |
496 | reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | | |
497 | LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); | |
498 | ||
499 | /* | |
500 | * subtract one from hfp, hbp, hsw because the hardware uses | |
501 | * a value of 0 as 1 | |
502 | */ | |
503 | if (priv->rev == 2) { | |
504 | /* clear bits we're going to set */ | |
505 | reg &= ~0x78000033; | |
506 | reg |= ((hfp-1) & 0x300) >> 8; | |
507 | reg |= ((hbp-1) & 0x300) >> 4; | |
508 | reg |= ((hsw-1) & 0x3c0) << 21; | |
509 | } | |
510 | tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); | |
511 | ||
512 | reg = (((mode->hdisplay >> 4) - 1) << 4) | | |
513 | (((hbp-1) & 0xff) << 24) | | |
514 | (((hfp-1) & 0xff) << 16) | | |
515 | (((hsw-1) & 0x3f) << 10); | |
516 | if (priv->rev == 2) | |
517 | reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; | |
518 | tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); | |
519 | ||
520 | reg = ((mode->vdisplay - 1) & 0x3ff) | | |
521 | ((vbp & 0xff) << 24) | | |
522 | ((vfp & 0xff) << 16) | | |
523 | (((vsw-1) & 0x3f) << 10); | |
524 | tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); | |
525 | ||
526 | /* | |
527 | * be sure to set Bit 10 for the V2 LCDC controller, | |
528 | * otherwise limited to 1024 pixels width, stopping | |
529 | * 1920x1080 being supported. | |
530 | */ | |
531 | if (priv->rev == 2) { | |
532 | if ((mode->vdisplay - 1) & 0x400) { | |
533 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, | |
534 | LCDC_LPP_B10); | |
535 | } else { | |
536 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, | |
537 | LCDC_LPP_B10); | |
538 | } | |
539 | } | |
540 | ||
541 | /* Configure display type: */ | |
542 | reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & | |
543 | ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | | |
544 | LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | | |
545 | 0x000ff000 /* Palette Loading Delay bits */); | |
546 | reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ | |
547 | if (info->tft_alt_mode) | |
548 | reg |= LCDC_TFT_ALT_ENABLE; | |
549 | if (priv->rev == 2) { | |
59f11a43 LP |
550 | switch (fb->pixel_format) { |
551 | case DRM_FORMAT_BGR565: | |
552 | case DRM_FORMAT_RGB565: | |
f6382f18 | 553 | break; |
59f11a43 LP |
554 | case DRM_FORMAT_XBGR8888: |
555 | case DRM_FORMAT_XRGB8888: | |
f6382f18 JS |
556 | reg |= LCDC_V2_TFT_24BPP_UNPACK; |
557 | /* fallthrough */ | |
59f11a43 LP |
558 | case DRM_FORMAT_BGR888: |
559 | case DRM_FORMAT_RGB888: | |
f6382f18 JS |
560 | reg |= LCDC_V2_TFT_24BPP_MODE; |
561 | break; | |
562 | default: | |
563 | dev_err(dev->dev, "invalid pixel format\n"); | |
564 | return; | |
565 | } | |
566 | } | |
567 | reg |= info->fdd < 12; | |
568 | tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); | |
569 | ||
570 | if (info->invert_pxl_clk) | |
571 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
572 | else | |
573 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
574 | ||
575 | if (info->sync_ctrl) | |
576 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
577 | else | |
578 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
579 | ||
580 | if (info->sync_edge) | |
581 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
582 | else | |
583 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
584 | ||
585 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
586 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
587 | else | |
588 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
589 | ||
590 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
591 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
592 | else | |
593 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
594 | ||
595 | if (info->raster_order) | |
596 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
597 | else | |
598 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
599 | ||
600 | drm_framebuffer_reference(fb); | |
601 | ||
602 | set_scanout(crtc, fb); | |
603 | ||
642e5167 | 604 | tilcdc_crtc_set_clk(crtc); |
f6382f18 | 605 | |
f6382f18 JS |
606 | crtc->hwmode = crtc->state->adjusted_mode; |
607 | } | |
608 | ||
db380c58 JS |
609 | static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, |
610 | struct drm_crtc_state *state) | |
611 | { | |
612 | struct drm_display_mode *mode = &state->mode; | |
613 | int ret; | |
614 | ||
615 | /* If we are not active we don't care */ | |
616 | if (!state->active) | |
617 | return 0; | |
618 | ||
619 | if (state->state->planes[0].ptr != crtc->primary || | |
620 | state->state->planes[0].state == NULL || | |
621 | state->state->planes[0].state->crtc != crtc) { | |
622 | dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | ret = tilcdc_crtc_mode_valid(crtc, mode); | |
627 | if (ret) { | |
628 | dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name); | |
629 | return -EINVAL; | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
16ea975e | 635 | static const struct drm_crtc_funcs tilcdc_crtc_funcs = { |
305198de JS |
636 | .destroy = tilcdc_crtc_destroy, |
637 | .set_config = drm_atomic_helper_set_config, | |
638 | .page_flip = drm_atomic_helper_page_flip, | |
639 | .reset = drm_atomic_helper_crtc_reset, | |
640 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
641 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
16ea975e RC |
642 | }; |
643 | ||
644 | static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { | |
16ea975e | 645 | .mode_fixup = tilcdc_crtc_mode_fixup, |
305198de JS |
646 | .enable = tilcdc_crtc_enable, |
647 | .disable = tilcdc_crtc_disable, | |
db380c58 | 648 | .atomic_check = tilcdc_crtc_atomic_check, |
f6382f18 | 649 | .mode_set_nofb = tilcdc_crtc_mode_set_nofb, |
16ea975e RC |
650 | }; |
651 | ||
652 | int tilcdc_crtc_max_width(struct drm_crtc *crtc) | |
653 | { | |
654 | struct drm_device *dev = crtc->dev; | |
655 | struct tilcdc_drm_private *priv = dev->dev_private; | |
656 | int max_width = 0; | |
657 | ||
658 | if (priv->rev == 1) | |
659 | max_width = 1024; | |
660 | else if (priv->rev == 2) | |
661 | max_width = 2048; | |
662 | ||
663 | return max_width; | |
664 | } | |
665 | ||
666 | int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
667 | { | |
668 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; | |
669 | unsigned int bandwidth; | |
e1c5d0a8 | 670 | uint32_t hbp, hfp, hsw, vbp, vfp, vsw; |
16ea975e | 671 | |
e1c5d0a8 DE |
672 | /* |
673 | * check to see if the width is within the range that | |
674 | * the LCD Controller physically supports | |
675 | */ | |
16ea975e RC |
676 | if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) |
677 | return MODE_VIRTUAL_X; | |
678 | ||
679 | /* width must be multiple of 16 */ | |
680 | if (mode->hdisplay & 0xf) | |
681 | return MODE_VIRTUAL_X; | |
682 | ||
683 | if (mode->vdisplay > 2048) | |
684 | return MODE_VIRTUAL_Y; | |
685 | ||
e1c5d0a8 DE |
686 | DBG("Processing mode %dx%d@%d with pixel clock %d", |
687 | mode->hdisplay, mode->vdisplay, | |
688 | drm_mode_vrefresh(mode), mode->clock); | |
689 | ||
690 | hbp = mode->htotal - mode->hsync_end; | |
691 | hfp = mode->hsync_start - mode->hdisplay; | |
692 | hsw = mode->hsync_end - mode->hsync_start; | |
693 | vbp = mode->vtotal - mode->vsync_end; | |
694 | vfp = mode->vsync_start - mode->vdisplay; | |
695 | vsw = mode->vsync_end - mode->vsync_start; | |
696 | ||
697 | if ((hbp-1) & ~0x3ff) { | |
698 | DBG("Pruning mode: Horizontal Back Porch out of range"); | |
699 | return MODE_HBLANK_WIDE; | |
700 | } | |
701 | ||
702 | if ((hfp-1) & ~0x3ff) { | |
703 | DBG("Pruning mode: Horizontal Front Porch out of range"); | |
704 | return MODE_HBLANK_WIDE; | |
705 | } | |
706 | ||
707 | if ((hsw-1) & ~0x3ff) { | |
708 | DBG("Pruning mode: Horizontal Sync Width out of range"); | |
709 | return MODE_HSYNC_WIDE; | |
710 | } | |
711 | ||
712 | if (vbp & ~0xff) { | |
713 | DBG("Pruning mode: Vertical Back Porch out of range"); | |
714 | return MODE_VBLANK_WIDE; | |
715 | } | |
716 | ||
717 | if (vfp & ~0xff) { | |
718 | DBG("Pruning mode: Vertical Front Porch out of range"); | |
719 | return MODE_VBLANK_WIDE; | |
720 | } | |
721 | ||
722 | if ((vsw-1) & ~0x3f) { | |
723 | DBG("Pruning mode: Vertical Sync Width out of range"); | |
724 | return MODE_VSYNC_WIDE; | |
725 | } | |
726 | ||
4e564346 DE |
727 | /* |
728 | * some devices have a maximum allowed pixel clock | |
729 | * configured from the DT | |
730 | */ | |
731 | if (mode->clock > priv->max_pixelclock) { | |
f7b45756 | 732 | DBG("Pruning mode: pixel clock too high"); |
4e564346 DE |
733 | return MODE_CLOCK_HIGH; |
734 | } | |
735 | ||
736 | /* | |
737 | * some devices further limit the max horizontal resolution | |
738 | * configured from the DT | |
739 | */ | |
740 | if (mode->hdisplay > priv->max_width) | |
741 | return MODE_BAD_WIDTH; | |
742 | ||
16ea975e | 743 | /* filter out modes that would require too much memory bandwidth: */ |
4e564346 DE |
744 | bandwidth = mode->hdisplay * mode->vdisplay * |
745 | drm_mode_vrefresh(mode); | |
746 | if (bandwidth > priv->max_bandwidth) { | |
f7b45756 | 747 | DBG("Pruning mode: exceeds defined bandwidth limit"); |
16ea975e | 748 | return MODE_BAD; |
4e564346 | 749 | } |
16ea975e RC |
750 | |
751 | return MODE_OK; | |
752 | } | |
753 | ||
754 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, | |
755 | const struct tilcdc_panel_info *info) | |
756 | { | |
757 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
758 | tilcdc_crtc->info = info; | |
759 | } | |
760 | ||
103cd8bc JS |
761 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
762 | bool simulate_vesa_sync) | |
763 | { | |
764 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
765 | ||
766 | tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; | |
767 | } | |
768 | ||
16ea975e RC |
769 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc) |
770 | { | |
16ea975e RC |
771 | struct drm_device *dev = crtc->dev; |
772 | struct tilcdc_drm_private *priv = dev->dev_private; | |
642e5167 | 773 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 774 | |
642e5167 JS |
775 | drm_modeset_lock_crtc(crtc, NULL); |
776 | if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) { | |
777 | if (tilcdc_crtc_is_on(crtc)) { | |
778 | pm_runtime_get_sync(dev->dev); | |
779 | tilcdc_crtc_disable(crtc); | |
16ea975e | 780 | |
642e5167 | 781 | tilcdc_crtc_set_clk(crtc); |
16ea975e | 782 | |
642e5167 JS |
783 | tilcdc_crtc_enable(crtc); |
784 | pm_runtime_put_sync(dev->dev); | |
785 | } | |
16ea975e | 786 | } |
642e5167 | 787 | drm_modeset_unlock_crtc(crtc); |
16ea975e RC |
788 | } |
789 | ||
5895d08f JS |
790 | #define SYNC_LOST_COUNT_LIMIT 50 |
791 | ||
16ea975e RC |
792 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) |
793 | { | |
794 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
795 | struct drm_device *dev = crtc->dev; | |
796 | struct tilcdc_drm_private *priv = dev->dev_private; | |
317aae73 | 797 | uint32_t stat; |
16ea975e | 798 | |
317aae73 TV |
799 | stat = tilcdc_read_irqstatus(dev); |
800 | tilcdc_clear_irqstatus(dev, stat); | |
801 | ||
2b2080d7 | 802 | if (stat & LCDC_END_OF_FRAME0) { |
16ea975e | 803 | unsigned long flags; |
2b3a8cd7 TV |
804 | bool skip_event = false; |
805 | ktime_t now; | |
806 | ||
807 | now = ktime_get(); | |
16ea975e | 808 | |
2b2080d7 | 809 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); |
16ea975e | 810 | |
2b3a8cd7 TV |
811 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
812 | ||
813 | tilcdc_crtc->last_vblank = now; | |
814 | ||
815 | if (tilcdc_crtc->next_fb) { | |
816 | set_scanout(crtc, tilcdc_crtc->next_fb); | |
817 | tilcdc_crtc->next_fb = NULL; | |
818 | skip_event = true; | |
819 | } | |
820 | ||
821 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
822 | ||
099ede83 | 823 | drm_crtc_handle_vblank(crtc); |
16ea975e | 824 | |
2b3a8cd7 TV |
825 | if (!skip_event) { |
826 | struct drm_pending_vblank_event *event; | |
16ea975e | 827 | |
2b3a8cd7 TV |
828 | spin_lock_irqsave(&dev->event_lock, flags); |
829 | ||
830 | event = tilcdc_crtc->event; | |
2b2080d7 | 831 | tilcdc_crtc->event = NULL; |
2b3a8cd7 | 832 | if (event) |
dfebc152 | 833 | drm_crtc_send_vblank_event(crtc, event); |
2b2080d7 | 834 | |
2b3a8cd7 TV |
835 | spin_unlock_irqrestore(&dev->event_lock, flags); |
836 | } | |
5895d08f JS |
837 | |
838 | if (tilcdc_crtc->frame_intact) | |
839 | tilcdc_crtc->sync_lost_count = 0; | |
840 | else | |
841 | tilcdc_crtc->frame_intact = true; | |
16ea975e RC |
842 | } |
843 | ||
14944113 | 844 | if (stat & LCDC_FIFO_UNDERFLOW) |
d701453b | 845 | dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow", |
14944113 JS |
846 | __func__, stat); |
847 | ||
848 | /* For revision 2 only */ | |
16ea975e RC |
849 | if (priv->rev == 2) { |
850 | if (stat & LCDC_FRAME_DONE) { | |
851 | tilcdc_crtc->frame_done = true; | |
852 | wake_up(&tilcdc_crtc->frame_done_wq); | |
853 | } | |
16ea975e | 854 | |
1abcdac8 JS |
855 | if (stat & LCDC_SYNC_LOST) { |
856 | dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", | |
857 | __func__, stat); | |
858 | tilcdc_crtc->frame_intact = false; | |
859 | if (tilcdc_crtc->sync_lost_count++ > | |
860 | SYNC_LOST_COUNT_LIMIT) { | |
13b3d727 JS |
861 | dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, recovering", __func__, stat); |
862 | queue_work(system_wq, | |
863 | &tilcdc_crtc->recover_work); | |
1abcdac8 JS |
864 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, |
865 | LCDC_SYNC_LOST); | |
13b3d727 | 866 | tilcdc_crtc->sync_lost_count = 0; |
1abcdac8 | 867 | } |
5895d08f | 868 | } |
c0c2baaa | 869 | |
14944113 JS |
870 | /* Indicate to LCDC that the interrupt service routine has |
871 | * completed, see 13.3.6.1.6 in AM335x TRM. | |
872 | */ | |
873 | tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); | |
874 | } | |
c0c2baaa | 875 | |
16ea975e RC |
876 | return IRQ_HANDLED; |
877 | } | |
878 | ||
16ea975e RC |
879 | struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) |
880 | { | |
d66284fb | 881 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e RC |
882 | struct tilcdc_crtc *tilcdc_crtc; |
883 | struct drm_crtc *crtc; | |
884 | int ret; | |
885 | ||
d0ec32ca | 886 | tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); |
16ea975e RC |
887 | if (!tilcdc_crtc) { |
888 | dev_err(dev->dev, "allocation failed\n"); | |
889 | return NULL; | |
890 | } | |
891 | ||
892 | crtc = &tilcdc_crtc->base; | |
893 | ||
47f571c6 JS |
894 | ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); |
895 | if (ret < 0) | |
896 | goto fail; | |
897 | ||
2d53a180 JS |
898 | mutex_init(&tilcdc_crtc->enable_lock); |
899 | ||
16ea975e RC |
900 | init_waitqueue_head(&tilcdc_crtc->frame_done_wq); |
901 | ||
d7f8db53 | 902 | drm_flip_work_init(&tilcdc_crtc->unref_work, |
a464d618 | 903 | "unref", unref_worker); |
16ea975e | 904 | |
2b3a8cd7 | 905 | spin_lock_init(&tilcdc_crtc->irq_lock); |
13b3d727 | 906 | INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work); |
2b3a8cd7 | 907 | |
47f571c6 JS |
908 | ret = drm_crtc_init_with_planes(dev, crtc, |
909 | &tilcdc_crtc->primary, | |
910 | NULL, | |
911 | &tilcdc_crtc_funcs, | |
912 | "tilcdc crtc"); | |
16ea975e RC |
913 | if (ret < 0) |
914 | goto fail; | |
915 | ||
916 | drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); | |
917 | ||
d66284fb JS |
918 | if (priv->is_componentized) { |
919 | struct device_node *ports = | |
920 | of_get_child_by_name(dev->dev->of_node, "ports"); | |
921 | ||
922 | if (ports) { | |
923 | crtc->port = of_get_child_by_name(ports, "port"); | |
924 | of_node_put(ports); | |
925 | } else { | |
926 | crtc->port = | |
927 | of_get_child_by_name(dev->dev->of_node, "port"); | |
928 | } | |
929 | if (!crtc->port) { /* This should never happen */ | |
930 | dev_err(dev->dev, "Port node not found in %s\n", | |
931 | dev->dev->of_node->full_name); | |
932 | goto fail; | |
933 | } | |
934 | } | |
935 | ||
16ea975e RC |
936 | return crtc; |
937 | ||
938 | fail: | |
939 | tilcdc_crtc_destroy(crtc); | |
940 | return NULL; | |
941 | } |