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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 CRTC module | |
11 | * | |
12 | * In VC4, the Pixel Valve is what most closely corresponds to the | |
13 | * DRM's concept of a CRTC. The PV generates video timings from the | |
14 | * output's clock plus its configuration. It pulls scaled pixels from | |
15 | * the HVS at that timing, and feeds it to the encoder. | |
16 | * | |
17 | * However, the DRM CRTC also collects the configuration of all the | |
18 | * DRM planes attached to it. As a result, this file also manages | |
19 | * setup of the VC4 HVS's display elements on the CRTC. | |
20 | * | |
21 | * The 2835 has 3 different pixel valves. pv0 in the audio power | |
22 | * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the | |
23 | * image domain can feed either HDMI or the SDTV controller. The | |
24 | * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for | |
25 | * SDTV, etc.) according to which output type is chosen in the mux. | |
26 | * | |
27 | * For power management, the pixel valve's registers are all clocked | |
28 | * by the AXI clock, while the timings and FIFOs make use of the | |
29 | * output-specific clock. Since the encoders also directly consume | |
30 | * the CPRMAN clocks, and know what timings they need, they are the | |
31 | * ones that set the clock. | |
32 | */ | |
33 | ||
34 | #include "drm_atomic.h" | |
35 | #include "drm_atomic_helper.h" | |
36 | #include "drm_crtc_helper.h" | |
37 | #include "linux/clk.h" | |
b501bacc | 38 | #include "drm_fb_cma_helper.h" |
c8b75bca EA |
39 | #include "linux/component.h" |
40 | #include "linux/of_device.h" | |
41 | #include "vc4_drv.h" | |
42 | #include "vc4_regs.h" | |
43 | ||
44 | struct vc4_crtc { | |
45 | struct drm_crtc base; | |
46 | const struct vc4_crtc_data *data; | |
47 | void __iomem *regs; | |
48 | ||
1bf59f1d MK |
49 | /* Timestamp at start of vblank irq - unaffected by lock delays. */ |
50 | ktime_t t_vblank; | |
51 | ||
c8b75bca EA |
52 | /* Which HVS channel we're using for our CRTC. */ |
53 | int channel; | |
54 | ||
e582b6c7 EA |
55 | u8 lut_r[256]; |
56 | u8 lut_g[256]; | |
57 | u8 lut_b[256]; | |
1bf59f1d MK |
58 | /* Size in pixels of the COB memory allocated to this CRTC. */ |
59 | u32 cob_size; | |
e582b6c7 | 60 | |
c8b75bca EA |
61 | struct drm_pending_vblank_event *event; |
62 | }; | |
63 | ||
d8dbf44f EA |
64 | struct vc4_crtc_state { |
65 | struct drm_crtc_state base; | |
66 | /* Dlist area for this CRTC configuration. */ | |
67 | struct drm_mm_node mm; | |
68 | }; | |
69 | ||
c8b75bca EA |
70 | static inline struct vc4_crtc * |
71 | to_vc4_crtc(struct drm_crtc *crtc) | |
72 | { | |
73 | return (struct vc4_crtc *)crtc; | |
74 | } | |
75 | ||
d8dbf44f EA |
76 | static inline struct vc4_crtc_state * |
77 | to_vc4_crtc_state(struct drm_crtc_state *crtc_state) | |
78 | { | |
79 | return (struct vc4_crtc_state *)crtc_state; | |
80 | } | |
81 | ||
c8b75bca EA |
82 | struct vc4_crtc_data { |
83 | /* Which channel of the HVS this pixelvalve sources from. */ | |
84 | int hvs_channel; | |
85 | ||
ab8df60e | 86 | enum vc4_encoder_type encoder_types[4]; |
c8b75bca EA |
87 | }; |
88 | ||
89 | #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) | |
90 | #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) | |
91 | ||
92 | #define CRTC_REG(reg) { reg, #reg } | |
93 | static const struct { | |
94 | u32 reg; | |
95 | const char *name; | |
96 | } crtc_regs[] = { | |
97 | CRTC_REG(PV_CONTROL), | |
98 | CRTC_REG(PV_V_CONTROL), | |
c31806fb | 99 | CRTC_REG(PV_VSYNCD_EVEN), |
c8b75bca EA |
100 | CRTC_REG(PV_HORZA), |
101 | CRTC_REG(PV_HORZB), | |
102 | CRTC_REG(PV_VERTA), | |
103 | CRTC_REG(PV_VERTB), | |
104 | CRTC_REG(PV_VERTA_EVEN), | |
105 | CRTC_REG(PV_VERTB_EVEN), | |
106 | CRTC_REG(PV_INTEN), | |
107 | CRTC_REG(PV_INTSTAT), | |
108 | CRTC_REG(PV_STAT), | |
109 | CRTC_REG(PV_HACT_ACT), | |
110 | }; | |
111 | ||
112 | static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) | |
113 | { | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
117 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
118 | crtc_regs[i].reg, crtc_regs[i].name, | |
119 | CRTC_READ(crtc_regs[i].reg)); | |
120 | } | |
121 | } | |
122 | ||
123 | #ifdef CONFIG_DEBUG_FS | |
124 | int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) | |
125 | { | |
126 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
127 | struct drm_device *dev = node->minor->dev; | |
128 | int crtc_index = (uintptr_t)node->info_ent->data; | |
129 | struct drm_crtc *crtc; | |
130 | struct vc4_crtc *vc4_crtc; | |
131 | int i; | |
132 | ||
133 | i = 0; | |
134 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
135 | if (i == crtc_index) | |
136 | break; | |
137 | i++; | |
138 | } | |
139 | if (!crtc) | |
140 | return 0; | |
141 | vc4_crtc = to_vc4_crtc(crtc); | |
142 | ||
143 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
144 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
145 | crtc_regs[i].name, crtc_regs[i].reg, | |
146 | CRTC_READ(crtc_regs[i].reg)); | |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | #endif | |
152 | ||
1bf59f1d MK |
153 | int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, |
154 | unsigned int flags, int *vpos, int *hpos, | |
155 | ktime_t *stime, ktime_t *etime, | |
156 | const struct drm_display_mode *mode) | |
157 | { | |
158 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
159 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
160 | u32 val; | |
161 | int fifo_lines; | |
162 | int vblank_lines; | |
163 | int ret = 0; | |
164 | ||
30c897dd EA |
165 | if (vc4->firmware_kms) |
166 | return 0; | |
167 | ||
1bf59f1d MK |
168 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
169 | ||
170 | /* Get optional system timestamp before query. */ | |
171 | if (stime) | |
172 | *stime = ktime_get(); | |
173 | ||
174 | /* | |
175 | * Read vertical scanline which is currently composed for our | |
176 | * pixelvalve by the HVS, and also the scaler status. | |
177 | */ | |
178 | val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel)); | |
179 | ||
180 | /* Get optional system timestamp after query. */ | |
181 | if (etime) | |
182 | *etime = ktime_get(); | |
183 | ||
184 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
185 | ||
186 | /* Vertical position of hvs composed scanline. */ | |
187 | *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); | |
e538092c MK |
188 | *hpos = 0; |
189 | ||
190 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
191 | *vpos /= 2; | |
1bf59f1d | 192 | |
e538092c MK |
193 | /* Use hpos to correct for field offset in interlaced mode. */ |
194 | if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) | |
195 | *hpos += mode->crtc_htotal / 2; | |
196 | } | |
1bf59f1d MK |
197 | |
198 | /* This is the offset we need for translating hvs -> pv scanout pos. */ | |
199 | fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay; | |
200 | ||
201 | if (fifo_lines > 0) | |
202 | ret |= DRM_SCANOUTPOS_VALID; | |
203 | ||
204 | /* HVS more than fifo_lines into frame for compositing? */ | |
205 | if (*vpos > fifo_lines) { | |
206 | /* | |
207 | * We are in active scanout and can get some meaningful results | |
208 | * from HVS. The actual PV scanout can not trail behind more | |
209 | * than fifo_lines as that is the fifo's capacity. Assume that | |
210 | * in active scanout the HVS and PV work in lockstep wrt. HVS | |
211 | * refilling the fifo and PV consuming from the fifo, ie. | |
212 | * whenever the PV consumes and frees up a scanline in the | |
213 | * fifo, the HVS will immediately refill it, therefore | |
214 | * incrementing vpos. Therefore we choose HVS read position - | |
215 | * fifo size in scanlines as a estimate of the real scanout | |
216 | * position of the PV. | |
217 | */ | |
218 | *vpos -= fifo_lines + 1; | |
1bf59f1d MK |
219 | |
220 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
221 | return ret; | |
222 | } | |
223 | ||
224 | /* | |
225 | * Less: This happens when we are in vblank and the HVS, after getting | |
226 | * the VSTART restart signal from the PV, just started refilling its | |
227 | * fifo with new lines from the top-most lines of the new framebuffers. | |
228 | * The PV does not scan out in vblank, so does not remove lines from | |
229 | * the fifo, so the fifo will be full quickly and the HVS has to pause. | |
230 | * We can't get meaningful readings wrt. scanline position of the PV | |
231 | * and need to make things up in a approximative but consistent way. | |
232 | */ | |
233 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
682e62c4 | 234 | vblank_lines = mode->vtotal - mode->vdisplay; |
1bf59f1d MK |
235 | |
236 | if (flags & DRM_CALLED_FROM_VBLIRQ) { | |
237 | /* | |
238 | * Assume the irq handler got called close to first | |
239 | * line of vblank, so PV has about a full vblank | |
240 | * scanlines to go, and as a base timestamp use the | |
241 | * one taken at entry into vblank irq handler, so it | |
242 | * is not affected by random delays due to lock | |
243 | * contention on event_lock or vblank_time lock in | |
244 | * the core. | |
245 | */ | |
246 | *vpos = -vblank_lines; | |
247 | ||
248 | if (stime) | |
249 | *stime = vc4_crtc->t_vblank; | |
250 | if (etime) | |
251 | *etime = vc4_crtc->t_vblank; | |
252 | ||
253 | /* | |
254 | * If the HVS fifo is not yet full then we know for certain | |
255 | * we are at the very beginning of vblank, as the hvs just | |
256 | * started refilling, and the stime and etime timestamps | |
257 | * truly correspond to start of vblank. | |
258 | */ | |
259 | if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL) | |
260 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
261 | } else { | |
262 | /* | |
263 | * No clue where we are inside vblank. Return a vpos of zero, | |
264 | * which will cause calling code to just return the etime | |
265 | * timestamp uncorrected. At least this is no worse than the | |
266 | * standard fallback. | |
267 | */ | |
268 | *vpos = 0; | |
269 | } | |
270 | ||
271 | return ret; | |
272 | } | |
273 | ||
274 | int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id, | |
275 | int *max_error, struct timeval *vblank_time, | |
276 | unsigned flags) | |
277 | { | |
278 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
279 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
280 | struct drm_crtc *crtc = &vc4_crtc->base; | |
281 | struct drm_crtc_state *state = crtc->state; | |
282 | ||
283 | /* Helper routine in DRM core does all the work: */ | |
284 | return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error, | |
285 | vblank_time, flags, | |
286 | &state->adjusted_mode); | |
287 | } | |
288 | ||
c8b75bca EA |
289 | static void vc4_crtc_destroy(struct drm_crtc *crtc) |
290 | { | |
291 | drm_crtc_cleanup(crtc); | |
292 | } | |
293 | ||
e582b6c7 EA |
294 | static void |
295 | vc4_crtc_lut_load(struct drm_crtc *crtc) | |
296 | { | |
297 | struct drm_device *dev = crtc->dev; | |
298 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
299 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
300 | u32 i; | |
301 | ||
302 | /* The LUT memory is laid out with each HVS channel in order, | |
303 | * each of which takes 256 writes for R, 256 for G, then 256 | |
304 | * for B. | |
305 | */ | |
306 | HVS_WRITE(SCALER_GAMADDR, | |
307 | SCALER_GAMADDR_AUTOINC | | |
308 | (vc4_crtc->channel * 3 * crtc->gamma_size)); | |
309 | ||
310 | for (i = 0; i < crtc->gamma_size; i++) | |
311 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); | |
312 | for (i = 0; i < crtc->gamma_size; i++) | |
313 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); | |
314 | for (i = 0; i < crtc->gamma_size; i++) | |
315 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); | |
316 | } | |
317 | ||
7ea77283 | 318 | static int |
e582b6c7 | 319 | vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
7ea77283 | 320 | uint32_t size) |
e582b6c7 EA |
321 | { |
322 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
323 | u32 i; | |
324 | ||
7ea77283 | 325 | for (i = 0; i < size; i++) { |
e582b6c7 EA |
326 | vc4_crtc->lut_r[i] = r[i] >> 8; |
327 | vc4_crtc->lut_g[i] = g[i] >> 8; | |
328 | vc4_crtc->lut_b[i] = b[i] >> 8; | |
329 | } | |
330 | ||
331 | vc4_crtc_lut_load(crtc); | |
7ea77283 ML |
332 | |
333 | return 0; | |
e582b6c7 EA |
334 | } |
335 | ||
c8b75bca EA |
336 | static u32 vc4_get_fifo_full_level(u32 format) |
337 | { | |
338 | static const u32 fifo_len_bytes = 64; | |
339 | static const u32 hvs_latency_pix = 6; | |
340 | ||
341 | switch (format) { | |
342 | case PV_CONTROL_FORMAT_DSIV_16: | |
343 | case PV_CONTROL_FORMAT_DSIC_16: | |
344 | return fifo_len_bytes - 2 * hvs_latency_pix; | |
345 | case PV_CONTROL_FORMAT_DSIV_18: | |
346 | return fifo_len_bytes - 14; | |
347 | case PV_CONTROL_FORMAT_24: | |
348 | case PV_CONTROL_FORMAT_DSIV_24: | |
349 | default: | |
350 | return fifo_len_bytes - 3 * hvs_latency_pix; | |
351 | } | |
352 | } | |
353 | ||
354 | /* | |
1370dadf EA |
355 | * Returns the encoder attached to the CRTC. |
356 | * | |
357 | * VC4 can only scan out to one encoder at a time, while the DRM core | |
358 | * allows drivers to push pixels to more than one encoder from the | |
359 | * same CRTC. | |
c8b75bca | 360 | */ |
1370dadf | 361 | static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) |
c8b75bca EA |
362 | { |
363 | struct drm_connector *connector; | |
364 | ||
365 | drm_for_each_connector(connector, crtc->dev) { | |
2fa8e904 | 366 | if (connector->state->crtc == crtc) { |
1370dadf | 367 | return connector->encoder; |
c8b75bca EA |
368 | } |
369 | } | |
370 | ||
1370dadf | 371 | return NULL; |
c8b75bca EA |
372 | } |
373 | ||
374 | static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
375 | { | |
6a609209 EA |
376 | struct drm_device *dev = crtc->dev; |
377 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
1370dadf EA |
378 | struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); |
379 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
c8b75bca EA |
380 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
381 | struct drm_crtc_state *state = crtc->state; | |
382 | struct drm_display_mode *mode = &state->adjusted_mode; | |
383 | bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
dfccd937 | 384 | u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; |
1370dadf EA |
385 | bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || |
386 | vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); | |
387 | u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; | |
c8b75bca | 388 | bool debug_dump_regs = false; |
c8b75bca EA |
389 | |
390 | if (debug_dump_regs) { | |
391 | DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); | |
392 | vc4_crtc_dump_regs(vc4_crtc); | |
393 | } | |
394 | ||
395 | /* Reset the PV fifo. */ | |
396 | CRTC_WRITE(PV_CONTROL, 0); | |
397 | CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); | |
398 | CRTC_WRITE(PV_CONTROL, 0); | |
399 | ||
400 | CRTC_WRITE(PV_HORZA, | |
dfccd937 EA |
401 | VC4_SET_FIELD((mode->htotal - |
402 | mode->hsync_end) * pixel_rep, | |
c8b75bca | 403 | PV_HORZA_HBP) | |
dfccd937 EA |
404 | VC4_SET_FIELD((mode->hsync_end - |
405 | mode->hsync_start) * pixel_rep, | |
c8b75bca EA |
406 | PV_HORZA_HSYNC)); |
407 | CRTC_WRITE(PV_HORZB, | |
dfccd937 EA |
408 | VC4_SET_FIELD((mode->hsync_start - |
409 | mode->hdisplay) * pixel_rep, | |
c8b75bca | 410 | PV_HORZB_HFP) | |
dfccd937 | 411 | VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); |
c8b75bca | 412 | |
a7c5047d | 413 | CRTC_WRITE(PV_VERTA, |
682e62c4 | 414 | VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, |
a7c5047d | 415 | PV_VERTA_VBP) | |
682e62c4 | 416 | VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, |
a7c5047d EA |
417 | PV_VERTA_VSYNC)); |
418 | CRTC_WRITE(PV_VERTB, | |
682e62c4 | 419 | VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, |
a7c5047d | 420 | PV_VERTB_VFP) | |
682e62c4 | 421 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
a7c5047d | 422 | |
c8b75bca EA |
423 | if (interlace) { |
424 | CRTC_WRITE(PV_VERTA_EVEN, | |
682e62c4 EA |
425 | VC4_SET_FIELD(mode->crtc_vtotal - |
426 | mode->crtc_vsync_end - 1, | |
c8b75bca | 427 | PV_VERTA_VBP) | |
682e62c4 EA |
428 | VC4_SET_FIELD(mode->crtc_vsync_end - |
429 | mode->crtc_vsync_start, | |
c8b75bca EA |
430 | PV_VERTA_VSYNC)); |
431 | CRTC_WRITE(PV_VERTB_EVEN, | |
682e62c4 EA |
432 | VC4_SET_FIELD(mode->crtc_vsync_start - |
433 | mode->crtc_vdisplay, | |
c8b75bca | 434 | PV_VERTB_VFP) | |
682e62c4 EA |
435 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
436 | ||
437 | /* We set up first field even mode for HDMI. VEC's | |
438 | * NTSC mode would want first field odd instead, once | |
439 | * we support it (to do so, set ODD_FIRST and put the | |
440 | * delay in VSYNCD_EVEN instead). | |
441 | */ | |
442 | CRTC_WRITE(PV_V_CONTROL, | |
443 | PV_VCONTROL_CONTINUOUS | | |
1370dadf | 444 | (is_dsi ? PV_VCONTROL_DSI : 0) | |
682e62c4 | 445 | PV_VCONTROL_INTERLACE | |
dfccd937 | 446 | VC4_SET_FIELD(mode->htotal * pixel_rep / 2, |
682e62c4 EA |
447 | PV_VCONTROL_ODD_DELAY)); |
448 | CRTC_WRITE(PV_VSYNCD_EVEN, 0); | |
449 | } else { | |
1370dadf EA |
450 | CRTC_WRITE(PV_V_CONTROL, |
451 | PV_VCONTROL_CONTINUOUS | | |
452 | (is_dsi ? PV_VCONTROL_DSI : 0)); | |
c8b75bca EA |
453 | } |
454 | ||
dfccd937 | 455 | CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); |
c8b75bca | 456 | |
c8b75bca EA |
457 | CRTC_WRITE(PV_CONTROL, |
458 | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | | |
459 | VC4_SET_FIELD(vc4_get_fifo_full_level(format), | |
460 | PV_CONTROL_FIFO_LEVEL) | | |
dfccd937 | 461 | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | |
c8b75bca EA |
462 | PV_CONTROL_CLR_AT_START | |
463 | PV_CONTROL_TRIGGER_UNDERFLOW | | |
464 | PV_CONTROL_WAIT_HSTART | | |
1370dadf EA |
465 | VC4_SET_FIELD(vc4_encoder->clock_select, |
466 | PV_CONTROL_CLK_SELECT) | | |
c8b75bca EA |
467 | PV_CONTROL_FIFO_CLR | |
468 | PV_CONTROL_EN); | |
469 | ||
6a609209 EA |
470 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), |
471 | SCALER_DISPBKGND_AUTOHS | | |
e582b6c7 | 472 | SCALER_DISPBKGND_GAMMA | |
6a609209 EA |
473 | (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); |
474 | ||
e582b6c7 EA |
475 | /* Reload the LUT, since the SRAMs would have been disabled if |
476 | * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. | |
477 | */ | |
478 | vc4_crtc_lut_load(crtc); | |
479 | ||
c8b75bca EA |
480 | if (debug_dump_regs) { |
481 | DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); | |
482 | vc4_crtc_dump_regs(vc4_crtc); | |
483 | } | |
484 | } | |
485 | ||
486 | static void require_hvs_enabled(struct drm_device *dev) | |
487 | { | |
488 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
489 | ||
490 | WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != | |
491 | SCALER_DISPCTRL_ENABLE); | |
492 | } | |
493 | ||
494 | static void vc4_crtc_disable(struct drm_crtc *crtc) | |
495 | { | |
496 | struct drm_device *dev = crtc->dev; | |
497 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
498 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
499 | u32 chan = vc4_crtc->channel; | |
500 | int ret; | |
501 | require_hvs_enabled(dev); | |
502 | ||
e941f05d MK |
503 | /* Disable vblank irq handling before crtc is disabled. */ |
504 | drm_crtc_vblank_off(crtc); | |
505 | ||
c8b75bca EA |
506 | CRTC_WRITE(PV_V_CONTROL, |
507 | CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); | |
508 | ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); | |
509 | WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); | |
510 | ||
511 | if (HVS_READ(SCALER_DISPCTRLX(chan)) & | |
512 | SCALER_DISPCTRLX_ENABLE) { | |
513 | HVS_WRITE(SCALER_DISPCTRLX(chan), | |
514 | SCALER_DISPCTRLX_RESET); | |
515 | ||
516 | /* While the docs say that reset is self-clearing, it | |
517 | * seems it doesn't actually. | |
518 | */ | |
519 | HVS_WRITE(SCALER_DISPCTRLX(chan), 0); | |
520 | } | |
521 | ||
522 | /* Once we leave, the scaler should be disabled and its fifo empty. */ | |
523 | ||
524 | WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); | |
525 | ||
526 | WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), | |
527 | SCALER_DISPSTATX_MODE) != | |
528 | SCALER_DISPSTATX_MODE_DISABLED); | |
529 | ||
530 | WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & | |
531 | (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != | |
532 | SCALER_DISPSTATX_EMPTY); | |
533 | } | |
534 | ||
535 | static void vc4_crtc_enable(struct drm_crtc *crtc) | |
536 | { | |
537 | struct drm_device *dev = crtc->dev; | |
538 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
539 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
540 | struct drm_crtc_state *state = crtc->state; | |
541 | struct drm_display_mode *mode = &state->adjusted_mode; | |
542 | ||
543 | require_hvs_enabled(dev); | |
544 | ||
545 | /* Turn on the scaler, which will wait for vstart to start | |
546 | * compositing. | |
547 | */ | |
548 | HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), | |
549 | VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | | |
550 | VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | | |
551 | SCALER_DISPCTRLX_ENABLE); | |
552 | ||
553 | /* Turn on the pixel valve, which will emit the vstart signal. */ | |
554 | CRTC_WRITE(PV_V_CONTROL, | |
555 | CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); | |
e941f05d MK |
556 | |
557 | /* Enable vblank irq handling after crtc is started. */ | |
558 | drm_crtc_vblank_on(crtc); | |
c8b75bca EA |
559 | } |
560 | ||
acc1be1d MK |
561 | static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc, |
562 | const struct drm_display_mode *mode, | |
563 | struct drm_display_mode *adjusted_mode) | |
564 | { | |
36451467 MK |
565 | /* Do not allow doublescan modes from user space */ |
566 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
567 | DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", | |
568 | crtc->base.id); | |
569 | return false; | |
570 | } | |
571 | ||
acc1be1d MK |
572 | return true; |
573 | } | |
574 | ||
c8b75bca EA |
575 | static int vc4_crtc_atomic_check(struct drm_crtc *crtc, |
576 | struct drm_crtc_state *state) | |
577 | { | |
d8dbf44f | 578 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); |
c8b75bca EA |
579 | struct drm_device *dev = crtc->dev; |
580 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
581 | struct drm_plane *plane; | |
d8dbf44f | 582 | unsigned long flags; |
2f196b7c | 583 | const struct drm_plane_state *plane_state; |
c8b75bca | 584 | u32 dlist_count = 0; |
d8dbf44f | 585 | int ret; |
c8b75bca EA |
586 | |
587 | /* The pixelvalve can only feed one encoder (and encoders are | |
588 | * 1:1 with connectors.) | |
589 | */ | |
14de6c44 | 590 | if (hweight32(state->connector_mask) > 1) |
c8b75bca EA |
591 | return -EINVAL; |
592 | ||
2f196b7c | 593 | drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) |
c8b75bca | 594 | dlist_count += vc4_plane_dlist_size(plane_state); |
c8b75bca EA |
595 | |
596 | dlist_count++; /* Account for SCALER_CTL0_END. */ | |
597 | ||
d8dbf44f EA |
598 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); |
599 | ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, | |
600 | dlist_count, 1, 0); | |
601 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
602 | if (ret) | |
603 | return ret; | |
c8b75bca EA |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, | |
609 | struct drm_crtc_state *old_state) | |
610 | { | |
611 | struct drm_device *dev = crtc->dev; | |
612 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
613 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
d8dbf44f | 614 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); |
c8b75bca EA |
615 | struct drm_plane *plane; |
616 | bool debug_dump_regs = false; | |
d8dbf44f EA |
617 | u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; |
618 | u32 __iomem *dlist_next = dlist_start; | |
c8b75bca EA |
619 | |
620 | if (debug_dump_regs) { | |
621 | DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); | |
622 | vc4_hvs_dump_state(dev); | |
623 | } | |
624 | ||
d8dbf44f | 625 | /* Copy all the active planes' dlist contents to the hardware dlist. */ |
c8b75bca EA |
626 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
627 | dlist_next += vc4_plane_write_dlist(plane, dlist_next); | |
628 | } | |
629 | ||
d8dbf44f EA |
630 | writel(SCALER_CTL0_END, dlist_next); |
631 | dlist_next++; | |
632 | ||
633 | WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); | |
634 | ||
c8b75bca EA |
635 | if (crtc->state->event) { |
636 | unsigned long flags; | |
637 | ||
638 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
639 | ||
640 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
641 | ||
642 | spin_lock_irqsave(&dev->event_lock, flags); | |
643 | vc4_crtc->event = crtc->state->event; | |
c8b75bca | 644 | crtc->state->event = NULL; |
56d1fe09 MK |
645 | |
646 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
647 | vc4_state->mm.start); | |
648 | ||
649 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
650 | } else { | |
651 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
652 | vc4_state->mm.start); | |
653 | } | |
654 | ||
655 | if (debug_dump_regs) { | |
656 | DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); | |
657 | vc4_hvs_dump_state(dev); | |
c8b75bca EA |
658 | } |
659 | } | |
660 | ||
1f43710a | 661 | int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id) |
c8b75bca EA |
662 | { |
663 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
664 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
665 | ||
30c897dd EA |
666 | if (vc4->firmware_kms) { |
667 | /* XXX: Can we mask the SMI interrupt? */ | |
668 | return 0; | |
669 | } | |
670 | ||
c8b75bca EA |
671 | CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
1f43710a | 676 | void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id) |
c8b75bca EA |
677 | { |
678 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
679 | struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; | |
680 | ||
30c897dd EA |
681 | if (vc4->firmware_kms) { |
682 | /* XXX: Can we mask the SMI interrupt? */ | |
683 | return; | |
684 | } | |
685 | ||
c8b75bca EA |
686 | CRTC_WRITE(PV_INTEN, 0); |
687 | } | |
688 | ||
26fc78f6 DF |
689 | /* Must be called with the event lock held */ |
690 | bool vc4_event_pending(struct drm_crtc *crtc) | |
691 | { | |
692 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
693 | ||
694 | return !!vc4_crtc->event; | |
695 | } | |
696 | ||
c8b75bca EA |
697 | static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) |
698 | { | |
699 | struct drm_crtc *crtc = &vc4_crtc->base; | |
700 | struct drm_device *dev = crtc->dev; | |
56d1fe09 MK |
701 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
702 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); | |
703 | u32 chan = vc4_crtc->channel; | |
c8b75bca EA |
704 | unsigned long flags; |
705 | ||
706 | spin_lock_irqsave(&dev->event_lock, flags); | |
56d1fe09 MK |
707 | if (vc4_crtc->event && |
708 | (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { | |
c8b75bca EA |
709 | drm_crtc_send_vblank_event(crtc, vc4_crtc->event); |
710 | vc4_crtc->event = NULL; | |
ee7c10e1 | 711 | drm_crtc_vblank_put(crtc); |
c8b75bca EA |
712 | } |
713 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
714 | } | |
715 | ||
716 | static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) | |
717 | { | |
718 | struct vc4_crtc *vc4_crtc = data; | |
719 | u32 stat = CRTC_READ(PV_INTSTAT); | |
720 | irqreturn_t ret = IRQ_NONE; | |
721 | ||
722 | if (stat & PV_INT_VFP_START) { | |
1bf59f1d | 723 | vc4_crtc->t_vblank = ktime_get(); |
c8b75bca EA |
724 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); |
725 | drm_crtc_handle_vblank(&vc4_crtc->base); | |
726 | vc4_crtc_handle_page_flip(vc4_crtc); | |
727 | ret = IRQ_HANDLED; | |
728 | } | |
729 | ||
730 | return ret; | |
731 | } | |
732 | ||
b501bacc EA |
733 | struct vc4_async_flip_state { |
734 | struct drm_crtc *crtc; | |
735 | struct drm_framebuffer *fb; | |
736 | struct drm_pending_vblank_event *event; | |
737 | ||
738 | struct vc4_seqno_cb cb; | |
739 | }; | |
740 | ||
741 | /* Called when the V3D execution for the BO being flipped to is done, so that | |
742 | * we can actually update the plane's address to point to it. | |
743 | */ | |
744 | static void | |
745 | vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) | |
746 | { | |
747 | struct vc4_async_flip_state *flip_state = | |
748 | container_of(cb, struct vc4_async_flip_state, cb); | |
749 | struct drm_crtc *crtc = flip_state->crtc; | |
750 | struct drm_device *dev = crtc->dev; | |
751 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
752 | struct drm_plane *plane = crtc->primary; | |
753 | ||
754 | vc4_plane_async_set_fb(plane, flip_state->fb); | |
755 | if (flip_state->event) { | |
756 | unsigned long flags; | |
757 | ||
758 | spin_lock_irqsave(&dev->event_lock, flags); | |
759 | drm_crtc_send_vblank_event(crtc, flip_state->event); | |
760 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
761 | } | |
762 | ||
ee7c10e1 | 763 | drm_crtc_vblank_put(crtc); |
b501bacc EA |
764 | drm_framebuffer_unreference(flip_state->fb); |
765 | kfree(flip_state); | |
766 | ||
767 | up(&vc4->async_modeset); | |
768 | } | |
769 | ||
770 | /* Implements async (non-vblank-synced) page flips. | |
771 | * | |
772 | * The page flip ioctl needs to return immediately, so we grab the | |
773 | * modeset semaphore on the pipe, and queue the address update for | |
774 | * when V3D is done with the BO being flipped to. | |
775 | */ | |
776 | static int vc4_async_page_flip(struct drm_crtc *crtc, | |
777 | struct drm_framebuffer *fb, | |
778 | struct drm_pending_vblank_event *event, | |
779 | uint32_t flags) | |
780 | { | |
781 | struct drm_device *dev = crtc->dev; | |
782 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
783 | struct drm_plane *plane = crtc->primary; | |
784 | int ret = 0; | |
785 | struct vc4_async_flip_state *flip_state; | |
786 | struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); | |
787 | struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); | |
788 | ||
789 | flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); | |
790 | if (!flip_state) | |
791 | return -ENOMEM; | |
792 | ||
793 | drm_framebuffer_reference(fb); | |
794 | flip_state->fb = fb; | |
795 | flip_state->crtc = crtc; | |
796 | flip_state->event = event; | |
797 | ||
798 | /* Make sure all other async modesetes have landed. */ | |
799 | ret = down_interruptible(&vc4->async_modeset); | |
800 | if (ret) { | |
48627eb8 | 801 | drm_framebuffer_unreference(fb); |
b501bacc EA |
802 | kfree(flip_state); |
803 | return ret; | |
804 | } | |
805 | ||
ee7c10e1 MK |
806 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
807 | ||
b501bacc EA |
808 | /* Immediately update the plane's legacy fb pointer, so that later |
809 | * modeset prep sees the state that will be present when the semaphore | |
810 | * is released. | |
811 | */ | |
812 | drm_atomic_set_fb_for_plane(plane->state, fb); | |
813 | plane->fb = fb; | |
814 | ||
815 | vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, | |
816 | vc4_async_page_flip_complete); | |
817 | ||
818 | /* Driver takes ownership of state on successful async commit. */ | |
819 | return 0; | |
820 | } | |
821 | ||
822 | static int vc4_page_flip(struct drm_crtc *crtc, | |
823 | struct drm_framebuffer *fb, | |
824 | struct drm_pending_vblank_event *event, | |
825 | uint32_t flags) | |
826 | { | |
827 | if (flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
828 | return vc4_async_page_flip(crtc, fb, event, flags); | |
829 | else | |
830 | return drm_atomic_helper_page_flip(crtc, fb, event, flags); | |
831 | } | |
832 | ||
d8dbf44f EA |
833 | static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) |
834 | { | |
835 | struct vc4_crtc_state *vc4_state; | |
836 | ||
837 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
838 | if (!vc4_state) | |
839 | return NULL; | |
840 | ||
841 | __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); | |
842 | return &vc4_state->base; | |
843 | } | |
844 | ||
845 | static void vc4_crtc_destroy_state(struct drm_crtc *crtc, | |
846 | struct drm_crtc_state *state) | |
847 | { | |
848 | struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); | |
849 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); | |
850 | ||
851 | if (vc4_state->mm.allocated) { | |
852 | unsigned long flags; | |
853 | ||
854 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); | |
855 | drm_mm_remove_node(&vc4_state->mm); | |
856 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
857 | ||
858 | } | |
859 | ||
7622b255 | 860 | drm_atomic_helper_crtc_destroy_state(crtc, state); |
d8dbf44f EA |
861 | } |
862 | ||
e8f3b40c EA |
863 | static void |
864 | vc4_crtc_reset(struct drm_crtc *crtc) | |
865 | { | |
866 | if (crtc->state) | |
867 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
868 | ||
869 | crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL); | |
870 | if (crtc->state) | |
871 | crtc->state->crtc = crtc; | |
872 | } | |
873 | ||
c8b75bca EA |
874 | static const struct drm_crtc_funcs vc4_crtc_funcs = { |
875 | .set_config = drm_atomic_helper_set_config, | |
876 | .destroy = vc4_crtc_destroy, | |
b501bacc | 877 | .page_flip = vc4_page_flip, |
c8b75bca EA |
878 | .set_property = NULL, |
879 | .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ | |
880 | .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ | |
e8f3b40c | 881 | .reset = vc4_crtc_reset, |
d8dbf44f EA |
882 | .atomic_duplicate_state = vc4_crtc_duplicate_state, |
883 | .atomic_destroy_state = vc4_crtc_destroy_state, | |
e582b6c7 | 884 | .gamma_set = vc4_crtc_gamma_set, |
c8b75bca EA |
885 | }; |
886 | ||
887 | static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { | |
888 | .mode_set_nofb = vc4_crtc_mode_set_nofb, | |
889 | .disable = vc4_crtc_disable, | |
890 | .enable = vc4_crtc_enable, | |
acc1be1d | 891 | .mode_fixup = vc4_crtc_mode_fixup, |
c8b75bca EA |
892 | .atomic_check = vc4_crtc_atomic_check, |
893 | .atomic_flush = vc4_crtc_atomic_flush, | |
894 | }; | |
895 | ||
c8b75bca EA |
896 | static const struct vc4_crtc_data pv0_data = { |
897 | .hvs_channel = 0, | |
ab8df60e BB |
898 | .encoder_types = { |
899 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, | |
900 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, | |
901 | }, | |
c8b75bca EA |
902 | }; |
903 | ||
904 | static const struct vc4_crtc_data pv1_data = { | |
905 | .hvs_channel = 2, | |
ab8df60e BB |
906 | .encoder_types = { |
907 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, | |
908 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, | |
909 | }, | |
c8b75bca EA |
910 | }; |
911 | ||
912 | static const struct vc4_crtc_data pv2_data = { | |
913 | .hvs_channel = 1, | |
ab8df60e BB |
914 | .encoder_types = { |
915 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, | |
916 | [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, | |
917 | }, | |
c8b75bca EA |
918 | }; |
919 | ||
920 | static const struct of_device_id vc4_crtc_dt_match[] = { | |
921 | { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, | |
922 | { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, | |
923 | { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, | |
924 | {} | |
925 | }; | |
926 | ||
927 | static void vc4_set_crtc_possible_masks(struct drm_device *drm, | |
928 | struct drm_crtc *crtc) | |
929 | { | |
930 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
ab8df60e BB |
931 | const struct vc4_crtc_data *crtc_data = vc4_crtc->data; |
932 | const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types; | |
c8b75bca EA |
933 | struct drm_encoder *encoder; |
934 | ||
935 | drm_for_each_encoder(encoder, drm) { | |
936 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
ab8df60e BB |
937 | int i; |
938 | ||
939 | for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) { | |
940 | if (vc4_encoder->type == encoder_types[i]) { | |
941 | vc4_encoder->clock_select = i; | |
942 | encoder->possible_crtcs |= drm_crtc_mask(crtc); | |
943 | break; | |
944 | } | |
c8b75bca EA |
945 | } |
946 | } | |
947 | } | |
948 | ||
1bf59f1d MK |
949 | static void |
950 | vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc) | |
951 | { | |
952 | struct drm_device *drm = vc4_crtc->base.dev; | |
953 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
954 | u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel)); | |
955 | /* Top/base are supposed to be 4-pixel aligned, but the | |
956 | * Raspberry Pi firmware fills the low bits (which are | |
957 | * presumably ignored). | |
958 | */ | |
959 | u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; | |
960 | u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; | |
961 | ||
962 | vc4_crtc->cob_size = top - base + 4; | |
963 | } | |
964 | ||
c8b75bca EA |
965 | static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) |
966 | { | |
967 | struct platform_device *pdev = to_platform_device(dev); | |
968 | struct drm_device *drm = dev_get_drvdata(master); | |
969 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
970 | struct vc4_crtc *vc4_crtc; | |
971 | struct drm_crtc *crtc; | |
fc2d6f1e | 972 | struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp; |
c8b75bca | 973 | const struct of_device_id *match; |
fc2d6f1e | 974 | int ret, i; |
c8b75bca EA |
975 | |
976 | vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); | |
977 | if (!vc4_crtc) | |
978 | return -ENOMEM; | |
979 | crtc = &vc4_crtc->base; | |
980 | ||
981 | match = of_match_device(vc4_crtc_dt_match, dev); | |
982 | if (!match) | |
983 | return -ENODEV; | |
984 | vc4_crtc->data = match->data; | |
985 | ||
986 | vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); | |
987 | if (IS_ERR(vc4_crtc->regs)) | |
988 | return PTR_ERR(vc4_crtc->regs); | |
989 | ||
990 | /* For now, we create just the primary and the legacy cursor | |
991 | * planes. We should be able to stack more planes on easily, | |
992 | * but to do that we would need to compute the bandwidth | |
993 | * requirement of the plane configuration, and reject ones | |
994 | * that will take too much. | |
995 | */ | |
996 | primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); | |
79513237 | 997 | if (IS_ERR(primary_plane)) { |
c8b75bca EA |
998 | dev_err(dev, "failed to construct primary plane\n"); |
999 | ret = PTR_ERR(primary_plane); | |
1000 | goto err; | |
1001 | } | |
1002 | ||
fc2d6f1e | 1003 | drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, |
f9882876 | 1004 | &vc4_crtc_funcs, NULL); |
c8b75bca EA |
1005 | drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); |
1006 | primary_plane->crtc = crtc; | |
c8b75bca EA |
1007 | vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc; |
1008 | vc4_crtc->channel = vc4_crtc->data->hvs_channel; | |
e582b6c7 | 1009 | drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); |
c8b75bca | 1010 | |
fc2d6f1e EA |
1011 | /* Set up some arbitrary number of planes. We're not limited |
1012 | * by a set number of physical registers, just the space in | |
1013 | * the HVS (16k) and how small an plane can be (28 bytes). | |
1014 | * However, each plane we set up takes up some memory, and | |
1015 | * increases the cost of looping over planes, which atomic | |
1016 | * modesetting does quite a bit. As a result, we pick a | |
1017 | * modest number of planes to expose, that should hopefully | |
1018 | * still cover any sane usecase. | |
1019 | */ | |
1020 | for (i = 0; i < 8; i++) { | |
1021 | struct drm_plane *plane = | |
1022 | vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); | |
1023 | ||
1024 | if (IS_ERR(plane)) | |
1025 | continue; | |
1026 | ||
1027 | plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1028 | } | |
1029 | ||
1030 | /* Set up the legacy cursor after overlay initialization, | |
1031 | * since we overlay planes on the CRTC in the order they were | |
1032 | * initialized. | |
1033 | */ | |
1034 | cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); | |
1035 | if (!IS_ERR(cursor_plane)) { | |
1036 | cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1037 | cursor_plane->crtc = crtc; | |
1038 | crtc->cursor = cursor_plane; | |
1039 | } | |
1040 | ||
1bf59f1d MK |
1041 | vc4_crtc_get_cob_allocation(vc4_crtc); |
1042 | ||
c8b75bca EA |
1043 | CRTC_WRITE(PV_INTEN, 0); |
1044 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); | |
1045 | ret = devm_request_irq(dev, platform_get_irq(pdev, 0), | |
1046 | vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); | |
1047 | if (ret) | |
fc2d6f1e | 1048 | goto err_destroy_planes; |
c8b75bca EA |
1049 | |
1050 | vc4_set_crtc_possible_masks(drm, crtc); | |
1051 | ||
e582b6c7 EA |
1052 | for (i = 0; i < crtc->gamma_size; i++) { |
1053 | vc4_crtc->lut_r[i] = i; | |
1054 | vc4_crtc->lut_g[i] = i; | |
1055 | vc4_crtc->lut_b[i] = i; | |
1056 | } | |
1057 | ||
c8b75bca EA |
1058 | platform_set_drvdata(pdev, vc4_crtc); |
1059 | ||
1060 | return 0; | |
1061 | ||
fc2d6f1e EA |
1062 | err_destroy_planes: |
1063 | list_for_each_entry_safe(destroy_plane, temp, | |
1064 | &drm->mode_config.plane_list, head) { | |
1065 | if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc)) | |
1066 | destroy_plane->funcs->destroy(destroy_plane); | |
1067 | } | |
c8b75bca EA |
1068 | err: |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | static void vc4_crtc_unbind(struct device *dev, struct device *master, | |
1073 | void *data) | |
1074 | { | |
1075 | struct platform_device *pdev = to_platform_device(dev); | |
1076 | struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); | |
1077 | ||
1078 | vc4_crtc_destroy(&vc4_crtc->base); | |
1079 | ||
1080 | CRTC_WRITE(PV_INTEN, 0); | |
1081 | ||
1082 | platform_set_drvdata(pdev, NULL); | |
1083 | } | |
1084 | ||
1085 | static const struct component_ops vc4_crtc_ops = { | |
1086 | .bind = vc4_crtc_bind, | |
1087 | .unbind = vc4_crtc_unbind, | |
1088 | }; | |
1089 | ||
1090 | static int vc4_crtc_dev_probe(struct platform_device *pdev) | |
1091 | { | |
1092 | return component_add(&pdev->dev, &vc4_crtc_ops); | |
1093 | } | |
1094 | ||
1095 | static int vc4_crtc_dev_remove(struct platform_device *pdev) | |
1096 | { | |
1097 | component_del(&pdev->dev, &vc4_crtc_ops); | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | struct platform_driver vc4_crtc_driver = { | |
1102 | .probe = vc4_crtc_dev_probe, | |
1103 | .remove = vc4_crtc_dev_remove, | |
1104 | .driver = { | |
1105 | .name = "vc4_crtc", | |
1106 | .of_match_table = vc4_crtc_dt_match, | |
1107 | }, | |
1108 | }; |