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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 CRTC module | |
11 | * | |
12 | * In VC4, the Pixel Valve is what most closely corresponds to the | |
13 | * DRM's concept of a CRTC. The PV generates video timings from the | |
f6c01530 | 14 | * encoder's clock plus its configuration. It pulls scaled pixels from |
c8b75bca EA |
15 | * the HVS at that timing, and feeds it to the encoder. |
16 | * | |
17 | * However, the DRM CRTC also collects the configuration of all the | |
f6c01530 EA |
18 | * DRM planes attached to it. As a result, the CRTC is also |
19 | * responsible for writing the display list for the HVS channel that | |
20 | * the CRTC will use. | |
c8b75bca EA |
21 | * |
22 | * The 2835 has 3 different pixel valves. pv0 in the audio power | |
23 | * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the | |
24 | * image domain can feed either HDMI or the SDTV controller. The | |
25 | * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for | |
26 | * SDTV, etc.) according to which output type is chosen in the mux. | |
27 | * | |
28 | * For power management, the pixel valve's registers are all clocked | |
29 | * by the AXI clock, while the timings and FIFOs make use of the | |
30 | * output-specific clock. Since the encoders also directly consume | |
31 | * the CPRMAN clocks, and know what timings they need, they are the | |
32 | * ones that set the clock. | |
33 | */ | |
34 | ||
b7e8e25b MY |
35 | #include <drm/drm_atomic.h> |
36 | #include <drm/drm_atomic_helper.h> | |
37 | #include <drm/drm_crtc_helper.h> | |
38 | #include <linux/clk.h> | |
39 | #include <drm/drm_fb_cma_helper.h> | |
40 | #include <linux/component.h> | |
41 | #include <linux/of_device.h> | |
c8b75bca EA |
42 | #include "vc4_drv.h" |
43 | #include "vc4_regs.h" | |
44 | ||
45 | struct vc4_crtc { | |
46 | struct drm_crtc base; | |
47 | const struct vc4_crtc_data *data; | |
48 | void __iomem *regs; | |
49 | ||
1bf59f1d MK |
50 | /* Timestamp at start of vblank irq - unaffected by lock delays. */ |
51 | ktime_t t_vblank; | |
52 | ||
c8b75bca EA |
53 | /* Which HVS channel we're using for our CRTC. */ |
54 | int channel; | |
55 | ||
e582b6c7 EA |
56 | u8 lut_r[256]; |
57 | u8 lut_g[256]; | |
58 | u8 lut_b[256]; | |
1bf59f1d MK |
59 | /* Size in pixels of the COB memory allocated to this CRTC. */ |
60 | u32 cob_size; | |
e582b6c7 | 61 | |
c8b75bca EA |
62 | struct drm_pending_vblank_event *event; |
63 | }; | |
64 | ||
d8dbf44f EA |
65 | struct vc4_crtc_state { |
66 | struct drm_crtc_state base; | |
67 | /* Dlist area for this CRTC configuration. */ | |
68 | struct drm_mm_node mm; | |
69 | }; | |
70 | ||
c8b75bca EA |
71 | static inline struct vc4_crtc * |
72 | to_vc4_crtc(struct drm_crtc *crtc) | |
73 | { | |
74 | return (struct vc4_crtc *)crtc; | |
75 | } | |
76 | ||
d8dbf44f EA |
77 | static inline struct vc4_crtc_state * |
78 | to_vc4_crtc_state(struct drm_crtc_state *crtc_state) | |
79 | { | |
80 | return (struct vc4_crtc_state *)crtc_state; | |
81 | } | |
82 | ||
c8b75bca EA |
83 | struct vc4_crtc_data { |
84 | /* Which channel of the HVS this pixelvalve sources from. */ | |
85 | int hvs_channel; | |
86 | ||
ab8df60e | 87 | enum vc4_encoder_type encoder_types[4]; |
c8b75bca EA |
88 | }; |
89 | ||
90 | #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) | |
91 | #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) | |
92 | ||
93 | #define CRTC_REG(reg) { reg, #reg } | |
94 | static const struct { | |
95 | u32 reg; | |
96 | const char *name; | |
97 | } crtc_regs[] = { | |
98 | CRTC_REG(PV_CONTROL), | |
99 | CRTC_REG(PV_V_CONTROL), | |
c31806fb | 100 | CRTC_REG(PV_VSYNCD_EVEN), |
c8b75bca EA |
101 | CRTC_REG(PV_HORZA), |
102 | CRTC_REG(PV_HORZB), | |
103 | CRTC_REG(PV_VERTA), | |
104 | CRTC_REG(PV_VERTB), | |
105 | CRTC_REG(PV_VERTA_EVEN), | |
106 | CRTC_REG(PV_VERTB_EVEN), | |
107 | CRTC_REG(PV_INTEN), | |
108 | CRTC_REG(PV_INTSTAT), | |
109 | CRTC_REG(PV_STAT), | |
110 | CRTC_REG(PV_HACT_ACT), | |
111 | }; | |
112 | ||
113 | static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) | |
114 | { | |
115 | int i; | |
116 | ||
117 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
118 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
119 | crtc_regs[i].reg, crtc_regs[i].name, | |
120 | CRTC_READ(crtc_regs[i].reg)); | |
121 | } | |
122 | } | |
123 | ||
124 | #ifdef CONFIG_DEBUG_FS | |
125 | int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) | |
126 | { | |
127 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
128 | struct drm_device *dev = node->minor->dev; | |
129 | int crtc_index = (uintptr_t)node->info_ent->data; | |
130 | struct drm_crtc *crtc; | |
131 | struct vc4_crtc *vc4_crtc; | |
132 | int i; | |
133 | ||
134 | i = 0; | |
135 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
136 | if (i == crtc_index) | |
137 | break; | |
138 | i++; | |
139 | } | |
140 | if (!crtc) | |
141 | return 0; | |
142 | vc4_crtc = to_vc4_crtc(crtc); | |
143 | ||
144 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
145 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
146 | crtc_regs[i].name, crtc_regs[i].reg, | |
147 | CRTC_READ(crtc_regs[i].reg)); | |
148 | } | |
149 | ||
150 | return 0; | |
151 | } | |
152 | #endif | |
153 | ||
1bf6ad62 DV |
154 | bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, |
155 | bool in_vblank_irq, int *vpos, int *hpos, | |
156 | ktime_t *stime, ktime_t *etime, | |
157 | const struct drm_display_mode *mode) | |
1bf59f1d MK |
158 | { |
159 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
c77b9abf SG |
160 | struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id); |
161 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
1bf59f1d MK |
162 | u32 val; |
163 | int fifo_lines; | |
164 | int vblank_lines; | |
1bf6ad62 | 165 | bool ret = false; |
1bf59f1d | 166 | |
1bf59f1d MK |
167 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
168 | ||
169 | /* Get optional system timestamp before query. */ | |
170 | if (stime) | |
171 | *stime = ktime_get(); | |
172 | ||
173 | /* | |
174 | * Read vertical scanline which is currently composed for our | |
175 | * pixelvalve by the HVS, and also the scaler status. | |
176 | */ | |
177 | val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel)); | |
178 | ||
179 | /* Get optional system timestamp after query. */ | |
180 | if (etime) | |
181 | *etime = ktime_get(); | |
182 | ||
183 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
184 | ||
185 | /* Vertical position of hvs composed scanline. */ | |
186 | *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); | |
e538092c MK |
187 | *hpos = 0; |
188 | ||
189 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
190 | *vpos /= 2; | |
1bf59f1d | 191 | |
e538092c MK |
192 | /* Use hpos to correct for field offset in interlaced mode. */ |
193 | if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) | |
194 | *hpos += mode->crtc_htotal / 2; | |
195 | } | |
1bf59f1d MK |
196 | |
197 | /* This is the offset we need for translating hvs -> pv scanout pos. */ | |
198 | fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay; | |
199 | ||
200 | if (fifo_lines > 0) | |
1bf6ad62 | 201 | ret = true; |
1bf59f1d MK |
202 | |
203 | /* HVS more than fifo_lines into frame for compositing? */ | |
204 | if (*vpos > fifo_lines) { | |
205 | /* | |
206 | * We are in active scanout and can get some meaningful results | |
207 | * from HVS. The actual PV scanout can not trail behind more | |
208 | * than fifo_lines as that is the fifo's capacity. Assume that | |
209 | * in active scanout the HVS and PV work in lockstep wrt. HVS | |
210 | * refilling the fifo and PV consuming from the fifo, ie. | |
211 | * whenever the PV consumes and frees up a scanline in the | |
212 | * fifo, the HVS will immediately refill it, therefore | |
213 | * incrementing vpos. Therefore we choose HVS read position - | |
214 | * fifo size in scanlines as a estimate of the real scanout | |
215 | * position of the PV. | |
216 | */ | |
217 | *vpos -= fifo_lines + 1; | |
1bf59f1d | 218 | |
1bf59f1d MK |
219 | return ret; |
220 | } | |
221 | ||
222 | /* | |
223 | * Less: This happens when we are in vblank and the HVS, after getting | |
224 | * the VSTART restart signal from the PV, just started refilling its | |
225 | * fifo with new lines from the top-most lines of the new framebuffers. | |
226 | * The PV does not scan out in vblank, so does not remove lines from | |
227 | * the fifo, so the fifo will be full quickly and the HVS has to pause. | |
228 | * We can't get meaningful readings wrt. scanline position of the PV | |
229 | * and need to make things up in a approximative but consistent way. | |
230 | */ | |
682e62c4 | 231 | vblank_lines = mode->vtotal - mode->vdisplay; |
1bf59f1d | 232 | |
1bf6ad62 | 233 | if (in_vblank_irq) { |
1bf59f1d MK |
234 | /* |
235 | * Assume the irq handler got called close to first | |
236 | * line of vblank, so PV has about a full vblank | |
237 | * scanlines to go, and as a base timestamp use the | |
238 | * one taken at entry into vblank irq handler, so it | |
239 | * is not affected by random delays due to lock | |
240 | * contention on event_lock or vblank_time lock in | |
241 | * the core. | |
242 | */ | |
243 | *vpos = -vblank_lines; | |
244 | ||
245 | if (stime) | |
246 | *stime = vc4_crtc->t_vblank; | |
247 | if (etime) | |
248 | *etime = vc4_crtc->t_vblank; | |
249 | ||
250 | /* | |
251 | * If the HVS fifo is not yet full then we know for certain | |
252 | * we are at the very beginning of vblank, as the hvs just | |
253 | * started refilling, and the stime and etime timestamps | |
254 | * truly correspond to start of vblank. | |
1bf6ad62 DV |
255 | * |
256 | * Unfortunately there's no way to report this to upper levels | |
257 | * and make it more useful. | |
1bf59f1d | 258 | */ |
1bf59f1d MK |
259 | } else { |
260 | /* | |
261 | * No clue where we are inside vblank. Return a vpos of zero, | |
262 | * which will cause calling code to just return the etime | |
263 | * timestamp uncorrected. At least this is no worse than the | |
264 | * standard fallback. | |
265 | */ | |
266 | *vpos = 0; | |
267 | } | |
268 | ||
269 | return ret; | |
270 | } | |
271 | ||
c8b75bca EA |
272 | static void vc4_crtc_destroy(struct drm_crtc *crtc) |
273 | { | |
274 | drm_crtc_cleanup(crtc); | |
275 | } | |
276 | ||
e582b6c7 EA |
277 | static void |
278 | vc4_crtc_lut_load(struct drm_crtc *crtc) | |
279 | { | |
280 | struct drm_device *dev = crtc->dev; | |
281 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
282 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
283 | u32 i; | |
284 | ||
285 | /* The LUT memory is laid out with each HVS channel in order, | |
286 | * each of which takes 256 writes for R, 256 for G, then 256 | |
287 | * for B. | |
288 | */ | |
289 | HVS_WRITE(SCALER_GAMADDR, | |
290 | SCALER_GAMADDR_AUTOINC | | |
291 | (vc4_crtc->channel * 3 * crtc->gamma_size)); | |
292 | ||
293 | for (i = 0; i < crtc->gamma_size; i++) | |
294 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); | |
295 | for (i = 0; i < crtc->gamma_size; i++) | |
296 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); | |
297 | for (i = 0; i < crtc->gamma_size; i++) | |
298 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); | |
299 | } | |
300 | ||
7ea77283 | 301 | static int |
e582b6c7 | 302 | vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
6d124ff8 DV |
303 | uint32_t size, |
304 | struct drm_modeset_acquire_ctx *ctx) | |
e582b6c7 EA |
305 | { |
306 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
307 | u32 i; | |
308 | ||
7ea77283 | 309 | for (i = 0; i < size; i++) { |
e582b6c7 EA |
310 | vc4_crtc->lut_r[i] = r[i] >> 8; |
311 | vc4_crtc->lut_g[i] = g[i] >> 8; | |
312 | vc4_crtc->lut_b[i] = b[i] >> 8; | |
313 | } | |
314 | ||
315 | vc4_crtc_lut_load(crtc); | |
7ea77283 ML |
316 | |
317 | return 0; | |
e582b6c7 EA |
318 | } |
319 | ||
c8b75bca EA |
320 | static u32 vc4_get_fifo_full_level(u32 format) |
321 | { | |
322 | static const u32 fifo_len_bytes = 64; | |
323 | static const u32 hvs_latency_pix = 6; | |
324 | ||
325 | switch (format) { | |
326 | case PV_CONTROL_FORMAT_DSIV_16: | |
327 | case PV_CONTROL_FORMAT_DSIC_16: | |
328 | return fifo_len_bytes - 2 * hvs_latency_pix; | |
329 | case PV_CONTROL_FORMAT_DSIV_18: | |
330 | return fifo_len_bytes - 14; | |
331 | case PV_CONTROL_FORMAT_24: | |
332 | case PV_CONTROL_FORMAT_DSIV_24: | |
333 | default: | |
334 | return fifo_len_bytes - 3 * hvs_latency_pix; | |
335 | } | |
336 | } | |
337 | ||
338 | /* | |
a86773d1 EA |
339 | * Returns the encoder attached to the CRTC. |
340 | * | |
341 | * VC4 can only scan out to one encoder at a time, while the DRM core | |
342 | * allows drivers to push pixels to more than one encoder from the | |
343 | * same CRTC. | |
c8b75bca | 344 | */ |
a86773d1 | 345 | static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) |
c8b75bca EA |
346 | { |
347 | struct drm_connector *connector; | |
4894bf71 | 348 | struct drm_connector_list_iter conn_iter; |
c8b75bca | 349 | |
4894bf71 GP |
350 | drm_connector_list_iter_begin(crtc->dev, &conn_iter); |
351 | drm_for_each_connector_iter(connector, &conn_iter) { | |
2fa8e904 | 352 | if (connector->state->crtc == crtc) { |
4894bf71 | 353 | drm_connector_list_iter_end(&conn_iter); |
a86773d1 | 354 | return connector->encoder; |
c8b75bca EA |
355 | } |
356 | } | |
4894bf71 | 357 | drm_connector_list_iter_end(&conn_iter); |
c8b75bca | 358 | |
a86773d1 | 359 | return NULL; |
c8b75bca EA |
360 | } |
361 | ||
362 | static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
363 | { | |
6a609209 EA |
364 | struct drm_device *dev = crtc->dev; |
365 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
a86773d1 EA |
366 | struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); |
367 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
c8b75bca EA |
368 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
369 | struct drm_crtc_state *state = crtc->state; | |
370 | struct drm_display_mode *mode = &state->adjusted_mode; | |
371 | bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
dfccd937 | 372 | u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; |
a86773d1 EA |
373 | bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || |
374 | vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); | |
375 | u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; | |
c8b75bca | 376 | bool debug_dump_regs = false; |
c8b75bca EA |
377 | |
378 | if (debug_dump_regs) { | |
379 | DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); | |
380 | vc4_crtc_dump_regs(vc4_crtc); | |
381 | } | |
382 | ||
383 | /* Reset the PV fifo. */ | |
384 | CRTC_WRITE(PV_CONTROL, 0); | |
385 | CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); | |
386 | CRTC_WRITE(PV_CONTROL, 0); | |
387 | ||
388 | CRTC_WRITE(PV_HORZA, | |
dfccd937 EA |
389 | VC4_SET_FIELD((mode->htotal - |
390 | mode->hsync_end) * pixel_rep, | |
c8b75bca | 391 | PV_HORZA_HBP) | |
dfccd937 EA |
392 | VC4_SET_FIELD((mode->hsync_end - |
393 | mode->hsync_start) * pixel_rep, | |
c8b75bca EA |
394 | PV_HORZA_HSYNC)); |
395 | CRTC_WRITE(PV_HORZB, | |
dfccd937 EA |
396 | VC4_SET_FIELD((mode->hsync_start - |
397 | mode->hdisplay) * pixel_rep, | |
c8b75bca | 398 | PV_HORZB_HFP) | |
dfccd937 | 399 | VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); |
c8b75bca | 400 | |
a7c5047d | 401 | CRTC_WRITE(PV_VERTA, |
682e62c4 | 402 | VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, |
a7c5047d | 403 | PV_VERTA_VBP) | |
682e62c4 | 404 | VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, |
a7c5047d EA |
405 | PV_VERTA_VSYNC)); |
406 | CRTC_WRITE(PV_VERTB, | |
682e62c4 | 407 | VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, |
a7c5047d | 408 | PV_VERTB_VFP) | |
682e62c4 | 409 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
a7c5047d | 410 | |
c8b75bca EA |
411 | if (interlace) { |
412 | CRTC_WRITE(PV_VERTA_EVEN, | |
682e62c4 EA |
413 | VC4_SET_FIELD(mode->crtc_vtotal - |
414 | mode->crtc_vsync_end - 1, | |
c8b75bca | 415 | PV_VERTA_VBP) | |
682e62c4 EA |
416 | VC4_SET_FIELD(mode->crtc_vsync_end - |
417 | mode->crtc_vsync_start, | |
c8b75bca EA |
418 | PV_VERTA_VSYNC)); |
419 | CRTC_WRITE(PV_VERTB_EVEN, | |
682e62c4 EA |
420 | VC4_SET_FIELD(mode->crtc_vsync_start - |
421 | mode->crtc_vdisplay, | |
c8b75bca | 422 | PV_VERTB_VFP) | |
682e62c4 EA |
423 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
424 | ||
425 | /* We set up first field even mode for HDMI. VEC's | |
426 | * NTSC mode would want first field odd instead, once | |
427 | * we support it (to do so, set ODD_FIRST and put the | |
428 | * delay in VSYNCD_EVEN instead). | |
429 | */ | |
430 | CRTC_WRITE(PV_V_CONTROL, | |
431 | PV_VCONTROL_CONTINUOUS | | |
a86773d1 | 432 | (is_dsi ? PV_VCONTROL_DSI : 0) | |
682e62c4 | 433 | PV_VCONTROL_INTERLACE | |
dfccd937 | 434 | VC4_SET_FIELD(mode->htotal * pixel_rep / 2, |
682e62c4 EA |
435 | PV_VCONTROL_ODD_DELAY)); |
436 | CRTC_WRITE(PV_VSYNCD_EVEN, 0); | |
437 | } else { | |
a86773d1 EA |
438 | CRTC_WRITE(PV_V_CONTROL, |
439 | PV_VCONTROL_CONTINUOUS | | |
440 | (is_dsi ? PV_VCONTROL_DSI : 0)); | |
c8b75bca EA |
441 | } |
442 | ||
dfccd937 | 443 | CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); |
c8b75bca | 444 | |
c8b75bca EA |
445 | CRTC_WRITE(PV_CONTROL, |
446 | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | | |
447 | VC4_SET_FIELD(vc4_get_fifo_full_level(format), | |
448 | PV_CONTROL_FIFO_LEVEL) | | |
dfccd937 | 449 | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | |
c8b75bca EA |
450 | PV_CONTROL_CLR_AT_START | |
451 | PV_CONTROL_TRIGGER_UNDERFLOW | | |
452 | PV_CONTROL_WAIT_HSTART | | |
a86773d1 EA |
453 | VC4_SET_FIELD(vc4_encoder->clock_select, |
454 | PV_CONTROL_CLK_SELECT) | | |
c8b75bca EA |
455 | PV_CONTROL_FIFO_CLR | |
456 | PV_CONTROL_EN); | |
457 | ||
6a609209 EA |
458 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), |
459 | SCALER_DISPBKGND_AUTOHS | | |
e582b6c7 | 460 | SCALER_DISPBKGND_GAMMA | |
6a609209 EA |
461 | (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); |
462 | ||
e582b6c7 EA |
463 | /* Reload the LUT, since the SRAMs would have been disabled if |
464 | * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. | |
465 | */ | |
466 | vc4_crtc_lut_load(crtc); | |
467 | ||
c8b75bca EA |
468 | if (debug_dump_regs) { |
469 | DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); | |
470 | vc4_crtc_dump_regs(vc4_crtc); | |
471 | } | |
472 | } | |
473 | ||
474 | static void require_hvs_enabled(struct drm_device *dev) | |
475 | { | |
476 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
477 | ||
478 | WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != | |
479 | SCALER_DISPCTRL_ENABLE); | |
480 | } | |
481 | ||
482 | static void vc4_crtc_disable(struct drm_crtc *crtc) | |
483 | { | |
484 | struct drm_device *dev = crtc->dev; | |
485 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
486 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
487 | u32 chan = vc4_crtc->channel; | |
488 | int ret; | |
489 | require_hvs_enabled(dev); | |
490 | ||
e941f05d MK |
491 | /* Disable vblank irq handling before crtc is disabled. */ |
492 | drm_crtc_vblank_off(crtc); | |
493 | ||
c8b75bca EA |
494 | CRTC_WRITE(PV_V_CONTROL, |
495 | CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); | |
496 | ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); | |
497 | WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); | |
498 | ||
499 | if (HVS_READ(SCALER_DISPCTRLX(chan)) & | |
500 | SCALER_DISPCTRLX_ENABLE) { | |
501 | HVS_WRITE(SCALER_DISPCTRLX(chan), | |
502 | SCALER_DISPCTRLX_RESET); | |
503 | ||
504 | /* While the docs say that reset is self-clearing, it | |
505 | * seems it doesn't actually. | |
506 | */ | |
507 | HVS_WRITE(SCALER_DISPCTRLX(chan), 0); | |
508 | } | |
509 | ||
510 | /* Once we leave, the scaler should be disabled and its fifo empty. */ | |
511 | ||
512 | WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); | |
513 | ||
514 | WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), | |
515 | SCALER_DISPSTATX_MODE) != | |
516 | SCALER_DISPSTATX_MODE_DISABLED); | |
517 | ||
518 | WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & | |
519 | (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != | |
520 | SCALER_DISPSTATX_EMPTY); | |
edeb729f BB |
521 | |
522 | /* | |
523 | * Make sure we issue a vblank event after disabling the CRTC if | |
524 | * someone was waiting it. | |
525 | */ | |
526 | if (crtc->state->event) { | |
527 | unsigned long flags; | |
528 | ||
529 | spin_lock_irqsave(&dev->event_lock, flags); | |
530 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
531 | crtc->state->event = NULL; | |
532 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
533 | } | |
c8b75bca EA |
534 | } |
535 | ||
536 | static void vc4_crtc_enable(struct drm_crtc *crtc) | |
537 | { | |
538 | struct drm_device *dev = crtc->dev; | |
539 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
540 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
541 | struct drm_crtc_state *state = crtc->state; | |
542 | struct drm_display_mode *mode = &state->adjusted_mode; | |
543 | ||
544 | require_hvs_enabled(dev); | |
545 | ||
546 | /* Turn on the scaler, which will wait for vstart to start | |
547 | * compositing. | |
548 | */ | |
549 | HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), | |
550 | VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | | |
551 | VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | | |
552 | SCALER_DISPCTRLX_ENABLE); | |
553 | ||
554 | /* Turn on the pixel valve, which will emit the vstart signal. */ | |
555 | CRTC_WRITE(PV_V_CONTROL, | |
556 | CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); | |
e941f05d MK |
557 | |
558 | /* Enable vblank irq handling after crtc is started. */ | |
559 | drm_crtc_vblank_on(crtc); | |
c8b75bca EA |
560 | } |
561 | ||
c50a115b JA |
562 | static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, |
563 | const struct drm_display_mode *mode) | |
acc1be1d | 564 | { |
36451467 | 565 | /* Do not allow doublescan modes from user space */ |
c50a115b | 566 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
36451467 MK |
567 | DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", |
568 | crtc->base.id); | |
c50a115b | 569 | return MODE_NO_DBLESCAN; |
36451467 MK |
570 | } |
571 | ||
c50a115b | 572 | return MODE_OK; |
acc1be1d MK |
573 | } |
574 | ||
c8b75bca EA |
575 | static int vc4_crtc_atomic_check(struct drm_crtc *crtc, |
576 | struct drm_crtc_state *state) | |
577 | { | |
d8dbf44f | 578 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); |
c8b75bca EA |
579 | struct drm_device *dev = crtc->dev; |
580 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
581 | struct drm_plane *plane; | |
d8dbf44f | 582 | unsigned long flags; |
2f196b7c | 583 | const struct drm_plane_state *plane_state; |
c8b75bca | 584 | u32 dlist_count = 0; |
d8dbf44f | 585 | int ret; |
c8b75bca EA |
586 | |
587 | /* The pixelvalve can only feed one encoder (and encoders are | |
588 | * 1:1 with connectors.) | |
589 | */ | |
14de6c44 | 590 | if (hweight32(state->connector_mask) > 1) |
c8b75bca EA |
591 | return -EINVAL; |
592 | ||
2f196b7c | 593 | drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) |
c8b75bca | 594 | dlist_count += vc4_plane_dlist_size(plane_state); |
c8b75bca EA |
595 | |
596 | dlist_count++; /* Account for SCALER_CTL0_END. */ | |
597 | ||
d8dbf44f EA |
598 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); |
599 | ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, | |
4e64e553 | 600 | dlist_count); |
d8dbf44f EA |
601 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); |
602 | if (ret) | |
603 | return ret; | |
c8b75bca EA |
604 | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, | |
609 | struct drm_crtc_state *old_state) | |
610 | { | |
611 | struct drm_device *dev = crtc->dev; | |
612 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
613 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
d8dbf44f | 614 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); |
c8b75bca EA |
615 | struct drm_plane *plane; |
616 | bool debug_dump_regs = false; | |
d8dbf44f EA |
617 | u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; |
618 | u32 __iomem *dlist_next = dlist_start; | |
c8b75bca EA |
619 | |
620 | if (debug_dump_regs) { | |
621 | DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); | |
622 | vc4_hvs_dump_state(dev); | |
623 | } | |
624 | ||
d8dbf44f | 625 | /* Copy all the active planes' dlist contents to the hardware dlist. */ |
c8b75bca EA |
626 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
627 | dlist_next += vc4_plane_write_dlist(plane, dlist_next); | |
628 | } | |
629 | ||
d8dbf44f EA |
630 | writel(SCALER_CTL0_END, dlist_next); |
631 | dlist_next++; | |
632 | ||
633 | WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); | |
634 | ||
c8b75bca EA |
635 | if (crtc->state->event) { |
636 | unsigned long flags; | |
637 | ||
638 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
639 | ||
640 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
641 | ||
642 | spin_lock_irqsave(&dev->event_lock, flags); | |
643 | vc4_crtc->event = crtc->state->event; | |
c8b75bca | 644 | crtc->state->event = NULL; |
56d1fe09 MK |
645 | |
646 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
647 | vc4_state->mm.start); | |
648 | ||
649 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
650 | } else { | |
651 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
652 | vc4_state->mm.start); | |
653 | } | |
654 | ||
655 | if (debug_dump_regs) { | |
656 | DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); | |
657 | vc4_hvs_dump_state(dev); | |
c8b75bca EA |
658 | } |
659 | } | |
660 | ||
0d5f46fa | 661 | static int vc4_enable_vblank(struct drm_crtc *crtc) |
c8b75bca | 662 | { |
c77b9abf | 663 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
c8b75bca EA |
664 | |
665 | CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
0d5f46fa | 670 | static void vc4_disable_vblank(struct drm_crtc *crtc) |
c8b75bca | 671 | { |
c77b9abf | 672 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
c8b75bca EA |
673 | |
674 | CRTC_WRITE(PV_INTEN, 0); | |
675 | } | |
676 | ||
677 | static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) | |
678 | { | |
679 | struct drm_crtc *crtc = &vc4_crtc->base; | |
680 | struct drm_device *dev = crtc->dev; | |
56d1fe09 MK |
681 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
682 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); | |
683 | u32 chan = vc4_crtc->channel; | |
c8b75bca EA |
684 | unsigned long flags; |
685 | ||
686 | spin_lock_irqsave(&dev->event_lock, flags); | |
56d1fe09 MK |
687 | if (vc4_crtc->event && |
688 | (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { | |
c8b75bca EA |
689 | drm_crtc_send_vblank_event(crtc, vc4_crtc->event); |
690 | vc4_crtc->event = NULL; | |
ee7c10e1 | 691 | drm_crtc_vblank_put(crtc); |
c8b75bca EA |
692 | } |
693 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
694 | } | |
695 | ||
696 | static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) | |
697 | { | |
698 | struct vc4_crtc *vc4_crtc = data; | |
699 | u32 stat = CRTC_READ(PV_INTSTAT); | |
700 | irqreturn_t ret = IRQ_NONE; | |
701 | ||
702 | if (stat & PV_INT_VFP_START) { | |
1bf59f1d | 703 | vc4_crtc->t_vblank = ktime_get(); |
c8b75bca EA |
704 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); |
705 | drm_crtc_handle_vblank(&vc4_crtc->base); | |
706 | vc4_crtc_handle_page_flip(vc4_crtc); | |
707 | ret = IRQ_HANDLED; | |
708 | } | |
709 | ||
710 | return ret; | |
711 | } | |
712 | ||
b501bacc EA |
713 | struct vc4_async_flip_state { |
714 | struct drm_crtc *crtc; | |
715 | struct drm_framebuffer *fb; | |
716 | struct drm_pending_vblank_event *event; | |
717 | ||
718 | struct vc4_seqno_cb cb; | |
719 | }; | |
720 | ||
721 | /* Called when the V3D execution for the BO being flipped to is done, so that | |
722 | * we can actually update the plane's address to point to it. | |
723 | */ | |
724 | static void | |
725 | vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) | |
726 | { | |
727 | struct vc4_async_flip_state *flip_state = | |
728 | container_of(cb, struct vc4_async_flip_state, cb); | |
729 | struct drm_crtc *crtc = flip_state->crtc; | |
730 | struct drm_device *dev = crtc->dev; | |
731 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
732 | struct drm_plane *plane = crtc->primary; | |
733 | ||
734 | vc4_plane_async_set_fb(plane, flip_state->fb); | |
735 | if (flip_state->event) { | |
736 | unsigned long flags; | |
737 | ||
738 | spin_lock_irqsave(&dev->event_lock, flags); | |
739 | drm_crtc_send_vblank_event(crtc, flip_state->event); | |
740 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
741 | } | |
742 | ||
ee7c10e1 | 743 | drm_crtc_vblank_put(crtc); |
b501bacc EA |
744 | drm_framebuffer_unreference(flip_state->fb); |
745 | kfree(flip_state); | |
746 | ||
747 | up(&vc4->async_modeset); | |
748 | } | |
749 | ||
750 | /* Implements async (non-vblank-synced) page flips. | |
751 | * | |
752 | * The page flip ioctl needs to return immediately, so we grab the | |
753 | * modeset semaphore on the pipe, and queue the address update for | |
754 | * when V3D is done with the BO being flipped to. | |
755 | */ | |
756 | static int vc4_async_page_flip(struct drm_crtc *crtc, | |
757 | struct drm_framebuffer *fb, | |
758 | struct drm_pending_vblank_event *event, | |
759 | uint32_t flags) | |
760 | { | |
761 | struct drm_device *dev = crtc->dev; | |
762 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
763 | struct drm_plane *plane = crtc->primary; | |
764 | int ret = 0; | |
765 | struct vc4_async_flip_state *flip_state; | |
766 | struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); | |
767 | struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); | |
768 | ||
769 | flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); | |
770 | if (!flip_state) | |
771 | return -ENOMEM; | |
772 | ||
773 | drm_framebuffer_reference(fb); | |
774 | flip_state->fb = fb; | |
775 | flip_state->crtc = crtc; | |
776 | flip_state->event = event; | |
777 | ||
778 | /* Make sure all other async modesetes have landed. */ | |
779 | ret = down_interruptible(&vc4->async_modeset); | |
780 | if (ret) { | |
48627eb8 | 781 | drm_framebuffer_unreference(fb); |
b501bacc EA |
782 | kfree(flip_state); |
783 | return ret; | |
784 | } | |
785 | ||
ee7c10e1 MK |
786 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
787 | ||
b501bacc EA |
788 | /* Immediately update the plane's legacy fb pointer, so that later |
789 | * modeset prep sees the state that will be present when the semaphore | |
790 | * is released. | |
791 | */ | |
792 | drm_atomic_set_fb_for_plane(plane->state, fb); | |
793 | plane->fb = fb; | |
794 | ||
795 | vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, | |
796 | vc4_async_page_flip_complete); | |
797 | ||
798 | /* Driver takes ownership of state on successful async commit. */ | |
799 | return 0; | |
800 | } | |
801 | ||
802 | static int vc4_page_flip(struct drm_crtc *crtc, | |
803 | struct drm_framebuffer *fb, | |
804 | struct drm_pending_vblank_event *event, | |
41292b1f DV |
805 | uint32_t flags, |
806 | struct drm_modeset_acquire_ctx *ctx) | |
b501bacc EA |
807 | { |
808 | if (flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
809 | return vc4_async_page_flip(crtc, fb, event, flags); | |
810 | else | |
41292b1f | 811 | return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); |
b501bacc EA |
812 | } |
813 | ||
d8dbf44f EA |
814 | static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) |
815 | { | |
816 | struct vc4_crtc_state *vc4_state; | |
817 | ||
818 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
819 | if (!vc4_state) | |
820 | return NULL; | |
821 | ||
822 | __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); | |
823 | return &vc4_state->base; | |
824 | } | |
825 | ||
826 | static void vc4_crtc_destroy_state(struct drm_crtc *crtc, | |
827 | struct drm_crtc_state *state) | |
828 | { | |
829 | struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); | |
830 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); | |
831 | ||
832 | if (vc4_state->mm.allocated) { | |
833 | unsigned long flags; | |
834 | ||
835 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); | |
836 | drm_mm_remove_node(&vc4_state->mm); | |
837 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
838 | ||
839 | } | |
840 | ||
7622b255 | 841 | drm_atomic_helper_crtc_destroy_state(crtc, state); |
d8dbf44f EA |
842 | } |
843 | ||
6d6e5003 EA |
844 | static void |
845 | vc4_crtc_reset(struct drm_crtc *crtc) | |
846 | { | |
847 | if (crtc->state) | |
848 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
849 | ||
850 | crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL); | |
851 | if (crtc->state) | |
852 | crtc->state->crtc = crtc; | |
853 | } | |
854 | ||
c8b75bca EA |
855 | static const struct drm_crtc_funcs vc4_crtc_funcs = { |
856 | .set_config = drm_atomic_helper_set_config, | |
857 | .destroy = vc4_crtc_destroy, | |
b501bacc | 858 | .page_flip = vc4_page_flip, |
c8b75bca EA |
859 | .set_property = NULL, |
860 | .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ | |
861 | .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ | |
6d6e5003 | 862 | .reset = vc4_crtc_reset, |
d8dbf44f EA |
863 | .atomic_duplicate_state = vc4_crtc_duplicate_state, |
864 | .atomic_destroy_state = vc4_crtc_destroy_state, | |
e582b6c7 | 865 | .gamma_set = vc4_crtc_gamma_set, |
0d5f46fa SG |
866 | .enable_vblank = vc4_enable_vblank, |
867 | .disable_vblank = vc4_disable_vblank, | |
c8b75bca EA |
868 | }; |
869 | ||
870 | static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { | |
871 | .mode_set_nofb = vc4_crtc_mode_set_nofb, | |
872 | .disable = vc4_crtc_disable, | |
873 | .enable = vc4_crtc_enable, | |
c50a115b | 874 | .mode_valid = vc4_crtc_mode_valid, |
c8b75bca EA |
875 | .atomic_check = vc4_crtc_atomic_check, |
876 | .atomic_flush = vc4_crtc_atomic_flush, | |
877 | }; | |
878 | ||
c8b75bca EA |
879 | static const struct vc4_crtc_data pv0_data = { |
880 | .hvs_channel = 0, | |
ab8df60e BB |
881 | .encoder_types = { |
882 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, | |
883 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, | |
884 | }, | |
c8b75bca EA |
885 | }; |
886 | ||
887 | static const struct vc4_crtc_data pv1_data = { | |
888 | .hvs_channel = 2, | |
ab8df60e BB |
889 | .encoder_types = { |
890 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, | |
891 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, | |
892 | }, | |
c8b75bca EA |
893 | }; |
894 | ||
895 | static const struct vc4_crtc_data pv2_data = { | |
896 | .hvs_channel = 1, | |
ab8df60e BB |
897 | .encoder_types = { |
898 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, | |
899 | [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, | |
900 | }, | |
c8b75bca EA |
901 | }; |
902 | ||
903 | static const struct of_device_id vc4_crtc_dt_match[] = { | |
904 | { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, | |
905 | { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, | |
906 | { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, | |
907 | {} | |
908 | }; | |
909 | ||
910 | static void vc4_set_crtc_possible_masks(struct drm_device *drm, | |
911 | struct drm_crtc *crtc) | |
912 | { | |
913 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
ab8df60e BB |
914 | const struct vc4_crtc_data *crtc_data = vc4_crtc->data; |
915 | const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types; | |
c8b75bca EA |
916 | struct drm_encoder *encoder; |
917 | ||
918 | drm_for_each_encoder(encoder, drm) { | |
919 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
ab8df60e BB |
920 | int i; |
921 | ||
922 | for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) { | |
923 | if (vc4_encoder->type == encoder_types[i]) { | |
924 | vc4_encoder->clock_select = i; | |
925 | encoder->possible_crtcs |= drm_crtc_mask(crtc); | |
926 | break; | |
927 | } | |
c8b75bca EA |
928 | } |
929 | } | |
930 | } | |
931 | ||
1bf59f1d MK |
932 | static void |
933 | vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc) | |
934 | { | |
935 | struct drm_device *drm = vc4_crtc->base.dev; | |
936 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
937 | u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel)); | |
938 | /* Top/base are supposed to be 4-pixel aligned, but the | |
939 | * Raspberry Pi firmware fills the low bits (which are | |
940 | * presumably ignored). | |
941 | */ | |
942 | u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; | |
943 | u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; | |
944 | ||
945 | vc4_crtc->cob_size = top - base + 4; | |
946 | } | |
947 | ||
c8b75bca EA |
948 | static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) |
949 | { | |
950 | struct platform_device *pdev = to_platform_device(dev); | |
951 | struct drm_device *drm = dev_get_drvdata(master); | |
c8b75bca EA |
952 | struct vc4_crtc *vc4_crtc; |
953 | struct drm_crtc *crtc; | |
fc2d6f1e | 954 | struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp; |
c8b75bca | 955 | const struct of_device_id *match; |
fc2d6f1e | 956 | int ret, i; |
c8b75bca EA |
957 | |
958 | vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); | |
959 | if (!vc4_crtc) | |
960 | return -ENOMEM; | |
961 | crtc = &vc4_crtc->base; | |
962 | ||
963 | match = of_match_device(vc4_crtc_dt_match, dev); | |
964 | if (!match) | |
965 | return -ENODEV; | |
966 | vc4_crtc->data = match->data; | |
967 | ||
968 | vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); | |
969 | if (IS_ERR(vc4_crtc->regs)) | |
970 | return PTR_ERR(vc4_crtc->regs); | |
971 | ||
972 | /* For now, we create just the primary and the legacy cursor | |
973 | * planes. We should be able to stack more planes on easily, | |
974 | * but to do that we would need to compute the bandwidth | |
975 | * requirement of the plane configuration, and reject ones | |
976 | * that will take too much. | |
977 | */ | |
978 | primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); | |
79513237 | 979 | if (IS_ERR(primary_plane)) { |
c8b75bca EA |
980 | dev_err(dev, "failed to construct primary plane\n"); |
981 | ret = PTR_ERR(primary_plane); | |
982 | goto err; | |
983 | } | |
984 | ||
fc2d6f1e | 985 | drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, |
f9882876 | 986 | &vc4_crtc_funcs, NULL); |
c8b75bca EA |
987 | drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); |
988 | primary_plane->crtc = crtc; | |
c8b75bca | 989 | vc4_crtc->channel = vc4_crtc->data->hvs_channel; |
e582b6c7 | 990 | drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); |
c8b75bca | 991 | |
fc2d6f1e EA |
992 | /* Set up some arbitrary number of planes. We're not limited |
993 | * by a set number of physical registers, just the space in | |
994 | * the HVS (16k) and how small an plane can be (28 bytes). | |
995 | * However, each plane we set up takes up some memory, and | |
996 | * increases the cost of looping over planes, which atomic | |
997 | * modesetting does quite a bit. As a result, we pick a | |
998 | * modest number of planes to expose, that should hopefully | |
999 | * still cover any sane usecase. | |
1000 | */ | |
1001 | for (i = 0; i < 8; i++) { | |
1002 | struct drm_plane *plane = | |
1003 | vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); | |
1004 | ||
1005 | if (IS_ERR(plane)) | |
1006 | continue; | |
1007 | ||
1008 | plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1009 | } | |
1010 | ||
1011 | /* Set up the legacy cursor after overlay initialization, | |
1012 | * since we overlay planes on the CRTC in the order they were | |
1013 | * initialized. | |
1014 | */ | |
1015 | cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); | |
1016 | if (!IS_ERR(cursor_plane)) { | |
1017 | cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1018 | cursor_plane->crtc = crtc; | |
1019 | crtc->cursor = cursor_plane; | |
1020 | } | |
1021 | ||
1bf59f1d MK |
1022 | vc4_crtc_get_cob_allocation(vc4_crtc); |
1023 | ||
c8b75bca EA |
1024 | CRTC_WRITE(PV_INTEN, 0); |
1025 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); | |
1026 | ret = devm_request_irq(dev, platform_get_irq(pdev, 0), | |
1027 | vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); | |
1028 | if (ret) | |
fc2d6f1e | 1029 | goto err_destroy_planes; |
c8b75bca EA |
1030 | |
1031 | vc4_set_crtc_possible_masks(drm, crtc); | |
1032 | ||
e582b6c7 EA |
1033 | for (i = 0; i < crtc->gamma_size; i++) { |
1034 | vc4_crtc->lut_r[i] = i; | |
1035 | vc4_crtc->lut_g[i] = i; | |
1036 | vc4_crtc->lut_b[i] = i; | |
1037 | } | |
1038 | ||
c8b75bca EA |
1039 | platform_set_drvdata(pdev, vc4_crtc); |
1040 | ||
1041 | return 0; | |
1042 | ||
fc2d6f1e EA |
1043 | err_destroy_planes: |
1044 | list_for_each_entry_safe(destroy_plane, temp, | |
1045 | &drm->mode_config.plane_list, head) { | |
1046 | if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc)) | |
1047 | destroy_plane->funcs->destroy(destroy_plane); | |
1048 | } | |
c8b75bca EA |
1049 | err: |
1050 | return ret; | |
1051 | } | |
1052 | ||
1053 | static void vc4_crtc_unbind(struct device *dev, struct device *master, | |
1054 | void *data) | |
1055 | { | |
1056 | struct platform_device *pdev = to_platform_device(dev); | |
1057 | struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); | |
1058 | ||
1059 | vc4_crtc_destroy(&vc4_crtc->base); | |
1060 | ||
1061 | CRTC_WRITE(PV_INTEN, 0); | |
1062 | ||
1063 | platform_set_drvdata(pdev, NULL); | |
1064 | } | |
1065 | ||
1066 | static const struct component_ops vc4_crtc_ops = { | |
1067 | .bind = vc4_crtc_bind, | |
1068 | .unbind = vc4_crtc_unbind, | |
1069 | }; | |
1070 | ||
1071 | static int vc4_crtc_dev_probe(struct platform_device *pdev) | |
1072 | { | |
1073 | return component_add(&pdev->dev, &vc4_crtc_ops); | |
1074 | } | |
1075 | ||
1076 | static int vc4_crtc_dev_remove(struct platform_device *pdev) | |
1077 | { | |
1078 | component_del(&pdev->dev, &vc4_crtc_ops); | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | struct platform_driver vc4_crtc_driver = { | |
1083 | .probe = vc4_crtc_dev_probe, | |
1084 | .remove = vc4_crtc_dev_remove, | |
1085 | .driver = { | |
1086 | .name = "vc4_crtc", | |
1087 | .of_match_table = vc4_crtc_dt_match, | |
1088 | }, | |
1089 | }; |