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Commit | Line | Data |
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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 CRTC module | |
11 | * | |
12 | * In VC4, the Pixel Valve is what most closely corresponds to the | |
13 | * DRM's concept of a CRTC. The PV generates video timings from the | |
f6c01530 | 14 | * encoder's clock plus its configuration. It pulls scaled pixels from |
c8b75bca EA |
15 | * the HVS at that timing, and feeds it to the encoder. |
16 | * | |
17 | * However, the DRM CRTC also collects the configuration of all the | |
f6c01530 EA |
18 | * DRM planes attached to it. As a result, the CRTC is also |
19 | * responsible for writing the display list for the HVS channel that | |
20 | * the CRTC will use. | |
c8b75bca EA |
21 | * |
22 | * The 2835 has 3 different pixel valves. pv0 in the audio power | |
23 | * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the | |
24 | * image domain can feed either HDMI or the SDTV controller. The | |
25 | * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for | |
26 | * SDTV, etc.) according to which output type is chosen in the mux. | |
27 | * | |
28 | * For power management, the pixel valve's registers are all clocked | |
29 | * by the AXI clock, while the timings and FIFOs make use of the | |
30 | * output-specific clock. Since the encoders also directly consume | |
31 | * the CPRMAN clocks, and know what timings they need, they are the | |
32 | * ones that set the clock. | |
33 | */ | |
34 | ||
b7e8e25b MY |
35 | #include <drm/drm_atomic.h> |
36 | #include <drm/drm_atomic_helper.h> | |
37 | #include <drm/drm_crtc_helper.h> | |
38 | #include <linux/clk.h> | |
39 | #include <drm/drm_fb_cma_helper.h> | |
40 | #include <linux/component.h> | |
41 | #include <linux/of_device.h> | |
c8b75bca EA |
42 | #include "vc4_drv.h" |
43 | #include "vc4_regs.h" | |
44 | ||
d8dbf44f EA |
45 | struct vc4_crtc_state { |
46 | struct drm_crtc_state base; | |
47 | /* Dlist area for this CRTC configuration. */ | |
48 | struct drm_mm_node mm; | |
49 | }; | |
50 | ||
d8dbf44f EA |
51 | static inline struct vc4_crtc_state * |
52 | to_vc4_crtc_state(struct drm_crtc_state *crtc_state) | |
53 | { | |
54 | return (struct vc4_crtc_state *)crtc_state; | |
55 | } | |
56 | ||
c8b75bca EA |
57 | #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) |
58 | #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) | |
59 | ||
60 | #define CRTC_REG(reg) { reg, #reg } | |
61 | static const struct { | |
62 | u32 reg; | |
63 | const char *name; | |
64 | } crtc_regs[] = { | |
65 | CRTC_REG(PV_CONTROL), | |
66 | CRTC_REG(PV_V_CONTROL), | |
c31806fb | 67 | CRTC_REG(PV_VSYNCD_EVEN), |
c8b75bca EA |
68 | CRTC_REG(PV_HORZA), |
69 | CRTC_REG(PV_HORZB), | |
70 | CRTC_REG(PV_VERTA), | |
71 | CRTC_REG(PV_VERTB), | |
72 | CRTC_REG(PV_VERTA_EVEN), | |
73 | CRTC_REG(PV_VERTB_EVEN), | |
74 | CRTC_REG(PV_INTEN), | |
75 | CRTC_REG(PV_INTSTAT), | |
76 | CRTC_REG(PV_STAT), | |
77 | CRTC_REG(PV_HACT_ACT), | |
78 | }; | |
79 | ||
80 | static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) | |
81 | { | |
82 | int i; | |
83 | ||
84 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
85 | DRM_INFO("0x%04x (%s): 0x%08x\n", | |
86 | crtc_regs[i].reg, crtc_regs[i].name, | |
87 | CRTC_READ(crtc_regs[i].reg)); | |
88 | } | |
89 | } | |
90 | ||
91 | #ifdef CONFIG_DEBUG_FS | |
92 | int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) | |
93 | { | |
94 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
95 | struct drm_device *dev = node->minor->dev; | |
96 | int crtc_index = (uintptr_t)node->info_ent->data; | |
97 | struct drm_crtc *crtc; | |
98 | struct vc4_crtc *vc4_crtc; | |
99 | int i; | |
100 | ||
101 | i = 0; | |
102 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
103 | if (i == crtc_index) | |
104 | break; | |
105 | i++; | |
106 | } | |
107 | if (!crtc) | |
108 | return 0; | |
109 | vc4_crtc = to_vc4_crtc(crtc); | |
110 | ||
111 | for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { | |
112 | seq_printf(m, "%s (0x%04x): 0x%08x\n", | |
113 | crtc_regs[i].name, crtc_regs[i].reg, | |
114 | CRTC_READ(crtc_regs[i].reg)); | |
115 | } | |
116 | ||
117 | return 0; | |
118 | } | |
119 | #endif | |
120 | ||
1bf6ad62 DV |
121 | bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, |
122 | bool in_vblank_irq, int *vpos, int *hpos, | |
123 | ktime_t *stime, ktime_t *etime, | |
124 | const struct drm_display_mode *mode) | |
1bf59f1d MK |
125 | { |
126 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
c77b9abf SG |
127 | struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id); |
128 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
1bf59f1d MK |
129 | u32 val; |
130 | int fifo_lines; | |
131 | int vblank_lines; | |
1bf6ad62 | 132 | bool ret = false; |
1bf59f1d | 133 | |
1bf59f1d MK |
134 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
135 | ||
136 | /* Get optional system timestamp before query. */ | |
137 | if (stime) | |
138 | *stime = ktime_get(); | |
139 | ||
140 | /* | |
141 | * Read vertical scanline which is currently composed for our | |
142 | * pixelvalve by the HVS, and also the scaler status. | |
143 | */ | |
144 | val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel)); | |
145 | ||
146 | /* Get optional system timestamp after query. */ | |
147 | if (etime) | |
148 | *etime = ktime_get(); | |
149 | ||
150 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
151 | ||
152 | /* Vertical position of hvs composed scanline. */ | |
153 | *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); | |
e538092c MK |
154 | *hpos = 0; |
155 | ||
156 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
157 | *vpos /= 2; | |
1bf59f1d | 158 | |
e538092c MK |
159 | /* Use hpos to correct for field offset in interlaced mode. */ |
160 | if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) | |
161 | *hpos += mode->crtc_htotal / 2; | |
162 | } | |
1bf59f1d MK |
163 | |
164 | /* This is the offset we need for translating hvs -> pv scanout pos. */ | |
165 | fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay; | |
166 | ||
167 | if (fifo_lines > 0) | |
1bf6ad62 | 168 | ret = true; |
1bf59f1d MK |
169 | |
170 | /* HVS more than fifo_lines into frame for compositing? */ | |
171 | if (*vpos > fifo_lines) { | |
172 | /* | |
173 | * We are in active scanout and can get some meaningful results | |
174 | * from HVS. The actual PV scanout can not trail behind more | |
175 | * than fifo_lines as that is the fifo's capacity. Assume that | |
176 | * in active scanout the HVS and PV work in lockstep wrt. HVS | |
177 | * refilling the fifo and PV consuming from the fifo, ie. | |
178 | * whenever the PV consumes and frees up a scanline in the | |
179 | * fifo, the HVS will immediately refill it, therefore | |
180 | * incrementing vpos. Therefore we choose HVS read position - | |
181 | * fifo size in scanlines as a estimate of the real scanout | |
182 | * position of the PV. | |
183 | */ | |
184 | *vpos -= fifo_lines + 1; | |
1bf59f1d | 185 | |
1bf59f1d MK |
186 | return ret; |
187 | } | |
188 | ||
189 | /* | |
190 | * Less: This happens when we are in vblank and the HVS, after getting | |
191 | * the VSTART restart signal from the PV, just started refilling its | |
192 | * fifo with new lines from the top-most lines of the new framebuffers. | |
193 | * The PV does not scan out in vblank, so does not remove lines from | |
194 | * the fifo, so the fifo will be full quickly and the HVS has to pause. | |
195 | * We can't get meaningful readings wrt. scanline position of the PV | |
196 | * and need to make things up in a approximative but consistent way. | |
197 | */ | |
682e62c4 | 198 | vblank_lines = mode->vtotal - mode->vdisplay; |
1bf59f1d | 199 | |
1bf6ad62 | 200 | if (in_vblank_irq) { |
1bf59f1d MK |
201 | /* |
202 | * Assume the irq handler got called close to first | |
203 | * line of vblank, so PV has about a full vblank | |
204 | * scanlines to go, and as a base timestamp use the | |
205 | * one taken at entry into vblank irq handler, so it | |
206 | * is not affected by random delays due to lock | |
207 | * contention on event_lock or vblank_time lock in | |
208 | * the core. | |
209 | */ | |
210 | *vpos = -vblank_lines; | |
211 | ||
212 | if (stime) | |
213 | *stime = vc4_crtc->t_vblank; | |
214 | if (etime) | |
215 | *etime = vc4_crtc->t_vblank; | |
216 | ||
217 | /* | |
218 | * If the HVS fifo is not yet full then we know for certain | |
219 | * we are at the very beginning of vblank, as the hvs just | |
220 | * started refilling, and the stime and etime timestamps | |
221 | * truly correspond to start of vblank. | |
1bf6ad62 DV |
222 | * |
223 | * Unfortunately there's no way to report this to upper levels | |
224 | * and make it more useful. | |
1bf59f1d | 225 | */ |
1bf59f1d MK |
226 | } else { |
227 | /* | |
228 | * No clue where we are inside vblank. Return a vpos of zero, | |
229 | * which will cause calling code to just return the etime | |
230 | * timestamp uncorrected. At least this is no worse than the | |
231 | * standard fallback. | |
232 | */ | |
233 | *vpos = 0; | |
234 | } | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
c8b75bca EA |
239 | static void vc4_crtc_destroy(struct drm_crtc *crtc) |
240 | { | |
241 | drm_crtc_cleanup(crtc); | |
242 | } | |
243 | ||
e582b6c7 EA |
244 | static void |
245 | vc4_crtc_lut_load(struct drm_crtc *crtc) | |
246 | { | |
247 | struct drm_device *dev = crtc->dev; | |
248 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
249 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
250 | u32 i; | |
251 | ||
252 | /* The LUT memory is laid out with each HVS channel in order, | |
253 | * each of which takes 256 writes for R, 256 for G, then 256 | |
254 | * for B. | |
255 | */ | |
256 | HVS_WRITE(SCALER_GAMADDR, | |
257 | SCALER_GAMADDR_AUTOINC | | |
258 | (vc4_crtc->channel * 3 * crtc->gamma_size)); | |
259 | ||
260 | for (i = 0; i < crtc->gamma_size; i++) | |
261 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); | |
262 | for (i = 0; i < crtc->gamma_size; i++) | |
263 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); | |
264 | for (i = 0; i < crtc->gamma_size; i++) | |
265 | HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); | |
266 | } | |
267 | ||
640e0c79 SS |
268 | static void |
269 | vc4_crtc_update_gamma_lut(struct drm_crtc *crtc) | |
e582b6c7 EA |
270 | { |
271 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
640e0c79 SS |
272 | struct drm_color_lut *lut = crtc->state->gamma_lut->data; |
273 | u32 length = drm_color_lut_size(crtc->state->gamma_lut); | |
e582b6c7 EA |
274 | u32 i; |
275 | ||
640e0c79 SS |
276 | for (i = 0; i < length; i++) { |
277 | vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); | |
278 | vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); | |
279 | vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); | |
e582b6c7 EA |
280 | } |
281 | ||
282 | vc4_crtc_lut_load(crtc); | |
283 | } | |
284 | ||
c8b75bca EA |
285 | static u32 vc4_get_fifo_full_level(u32 format) |
286 | { | |
287 | static const u32 fifo_len_bytes = 64; | |
288 | static const u32 hvs_latency_pix = 6; | |
289 | ||
290 | switch (format) { | |
291 | case PV_CONTROL_FORMAT_DSIV_16: | |
292 | case PV_CONTROL_FORMAT_DSIC_16: | |
293 | return fifo_len_bytes - 2 * hvs_latency_pix; | |
294 | case PV_CONTROL_FORMAT_DSIV_18: | |
295 | return fifo_len_bytes - 14; | |
296 | case PV_CONTROL_FORMAT_24: | |
297 | case PV_CONTROL_FORMAT_DSIV_24: | |
298 | default: | |
299 | return fifo_len_bytes - 3 * hvs_latency_pix; | |
300 | } | |
301 | } | |
302 | ||
303 | /* | |
a86773d1 EA |
304 | * Returns the encoder attached to the CRTC. |
305 | * | |
306 | * VC4 can only scan out to one encoder at a time, while the DRM core | |
307 | * allows drivers to push pixels to more than one encoder from the | |
308 | * same CRTC. | |
c8b75bca | 309 | */ |
a86773d1 | 310 | static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) |
c8b75bca EA |
311 | { |
312 | struct drm_connector *connector; | |
4894bf71 | 313 | struct drm_connector_list_iter conn_iter; |
c8b75bca | 314 | |
4894bf71 GP |
315 | drm_connector_list_iter_begin(crtc->dev, &conn_iter); |
316 | drm_for_each_connector_iter(connector, &conn_iter) { | |
2fa8e904 | 317 | if (connector->state->crtc == crtc) { |
4894bf71 | 318 | drm_connector_list_iter_end(&conn_iter); |
a86773d1 | 319 | return connector->encoder; |
c8b75bca EA |
320 | } |
321 | } | |
4894bf71 | 322 | drm_connector_list_iter_end(&conn_iter); |
c8b75bca | 323 | |
a86773d1 | 324 | return NULL; |
c8b75bca EA |
325 | } |
326 | ||
327 | static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) | |
328 | { | |
6a609209 EA |
329 | struct drm_device *dev = crtc->dev; |
330 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
a86773d1 EA |
331 | struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); |
332 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
c8b75bca EA |
333 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
334 | struct drm_crtc_state *state = crtc->state; | |
335 | struct drm_display_mode *mode = &state->adjusted_mode; | |
336 | bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
dfccd937 | 337 | u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; |
a86773d1 EA |
338 | bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || |
339 | vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); | |
340 | u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; | |
c8b75bca | 341 | bool debug_dump_regs = false; |
c8b75bca EA |
342 | |
343 | if (debug_dump_regs) { | |
344 | DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); | |
345 | vc4_crtc_dump_regs(vc4_crtc); | |
346 | } | |
347 | ||
348 | /* Reset the PV fifo. */ | |
349 | CRTC_WRITE(PV_CONTROL, 0); | |
350 | CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); | |
351 | CRTC_WRITE(PV_CONTROL, 0); | |
352 | ||
353 | CRTC_WRITE(PV_HORZA, | |
dfccd937 EA |
354 | VC4_SET_FIELD((mode->htotal - |
355 | mode->hsync_end) * pixel_rep, | |
c8b75bca | 356 | PV_HORZA_HBP) | |
dfccd937 EA |
357 | VC4_SET_FIELD((mode->hsync_end - |
358 | mode->hsync_start) * pixel_rep, | |
c8b75bca EA |
359 | PV_HORZA_HSYNC)); |
360 | CRTC_WRITE(PV_HORZB, | |
dfccd937 EA |
361 | VC4_SET_FIELD((mode->hsync_start - |
362 | mode->hdisplay) * pixel_rep, | |
c8b75bca | 363 | PV_HORZB_HFP) | |
dfccd937 | 364 | VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); |
c8b75bca | 365 | |
a7c5047d | 366 | CRTC_WRITE(PV_VERTA, |
682e62c4 | 367 | VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, |
a7c5047d | 368 | PV_VERTA_VBP) | |
682e62c4 | 369 | VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, |
a7c5047d EA |
370 | PV_VERTA_VSYNC)); |
371 | CRTC_WRITE(PV_VERTB, | |
682e62c4 | 372 | VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, |
a7c5047d | 373 | PV_VERTB_VFP) | |
682e62c4 | 374 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
a7c5047d | 375 | |
c8b75bca EA |
376 | if (interlace) { |
377 | CRTC_WRITE(PV_VERTA_EVEN, | |
682e62c4 EA |
378 | VC4_SET_FIELD(mode->crtc_vtotal - |
379 | mode->crtc_vsync_end - 1, | |
c8b75bca | 380 | PV_VERTA_VBP) | |
682e62c4 EA |
381 | VC4_SET_FIELD(mode->crtc_vsync_end - |
382 | mode->crtc_vsync_start, | |
c8b75bca EA |
383 | PV_VERTA_VSYNC)); |
384 | CRTC_WRITE(PV_VERTB_EVEN, | |
682e62c4 EA |
385 | VC4_SET_FIELD(mode->crtc_vsync_start - |
386 | mode->crtc_vdisplay, | |
c8b75bca | 387 | PV_VERTB_VFP) | |
682e62c4 EA |
388 | VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); |
389 | ||
390 | /* We set up first field even mode for HDMI. VEC's | |
391 | * NTSC mode would want first field odd instead, once | |
392 | * we support it (to do so, set ODD_FIRST and put the | |
393 | * delay in VSYNCD_EVEN instead). | |
394 | */ | |
395 | CRTC_WRITE(PV_V_CONTROL, | |
396 | PV_VCONTROL_CONTINUOUS | | |
a86773d1 | 397 | (is_dsi ? PV_VCONTROL_DSI : 0) | |
682e62c4 | 398 | PV_VCONTROL_INTERLACE | |
dfccd937 | 399 | VC4_SET_FIELD(mode->htotal * pixel_rep / 2, |
682e62c4 EA |
400 | PV_VCONTROL_ODD_DELAY)); |
401 | CRTC_WRITE(PV_VSYNCD_EVEN, 0); | |
402 | } else { | |
a86773d1 EA |
403 | CRTC_WRITE(PV_V_CONTROL, |
404 | PV_VCONTROL_CONTINUOUS | | |
405 | (is_dsi ? PV_VCONTROL_DSI : 0)); | |
c8b75bca EA |
406 | } |
407 | ||
dfccd937 | 408 | CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); |
c8b75bca | 409 | |
c8b75bca EA |
410 | CRTC_WRITE(PV_CONTROL, |
411 | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | | |
412 | VC4_SET_FIELD(vc4_get_fifo_full_level(format), | |
413 | PV_CONTROL_FIFO_LEVEL) | | |
dfccd937 | 414 | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | |
c8b75bca EA |
415 | PV_CONTROL_CLR_AT_START | |
416 | PV_CONTROL_TRIGGER_UNDERFLOW | | |
417 | PV_CONTROL_WAIT_HSTART | | |
a86773d1 EA |
418 | VC4_SET_FIELD(vc4_encoder->clock_select, |
419 | PV_CONTROL_CLK_SELECT) | | |
c8b75bca EA |
420 | PV_CONTROL_FIFO_CLR | |
421 | PV_CONTROL_EN); | |
422 | ||
6a609209 EA |
423 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), |
424 | SCALER_DISPBKGND_AUTOHS | | |
e582b6c7 | 425 | SCALER_DISPBKGND_GAMMA | |
6a609209 EA |
426 | (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); |
427 | ||
e582b6c7 EA |
428 | /* Reload the LUT, since the SRAMs would have been disabled if |
429 | * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. | |
430 | */ | |
431 | vc4_crtc_lut_load(crtc); | |
432 | ||
c8b75bca EA |
433 | if (debug_dump_regs) { |
434 | DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); | |
435 | vc4_crtc_dump_regs(vc4_crtc); | |
436 | } | |
437 | } | |
438 | ||
439 | static void require_hvs_enabled(struct drm_device *dev) | |
440 | { | |
441 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
442 | ||
443 | WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != | |
444 | SCALER_DISPCTRL_ENABLE); | |
445 | } | |
446 | ||
64581714 LP |
447 | static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, |
448 | struct drm_crtc_state *old_state) | |
c8b75bca EA |
449 | { |
450 | struct drm_device *dev = crtc->dev; | |
451 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
452 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
453 | u32 chan = vc4_crtc->channel; | |
454 | int ret; | |
455 | require_hvs_enabled(dev); | |
456 | ||
e941f05d MK |
457 | /* Disable vblank irq handling before crtc is disabled. */ |
458 | drm_crtc_vblank_off(crtc); | |
459 | ||
c8b75bca EA |
460 | CRTC_WRITE(PV_V_CONTROL, |
461 | CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); | |
462 | ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); | |
463 | WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); | |
464 | ||
465 | if (HVS_READ(SCALER_DISPCTRLX(chan)) & | |
466 | SCALER_DISPCTRLX_ENABLE) { | |
467 | HVS_WRITE(SCALER_DISPCTRLX(chan), | |
468 | SCALER_DISPCTRLX_RESET); | |
469 | ||
470 | /* While the docs say that reset is self-clearing, it | |
471 | * seems it doesn't actually. | |
472 | */ | |
473 | HVS_WRITE(SCALER_DISPCTRLX(chan), 0); | |
474 | } | |
475 | ||
476 | /* Once we leave, the scaler should be disabled and its fifo empty. */ | |
477 | ||
478 | WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); | |
479 | ||
480 | WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), | |
481 | SCALER_DISPSTATX_MODE) != | |
482 | SCALER_DISPSTATX_MODE_DISABLED); | |
483 | ||
484 | WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & | |
485 | (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != | |
486 | SCALER_DISPSTATX_EMPTY); | |
edeb729f BB |
487 | |
488 | /* | |
489 | * Make sure we issue a vblank event after disabling the CRTC if | |
490 | * someone was waiting it. | |
491 | */ | |
492 | if (crtc->state->event) { | |
493 | unsigned long flags; | |
494 | ||
495 | spin_lock_irqsave(&dev->event_lock, flags); | |
496 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
497 | crtc->state->event = NULL; | |
498 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
499 | } | |
c8b75bca EA |
500 | } |
501 | ||
1ed134e6 BB |
502 | static void vc4_crtc_update_dlist(struct drm_crtc *crtc) |
503 | { | |
504 | struct drm_device *dev = crtc->dev; | |
505 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
506 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
507 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); | |
508 | ||
509 | if (crtc->state->event) { | |
510 | unsigned long flags; | |
511 | ||
512 | crtc->state->event->pipe = drm_crtc_index(crtc); | |
513 | ||
514 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); | |
515 | ||
516 | spin_lock_irqsave(&dev->event_lock, flags); | |
517 | vc4_crtc->event = crtc->state->event; | |
518 | crtc->state->event = NULL; | |
519 | ||
520 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
521 | vc4_state->mm.start); | |
522 | ||
523 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
524 | } else { | |
525 | HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), | |
526 | vc4_state->mm.start); | |
527 | } | |
528 | } | |
529 | ||
0b20a0f8 LP |
530 | static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, |
531 | struct drm_crtc_state *old_state) | |
c8b75bca EA |
532 | { |
533 | struct drm_device *dev = crtc->dev; | |
534 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
535 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
536 | struct drm_crtc_state *state = crtc->state; | |
537 | struct drm_display_mode *mode = &state->adjusted_mode; | |
538 | ||
539 | require_hvs_enabled(dev); | |
540 | ||
1ed134e6 BB |
541 | /* Enable vblank irq handling before crtc is started otherwise |
542 | * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). | |
543 | */ | |
544 | drm_crtc_vblank_on(crtc); | |
545 | vc4_crtc_update_dlist(crtc); | |
546 | ||
c8b75bca EA |
547 | /* Turn on the scaler, which will wait for vstart to start |
548 | * compositing. | |
549 | */ | |
550 | HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), | |
551 | VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | | |
552 | VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | | |
553 | SCALER_DISPCTRLX_ENABLE); | |
554 | ||
555 | /* Turn on the pixel valve, which will emit the vstart signal. */ | |
556 | CRTC_WRITE(PV_V_CONTROL, | |
557 | CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); | |
558 | } | |
559 | ||
c50a115b JA |
560 | static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, |
561 | const struct drm_display_mode *mode) | |
acc1be1d | 562 | { |
36451467 | 563 | /* Do not allow doublescan modes from user space */ |
c50a115b | 564 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
36451467 MK |
565 | DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", |
566 | crtc->base.id); | |
c50a115b | 567 | return MODE_NO_DBLESCAN; |
36451467 MK |
568 | } |
569 | ||
c50a115b | 570 | return MODE_OK; |
acc1be1d MK |
571 | } |
572 | ||
c8b75bca EA |
573 | static int vc4_crtc_atomic_check(struct drm_crtc *crtc, |
574 | struct drm_crtc_state *state) | |
575 | { | |
d8dbf44f | 576 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); |
c8b75bca EA |
577 | struct drm_device *dev = crtc->dev; |
578 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
579 | struct drm_plane *plane; | |
d8dbf44f | 580 | unsigned long flags; |
2f196b7c | 581 | const struct drm_plane_state *plane_state; |
c8b75bca | 582 | u32 dlist_count = 0; |
d8dbf44f | 583 | int ret; |
c8b75bca EA |
584 | |
585 | /* The pixelvalve can only feed one encoder (and encoders are | |
586 | * 1:1 with connectors.) | |
587 | */ | |
14de6c44 | 588 | if (hweight32(state->connector_mask) > 1) |
c8b75bca EA |
589 | return -EINVAL; |
590 | ||
2f196b7c | 591 | drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) |
c8b75bca | 592 | dlist_count += vc4_plane_dlist_size(plane_state); |
c8b75bca EA |
593 | |
594 | dlist_count++; /* Account for SCALER_CTL0_END. */ | |
595 | ||
d8dbf44f EA |
596 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); |
597 | ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, | |
4e64e553 | 598 | dlist_count); |
d8dbf44f EA |
599 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); |
600 | if (ret) | |
601 | return ret; | |
c8b75bca EA |
602 | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, | |
607 | struct drm_crtc_state *old_state) | |
608 | { | |
609 | struct drm_device *dev = crtc->dev; | |
610 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
1d49f2e5 | 611 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
d8dbf44f | 612 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); |
c8b75bca | 613 | struct drm_plane *plane; |
1d49f2e5 | 614 | struct vc4_plane_state *vc4_plane_state; |
c8b75bca | 615 | bool debug_dump_regs = false; |
1d49f2e5 | 616 | bool enable_bg_fill = false; |
d8dbf44f EA |
617 | u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; |
618 | u32 __iomem *dlist_next = dlist_start; | |
c8b75bca EA |
619 | |
620 | if (debug_dump_regs) { | |
621 | DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); | |
622 | vc4_hvs_dump_state(dev); | |
623 | } | |
624 | ||
d8dbf44f | 625 | /* Copy all the active planes' dlist contents to the hardware dlist. */ |
c8b75bca | 626 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
1d49f2e5 SS |
627 | /* Is this the first active plane? */ |
628 | if (dlist_next == dlist_start) { | |
629 | /* We need to enable background fill when a plane | |
630 | * could be alpha blending from the background, i.e. | |
631 | * where no other plane is underneath. It suffices to | |
632 | * consider the first active plane here since we set | |
633 | * needs_bg_fill such that either the first plane | |
634 | * already needs it or all planes on top blend from | |
635 | * the first or a lower plane. | |
636 | */ | |
637 | vc4_plane_state = to_vc4_plane_state(plane->state); | |
638 | enable_bg_fill = vc4_plane_state->needs_bg_fill; | |
639 | } | |
640 | ||
c8b75bca EA |
641 | dlist_next += vc4_plane_write_dlist(plane, dlist_next); |
642 | } | |
643 | ||
d8dbf44f EA |
644 | writel(SCALER_CTL0_END, dlist_next); |
645 | dlist_next++; | |
646 | ||
647 | WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); | |
648 | ||
1d49f2e5 SS |
649 | if (enable_bg_fill) |
650 | /* This sets a black background color fill, as is the case | |
651 | * with other DRM drivers. | |
652 | */ | |
653 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), | |
654 | HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) | | |
655 | SCALER_DISPBKGND_FILL); | |
656 | ||
1ed134e6 BB |
657 | /* Only update DISPLIST if the CRTC was already running and is not |
658 | * being disabled. | |
659 | * vc4_crtc_enable() takes care of updating the dlist just after | |
660 | * re-enabling VBLANK interrupts and before enabling the engine. | |
661 | * If the CRTC is being disabled, there's no point in updating this | |
662 | * information. | |
663 | */ | |
664 | if (crtc->state->active && old_state->active) | |
665 | vc4_crtc_update_dlist(crtc); | |
56d1fe09 | 666 | |
640e0c79 SS |
667 | if (crtc->state->color_mgmt_changed) { |
668 | u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)); | |
669 | ||
670 | if (crtc->state->gamma_lut) { | |
671 | vc4_crtc_update_gamma_lut(crtc); | |
672 | dispbkgndx |= SCALER_DISPBKGND_GAMMA; | |
673 | } else { | |
674 | /* Unsetting DISPBKGND_GAMMA skips the gamma lut step | |
675 | * in hardware, which is the same as a linear lut that | |
676 | * DRM expects us to use in absence of a user lut. | |
677 | */ | |
678 | dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; | |
679 | } | |
680 | HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx); | |
681 | } | |
682 | ||
56d1fe09 MK |
683 | if (debug_dump_regs) { |
684 | DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); | |
685 | vc4_hvs_dump_state(dev); | |
c8b75bca EA |
686 | } |
687 | } | |
688 | ||
0d5f46fa | 689 | static int vc4_enable_vblank(struct drm_crtc *crtc) |
c8b75bca | 690 | { |
c77b9abf | 691 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
c8b75bca EA |
692 | |
693 | CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
0d5f46fa | 698 | static void vc4_disable_vblank(struct drm_crtc *crtc) |
c8b75bca | 699 | { |
c77b9abf | 700 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); |
c8b75bca EA |
701 | |
702 | CRTC_WRITE(PV_INTEN, 0); | |
703 | } | |
704 | ||
705 | static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) | |
706 | { | |
707 | struct drm_crtc *crtc = &vc4_crtc->base; | |
708 | struct drm_device *dev = crtc->dev; | |
56d1fe09 MK |
709 | struct vc4_dev *vc4 = to_vc4_dev(dev); |
710 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); | |
711 | u32 chan = vc4_crtc->channel; | |
c8b75bca EA |
712 | unsigned long flags; |
713 | ||
714 | spin_lock_irqsave(&dev->event_lock, flags); | |
56d1fe09 MK |
715 | if (vc4_crtc->event && |
716 | (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { | |
c8b75bca EA |
717 | drm_crtc_send_vblank_event(crtc, vc4_crtc->event); |
718 | vc4_crtc->event = NULL; | |
ee7c10e1 | 719 | drm_crtc_vblank_put(crtc); |
c8b75bca EA |
720 | } |
721 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
722 | } | |
723 | ||
724 | static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) | |
725 | { | |
726 | struct vc4_crtc *vc4_crtc = data; | |
727 | u32 stat = CRTC_READ(PV_INTSTAT); | |
728 | irqreturn_t ret = IRQ_NONE; | |
729 | ||
730 | if (stat & PV_INT_VFP_START) { | |
1bf59f1d | 731 | vc4_crtc->t_vblank = ktime_get(); |
c8b75bca EA |
732 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); |
733 | drm_crtc_handle_vblank(&vc4_crtc->base); | |
734 | vc4_crtc_handle_page_flip(vc4_crtc); | |
735 | ret = IRQ_HANDLED; | |
736 | } | |
737 | ||
738 | return ret; | |
739 | } | |
740 | ||
b501bacc EA |
741 | struct vc4_async_flip_state { |
742 | struct drm_crtc *crtc; | |
743 | struct drm_framebuffer *fb; | |
f7aef1c2 | 744 | struct drm_framebuffer *old_fb; |
b501bacc EA |
745 | struct drm_pending_vblank_event *event; |
746 | ||
747 | struct vc4_seqno_cb cb; | |
748 | }; | |
749 | ||
750 | /* Called when the V3D execution for the BO being flipped to is done, so that | |
751 | * we can actually update the plane's address to point to it. | |
752 | */ | |
753 | static void | |
754 | vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) | |
755 | { | |
756 | struct vc4_async_flip_state *flip_state = | |
757 | container_of(cb, struct vc4_async_flip_state, cb); | |
758 | struct drm_crtc *crtc = flip_state->crtc; | |
759 | struct drm_device *dev = crtc->dev; | |
760 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
761 | struct drm_plane *plane = crtc->primary; | |
762 | ||
763 | vc4_plane_async_set_fb(plane, flip_state->fb); | |
764 | if (flip_state->event) { | |
765 | unsigned long flags; | |
766 | ||
767 | spin_lock_irqsave(&dev->event_lock, flags); | |
768 | drm_crtc_send_vblank_event(crtc, flip_state->event); | |
769 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
770 | } | |
771 | ||
ee7c10e1 | 772 | drm_crtc_vblank_put(crtc); |
1d5494e9 | 773 | drm_framebuffer_put(flip_state->fb); |
f7aef1c2 BB |
774 | |
775 | /* Decrement the BO usecnt in order to keep the inc/dec calls balanced | |
776 | * when the planes are updated through the async update path. | |
777 | * FIXME: we should move to generic async-page-flip when it's | |
778 | * available, so that we can get rid of this hand-made cleanup_fb() | |
779 | * logic. | |
780 | */ | |
781 | if (flip_state->old_fb) { | |
782 | struct drm_gem_cma_object *cma_bo; | |
783 | struct vc4_bo *bo; | |
784 | ||
785 | cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); | |
786 | bo = to_vc4_bo(&cma_bo->base); | |
787 | vc4_bo_dec_usecnt(bo); | |
788 | drm_framebuffer_put(flip_state->old_fb); | |
789 | } | |
790 | ||
b501bacc EA |
791 | kfree(flip_state); |
792 | ||
793 | up(&vc4->async_modeset); | |
794 | } | |
795 | ||
796 | /* Implements async (non-vblank-synced) page flips. | |
797 | * | |
798 | * The page flip ioctl needs to return immediately, so we grab the | |
799 | * modeset semaphore on the pipe, and queue the address update for | |
800 | * when V3D is done with the BO being flipped to. | |
801 | */ | |
802 | static int vc4_async_page_flip(struct drm_crtc *crtc, | |
803 | struct drm_framebuffer *fb, | |
804 | struct drm_pending_vblank_event *event, | |
805 | uint32_t flags) | |
806 | { | |
807 | struct drm_device *dev = crtc->dev; | |
808 | struct vc4_dev *vc4 = to_vc4_dev(dev); | |
809 | struct drm_plane *plane = crtc->primary; | |
810 | int ret = 0; | |
811 | struct vc4_async_flip_state *flip_state; | |
812 | struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); | |
813 | struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); | |
814 | ||
f7aef1c2 BB |
815 | /* Increment the BO usecnt here, so that we never end up with an |
816 | * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the | |
817 | * plane is later updated through the non-async path. | |
818 | * FIXME: we should move to generic async-page-flip when it's | |
819 | * available, so that we can get rid of this hand-made prepare_fb() | |
820 | * logic. | |
821 | */ | |
822 | ret = vc4_bo_inc_usecnt(bo); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
b501bacc | 826 | flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); |
f7aef1c2 BB |
827 | if (!flip_state) { |
828 | vc4_bo_dec_usecnt(bo); | |
b501bacc | 829 | return -ENOMEM; |
f7aef1c2 | 830 | } |
b501bacc | 831 | |
1d5494e9 | 832 | drm_framebuffer_get(fb); |
b501bacc EA |
833 | flip_state->fb = fb; |
834 | flip_state->crtc = crtc; | |
835 | flip_state->event = event; | |
836 | ||
837 | /* Make sure all other async modesetes have landed. */ | |
838 | ret = down_interruptible(&vc4->async_modeset); | |
839 | if (ret) { | |
1d5494e9 | 840 | drm_framebuffer_put(fb); |
f7aef1c2 | 841 | vc4_bo_dec_usecnt(bo); |
b501bacc EA |
842 | kfree(flip_state); |
843 | return ret; | |
844 | } | |
845 | ||
f7aef1c2 BB |
846 | /* Save the current FB before it's replaced by the new one in |
847 | * drm_atomic_set_fb_for_plane(). We'll need the old FB in | |
848 | * vc4_async_page_flip_complete() to decrement the BO usecnt and keep | |
849 | * it consistent. | |
850 | * FIXME: we should move to generic async-page-flip when it's | |
851 | * available, so that we can get rid of this hand-made cleanup_fb() | |
852 | * logic. | |
853 | */ | |
854 | flip_state->old_fb = plane->state->fb; | |
855 | if (flip_state->old_fb) | |
856 | drm_framebuffer_get(flip_state->old_fb); | |
857 | ||
ee7c10e1 MK |
858 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
859 | ||
b501bacc EA |
860 | /* Immediately update the plane's legacy fb pointer, so that later |
861 | * modeset prep sees the state that will be present when the semaphore | |
862 | * is released. | |
863 | */ | |
864 | drm_atomic_set_fb_for_plane(plane->state, fb); | |
865 | plane->fb = fb; | |
866 | ||
867 | vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, | |
868 | vc4_async_page_flip_complete); | |
869 | ||
870 | /* Driver takes ownership of state on successful async commit. */ | |
871 | return 0; | |
872 | } | |
873 | ||
874 | static int vc4_page_flip(struct drm_crtc *crtc, | |
875 | struct drm_framebuffer *fb, | |
876 | struct drm_pending_vblank_event *event, | |
41292b1f DV |
877 | uint32_t flags, |
878 | struct drm_modeset_acquire_ctx *ctx) | |
b501bacc EA |
879 | { |
880 | if (flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
881 | return vc4_async_page_flip(crtc, fb, event, flags); | |
882 | else | |
41292b1f | 883 | return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); |
b501bacc EA |
884 | } |
885 | ||
d8dbf44f EA |
886 | static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) |
887 | { | |
888 | struct vc4_crtc_state *vc4_state; | |
889 | ||
890 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
891 | if (!vc4_state) | |
892 | return NULL; | |
893 | ||
894 | __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); | |
895 | return &vc4_state->base; | |
896 | } | |
897 | ||
898 | static void vc4_crtc_destroy_state(struct drm_crtc *crtc, | |
899 | struct drm_crtc_state *state) | |
900 | { | |
901 | struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); | |
902 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); | |
903 | ||
904 | if (vc4_state->mm.allocated) { | |
905 | unsigned long flags; | |
906 | ||
907 | spin_lock_irqsave(&vc4->hvs->mm_lock, flags); | |
908 | drm_mm_remove_node(&vc4_state->mm); | |
909 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); | |
910 | ||
911 | } | |
912 | ||
7622b255 | 913 | drm_atomic_helper_crtc_destroy_state(crtc, state); |
d8dbf44f EA |
914 | } |
915 | ||
6d6e5003 EA |
916 | static void |
917 | vc4_crtc_reset(struct drm_crtc *crtc) | |
918 | { | |
919 | if (crtc->state) | |
920 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
921 | ||
922 | crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL); | |
923 | if (crtc->state) | |
924 | crtc->state->crtc = crtc; | |
925 | } | |
926 | ||
c8b75bca EA |
927 | static const struct drm_crtc_funcs vc4_crtc_funcs = { |
928 | .set_config = drm_atomic_helper_set_config, | |
929 | .destroy = vc4_crtc_destroy, | |
b501bacc | 930 | .page_flip = vc4_page_flip, |
c8b75bca EA |
931 | .set_property = NULL, |
932 | .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ | |
933 | .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ | |
6d6e5003 | 934 | .reset = vc4_crtc_reset, |
d8dbf44f EA |
935 | .atomic_duplicate_state = vc4_crtc_duplicate_state, |
936 | .atomic_destroy_state = vc4_crtc_destroy_state, | |
640e0c79 | 937 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
0d5f46fa SG |
938 | .enable_vblank = vc4_enable_vblank, |
939 | .disable_vblank = vc4_disable_vblank, | |
c8b75bca EA |
940 | }; |
941 | ||
942 | static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { | |
943 | .mode_set_nofb = vc4_crtc_mode_set_nofb, | |
c50a115b | 944 | .mode_valid = vc4_crtc_mode_valid, |
c8b75bca EA |
945 | .atomic_check = vc4_crtc_atomic_check, |
946 | .atomic_flush = vc4_crtc_atomic_flush, | |
0b20a0f8 | 947 | .atomic_enable = vc4_crtc_atomic_enable, |
64581714 | 948 | .atomic_disable = vc4_crtc_atomic_disable, |
c8b75bca EA |
949 | }; |
950 | ||
c8b75bca EA |
951 | static const struct vc4_crtc_data pv0_data = { |
952 | .hvs_channel = 0, | |
ab8df60e BB |
953 | .encoder_types = { |
954 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, | |
955 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, | |
956 | }, | |
c8b75bca EA |
957 | }; |
958 | ||
959 | static const struct vc4_crtc_data pv1_data = { | |
960 | .hvs_channel = 2, | |
ab8df60e BB |
961 | .encoder_types = { |
962 | [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, | |
963 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, | |
964 | }, | |
c8b75bca EA |
965 | }; |
966 | ||
967 | static const struct vc4_crtc_data pv2_data = { | |
968 | .hvs_channel = 1, | |
ab8df60e BB |
969 | .encoder_types = { |
970 | [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, | |
971 | [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, | |
972 | }, | |
c8b75bca EA |
973 | }; |
974 | ||
975 | static const struct of_device_id vc4_crtc_dt_match[] = { | |
976 | { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, | |
977 | { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, | |
978 | { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, | |
979 | {} | |
980 | }; | |
981 | ||
982 | static void vc4_set_crtc_possible_masks(struct drm_device *drm, | |
983 | struct drm_crtc *crtc) | |
984 | { | |
985 | struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); | |
ab8df60e BB |
986 | const struct vc4_crtc_data *crtc_data = vc4_crtc->data; |
987 | const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types; | |
c8b75bca EA |
988 | struct drm_encoder *encoder; |
989 | ||
990 | drm_for_each_encoder(encoder, drm) { | |
991 | struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); | |
ab8df60e BB |
992 | int i; |
993 | ||
994 | for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) { | |
995 | if (vc4_encoder->type == encoder_types[i]) { | |
996 | vc4_encoder->clock_select = i; | |
997 | encoder->possible_crtcs |= drm_crtc_mask(crtc); | |
998 | break; | |
999 | } | |
c8b75bca EA |
1000 | } |
1001 | } | |
1002 | } | |
1003 | ||
1bf59f1d MK |
1004 | static void |
1005 | vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc) | |
1006 | { | |
1007 | struct drm_device *drm = vc4_crtc->base.dev; | |
1008 | struct vc4_dev *vc4 = to_vc4_dev(drm); | |
1009 | u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel)); | |
1010 | /* Top/base are supposed to be 4-pixel aligned, but the | |
1011 | * Raspberry Pi firmware fills the low bits (which are | |
1012 | * presumably ignored). | |
1013 | */ | |
1014 | u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; | |
1015 | u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; | |
1016 | ||
1017 | vc4_crtc->cob_size = top - base + 4; | |
1018 | } | |
1019 | ||
c8b75bca EA |
1020 | static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) |
1021 | { | |
1022 | struct platform_device *pdev = to_platform_device(dev); | |
1023 | struct drm_device *drm = dev_get_drvdata(master); | |
c8b75bca EA |
1024 | struct vc4_crtc *vc4_crtc; |
1025 | struct drm_crtc *crtc; | |
fc2d6f1e | 1026 | struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp; |
c8b75bca | 1027 | const struct of_device_id *match; |
fc2d6f1e | 1028 | int ret, i; |
c8b75bca EA |
1029 | |
1030 | vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); | |
1031 | if (!vc4_crtc) | |
1032 | return -ENOMEM; | |
1033 | crtc = &vc4_crtc->base; | |
1034 | ||
1035 | match = of_match_device(vc4_crtc_dt_match, dev); | |
1036 | if (!match) | |
1037 | return -ENODEV; | |
1038 | vc4_crtc->data = match->data; | |
1039 | ||
1040 | vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); | |
1041 | if (IS_ERR(vc4_crtc->regs)) | |
1042 | return PTR_ERR(vc4_crtc->regs); | |
1043 | ||
1044 | /* For now, we create just the primary and the legacy cursor | |
1045 | * planes. We should be able to stack more planes on easily, | |
1046 | * but to do that we would need to compute the bandwidth | |
1047 | * requirement of the plane configuration, and reject ones | |
1048 | * that will take too much. | |
1049 | */ | |
1050 | primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); | |
79513237 | 1051 | if (IS_ERR(primary_plane)) { |
c8b75bca EA |
1052 | dev_err(dev, "failed to construct primary plane\n"); |
1053 | ret = PTR_ERR(primary_plane); | |
1054 | goto err; | |
1055 | } | |
1056 | ||
fc2d6f1e | 1057 | drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, |
f9882876 | 1058 | &vc4_crtc_funcs, NULL); |
c8b75bca EA |
1059 | drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); |
1060 | primary_plane->crtc = crtc; | |
c8b75bca | 1061 | vc4_crtc->channel = vc4_crtc->data->hvs_channel; |
e582b6c7 | 1062 | drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); |
640e0c79 | 1063 | drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); |
c8b75bca | 1064 | |
766cc6b1 SS |
1065 | /* We support CTM, but only for one CRTC at a time. It's therefore |
1066 | * implemented as private driver state in vc4_kms, not here. | |
1067 | */ | |
1068 | drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); | |
1069 | ||
fc2d6f1e EA |
1070 | /* Set up some arbitrary number of planes. We're not limited |
1071 | * by a set number of physical registers, just the space in | |
1072 | * the HVS (16k) and how small an plane can be (28 bytes). | |
1073 | * However, each plane we set up takes up some memory, and | |
1074 | * increases the cost of looping over planes, which atomic | |
1075 | * modesetting does quite a bit. As a result, we pick a | |
1076 | * modest number of planes to expose, that should hopefully | |
1077 | * still cover any sane usecase. | |
1078 | */ | |
1079 | for (i = 0; i < 8; i++) { | |
1080 | struct drm_plane *plane = | |
1081 | vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); | |
1082 | ||
1083 | if (IS_ERR(plane)) | |
1084 | continue; | |
1085 | ||
1086 | plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1087 | } | |
1088 | ||
1089 | /* Set up the legacy cursor after overlay initialization, | |
1090 | * since we overlay planes on the CRTC in the order they were | |
1091 | * initialized. | |
1092 | */ | |
1093 | cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); | |
1094 | if (!IS_ERR(cursor_plane)) { | |
1095 | cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc); | |
1096 | cursor_plane->crtc = crtc; | |
1097 | crtc->cursor = cursor_plane; | |
1098 | } | |
1099 | ||
1bf59f1d MK |
1100 | vc4_crtc_get_cob_allocation(vc4_crtc); |
1101 | ||
c8b75bca EA |
1102 | CRTC_WRITE(PV_INTEN, 0); |
1103 | CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); | |
1104 | ret = devm_request_irq(dev, platform_get_irq(pdev, 0), | |
1105 | vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); | |
1106 | if (ret) | |
fc2d6f1e | 1107 | goto err_destroy_planes; |
c8b75bca EA |
1108 | |
1109 | vc4_set_crtc_possible_masks(drm, crtc); | |
1110 | ||
e582b6c7 EA |
1111 | for (i = 0; i < crtc->gamma_size; i++) { |
1112 | vc4_crtc->lut_r[i] = i; | |
1113 | vc4_crtc->lut_g[i] = i; | |
1114 | vc4_crtc->lut_b[i] = i; | |
1115 | } | |
1116 | ||
c8b75bca EA |
1117 | platform_set_drvdata(pdev, vc4_crtc); |
1118 | ||
1119 | return 0; | |
1120 | ||
fc2d6f1e EA |
1121 | err_destroy_planes: |
1122 | list_for_each_entry_safe(destroy_plane, temp, | |
1123 | &drm->mode_config.plane_list, head) { | |
1124 | if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc)) | |
1125 | destroy_plane->funcs->destroy(destroy_plane); | |
1126 | } | |
c8b75bca EA |
1127 | err: |
1128 | return ret; | |
1129 | } | |
1130 | ||
1131 | static void vc4_crtc_unbind(struct device *dev, struct device *master, | |
1132 | void *data) | |
1133 | { | |
1134 | struct platform_device *pdev = to_platform_device(dev); | |
1135 | struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); | |
1136 | ||
1137 | vc4_crtc_destroy(&vc4_crtc->base); | |
1138 | ||
1139 | CRTC_WRITE(PV_INTEN, 0); | |
1140 | ||
1141 | platform_set_drvdata(pdev, NULL); | |
1142 | } | |
1143 | ||
1144 | static const struct component_ops vc4_crtc_ops = { | |
1145 | .bind = vc4_crtc_bind, | |
1146 | .unbind = vc4_crtc_unbind, | |
1147 | }; | |
1148 | ||
1149 | static int vc4_crtc_dev_probe(struct platform_device *pdev) | |
1150 | { | |
1151 | return component_add(&pdev->dev, &vc4_crtc_ops); | |
1152 | } | |
1153 | ||
1154 | static int vc4_crtc_dev_remove(struct platform_device *pdev) | |
1155 | { | |
1156 | component_del(&pdev->dev, &vc4_crtc_ops); | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | struct platform_driver vc4_crtc_driver = { | |
1161 | .probe = vc4_crtc_dev_probe, | |
1162 | .remove = vc4_crtc_dev_remove, | |
1163 | .driver = { | |
1164 | .name = "vc4_crtc", | |
1165 | .of_match_table = vc4_crtc_dt_match, | |
1166 | }, | |
1167 | }; |