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Commit | Line | Data |
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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 plane module | |
11 | * | |
12 | * Each DRM plane is a layer of pixels being scanned out by the HVS. | |
13 | * | |
14 | * At atomic modeset check time, we compute the HVS display element | |
15 | * state that would be necessary for displaying the plane (giving us a | |
16 | * chance to figure out if a plane configuration is invalid), then at | |
17 | * atomic flush time the CRTC will ask us to write our element state | |
18 | * into the region of the HVS that it has allocated for us. | |
19 | */ | |
20 | ||
b7e8e25b MY |
21 | #include <drm/drm_atomic.h> |
22 | #include <drm/drm_atomic_helper.h> | |
23 | #include <drm/drm_fb_cma_helper.h> | |
24 | #include <drm/drm_plane_helper.h> | |
72fdb40c | 25 | #include <drm/drm_atomic_uapi.h> |
b7e8e25b | 26 | |
b9f19259 | 27 | #include "uapi/drm/vc4_drm.h" |
c8b75bca EA |
28 | #include "vc4_drv.h" |
29 | #include "vc4_regs.h" | |
c8b75bca | 30 | |
c8b75bca EA |
31 | static const struct hvs_format { |
32 | u32 drm; /* DRM_FORMAT_* */ | |
33 | u32 hvs; /* HVS_FORMAT_* */ | |
34 | u32 pixel_order; | |
c8b75bca EA |
35 | } hvs_formats[] = { |
36 | { | |
37 | .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 38 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
c8b75bca EA |
39 | }, |
40 | { | |
41 | .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 42 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
c8b75bca | 43 | }, |
93977767 RH |
44 | { |
45 | .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 46 | .pixel_order = HVS_PIXEL_ORDER_ARGB, |
93977767 RH |
47 | }, |
48 | { | |
49 | .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 50 | .pixel_order = HVS_PIXEL_ORDER_ARGB, |
93977767 | 51 | }, |
fe4cd847 EA |
52 | { |
53 | .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565, | |
124e5dac | 54 | .pixel_order = HVS_PIXEL_ORDER_XRGB, |
fe4cd847 EA |
55 | }, |
56 | { | |
57 | .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565, | |
124e5dac | 58 | .pixel_order = HVS_PIXEL_ORDER_XBGR, |
fe4cd847 EA |
59 | }, |
60 | { | |
61 | .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, | |
124e5dac | 62 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
fe4cd847 EA |
63 | }, |
64 | { | |
65 | .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, | |
124e5dac | 66 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
fe4cd847 | 67 | }, |
88f8156f DS |
68 | { |
69 | .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888, | |
124e5dac | 70 | .pixel_order = HVS_PIXEL_ORDER_XRGB, |
88f8156f DS |
71 | }, |
72 | { | |
73 | .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888, | |
124e5dac | 74 | .pixel_order = HVS_PIXEL_ORDER_XBGR, |
88f8156f | 75 | }, |
fc04023f EA |
76 | { |
77 | .drm = DRM_FORMAT_YUV422, | |
78 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, | |
090cb0c6 | 79 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f EA |
80 | }, |
81 | { | |
82 | .drm = DRM_FORMAT_YVU422, | |
83 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, | |
090cb0c6 | 84 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, |
fc04023f EA |
85 | }, |
86 | { | |
87 | .drm = DRM_FORMAT_YUV420, | |
88 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, | |
090cb0c6 | 89 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f EA |
90 | }, |
91 | { | |
92 | .drm = DRM_FORMAT_YVU420, | |
93 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, | |
090cb0c6 | 94 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, |
fc04023f EA |
95 | }, |
96 | { | |
97 | .drm = DRM_FORMAT_NV12, | |
98 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, | |
090cb0c6 | 99 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f | 100 | }, |
cb20dd17 DS |
101 | { |
102 | .drm = DRM_FORMAT_NV21, | |
103 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, | |
104 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, | |
105 | }, | |
fc04023f EA |
106 | { |
107 | .drm = DRM_FORMAT_NV16, | |
108 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, | |
090cb0c6 | 109 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f | 110 | }, |
cb20dd17 DS |
111 | { |
112 | .drm = DRM_FORMAT_NV61, | |
113 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, | |
114 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, | |
115 | }, | |
c8b75bca EA |
116 | }; |
117 | ||
118 | static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) | |
119 | { | |
120 | unsigned i; | |
121 | ||
122 | for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { | |
123 | if (hvs_formats[i].drm == drm_format) | |
124 | return &hvs_formats[i]; | |
125 | } | |
126 | ||
127 | return NULL; | |
128 | } | |
129 | ||
21af94cf EA |
130 | static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) |
131 | { | |
eb8dd3ab BB |
132 | if (dst == src) |
133 | return VC4_SCALING_NONE; | |
134 | if (3 * dst >= 2 * src) | |
21af94cf | 135 | return VC4_SCALING_PPF; |
21af94cf | 136 | else |
eb8dd3ab | 137 | return VC4_SCALING_TPZ; |
21af94cf EA |
138 | } |
139 | ||
c8b75bca EA |
140 | static bool plane_enabled(struct drm_plane_state *state) |
141 | { | |
142 | return state->fb && state->crtc; | |
143 | } | |
144 | ||
91276ae2 | 145 | static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) |
c8b75bca EA |
146 | { |
147 | struct vc4_plane_state *vc4_state; | |
148 | ||
149 | if (WARN_ON(!plane->state)) | |
150 | return NULL; | |
151 | ||
152 | vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); | |
153 | if (!vc4_state) | |
154 | return NULL; | |
155 | ||
21af94cf | 156 | memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); |
8d938449 | 157 | vc4_state->dlist_initialized = 0; |
21af94cf | 158 | |
c8b75bca EA |
159 | __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); |
160 | ||
161 | if (vc4_state->dlist) { | |
162 | vc4_state->dlist = kmemdup(vc4_state->dlist, | |
163 | vc4_state->dlist_count * 4, | |
164 | GFP_KERNEL); | |
165 | if (!vc4_state->dlist) { | |
166 | kfree(vc4_state); | |
167 | return NULL; | |
168 | } | |
169 | vc4_state->dlist_size = vc4_state->dlist_count; | |
170 | } | |
171 | ||
172 | return &vc4_state->base; | |
173 | } | |
174 | ||
91276ae2 | 175 | static void vc4_plane_destroy_state(struct drm_plane *plane, |
176 | struct drm_plane_state *state) | |
c8b75bca | 177 | { |
21af94cf | 178 | struct vc4_dev *vc4 = to_vc4_dev(plane->dev); |
c8b75bca EA |
179 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); |
180 | ||
21af94cf EA |
181 | if (vc4_state->lbm.allocated) { |
182 | unsigned long irqflags; | |
183 | ||
184 | spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); | |
185 | drm_mm_remove_node(&vc4_state->lbm); | |
186 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); | |
187 | } | |
188 | ||
c8b75bca | 189 | kfree(vc4_state->dlist); |
2f701695 | 190 | __drm_atomic_helper_plane_destroy_state(&vc4_state->base); |
c8b75bca EA |
191 | kfree(state); |
192 | } | |
193 | ||
194 | /* Called during init to allocate the plane's atomic state. */ | |
91276ae2 | 195 | static void vc4_plane_reset(struct drm_plane *plane) |
c8b75bca EA |
196 | { |
197 | struct vc4_plane_state *vc4_state; | |
198 | ||
199 | WARN_ON(plane->state); | |
200 | ||
201 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
202 | if (!vc4_state) | |
203 | return; | |
204 | ||
42da6338 | 205 | __drm_atomic_helper_plane_reset(plane, &vc4_state->base); |
c8b75bca EA |
206 | } |
207 | ||
208 | static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) | |
209 | { | |
210 | if (vc4_state->dlist_count == vc4_state->dlist_size) { | |
211 | u32 new_size = max(4u, vc4_state->dlist_count * 2); | |
6da2ec56 | 212 | u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL); |
c8b75bca EA |
213 | |
214 | if (!new_dlist) | |
215 | return; | |
216 | memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); | |
217 | ||
218 | kfree(vc4_state->dlist); | |
219 | vc4_state->dlist = new_dlist; | |
220 | vc4_state->dlist_size = new_size; | |
221 | } | |
222 | ||
223 | vc4_state->dlist[vc4_state->dlist_count++] = val; | |
224 | } | |
225 | ||
21af94cf EA |
226 | /* Returns the scl0/scl1 field based on whether the dimensions need to |
227 | * be up/down/non-scaled. | |
228 | * | |
229 | * This is a replication of a table from the spec. | |
230 | */ | |
fc04023f | 231 | static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane) |
21af94cf EA |
232 | { |
233 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
234 | ||
fc04023f | 235 | switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) { |
21af94cf EA |
236 | case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF: |
237 | return SCALER_CTL0_SCL_H_PPF_V_PPF; | |
238 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF: | |
239 | return SCALER_CTL0_SCL_H_TPZ_V_PPF; | |
240 | case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ: | |
241 | return SCALER_CTL0_SCL_H_PPF_V_TPZ; | |
242 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ: | |
243 | return SCALER_CTL0_SCL_H_TPZ_V_TPZ; | |
244 | case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE: | |
245 | return SCALER_CTL0_SCL_H_PPF_V_NONE; | |
246 | case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF: | |
247 | return SCALER_CTL0_SCL_H_NONE_V_PPF; | |
248 | case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ: | |
249 | return SCALER_CTL0_SCL_H_NONE_V_TPZ; | |
250 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE: | |
251 | return SCALER_CTL0_SCL_H_TPZ_V_NONE; | |
252 | default: | |
253 | case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE: | |
254 | /* The unity case is independently handled by | |
255 | * SCALER_CTL0_UNITY. | |
256 | */ | |
257 | return 0; | |
258 | } | |
259 | } | |
260 | ||
5c679994 | 261 | static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) |
c8b75bca EA |
262 | { |
263 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
264 | struct drm_framebuffer *fb = state->fb; | |
fc04023f | 265 | struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); |
21af94cf | 266 | u32 subpixel_src_mask = (1 << 16) - 1; |
438b74a5 | 267 | u32 format = fb->format->format; |
bcb0b461 | 268 | int num_planes = fb->format->num_planes; |
58a6a36f BB |
269 | struct drm_crtc_state *crtc_state; |
270 | u32 h_subsample, v_subsample; | |
271 | int i, ret; | |
272 | ||
273 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, | |
274 | state->crtc); | |
275 | if (!crtc_state) { | |
276 | DRM_DEBUG_KMS("Invalid crtc state\n"); | |
277 | return -EINVAL; | |
278 | } | |
279 | ||
5dc416d9 BB |
280 | ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1, |
281 | INT_MAX, true, true); | |
58a6a36f BB |
282 | if (ret) |
283 | return ret; | |
284 | ||
285 | h_subsample = drm_format_horz_chroma_subsampling(format); | |
286 | v_subsample = drm_format_vert_chroma_subsampling(format); | |
5c679994 | 287 | |
fc04023f EA |
288 | for (i = 0; i < num_planes; i++) |
289 | vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; | |
5c679994 | 290 | |
21af94cf | 291 | /* We don't support subpixel source positioning for scaling. */ |
58a6a36f BB |
292 | if ((state->src.x1 & subpixel_src_mask) || |
293 | (state->src.x2 & subpixel_src_mask) || | |
294 | (state->src.y1 & subpixel_src_mask) || | |
295 | (state->src.y2 & subpixel_src_mask)) { | |
bf893acc EA |
296 | return -EINVAL; |
297 | } | |
298 | ||
58a6a36f BB |
299 | vc4_state->src_x = state->src.x1 >> 16; |
300 | vc4_state->src_y = state->src.y1 >> 16; | |
301 | vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16; | |
302 | vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16; | |
f863e356 | 303 | |
58a6a36f BB |
304 | vc4_state->crtc_x = state->dst.x1; |
305 | vc4_state->crtc_y = state->dst.y1; | |
306 | vc4_state->crtc_w = state->dst.x2 - state->dst.x1; | |
307 | vc4_state->crtc_h = state->dst.y2 - state->dst.y1; | |
f863e356 | 308 | |
fc04023f EA |
309 | vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], |
310 | vc4_state->crtc_w); | |
311 | vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], | |
312 | vc4_state->crtc_h); | |
313 | ||
658d8cbd BB |
314 | vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE && |
315 | vc4_state->y_scaling[0] == VC4_SCALING_NONE); | |
316 | ||
fc04023f EA |
317 | if (num_planes > 1) { |
318 | vc4_state->is_yuv = true; | |
319 | ||
fc04023f EA |
320 | vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; |
321 | vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; | |
322 | ||
323 | vc4_state->x_scaling[1] = | |
324 | vc4_get_scaling_mode(vc4_state->src_w[1], | |
325 | vc4_state->crtc_w); | |
326 | vc4_state->y_scaling[1] = | |
327 | vc4_get_scaling_mode(vc4_state->src_h[1], | |
328 | vc4_state->crtc_h); | |
329 | ||
0560054d BB |
330 | /* YUV conversion requires that horizontal scaling be enabled |
331 | * on the UV plane even if vc4_get_scaling_mode() returned | |
332 | * VC4_SCALING_NONE (which can happen when the down-scaling | |
333 | * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this | |
334 | * case. | |
fc04023f | 335 | */ |
0560054d BB |
336 | if (vc4_state->x_scaling[1] == VC4_SCALING_NONE) |
337 | vc4_state->x_scaling[1] = VC4_SCALING_PPF; | |
a6a00918 | 338 | } else { |
2b02a05b | 339 | vc4_state->is_yuv = false; |
a6a00918 BB |
340 | vc4_state->x_scaling[1] = VC4_SCALING_NONE; |
341 | vc4_state->y_scaling[1] = VC4_SCALING_NONE; | |
fc04023f EA |
342 | } |
343 | ||
5c679994 EA |
344 | return 0; |
345 | } | |
346 | ||
21af94cf EA |
347 | static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst) |
348 | { | |
349 | u32 scale, recip; | |
350 | ||
351 | scale = (1 << 16) * src / dst; | |
352 | ||
353 | /* The specs note that while the reciprocal would be defined | |
354 | * as (1<<32)/scale, ~0 is close enough. | |
355 | */ | |
356 | recip = ~0 / scale; | |
357 | ||
358 | vc4_dlist_write(vc4_state, | |
359 | VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | | |
360 | VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); | |
361 | vc4_dlist_write(vc4_state, | |
362 | VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); | |
363 | } | |
364 | ||
365 | static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst) | |
366 | { | |
367 | u32 scale = (1 << 16) * src / dst; | |
368 | ||
369 | vc4_dlist_write(vc4_state, | |
370 | SCALER_PPF_AGC | | |
371 | VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | | |
372 | VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); | |
373 | } | |
374 | ||
375 | static u32 vc4_lbm_size(struct drm_plane_state *state) | |
376 | { | |
377 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
378 | /* This is the worst case number. One of the two sizes will | |
379 | * be used depending on the scaling configuration. | |
380 | */ | |
fc04023f | 381 | u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); |
21af94cf EA |
382 | u32 lbm; |
383 | ||
b2e554d4 BB |
384 | /* LBM is not needed when there's no vertical scaling. */ |
385 | if (vc4_state->y_scaling[0] == VC4_SCALING_NONE && | |
386 | vc4_state->y_scaling[1] == VC4_SCALING_NONE) | |
387 | return 0; | |
388 | ||
fc04023f | 389 | if (!vc4_state->is_yuv) { |
b2e554d4 | 390 | if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) |
fc04023f EA |
391 | lbm = pix_per_line * 8; |
392 | else { | |
393 | /* In special cases, this multiplier might be 12. */ | |
394 | lbm = pix_per_line * 16; | |
395 | } | |
396 | } else { | |
397 | /* There are cases for this going down to a multiplier | |
398 | * of 2, but according to the firmware source, the | |
399 | * table in the docs is somewhat wrong. | |
400 | */ | |
21af94cf EA |
401 | lbm = pix_per_line * 16; |
402 | } | |
403 | ||
404 | lbm = roundup(lbm, 32); | |
405 | ||
406 | return lbm; | |
407 | } | |
408 | ||
fc04023f EA |
409 | static void vc4_write_scaling_parameters(struct drm_plane_state *state, |
410 | int channel) | |
21af94cf EA |
411 | { |
412 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
413 | ||
414 | /* Ch0 H-PPF Word 0: Scaling Parameters */ | |
fc04023f | 415 | if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) { |
21af94cf | 416 | vc4_write_ppf(vc4_state, |
fc04023f | 417 | vc4_state->src_w[channel], vc4_state->crtc_w); |
21af94cf EA |
418 | } |
419 | ||
420 | /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */ | |
fc04023f | 421 | if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) { |
21af94cf | 422 | vc4_write_ppf(vc4_state, |
fc04023f | 423 | vc4_state->src_h[channel], vc4_state->crtc_h); |
21af94cf EA |
424 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); |
425 | } | |
426 | ||
427 | /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */ | |
fc04023f | 428 | if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) { |
21af94cf | 429 | vc4_write_tpz(vc4_state, |
fc04023f | 430 | vc4_state->src_w[channel], vc4_state->crtc_w); |
21af94cf EA |
431 | } |
432 | ||
433 | /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */ | |
fc04023f | 434 | if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) { |
21af94cf | 435 | vc4_write_tpz(vc4_state, |
fc04023f | 436 | vc4_state->src_h[channel], vc4_state->crtc_h); |
21af94cf EA |
437 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); |
438 | } | |
439 | } | |
5c679994 | 440 | |
0a038c1c BB |
441 | static int vc4_plane_allocate_lbm(struct drm_plane_state *state) |
442 | { | |
443 | struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev); | |
444 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
445 | unsigned long irqflags; | |
446 | u32 lbm_size; | |
447 | ||
448 | lbm_size = vc4_lbm_size(state); | |
449 | if (!lbm_size) | |
450 | return 0; | |
451 | ||
452 | if (WARN_ON(!vc4_state->lbm_offset)) | |
453 | return -EINVAL; | |
454 | ||
455 | /* Allocate the LBM memory that the HVS will use for temporary | |
456 | * storage due to our scaling/format conversion. | |
457 | */ | |
458 | if (!vc4_state->lbm.allocated) { | |
459 | int ret; | |
460 | ||
461 | spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); | |
462 | ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, | |
463 | &vc4_state->lbm, | |
464 | lbm_size, 32, 0, 0); | |
465 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); | |
466 | ||
467 | if (ret) | |
468 | return ret; | |
469 | } else { | |
470 | WARN_ON_ONCE(lbm_size != vc4_state->lbm.size); | |
471 | } | |
472 | ||
473 | vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start; | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
5c679994 EA |
478 | /* Writes out a full display list for an active plane to the plane's |
479 | * private dlist state. | |
480 | */ | |
481 | static int vc4_plane_mode_set(struct drm_plane *plane, | |
482 | struct drm_plane_state *state) | |
483 | { | |
21af94cf | 484 | struct vc4_dev *vc4 = to_vc4_dev(plane->dev); |
5c679994 EA |
485 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); |
486 | struct drm_framebuffer *fb = state->fb; | |
5c679994 | 487 | u32 ctl0_offset = vc4_state->dlist_count; |
438b74a5 | 488 | const struct hvs_format *format = vc4_get_hvs_format(fb->format->format); |
e065a8dd | 489 | u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier); |
fc04023f | 490 | int num_planes = drm_format_num_planes(format->drm); |
a65511b1 | 491 | u32 h_subsample, v_subsample; |
22445f03 | 492 | bool mix_plane_alpha; |
3d67b68a | 493 | bool covers_screen; |
98830d91 | 494 | u32 scl0, scl1, pitch0; |
0a038c1c | 495 | u32 tiling; |
e065a8dd | 496 | u32 hvs_format = format->hvs; |
fc04023f | 497 | int ret, i; |
5c679994 | 498 | |
8d938449 BB |
499 | if (vc4_state->dlist_initialized) |
500 | return 0; | |
501 | ||
5c679994 | 502 | ret = vc4_plane_setup_clipping_and_scaling(state); |
21af94cf EA |
503 | if (ret) |
504 | return ret; | |
505 | ||
fc04023f EA |
506 | /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB |
507 | * and 4:4:4, scl1 should be set to scl0 so both channels of | |
508 | * the scaler do the same thing. For YUV, the Y plane needs | |
509 | * to be put in channel 1 and Cb/Cr in channel 0, so we swap | |
510 | * the scl fields here. | |
511 | */ | |
512 | if (num_planes == 1) { | |
9a0e9802 | 513 | scl0 = vc4_get_scl_field(state, 0); |
fc04023f EA |
514 | scl1 = scl0; |
515 | } else { | |
516 | scl0 = vc4_get_scl_field(state, 1); | |
517 | scl1 = vc4_get_scl_field(state, 0); | |
518 | } | |
21af94cf | 519 | |
a65511b1 BB |
520 | h_subsample = drm_format_horz_chroma_subsampling(format->drm); |
521 | v_subsample = drm_format_vert_chroma_subsampling(format->drm); | |
522 | ||
e065a8dd | 523 | switch (base_format_mod) { |
98830d91 EA |
524 | case DRM_FORMAT_MOD_LINEAR: |
525 | tiling = SCALER_CTL0_TILING_LINEAR; | |
526 | pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); | |
a65511b1 BB |
527 | |
528 | /* Adjust the base pointer to the first pixel to be scanned | |
529 | * out. | |
530 | */ | |
531 | for (i = 0; i < num_planes; i++) { | |
532 | vc4_state->offsets[i] += vc4_state->src_y / | |
533 | (i ? v_subsample : 1) * | |
534 | fb->pitches[i]; | |
535 | vc4_state->offsets[i] += vc4_state->src_x / | |
536 | (i ? h_subsample : 1) * | |
537 | fb->format->cpp[i]; | |
538 | } | |
3e407417 | 539 | |
98830d91 | 540 | break; |
652badb9 EA |
541 | |
542 | case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { | |
652badb9 | 543 | u32 tile_size_shift = 12; /* T tiles are 4kb */ |
3e407417 BB |
544 | /* Whole-tile offsets, mostly for setting the pitch. */ |
545 | u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5; | |
652badb9 | 546 | u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ |
3e407417 BB |
547 | u32 tile_w_mask = (1 << tile_w_shift) - 1; |
548 | /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice | |
549 | * the height (in pixels) of a 4k tile. | |
550 | */ | |
551 | u32 tile_h_mask = (2 << tile_h_shift) - 1; | |
552 | /* For T-tiled, the FB pitch is "how many bytes from one row to | |
553 | * the next, such that | |
554 | * | |
555 | * pitch * tile_h == tile_size * tiles_per_row | |
556 | */ | |
652badb9 | 557 | u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); |
3e407417 BB |
558 | u32 tiles_l = vc4_state->src_x >> tile_w_shift; |
559 | u32 tiles_r = tiles_w - tiles_l; | |
560 | u32 tiles_t = vc4_state->src_y >> tile_h_shift; | |
561 | /* Intra-tile offsets, which modify the base address (the | |
562 | * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that | |
563 | * base address). | |
564 | */ | |
565 | u32 tile_y = (vc4_state->src_y >> 4) & 1; | |
566 | u32 subtile_y = (vc4_state->src_y >> 2) & 3; | |
567 | u32 utile_y = vc4_state->src_y & 3; | |
568 | u32 x_off = vc4_state->src_x & tile_w_mask; | |
569 | u32 y_off = vc4_state->src_y & tile_h_mask; | |
652badb9 | 570 | |
98830d91 | 571 | tiling = SCALER_CTL0_TILING_256B_OR_T; |
3e407417 BB |
572 | pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | |
573 | VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | | |
574 | VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | | |
575 | VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); | |
576 | vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift); | |
577 | vc4_state->offsets[0] += subtile_y << 8; | |
578 | vc4_state->offsets[0] += utile_y << 4; | |
579 | ||
580 | /* Rows of tiles alternate left-to-right and right-to-left. */ | |
581 | if (tiles_t & 1) { | |
582 | pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR; | |
583 | vc4_state->offsets[0] += (tiles_w - tiles_l) << | |
584 | tile_size_shift; | |
585 | vc4_state->offsets[0] -= (1 + !tile_y) << 10; | |
586 | } else { | |
587 | vc4_state->offsets[0] += tiles_l << tile_size_shift; | |
588 | vc4_state->offsets[0] += tile_y << 10; | |
589 | } | |
98830d91 | 590 | |
98830d91 | 591 | break; |
652badb9 EA |
592 | } |
593 | ||
e065a8dd DS |
594 | case DRM_FORMAT_MOD_BROADCOM_SAND64: |
595 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
596 | case DRM_FORMAT_MOD_BROADCOM_SAND256: { | |
597 | uint32_t param = fourcc_mod_broadcom_param(fb->modifier); | |
8e75d582 | 598 | u32 tile_w, tile, x_off, pix_per_tile; |
e065a8dd DS |
599 | |
600 | /* Column-based NV12 or RGBA. | |
601 | */ | |
602 | if (fb->format->num_planes > 1) { | |
603 | if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) { | |
604 | DRM_DEBUG_KMS("SAND format only valid for NV12/21"); | |
605 | return -EINVAL; | |
606 | } | |
607 | hvs_format = HVS_PIXEL_FORMAT_H264; | |
608 | } else { | |
609 | if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) { | |
610 | DRM_DEBUG_KMS("SAND256 format only valid for H.264"); | |
611 | return -EINVAL; | |
612 | } | |
613 | } | |
614 | ||
615 | switch (base_format_mod) { | |
616 | case DRM_FORMAT_MOD_BROADCOM_SAND64: | |
617 | tiling = SCALER_CTL0_TILING_64B; | |
8e75d582 | 618 | tile_w = 64; |
e065a8dd DS |
619 | break; |
620 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
621 | tiling = SCALER_CTL0_TILING_128B; | |
8e75d582 | 622 | tile_w = 128; |
e065a8dd DS |
623 | break; |
624 | case DRM_FORMAT_MOD_BROADCOM_SAND256: | |
625 | tiling = SCALER_CTL0_TILING_256B_OR_T; | |
8e75d582 | 626 | tile_w = 256; |
e065a8dd DS |
627 | break; |
628 | default: | |
629 | break; | |
630 | } | |
631 | ||
632 | if (param > SCALER_TILE_HEIGHT_MASK) { | |
633 | DRM_DEBUG_KMS("SAND height too large (%d)\n", param); | |
634 | return -EINVAL; | |
635 | } | |
636 | ||
8e75d582 BB |
637 | pix_per_tile = tile_w / fb->format->cpp[0]; |
638 | tile = vc4_state->src_x / pix_per_tile; | |
639 | x_off = vc4_state->src_x % pix_per_tile; | |
640 | ||
641 | /* Adjust the base pointer to the first pixel to be scanned | |
642 | * out. | |
643 | */ | |
644 | for (i = 0; i < num_planes; i++) { | |
645 | vc4_state->offsets[i] += param * tile_w * tile; | |
646 | vc4_state->offsets[i] += vc4_state->src_y / | |
647 | (i ? v_subsample : 1) * | |
648 | tile_w; | |
649 | vc4_state->offsets[i] += x_off / | |
650 | (i ? h_subsample : 1) * | |
651 | fb->format->cpp[i]; | |
652 | } | |
653 | ||
e065a8dd DS |
654 | pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); |
655 | break; | |
656 | } | |
657 | ||
98830d91 EA |
658 | default: |
659 | DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", | |
660 | (long long)fb->modifier); | |
661 | return -EINVAL; | |
662 | } | |
663 | ||
21af94cf | 664 | /* Control word */ |
c8b75bca EA |
665 | vc4_dlist_write(vc4_state, |
666 | SCALER_CTL0_VALID | | |
3257ec79 | 667 | VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | |
c8b75bca | 668 | (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | |
e065a8dd | 669 | (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | |
98830d91 | 670 | VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | |
21af94cf | 671 | (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) | |
fc04023f EA |
672 | VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | |
673 | VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); | |
c8b75bca EA |
674 | |
675 | /* Position Word 0: Image Positions and Alpha Value */ | |
6674a904 | 676 | vc4_state->pos0_offset = vc4_state->dlist_count; |
c8b75bca | 677 | vc4_dlist_write(vc4_state, |
22445f03 | 678 | VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | |
5c679994 EA |
679 | VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | |
680 | VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); | |
c8b75bca | 681 | |
21af94cf EA |
682 | /* Position Word 1: Scaled Image Dimensions. */ |
683 | if (!vc4_state->is_unity) { | |
684 | vc4_dlist_write(vc4_state, | |
685 | VC4_SET_FIELD(vc4_state->crtc_w, | |
686 | SCALER_POS1_SCL_WIDTH) | | |
687 | VC4_SET_FIELD(vc4_state->crtc_h, | |
688 | SCALER_POS1_SCL_HEIGHT)); | |
689 | } | |
c8b75bca | 690 | |
22445f03 SS |
691 | /* Don't waste cycles mixing with plane alpha if the set alpha |
692 | * is opaque or there is no per-pixel alpha information. | |
693 | * In any case we use the alpha property value as the fixed alpha. | |
694 | */ | |
695 | mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE && | |
696 | fb->format->has_alpha; | |
697 | ||
05202c24 | 698 | /* Position Word 2: Source Image Size, Alpha */ |
6674a904 | 699 | vc4_state->pos2_offset = vc4_state->dlist_count; |
c8b75bca | 700 | vc4_dlist_write(vc4_state, |
124e5dac | 701 | VC4_SET_FIELD(fb->format->has_alpha ? |
c8b75bca EA |
702 | SCALER_POS2_ALPHA_MODE_PIPELINE : |
703 | SCALER_POS2_ALPHA_MODE_FIXED, | |
704 | SCALER_POS2_ALPHA_MODE) | | |
22445f03 | 705 | (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | |
05202c24 | 706 | (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) | |
fc04023f EA |
707 | VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) | |
708 | VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); | |
c8b75bca EA |
709 | |
710 | /* Position Word 3: Context. Written by the HVS. */ | |
711 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); | |
712 | ||
fc04023f EA |
713 | |
714 | /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers | |
715 | * | |
716 | * The pointers may be any byte address. | |
717 | */ | |
6674a904 | 718 | vc4_state->ptr0_offset = vc4_state->dlist_count; |
090cb0c6 DS |
719 | for (i = 0; i < num_planes; i++) |
720 | vc4_dlist_write(vc4_state, vc4_state->offsets[i]); | |
c8b75bca | 721 | |
fc04023f EA |
722 | /* Pointer Context Word 0/1/2: Written by the HVS */ |
723 | for (i = 0; i < num_planes; i++) | |
724 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); | |
c8b75bca | 725 | |
98830d91 EA |
726 | /* Pitch word 0 */ |
727 | vc4_dlist_write(vc4_state, pitch0); | |
728 | ||
729 | /* Pitch word 1/2 */ | |
730 | for (i = 1; i < num_planes; i++) { | |
e065a8dd DS |
731 | if (hvs_format != HVS_PIXEL_FORMAT_H264) { |
732 | vc4_dlist_write(vc4_state, | |
733 | VC4_SET_FIELD(fb->pitches[i], | |
734 | SCALER_SRC_PITCH)); | |
735 | } else { | |
736 | vc4_dlist_write(vc4_state, pitch0); | |
737 | } | |
fc04023f EA |
738 | } |
739 | ||
740 | /* Colorspace conversion words */ | |
741 | if (vc4_state->is_yuv) { | |
742 | vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5); | |
743 | vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5); | |
744 | vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5); | |
745 | } | |
c8b75bca | 746 | |
0a038c1c BB |
747 | vc4_state->lbm_offset = 0; |
748 | ||
658d8cbd BB |
749 | if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || |
750 | vc4_state->x_scaling[1] != VC4_SCALING_NONE || | |
751 | vc4_state->y_scaling[0] != VC4_SCALING_NONE || | |
752 | vc4_state->y_scaling[1] != VC4_SCALING_NONE) { | |
0a038c1c BB |
753 | /* Reserve a slot for the LBM Base Address. The real value will |
754 | * be set when calling vc4_plane_allocate_lbm(). | |
755 | */ | |
fc04023f | 756 | if (vc4_state->y_scaling[0] != VC4_SCALING_NONE || |
0a038c1c BB |
757 | vc4_state->y_scaling[1] != VC4_SCALING_NONE) |
758 | vc4_state->lbm_offset = vc4_state->dlist_count++; | |
21af94cf | 759 | |
fc04023f EA |
760 | if (num_planes > 1) { |
761 | /* Emit Cb/Cr as channel 0 and Y as channel | |
762 | * 1. This matches how we set up scl0/scl1 | |
763 | * above. | |
764 | */ | |
765 | vc4_write_scaling_parameters(state, 1); | |
766 | } | |
767 | vc4_write_scaling_parameters(state, 0); | |
21af94cf EA |
768 | |
769 | /* If any PPF setup was done, then all the kernel | |
770 | * pointers get uploaded. | |
771 | */ | |
fc04023f EA |
772 | if (vc4_state->x_scaling[0] == VC4_SCALING_PPF || |
773 | vc4_state->y_scaling[0] == VC4_SCALING_PPF || | |
774 | vc4_state->x_scaling[1] == VC4_SCALING_PPF || | |
775 | vc4_state->y_scaling[1] == VC4_SCALING_PPF) { | |
21af94cf EA |
776 | u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, |
777 | SCALER_PPF_KERNEL_OFFSET); | |
778 | ||
779 | /* HPPF plane 0 */ | |
780 | vc4_dlist_write(vc4_state, kernel); | |
781 | /* VPPF plane 0 */ | |
782 | vc4_dlist_write(vc4_state, kernel); | |
783 | /* HPPF plane 1 */ | |
784 | vc4_dlist_write(vc4_state, kernel); | |
785 | /* VPPF plane 1 */ | |
786 | vc4_dlist_write(vc4_state, kernel); | |
787 | } | |
788 | } | |
789 | ||
c8b75bca EA |
790 | vc4_state->dlist[ctl0_offset] |= |
791 | VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); | |
792 | ||
3d67b68a SS |
793 | /* crtc_* are already clipped coordinates. */ |
794 | covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 && | |
795 | vc4_state->crtc_w == state->crtc->mode.hdisplay && | |
796 | vc4_state->crtc_h == state->crtc->mode.vdisplay; | |
797 | /* Background fill might be necessary when the plane has per-pixel | |
22445f03 SS |
798 | * alpha content or a non-opaque plane alpha and could blend from the |
799 | * background or does not cover the entire screen. | |
3d67b68a | 800 | */ |
22445f03 SS |
801 | vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen || |
802 | state->alpha != DRM_BLEND_ALPHA_OPAQUE; | |
3d67b68a | 803 | |
8d938449 BB |
804 | /* Flag the dlist as initialized to avoid checking it twice in case |
805 | * the async update check already called vc4_plane_mode_set() and | |
806 | * decided to fallback to sync update because async update was not | |
807 | * possible. | |
808 | */ | |
809 | vc4_state->dlist_initialized = 1; | |
810 | ||
c8b75bca EA |
811 | return 0; |
812 | } | |
813 | ||
814 | /* If a modeset involves changing the setup of a plane, the atomic | |
815 | * infrastructure will call this to validate a proposed plane setup. | |
816 | * However, if a plane isn't getting updated, this (and the | |
817 | * corresponding vc4_plane_atomic_update) won't get called. Thus, we | |
818 | * compute the dlist here and have all active plane dlists get updated | |
819 | * in the CRTC's flush. | |
820 | */ | |
821 | static int vc4_plane_atomic_check(struct drm_plane *plane, | |
822 | struct drm_plane_state *state) | |
823 | { | |
824 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
0a038c1c | 825 | int ret; |
c8b75bca EA |
826 | |
827 | vc4_state->dlist_count = 0; | |
828 | ||
0a038c1c | 829 | if (!plane_enabled(state)) |
c8b75bca | 830 | return 0; |
0a038c1c BB |
831 | |
832 | ret = vc4_plane_mode_set(plane, state); | |
833 | if (ret) | |
834 | return ret; | |
835 | ||
836 | return vc4_plane_allocate_lbm(state); | |
c8b75bca EA |
837 | } |
838 | ||
839 | static void vc4_plane_atomic_update(struct drm_plane *plane, | |
840 | struct drm_plane_state *old_state) | |
841 | { | |
842 | /* No contents here. Since we don't know where in the CRTC's | |
843 | * dlist we should be stored, our dlist is uploaded to the | |
844 | * hardware with vc4_plane_write_dlist() at CRTC atomic_flush | |
845 | * time. | |
846 | */ | |
847 | } | |
848 | ||
849 | u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) | |
850 | { | |
851 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); | |
852 | int i; | |
853 | ||
b501bacc EA |
854 | vc4_state->hw_dlist = dlist; |
855 | ||
c8b75bca EA |
856 | /* Can't memcpy_toio() because it needs to be 32-bit writes. */ |
857 | for (i = 0; i < vc4_state->dlist_count; i++) | |
858 | writel(vc4_state->dlist[i], &dlist[i]); | |
859 | ||
860 | return vc4_state->dlist_count; | |
861 | } | |
862 | ||
2f196b7c | 863 | u32 vc4_plane_dlist_size(const struct drm_plane_state *state) |
c8b75bca | 864 | { |
2f196b7c DV |
865 | const struct vc4_plane_state *vc4_state = |
866 | container_of(state, typeof(*vc4_state), base); | |
c8b75bca EA |
867 | |
868 | return vc4_state->dlist_count; | |
869 | } | |
870 | ||
b501bacc EA |
871 | /* Updates the plane to immediately (well, once the FIFO needs |
872 | * refilling) scan out from at a new framebuffer. | |
873 | */ | |
874 | void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) | |
875 | { | |
876 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); | |
877 | struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); | |
878 | uint32_t addr; | |
879 | ||
880 | /* We're skipping the address adjustment for negative origin, | |
881 | * because this is only called on the primary plane. | |
882 | */ | |
883 | WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0); | |
884 | addr = bo->paddr + fb->offsets[0]; | |
885 | ||
886 | /* Write the new address into the hardware immediately. The | |
887 | * scanout will start from this address as soon as the FIFO | |
888 | * needs to refill with pixels. | |
889 | */ | |
6674a904 | 890 | writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]); |
b501bacc EA |
891 | |
892 | /* Also update the CPU-side dlist copy, so that any later | |
893 | * atomic updates that don't do a new modeset on our plane | |
894 | * also use our updated address. | |
895 | */ | |
6674a904 | 896 | vc4_state->dlist[vc4_state->ptr0_offset] = addr; |
b501bacc EA |
897 | } |
898 | ||
539c320b GP |
899 | static void vc4_plane_atomic_async_update(struct drm_plane *plane, |
900 | struct drm_plane_state *state) | |
901 | { | |
5a43911f | 902 | struct vc4_plane_state *vc4_state, *new_vc4_state; |
539c320b | 903 | |
1d4118ca | 904 | drm_atomic_set_fb_for_plane(plane->state, state->fb); |
539c320b GP |
905 | plane->state->crtc_x = state->crtc_x; |
906 | plane->state->crtc_y = state->crtc_y; | |
1d4118ca BB |
907 | plane->state->crtc_w = state->crtc_w; |
908 | plane->state->crtc_h = state->crtc_h; | |
539c320b GP |
909 | plane->state->src_x = state->src_x; |
910 | plane->state->src_y = state->src_y; | |
1d4118ca BB |
911 | plane->state->src_w = state->src_w; |
912 | plane->state->src_h = state->src_h; | |
913 | plane->state->src_h = state->src_h; | |
914 | plane->state->alpha = state->alpha; | |
915 | plane->state->pixel_blend_mode = state->pixel_blend_mode; | |
916 | plane->state->rotation = state->rotation; | |
917 | plane->state->zpos = state->zpos; | |
918 | plane->state->normalized_zpos = state->normalized_zpos; | |
919 | plane->state->color_encoding = state->color_encoding; | |
920 | plane->state->color_range = state->color_range; | |
921 | plane->state->src = state->src; | |
922 | plane->state->dst = state->dst; | |
923 | plane->state->visible = state->visible; | |
5a43911f BB |
924 | |
925 | new_vc4_state = to_vc4_plane_state(state); | |
926 | vc4_state = to_vc4_plane_state(plane->state); | |
927 | ||
1d4118ca BB |
928 | vc4_state->crtc_x = new_vc4_state->crtc_x; |
929 | vc4_state->crtc_y = new_vc4_state->crtc_y; | |
930 | vc4_state->crtc_h = new_vc4_state->crtc_h; | |
931 | vc4_state->crtc_w = new_vc4_state->crtc_w; | |
932 | vc4_state->src_x = new_vc4_state->src_x; | |
933 | vc4_state->src_y = new_vc4_state->src_y; | |
934 | memcpy(vc4_state->src_w, new_vc4_state->src_w, | |
935 | sizeof(vc4_state->src_w)); | |
936 | memcpy(vc4_state->src_h, new_vc4_state->src_h, | |
937 | sizeof(vc4_state->src_h)); | |
938 | memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling, | |
939 | sizeof(vc4_state->x_scaling)); | |
940 | memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling, | |
941 | sizeof(vc4_state->y_scaling)); | |
942 | vc4_state->is_unity = new_vc4_state->is_unity; | |
943 | vc4_state->is_yuv = new_vc4_state->is_yuv; | |
944 | memcpy(vc4_state->offsets, new_vc4_state->offsets, | |
945 | sizeof(vc4_state->offsets)); | |
946 | vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill; | |
947 | ||
5a43911f BB |
948 | /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */ |
949 | vc4_state->dlist[vc4_state->pos0_offset] = | |
950 | new_vc4_state->dlist[vc4_state->pos0_offset]; | |
951 | vc4_state->dlist[vc4_state->pos2_offset] = | |
952 | new_vc4_state->dlist[vc4_state->pos2_offset]; | |
953 | vc4_state->dlist[vc4_state->ptr0_offset] = | |
954 | new_vc4_state->dlist[vc4_state->ptr0_offset]; | |
539c320b GP |
955 | |
956 | /* Note that we can't just call vc4_plane_write_dlist() | |
957 | * because that would smash the context data that the HVS is | |
958 | * currently using. | |
959 | */ | |
960 | writel(vc4_state->dlist[vc4_state->pos0_offset], | |
961 | &vc4_state->hw_dlist[vc4_state->pos0_offset]); | |
962 | writel(vc4_state->dlist[vc4_state->pos2_offset], | |
963 | &vc4_state->hw_dlist[vc4_state->pos2_offset]); | |
964 | writel(vc4_state->dlist[vc4_state->ptr0_offset], | |
965 | &vc4_state->hw_dlist[vc4_state->ptr0_offset]); | |
966 | } | |
967 | ||
968 | static int vc4_plane_atomic_async_check(struct drm_plane *plane, | |
969 | struct drm_plane_state *state) | |
970 | { | |
1d4118ca BB |
971 | struct vc4_plane_state *old_vc4_state, *new_vc4_state; |
972 | int ret; | |
973 | u32 i; | |
974 | ||
975 | ret = vc4_plane_mode_set(plane, state); | |
976 | if (ret) | |
977 | return ret; | |
978 | ||
979 | old_vc4_state = to_vc4_plane_state(plane->state); | |
980 | new_vc4_state = to_vc4_plane_state(state); | |
981 | if (old_vc4_state->dlist_count != new_vc4_state->dlist_count || | |
982 | old_vc4_state->pos0_offset != new_vc4_state->pos0_offset || | |
983 | old_vc4_state->pos2_offset != new_vc4_state->pos2_offset || | |
984 | old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset || | |
985 | vc4_lbm_size(plane->state) != vc4_lbm_size(state)) | |
539c320b GP |
986 | return -EINVAL; |
987 | ||
1d4118ca BB |
988 | /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update |
989 | * if anything else has changed, fallback to a sync update. | |
990 | */ | |
991 | for (i = 0; i < new_vc4_state->dlist_count; i++) { | |
992 | if (i == new_vc4_state->pos0_offset || | |
993 | i == new_vc4_state->pos2_offset || | |
994 | i == new_vc4_state->ptr0_offset || | |
995 | (new_vc4_state->lbm_offset && | |
996 | i == new_vc4_state->lbm_offset)) | |
997 | continue; | |
998 | ||
999 | if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i]) | |
1000 | return -EINVAL; | |
1001 | } | |
1002 | ||
539c320b GP |
1003 | return 0; |
1004 | } | |
1005 | ||
334dbd69 EA |
1006 | static int vc4_prepare_fb(struct drm_plane *plane, |
1007 | struct drm_plane_state *state) | |
1008 | { | |
1009 | struct vc4_bo *bo; | |
1010 | struct dma_fence *fence; | |
b9f19259 | 1011 | int ret; |
334dbd69 | 1012 | |
2227a7a2 | 1013 | if (!state->fb) |
334dbd69 EA |
1014 | return 0; |
1015 | ||
1016 | bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); | |
b9f19259 | 1017 | |
2227a7a2 DV |
1018 | fence = reservation_object_get_excl_rcu(bo->resv); |
1019 | drm_atomic_set_fence_for_plane(state, fence); | |
1020 | ||
1021 | if (plane->state->fb == state->fb) | |
1022 | return 0; | |
1023 | ||
b9f19259 BB |
1024 | ret = vc4_bo_inc_usecnt(bo); |
1025 | if (ret) | |
1026 | return ret; | |
1027 | ||
334dbd69 EA |
1028 | return 0; |
1029 | } | |
1030 | ||
b9f19259 BB |
1031 | static void vc4_cleanup_fb(struct drm_plane *plane, |
1032 | struct drm_plane_state *state) | |
1033 | { | |
1034 | struct vc4_bo *bo; | |
1035 | ||
1036 | if (plane->state->fb == state->fb || !state->fb) | |
1037 | return; | |
1038 | ||
1039 | bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); | |
1040 | vc4_bo_dec_usecnt(bo); | |
1041 | } | |
1042 | ||
c8b75bca | 1043 | static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { |
c8b75bca EA |
1044 | .atomic_check = vc4_plane_atomic_check, |
1045 | .atomic_update = vc4_plane_atomic_update, | |
334dbd69 | 1046 | .prepare_fb = vc4_prepare_fb, |
b9f19259 | 1047 | .cleanup_fb = vc4_cleanup_fb, |
539c320b GP |
1048 | .atomic_async_check = vc4_plane_atomic_async_check, |
1049 | .atomic_async_update = vc4_plane_atomic_async_update, | |
c8b75bca EA |
1050 | }; |
1051 | ||
1052 | static void vc4_plane_destroy(struct drm_plane *plane) | |
1053 | { | |
c8b75bca EA |
1054 | drm_plane_cleanup(plane); |
1055 | } | |
1056 | ||
423ad7b3 DS |
1057 | static bool vc4_format_mod_supported(struct drm_plane *plane, |
1058 | uint32_t format, | |
1059 | uint64_t modifier) | |
1060 | { | |
1061 | /* Support T_TILING for RGB formats only. */ | |
1062 | switch (format) { | |
1063 | case DRM_FORMAT_XRGB8888: | |
1064 | case DRM_FORMAT_ARGB8888: | |
1065 | case DRM_FORMAT_ABGR8888: | |
1066 | case DRM_FORMAT_XBGR8888: | |
1067 | case DRM_FORMAT_RGB565: | |
1068 | case DRM_FORMAT_BGR565: | |
1069 | case DRM_FORMAT_ARGB1555: | |
1070 | case DRM_FORMAT_XRGB1555: | |
e065a8dd DS |
1071 | switch (fourcc_mod_broadcom_mod(modifier)) { |
1072 | case DRM_FORMAT_MOD_LINEAR: | |
1073 | case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: | |
1074 | case DRM_FORMAT_MOD_BROADCOM_SAND64: | |
1075 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
1076 | return true; | |
1077 | default: | |
1078 | return false; | |
1079 | } | |
1080 | case DRM_FORMAT_NV12: | |
1081 | case DRM_FORMAT_NV21: | |
1082 | switch (fourcc_mod_broadcom_mod(modifier)) { | |
1083 | case DRM_FORMAT_MOD_LINEAR: | |
1084 | case DRM_FORMAT_MOD_BROADCOM_SAND64: | |
1085 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
1086 | case DRM_FORMAT_MOD_BROADCOM_SAND256: | |
1087 | return true; | |
1088 | default: | |
1089 | return false; | |
1090 | } | |
423ad7b3 DS |
1091 | case DRM_FORMAT_YUV422: |
1092 | case DRM_FORMAT_YVU422: | |
1093 | case DRM_FORMAT_YUV420: | |
1094 | case DRM_FORMAT_YVU420: | |
423ad7b3 | 1095 | case DRM_FORMAT_NV16: |
1e871d65 | 1096 | case DRM_FORMAT_NV61: |
423ad7b3 DS |
1097 | default: |
1098 | return (modifier == DRM_FORMAT_MOD_LINEAR); | |
1099 | } | |
1100 | } | |
1101 | ||
c8b75bca | 1102 | static const struct drm_plane_funcs vc4_plane_funcs = { |
539c320b | 1103 | .update_plane = drm_atomic_helper_update_plane, |
c8b75bca EA |
1104 | .disable_plane = drm_atomic_helper_disable_plane, |
1105 | .destroy = vc4_plane_destroy, | |
1106 | .set_property = NULL, | |
1107 | .reset = vc4_plane_reset, | |
1108 | .atomic_duplicate_state = vc4_plane_duplicate_state, | |
1109 | .atomic_destroy_state = vc4_plane_destroy_state, | |
423ad7b3 | 1110 | .format_mod_supported = vc4_format_mod_supported, |
c8b75bca EA |
1111 | }; |
1112 | ||
1113 | struct drm_plane *vc4_plane_init(struct drm_device *dev, | |
1114 | enum drm_plane_type type) | |
1115 | { | |
1116 | struct drm_plane *plane = NULL; | |
1117 | struct vc4_plane *vc4_plane; | |
1118 | u32 formats[ARRAY_SIZE(hvs_formats)]; | |
1119 | int ret = 0; | |
1120 | unsigned i; | |
423ad7b3 DS |
1121 | static const uint64_t modifiers[] = { |
1122 | DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, | |
e065a8dd DS |
1123 | DRM_FORMAT_MOD_BROADCOM_SAND128, |
1124 | DRM_FORMAT_MOD_BROADCOM_SAND64, | |
1125 | DRM_FORMAT_MOD_BROADCOM_SAND256, | |
423ad7b3 DS |
1126 | DRM_FORMAT_MOD_LINEAR, |
1127 | DRM_FORMAT_MOD_INVALID | |
1128 | }; | |
c8b75bca EA |
1129 | |
1130 | vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane), | |
1131 | GFP_KERNEL); | |
7b347348 CIK |
1132 | if (!vc4_plane) |
1133 | return ERR_PTR(-ENOMEM); | |
c8b75bca | 1134 | |
2c2853f7 BB |
1135 | for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) |
1136 | formats[i] = hvs_formats[i].drm; | |
1137 | ||
c8b75bca | 1138 | plane = &vc4_plane->base; |
49d29a07 | 1139 | ret = drm_universal_plane_init(dev, plane, 0, |
c8b75bca | 1140 | &vc4_plane_funcs, |
2c2853f7 | 1141 | formats, ARRAY_SIZE(formats), |
423ad7b3 | 1142 | modifiers, type, NULL); |
c8b75bca EA |
1143 | |
1144 | drm_plane_helper_add(plane, &vc4_plane_helper_funcs); | |
1145 | ||
22445f03 SS |
1146 | drm_plane_create_alpha_property(plane); |
1147 | ||
c8b75bca | 1148 | return plane; |
c8b75bca | 1149 | } |