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Commit | Line | Data |
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c8b75bca EA |
1 | /* |
2 | * Copyright (C) 2015 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /** | |
10 | * DOC: VC4 plane module | |
11 | * | |
12 | * Each DRM plane is a layer of pixels being scanned out by the HVS. | |
13 | * | |
14 | * At atomic modeset check time, we compute the HVS display element | |
15 | * state that would be necessary for displaying the plane (giving us a | |
16 | * chance to figure out if a plane configuration is invalid), then at | |
17 | * atomic flush time the CRTC will ask us to write our element state | |
18 | * into the region of the HVS that it has allocated for us. | |
19 | */ | |
20 | ||
b7e8e25b MY |
21 | #include <drm/drm_atomic.h> |
22 | #include <drm/drm_atomic_helper.h> | |
72fdb40c | 23 | #include <drm/drm_atomic_uapi.h> |
fd6d6d80 SR |
24 | #include <drm/drm_fb_cma_helper.h> |
25 | #include <drm/drm_fourcc.h> | |
66ab7005 | 26 | #include <drm/drm_gem_framebuffer_helper.h> |
fd6d6d80 | 27 | #include <drm/drm_plane_helper.h> |
b7e8e25b | 28 | |
b9f19259 | 29 | #include "uapi/drm/vc4_drm.h" |
fd6d6d80 | 30 | |
c8b75bca EA |
31 | #include "vc4_drv.h" |
32 | #include "vc4_regs.h" | |
c8b75bca | 33 | |
c8b75bca EA |
34 | static const struct hvs_format { |
35 | u32 drm; /* DRM_FORMAT_* */ | |
36 | u32 hvs; /* HVS_FORMAT_* */ | |
37 | u32 pixel_order; | |
c8b75bca EA |
38 | } hvs_formats[] = { |
39 | { | |
40 | .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 41 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
c8b75bca EA |
42 | }, |
43 | { | |
44 | .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 45 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
c8b75bca | 46 | }, |
93977767 RH |
47 | { |
48 | .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 49 | .pixel_order = HVS_PIXEL_ORDER_ARGB, |
93977767 RH |
50 | }, |
51 | { | |
52 | .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, | |
124e5dac | 53 | .pixel_order = HVS_PIXEL_ORDER_ARGB, |
93977767 | 54 | }, |
fe4cd847 EA |
55 | { |
56 | .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565, | |
124e5dac | 57 | .pixel_order = HVS_PIXEL_ORDER_XRGB, |
fe4cd847 EA |
58 | }, |
59 | { | |
60 | .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565, | |
124e5dac | 61 | .pixel_order = HVS_PIXEL_ORDER_XBGR, |
fe4cd847 EA |
62 | }, |
63 | { | |
64 | .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, | |
124e5dac | 65 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
fe4cd847 EA |
66 | }, |
67 | { | |
68 | .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, | |
124e5dac | 69 | .pixel_order = HVS_PIXEL_ORDER_ABGR, |
fe4cd847 | 70 | }, |
88f8156f DS |
71 | { |
72 | .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888, | |
124e5dac | 73 | .pixel_order = HVS_PIXEL_ORDER_XRGB, |
88f8156f DS |
74 | }, |
75 | { | |
76 | .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888, | |
124e5dac | 77 | .pixel_order = HVS_PIXEL_ORDER_XBGR, |
88f8156f | 78 | }, |
fc04023f EA |
79 | { |
80 | .drm = DRM_FORMAT_YUV422, | |
81 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, | |
090cb0c6 | 82 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f EA |
83 | }, |
84 | { | |
85 | .drm = DRM_FORMAT_YVU422, | |
86 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, | |
090cb0c6 | 87 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, |
fc04023f EA |
88 | }, |
89 | { | |
90 | .drm = DRM_FORMAT_YUV420, | |
91 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, | |
090cb0c6 | 92 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f EA |
93 | }, |
94 | { | |
95 | .drm = DRM_FORMAT_YVU420, | |
96 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, | |
090cb0c6 | 97 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, |
fc04023f EA |
98 | }, |
99 | { | |
100 | .drm = DRM_FORMAT_NV12, | |
101 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, | |
090cb0c6 | 102 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f | 103 | }, |
cb20dd17 DS |
104 | { |
105 | .drm = DRM_FORMAT_NV21, | |
106 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, | |
107 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, | |
108 | }, | |
fc04023f EA |
109 | { |
110 | .drm = DRM_FORMAT_NV16, | |
111 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, | |
090cb0c6 | 112 | .pixel_order = HVS_PIXEL_ORDER_XYCBCR, |
fc04023f | 113 | }, |
cb20dd17 DS |
114 | { |
115 | .drm = DRM_FORMAT_NV61, | |
116 | .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, | |
117 | .pixel_order = HVS_PIXEL_ORDER_XYCRCB, | |
118 | }, | |
c8b75bca EA |
119 | }; |
120 | ||
121 | static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) | |
122 | { | |
123 | unsigned i; | |
124 | ||
125 | for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { | |
126 | if (hvs_formats[i].drm == drm_format) | |
127 | return &hvs_formats[i]; | |
128 | } | |
129 | ||
130 | return NULL; | |
131 | } | |
132 | ||
21af94cf EA |
133 | static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) |
134 | { | |
eb8dd3ab BB |
135 | if (dst == src) |
136 | return VC4_SCALING_NONE; | |
137 | if (3 * dst >= 2 * src) | |
21af94cf | 138 | return VC4_SCALING_PPF; |
21af94cf | 139 | else |
eb8dd3ab | 140 | return VC4_SCALING_TPZ; |
21af94cf EA |
141 | } |
142 | ||
c8b75bca EA |
143 | static bool plane_enabled(struct drm_plane_state *state) |
144 | { | |
145 | return state->fb && state->crtc; | |
146 | } | |
147 | ||
91276ae2 | 148 | static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) |
c8b75bca EA |
149 | { |
150 | struct vc4_plane_state *vc4_state; | |
151 | ||
152 | if (WARN_ON(!plane->state)) | |
153 | return NULL; | |
154 | ||
155 | vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); | |
156 | if (!vc4_state) | |
157 | return NULL; | |
158 | ||
21af94cf | 159 | memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); |
8d938449 | 160 | vc4_state->dlist_initialized = 0; |
21af94cf | 161 | |
c8b75bca EA |
162 | __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); |
163 | ||
164 | if (vc4_state->dlist) { | |
165 | vc4_state->dlist = kmemdup(vc4_state->dlist, | |
166 | vc4_state->dlist_count * 4, | |
167 | GFP_KERNEL); | |
168 | if (!vc4_state->dlist) { | |
169 | kfree(vc4_state); | |
170 | return NULL; | |
171 | } | |
172 | vc4_state->dlist_size = vc4_state->dlist_count; | |
173 | } | |
174 | ||
175 | return &vc4_state->base; | |
176 | } | |
177 | ||
91276ae2 | 178 | static void vc4_plane_destroy_state(struct drm_plane *plane, |
179 | struct drm_plane_state *state) | |
c8b75bca | 180 | { |
21af94cf | 181 | struct vc4_dev *vc4 = to_vc4_dev(plane->dev); |
c8b75bca EA |
182 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); |
183 | ||
21af94cf EA |
184 | if (vc4_state->lbm.allocated) { |
185 | unsigned long irqflags; | |
186 | ||
187 | spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); | |
188 | drm_mm_remove_node(&vc4_state->lbm); | |
189 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); | |
190 | } | |
191 | ||
c8b75bca | 192 | kfree(vc4_state->dlist); |
2f701695 | 193 | __drm_atomic_helper_plane_destroy_state(&vc4_state->base); |
c8b75bca EA |
194 | kfree(state); |
195 | } | |
196 | ||
197 | /* Called during init to allocate the plane's atomic state. */ | |
91276ae2 | 198 | static void vc4_plane_reset(struct drm_plane *plane) |
c8b75bca EA |
199 | { |
200 | struct vc4_plane_state *vc4_state; | |
201 | ||
202 | WARN_ON(plane->state); | |
203 | ||
204 | vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); | |
205 | if (!vc4_state) | |
206 | return; | |
207 | ||
42da6338 | 208 | __drm_atomic_helper_plane_reset(plane, &vc4_state->base); |
c8b75bca EA |
209 | } |
210 | ||
211 | static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) | |
212 | { | |
213 | if (vc4_state->dlist_count == vc4_state->dlist_size) { | |
214 | u32 new_size = max(4u, vc4_state->dlist_count * 2); | |
6da2ec56 | 215 | u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL); |
c8b75bca EA |
216 | |
217 | if (!new_dlist) | |
218 | return; | |
219 | memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); | |
220 | ||
221 | kfree(vc4_state->dlist); | |
222 | vc4_state->dlist = new_dlist; | |
223 | vc4_state->dlist_size = new_size; | |
224 | } | |
225 | ||
226 | vc4_state->dlist[vc4_state->dlist_count++] = val; | |
227 | } | |
228 | ||
21af94cf EA |
229 | /* Returns the scl0/scl1 field based on whether the dimensions need to |
230 | * be up/down/non-scaled. | |
231 | * | |
232 | * This is a replication of a table from the spec. | |
233 | */ | |
fc04023f | 234 | static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane) |
21af94cf EA |
235 | { |
236 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
237 | ||
fc04023f | 238 | switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) { |
21af94cf EA |
239 | case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF: |
240 | return SCALER_CTL0_SCL_H_PPF_V_PPF; | |
241 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF: | |
242 | return SCALER_CTL0_SCL_H_TPZ_V_PPF; | |
243 | case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ: | |
244 | return SCALER_CTL0_SCL_H_PPF_V_TPZ; | |
245 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ: | |
246 | return SCALER_CTL0_SCL_H_TPZ_V_TPZ; | |
247 | case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE: | |
248 | return SCALER_CTL0_SCL_H_PPF_V_NONE; | |
249 | case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF: | |
250 | return SCALER_CTL0_SCL_H_NONE_V_PPF; | |
251 | case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ: | |
252 | return SCALER_CTL0_SCL_H_NONE_V_TPZ; | |
253 | case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE: | |
254 | return SCALER_CTL0_SCL_H_TPZ_V_NONE; | |
255 | default: | |
256 | case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE: | |
257 | /* The unity case is independently handled by | |
258 | * SCALER_CTL0_UNITY. | |
259 | */ | |
260 | return 0; | |
261 | } | |
262 | } | |
263 | ||
666e7358 BB |
264 | static int vc4_plane_margins_adj(struct drm_plane_state *pstate) |
265 | { | |
266 | struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate); | |
267 | unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay; | |
268 | struct drm_crtc_state *crtc_state; | |
269 | ||
270 | crtc_state = drm_atomic_get_new_crtc_state(pstate->state, | |
271 | pstate->crtc); | |
272 | ||
273 | vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom); | |
274 | if (!left && !right && !top && !bottom) | |
275 | return 0; | |
276 | ||
277 | if (left + right >= crtc_state->mode.hdisplay || | |
278 | top + bottom >= crtc_state->mode.vdisplay) | |
279 | return -EINVAL; | |
280 | ||
281 | adjhdisplay = crtc_state->mode.hdisplay - (left + right); | |
282 | vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x * | |
283 | adjhdisplay, | |
284 | crtc_state->mode.hdisplay); | |
285 | vc4_pstate->crtc_x += left; | |
286 | if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left) | |
287 | vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left; | |
288 | ||
289 | adjvdisplay = crtc_state->mode.vdisplay - (top + bottom); | |
290 | vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y * | |
291 | adjvdisplay, | |
292 | crtc_state->mode.vdisplay); | |
293 | vc4_pstate->crtc_y += top; | |
294 | if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top) | |
295 | vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top; | |
296 | ||
297 | vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w * | |
298 | adjhdisplay, | |
299 | crtc_state->mode.hdisplay); | |
300 | vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h * | |
301 | adjvdisplay, | |
302 | crtc_state->mode.vdisplay); | |
303 | ||
304 | if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h) | |
305 | return -EINVAL; | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
5c679994 | 310 | static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) |
c8b75bca EA |
311 | { |
312 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
313 | struct drm_framebuffer *fb = state->fb; | |
fc04023f | 314 | struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); |
21af94cf | 315 | u32 subpixel_src_mask = (1 << 16) - 1; |
bcb0b461 | 316 | int num_planes = fb->format->num_planes; |
58a6a36f | 317 | struct drm_crtc_state *crtc_state; |
f3e9632c MR |
318 | u32 h_subsample = fb->format->hsub; |
319 | u32 v_subsample = fb->format->vsub; | |
58a6a36f BB |
320 | int i, ret; |
321 | ||
322 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, | |
323 | state->crtc); | |
324 | if (!crtc_state) { | |
325 | DRM_DEBUG_KMS("Invalid crtc state\n"); | |
326 | return -EINVAL; | |
327 | } | |
328 | ||
5dc416d9 BB |
329 | ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1, |
330 | INT_MAX, true, true); | |
58a6a36f BB |
331 | if (ret) |
332 | return ret; | |
333 | ||
fc04023f EA |
334 | for (i = 0; i < num_planes; i++) |
335 | vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; | |
5c679994 | 336 | |
21af94cf | 337 | /* We don't support subpixel source positioning for scaling. */ |
58a6a36f BB |
338 | if ((state->src.x1 & subpixel_src_mask) || |
339 | (state->src.x2 & subpixel_src_mask) || | |
340 | (state->src.y1 & subpixel_src_mask) || | |
341 | (state->src.y2 & subpixel_src_mask)) { | |
bf893acc EA |
342 | return -EINVAL; |
343 | } | |
344 | ||
58a6a36f BB |
345 | vc4_state->src_x = state->src.x1 >> 16; |
346 | vc4_state->src_y = state->src.y1 >> 16; | |
347 | vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16; | |
348 | vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16; | |
f863e356 | 349 | |
58a6a36f BB |
350 | vc4_state->crtc_x = state->dst.x1; |
351 | vc4_state->crtc_y = state->dst.y1; | |
352 | vc4_state->crtc_w = state->dst.x2 - state->dst.x1; | |
353 | vc4_state->crtc_h = state->dst.y2 - state->dst.y1; | |
f863e356 | 354 | |
666e7358 BB |
355 | ret = vc4_plane_margins_adj(state); |
356 | if (ret) | |
357 | return ret; | |
358 | ||
fc04023f EA |
359 | vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], |
360 | vc4_state->crtc_w); | |
361 | vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], | |
362 | vc4_state->crtc_h); | |
363 | ||
658d8cbd BB |
364 | vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE && |
365 | vc4_state->y_scaling[0] == VC4_SCALING_NONE); | |
366 | ||
fc04023f EA |
367 | if (num_planes > 1) { |
368 | vc4_state->is_yuv = true; | |
369 | ||
fc04023f EA |
370 | vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; |
371 | vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; | |
372 | ||
373 | vc4_state->x_scaling[1] = | |
374 | vc4_get_scaling_mode(vc4_state->src_w[1], | |
375 | vc4_state->crtc_w); | |
376 | vc4_state->y_scaling[1] = | |
377 | vc4_get_scaling_mode(vc4_state->src_h[1], | |
378 | vc4_state->crtc_h); | |
379 | ||
0560054d BB |
380 | /* YUV conversion requires that horizontal scaling be enabled |
381 | * on the UV plane even if vc4_get_scaling_mode() returned | |
382 | * VC4_SCALING_NONE (which can happen when the down-scaling | |
383 | * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this | |
384 | * case. | |
fc04023f | 385 | */ |
0560054d BB |
386 | if (vc4_state->x_scaling[1] == VC4_SCALING_NONE) |
387 | vc4_state->x_scaling[1] = VC4_SCALING_PPF; | |
a6a00918 | 388 | } else { |
2b02a05b | 389 | vc4_state->is_yuv = false; |
a6a00918 BB |
390 | vc4_state->x_scaling[1] = VC4_SCALING_NONE; |
391 | vc4_state->y_scaling[1] = VC4_SCALING_NONE; | |
fc04023f EA |
392 | } |
393 | ||
5c679994 EA |
394 | return 0; |
395 | } | |
396 | ||
21af94cf EA |
397 | static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst) |
398 | { | |
399 | u32 scale, recip; | |
400 | ||
401 | scale = (1 << 16) * src / dst; | |
402 | ||
403 | /* The specs note that while the reciprocal would be defined | |
404 | * as (1<<32)/scale, ~0 is close enough. | |
405 | */ | |
406 | recip = ~0 / scale; | |
407 | ||
408 | vc4_dlist_write(vc4_state, | |
409 | VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | | |
410 | VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); | |
411 | vc4_dlist_write(vc4_state, | |
412 | VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); | |
413 | } | |
414 | ||
415 | static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst) | |
416 | { | |
417 | u32 scale = (1 << 16) * src / dst; | |
418 | ||
419 | vc4_dlist_write(vc4_state, | |
420 | SCALER_PPF_AGC | | |
421 | VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | | |
422 | VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); | |
423 | } | |
424 | ||
425 | static u32 vc4_lbm_size(struct drm_plane_state *state) | |
426 | { | |
427 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
428 | /* This is the worst case number. One of the two sizes will | |
429 | * be used depending on the scaling configuration. | |
430 | */ | |
fc04023f | 431 | u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); |
21af94cf EA |
432 | u32 lbm; |
433 | ||
b2e554d4 BB |
434 | /* LBM is not needed when there's no vertical scaling. */ |
435 | if (vc4_state->y_scaling[0] == VC4_SCALING_NONE && | |
436 | vc4_state->y_scaling[1] == VC4_SCALING_NONE) | |
437 | return 0; | |
438 | ||
fc04023f | 439 | if (!vc4_state->is_yuv) { |
b2e554d4 | 440 | if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) |
fc04023f EA |
441 | lbm = pix_per_line * 8; |
442 | else { | |
443 | /* In special cases, this multiplier might be 12. */ | |
444 | lbm = pix_per_line * 16; | |
445 | } | |
446 | } else { | |
447 | /* There are cases for this going down to a multiplier | |
448 | * of 2, but according to the firmware source, the | |
449 | * table in the docs is somewhat wrong. | |
450 | */ | |
21af94cf EA |
451 | lbm = pix_per_line * 16; |
452 | } | |
453 | ||
454 | lbm = roundup(lbm, 32); | |
455 | ||
456 | return lbm; | |
457 | } | |
458 | ||
fc04023f EA |
459 | static void vc4_write_scaling_parameters(struct drm_plane_state *state, |
460 | int channel) | |
21af94cf EA |
461 | { |
462 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
463 | ||
464 | /* Ch0 H-PPF Word 0: Scaling Parameters */ | |
fc04023f | 465 | if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) { |
21af94cf | 466 | vc4_write_ppf(vc4_state, |
fc04023f | 467 | vc4_state->src_w[channel], vc4_state->crtc_w); |
21af94cf EA |
468 | } |
469 | ||
470 | /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */ | |
fc04023f | 471 | if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) { |
21af94cf | 472 | vc4_write_ppf(vc4_state, |
fc04023f | 473 | vc4_state->src_h[channel], vc4_state->crtc_h); |
21af94cf EA |
474 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); |
475 | } | |
476 | ||
477 | /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */ | |
fc04023f | 478 | if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) { |
21af94cf | 479 | vc4_write_tpz(vc4_state, |
fc04023f | 480 | vc4_state->src_w[channel], vc4_state->crtc_w); |
21af94cf EA |
481 | } |
482 | ||
483 | /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */ | |
fc04023f | 484 | if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) { |
21af94cf | 485 | vc4_write_tpz(vc4_state, |
fc04023f | 486 | vc4_state->src_h[channel], vc4_state->crtc_h); |
21af94cf EA |
487 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); |
488 | } | |
489 | } | |
5c679994 | 490 | |
4686da83 BB |
491 | static void vc4_plane_calc_load(struct drm_plane_state *state) |
492 | { | |
493 | unsigned int hvs_load_shift, vrefresh, i; | |
494 | struct drm_framebuffer *fb = state->fb; | |
495 | struct vc4_plane_state *vc4_state; | |
496 | struct drm_crtc_state *crtc_state; | |
497 | unsigned int vscale_factor; | |
498 | ||
499 | vc4_state = to_vc4_plane_state(state); | |
500 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, | |
501 | state->crtc); | |
502 | vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode); | |
503 | ||
504 | /* The HVS is able to process 2 pixels/cycle when scaling the source, | |
505 | * 4 pixels/cycle otherwise. | |
506 | * Alpha blending step seems to be pipelined and it's always operating | |
507 | * at 4 pixels/cycle, so the limiting aspect here seems to be the | |
508 | * scaler block. | |
509 | * HVS load is expressed in clk-cycles/sec (AKA Hz). | |
510 | */ | |
511 | if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || | |
512 | vc4_state->x_scaling[1] != VC4_SCALING_NONE || | |
513 | vc4_state->y_scaling[0] != VC4_SCALING_NONE || | |
514 | vc4_state->y_scaling[1] != VC4_SCALING_NONE) | |
515 | hvs_load_shift = 1; | |
516 | else | |
517 | hvs_load_shift = 2; | |
518 | ||
519 | vc4_state->membus_load = 0; | |
520 | vc4_state->hvs_load = 0; | |
521 | for (i = 0; i < fb->format->num_planes; i++) { | |
522 | /* Even if the bandwidth/plane required for a single frame is | |
523 | * | |
524 | * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh | |
525 | * | |
526 | * when downscaling, we have to read more pixels per line in | |
527 | * the time frame reserved for a single line, so the bandwidth | |
528 | * demand can be punctually higher. To account for that, we | |
529 | * calculate the down-scaling factor and multiply the plane | |
530 | * load by this number. We're likely over-estimating the read | |
531 | * demand, but that's better than under-estimating it. | |
532 | */ | |
533 | vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i], | |
534 | vc4_state->crtc_h); | |
535 | vc4_state->membus_load += vc4_state->src_w[i] * | |
536 | vc4_state->src_h[i] * vscale_factor * | |
537 | fb->format->cpp[i]; | |
538 | vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; | |
539 | } | |
540 | ||
541 | vc4_state->hvs_load *= vrefresh; | |
542 | vc4_state->hvs_load >>= hvs_load_shift; | |
543 | vc4_state->membus_load *= vrefresh; | |
544 | } | |
545 | ||
0a038c1c BB |
546 | static int vc4_plane_allocate_lbm(struct drm_plane_state *state) |
547 | { | |
548 | struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev); | |
549 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
550 | unsigned long irqflags; | |
551 | u32 lbm_size; | |
552 | ||
553 | lbm_size = vc4_lbm_size(state); | |
554 | if (!lbm_size) | |
555 | return 0; | |
556 | ||
557 | if (WARN_ON(!vc4_state->lbm_offset)) | |
558 | return -EINVAL; | |
559 | ||
560 | /* Allocate the LBM memory that the HVS will use for temporary | |
561 | * storage due to our scaling/format conversion. | |
562 | */ | |
563 | if (!vc4_state->lbm.allocated) { | |
564 | int ret; | |
565 | ||
566 | spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); | |
567 | ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, | |
568 | &vc4_state->lbm, | |
569 | lbm_size, 32, 0, 0); | |
570 | spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); | |
571 | ||
572 | if (ret) | |
573 | return ret; | |
574 | } else { | |
575 | WARN_ON_ONCE(lbm_size != vc4_state->lbm.size); | |
576 | } | |
577 | ||
578 | vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start; | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
5c679994 EA |
583 | /* Writes out a full display list for an active plane to the plane's |
584 | * private dlist state. | |
585 | */ | |
586 | static int vc4_plane_mode_set(struct drm_plane *plane, | |
587 | struct drm_plane_state *state) | |
588 | { | |
21af94cf | 589 | struct vc4_dev *vc4 = to_vc4_dev(plane->dev); |
5c679994 EA |
590 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); |
591 | struct drm_framebuffer *fb = state->fb; | |
5c679994 | 592 | u32 ctl0_offset = vc4_state->dlist_count; |
438b74a5 | 593 | const struct hvs_format *format = vc4_get_hvs_format(fb->format->format); |
e065a8dd | 594 | u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier); |
05c452c1 | 595 | int num_planes = fb->format->num_planes; |
f3e9632c MR |
596 | u32 h_subsample = fb->format->hsub; |
597 | u32 v_subsample = fb->format->vsub; | |
22445f03 | 598 | bool mix_plane_alpha; |
3d67b68a | 599 | bool covers_screen; |
98830d91 | 600 | u32 scl0, scl1, pitch0; |
7cd3cf35 | 601 | u32 tiling, src_y; |
e065a8dd | 602 | u32 hvs_format = format->hvs; |
7cd3cf35 | 603 | unsigned int rotation; |
fc04023f | 604 | int ret, i; |
5c679994 | 605 | |
8d938449 BB |
606 | if (vc4_state->dlist_initialized) |
607 | return 0; | |
608 | ||
5c679994 | 609 | ret = vc4_plane_setup_clipping_and_scaling(state); |
21af94cf EA |
610 | if (ret) |
611 | return ret; | |
612 | ||
fc04023f EA |
613 | /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB |
614 | * and 4:4:4, scl1 should be set to scl0 so both channels of | |
615 | * the scaler do the same thing. For YUV, the Y plane needs | |
616 | * to be put in channel 1 and Cb/Cr in channel 0, so we swap | |
617 | * the scl fields here. | |
618 | */ | |
619 | if (num_planes == 1) { | |
9a0e9802 | 620 | scl0 = vc4_get_scl_field(state, 0); |
fc04023f EA |
621 | scl1 = scl0; |
622 | } else { | |
623 | scl0 = vc4_get_scl_field(state, 1); | |
624 | scl1 = vc4_get_scl_field(state, 0); | |
625 | } | |
21af94cf | 626 | |
7cd3cf35 BB |
627 | rotation = drm_rotation_simplify(state->rotation, |
628 | DRM_MODE_ROTATE_0 | | |
629 | DRM_MODE_REFLECT_X | | |
630 | DRM_MODE_REFLECT_Y); | |
631 | ||
632 | /* We must point to the last line when Y reflection is enabled. */ | |
633 | src_y = vc4_state->src_y; | |
634 | if (rotation & DRM_MODE_REFLECT_Y) | |
635 | src_y += vc4_state->src_h[0] - 1; | |
636 | ||
e065a8dd | 637 | switch (base_format_mod) { |
98830d91 EA |
638 | case DRM_FORMAT_MOD_LINEAR: |
639 | tiling = SCALER_CTL0_TILING_LINEAR; | |
640 | pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); | |
a65511b1 BB |
641 | |
642 | /* Adjust the base pointer to the first pixel to be scanned | |
643 | * out. | |
644 | */ | |
645 | for (i = 0; i < num_planes; i++) { | |
7cd3cf35 | 646 | vc4_state->offsets[i] += src_y / |
a65511b1 BB |
647 | (i ? v_subsample : 1) * |
648 | fb->pitches[i]; | |
7cd3cf35 | 649 | |
a65511b1 BB |
650 | vc4_state->offsets[i] += vc4_state->src_x / |
651 | (i ? h_subsample : 1) * | |
652 | fb->format->cpp[i]; | |
653 | } | |
3e407417 | 654 | |
98830d91 | 655 | break; |
652badb9 EA |
656 | |
657 | case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { | |
652badb9 | 658 | u32 tile_size_shift = 12; /* T tiles are 4kb */ |
3e407417 BB |
659 | /* Whole-tile offsets, mostly for setting the pitch. */ |
660 | u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5; | |
652badb9 | 661 | u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ |
3e407417 BB |
662 | u32 tile_w_mask = (1 << tile_w_shift) - 1; |
663 | /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice | |
664 | * the height (in pixels) of a 4k tile. | |
665 | */ | |
666 | u32 tile_h_mask = (2 << tile_h_shift) - 1; | |
667 | /* For T-tiled, the FB pitch is "how many bytes from one row to | |
668 | * the next, such that | |
669 | * | |
670 | * pitch * tile_h == tile_size * tiles_per_row | |
671 | */ | |
652badb9 | 672 | u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); |
3e407417 BB |
673 | u32 tiles_l = vc4_state->src_x >> tile_w_shift; |
674 | u32 tiles_r = tiles_w - tiles_l; | |
7cd3cf35 | 675 | u32 tiles_t = src_y >> tile_h_shift; |
3e407417 BB |
676 | /* Intra-tile offsets, which modify the base address (the |
677 | * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that | |
678 | * base address). | |
679 | */ | |
7cd3cf35 BB |
680 | u32 tile_y = (src_y >> 4) & 1; |
681 | u32 subtile_y = (src_y >> 2) & 3; | |
682 | u32 utile_y = src_y & 3; | |
3e407417 | 683 | u32 x_off = vc4_state->src_x & tile_w_mask; |
7cd3cf35 BB |
684 | u32 y_off = src_y & tile_h_mask; |
685 | ||
686 | /* When Y reflection is requested we must set the | |
687 | * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines | |
688 | * after the initial one should be fetched in descending order, | |
689 | * which makes sense since we start from the last line and go | |
690 | * backward. | |
691 | * Don't know why we need y_off = max_y_off - y_off, but it's | |
692 | * definitely required (I guess it's also related to the "going | |
693 | * backward" situation). | |
694 | */ | |
695 | if (rotation & DRM_MODE_REFLECT_Y) { | |
696 | y_off = tile_h_mask - y_off; | |
697 | pitch0 = SCALER_PITCH0_TILE_LINE_DIR; | |
698 | } else { | |
699 | pitch0 = 0; | |
700 | } | |
652badb9 | 701 | |
98830d91 | 702 | tiling = SCALER_CTL0_TILING_256B_OR_T; |
7cd3cf35 BB |
703 | pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | |
704 | VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | | |
705 | VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | | |
706 | VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); | |
3e407417 BB |
707 | vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift); |
708 | vc4_state->offsets[0] += subtile_y << 8; | |
709 | vc4_state->offsets[0] += utile_y << 4; | |
710 | ||
711 | /* Rows of tiles alternate left-to-right and right-to-left. */ | |
712 | if (tiles_t & 1) { | |
713 | pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR; | |
714 | vc4_state->offsets[0] += (tiles_w - tiles_l) << | |
715 | tile_size_shift; | |
716 | vc4_state->offsets[0] -= (1 + !tile_y) << 10; | |
717 | } else { | |
718 | vc4_state->offsets[0] += tiles_l << tile_size_shift; | |
719 | vc4_state->offsets[0] += tile_y << 10; | |
720 | } | |
98830d91 | 721 | |
98830d91 | 722 | break; |
652badb9 EA |
723 | } |
724 | ||
e065a8dd DS |
725 | case DRM_FORMAT_MOD_BROADCOM_SAND64: |
726 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
727 | case DRM_FORMAT_MOD_BROADCOM_SAND256: { | |
728 | uint32_t param = fourcc_mod_broadcom_param(fb->modifier); | |
8e75d582 | 729 | u32 tile_w, tile, x_off, pix_per_tile; |
e065a8dd | 730 | |
0ea3305d | 731 | hvs_format = HVS_PIXEL_FORMAT_H264; |
e065a8dd DS |
732 | |
733 | switch (base_format_mod) { | |
734 | case DRM_FORMAT_MOD_BROADCOM_SAND64: | |
735 | tiling = SCALER_CTL0_TILING_64B; | |
8e75d582 | 736 | tile_w = 64; |
e065a8dd DS |
737 | break; |
738 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
739 | tiling = SCALER_CTL0_TILING_128B; | |
8e75d582 | 740 | tile_w = 128; |
e065a8dd DS |
741 | break; |
742 | case DRM_FORMAT_MOD_BROADCOM_SAND256: | |
743 | tiling = SCALER_CTL0_TILING_256B_OR_T; | |
8e75d582 | 744 | tile_w = 256; |
e065a8dd DS |
745 | break; |
746 | default: | |
747 | break; | |
748 | } | |
749 | ||
750 | if (param > SCALER_TILE_HEIGHT_MASK) { | |
751 | DRM_DEBUG_KMS("SAND height too large (%d)\n", param); | |
752 | return -EINVAL; | |
753 | } | |
754 | ||
8e75d582 BB |
755 | pix_per_tile = tile_w / fb->format->cpp[0]; |
756 | tile = vc4_state->src_x / pix_per_tile; | |
757 | x_off = vc4_state->src_x % pix_per_tile; | |
758 | ||
759 | /* Adjust the base pointer to the first pixel to be scanned | |
760 | * out. | |
761 | */ | |
762 | for (i = 0; i < num_planes; i++) { | |
763 | vc4_state->offsets[i] += param * tile_w * tile; | |
7cd3cf35 | 764 | vc4_state->offsets[i] += src_y / |
8e75d582 BB |
765 | (i ? v_subsample : 1) * |
766 | tile_w; | |
767 | vc4_state->offsets[i] += x_off / | |
768 | (i ? h_subsample : 1) * | |
769 | fb->format->cpp[i]; | |
770 | } | |
771 | ||
e065a8dd DS |
772 | pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); |
773 | break; | |
774 | } | |
775 | ||
98830d91 EA |
776 | default: |
777 | DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", | |
778 | (long long)fb->modifier); | |
779 | return -EINVAL; | |
780 | } | |
781 | ||
21af94cf | 782 | /* Control word */ |
c8b75bca EA |
783 | vc4_dlist_write(vc4_state, |
784 | SCALER_CTL0_VALID | | |
7cd3cf35 BB |
785 | (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) | |
786 | (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) | | |
3257ec79 | 787 | VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | |
c8b75bca | 788 | (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | |
e065a8dd | 789 | (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | |
98830d91 | 790 | VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | |
21af94cf | 791 | (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) | |
fc04023f EA |
792 | VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | |
793 | VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); | |
c8b75bca EA |
794 | |
795 | /* Position Word 0: Image Positions and Alpha Value */ | |
6674a904 | 796 | vc4_state->pos0_offset = vc4_state->dlist_count; |
c8b75bca | 797 | vc4_dlist_write(vc4_state, |
22445f03 | 798 | VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | |
5c679994 EA |
799 | VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | |
800 | VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); | |
c8b75bca | 801 | |
21af94cf EA |
802 | /* Position Word 1: Scaled Image Dimensions. */ |
803 | if (!vc4_state->is_unity) { | |
804 | vc4_dlist_write(vc4_state, | |
805 | VC4_SET_FIELD(vc4_state->crtc_w, | |
806 | SCALER_POS1_SCL_WIDTH) | | |
807 | VC4_SET_FIELD(vc4_state->crtc_h, | |
808 | SCALER_POS1_SCL_HEIGHT)); | |
809 | } | |
c8b75bca | 810 | |
22445f03 SS |
811 | /* Don't waste cycles mixing with plane alpha if the set alpha |
812 | * is opaque or there is no per-pixel alpha information. | |
813 | * In any case we use the alpha property value as the fixed alpha. | |
814 | */ | |
815 | mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE && | |
816 | fb->format->has_alpha; | |
817 | ||
05202c24 | 818 | /* Position Word 2: Source Image Size, Alpha */ |
6674a904 | 819 | vc4_state->pos2_offset = vc4_state->dlist_count; |
c8b75bca | 820 | vc4_dlist_write(vc4_state, |
124e5dac | 821 | VC4_SET_FIELD(fb->format->has_alpha ? |
c8b75bca EA |
822 | SCALER_POS2_ALPHA_MODE_PIPELINE : |
823 | SCALER_POS2_ALPHA_MODE_FIXED, | |
824 | SCALER_POS2_ALPHA_MODE) | | |
22445f03 | 825 | (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | |
05202c24 | 826 | (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) | |
fc04023f EA |
827 | VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) | |
828 | VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); | |
c8b75bca EA |
829 | |
830 | /* Position Word 3: Context. Written by the HVS. */ | |
831 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); | |
832 | ||
fc04023f EA |
833 | |
834 | /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers | |
835 | * | |
836 | * The pointers may be any byte address. | |
837 | */ | |
6674a904 | 838 | vc4_state->ptr0_offset = vc4_state->dlist_count; |
090cb0c6 DS |
839 | for (i = 0; i < num_planes; i++) |
840 | vc4_dlist_write(vc4_state, vc4_state->offsets[i]); | |
c8b75bca | 841 | |
fc04023f EA |
842 | /* Pointer Context Word 0/1/2: Written by the HVS */ |
843 | for (i = 0; i < num_planes; i++) | |
844 | vc4_dlist_write(vc4_state, 0xc0c0c0c0); | |
c8b75bca | 845 | |
98830d91 EA |
846 | /* Pitch word 0 */ |
847 | vc4_dlist_write(vc4_state, pitch0); | |
848 | ||
849 | /* Pitch word 1/2 */ | |
850 | for (i = 1; i < num_planes; i++) { | |
e065a8dd DS |
851 | if (hvs_format != HVS_PIXEL_FORMAT_H264) { |
852 | vc4_dlist_write(vc4_state, | |
853 | VC4_SET_FIELD(fb->pitches[i], | |
854 | SCALER_SRC_PITCH)); | |
855 | } else { | |
856 | vc4_dlist_write(vc4_state, pitch0); | |
857 | } | |
fc04023f EA |
858 | } |
859 | ||
860 | /* Colorspace conversion words */ | |
861 | if (vc4_state->is_yuv) { | |
862 | vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5); | |
863 | vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5); | |
864 | vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5); | |
865 | } | |
c8b75bca | 866 | |
0a038c1c BB |
867 | vc4_state->lbm_offset = 0; |
868 | ||
658d8cbd BB |
869 | if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || |
870 | vc4_state->x_scaling[1] != VC4_SCALING_NONE || | |
871 | vc4_state->y_scaling[0] != VC4_SCALING_NONE || | |
872 | vc4_state->y_scaling[1] != VC4_SCALING_NONE) { | |
0a038c1c BB |
873 | /* Reserve a slot for the LBM Base Address. The real value will |
874 | * be set when calling vc4_plane_allocate_lbm(). | |
875 | */ | |
fc04023f | 876 | if (vc4_state->y_scaling[0] != VC4_SCALING_NONE || |
0a038c1c BB |
877 | vc4_state->y_scaling[1] != VC4_SCALING_NONE) |
878 | vc4_state->lbm_offset = vc4_state->dlist_count++; | |
21af94cf | 879 | |
fc04023f EA |
880 | if (num_planes > 1) { |
881 | /* Emit Cb/Cr as channel 0 and Y as channel | |
882 | * 1. This matches how we set up scl0/scl1 | |
883 | * above. | |
884 | */ | |
885 | vc4_write_scaling_parameters(state, 1); | |
886 | } | |
887 | vc4_write_scaling_parameters(state, 0); | |
21af94cf EA |
888 | |
889 | /* If any PPF setup was done, then all the kernel | |
890 | * pointers get uploaded. | |
891 | */ | |
fc04023f EA |
892 | if (vc4_state->x_scaling[0] == VC4_SCALING_PPF || |
893 | vc4_state->y_scaling[0] == VC4_SCALING_PPF || | |
894 | vc4_state->x_scaling[1] == VC4_SCALING_PPF || | |
895 | vc4_state->y_scaling[1] == VC4_SCALING_PPF) { | |
21af94cf EA |
896 | u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, |
897 | SCALER_PPF_KERNEL_OFFSET); | |
898 | ||
899 | /* HPPF plane 0 */ | |
900 | vc4_dlist_write(vc4_state, kernel); | |
901 | /* VPPF plane 0 */ | |
902 | vc4_dlist_write(vc4_state, kernel); | |
903 | /* HPPF plane 1 */ | |
904 | vc4_dlist_write(vc4_state, kernel); | |
905 | /* VPPF plane 1 */ | |
906 | vc4_dlist_write(vc4_state, kernel); | |
907 | } | |
908 | } | |
909 | ||
c8b75bca EA |
910 | vc4_state->dlist[ctl0_offset] |= |
911 | VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); | |
912 | ||
3d67b68a SS |
913 | /* crtc_* are already clipped coordinates. */ |
914 | covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 && | |
915 | vc4_state->crtc_w == state->crtc->mode.hdisplay && | |
916 | vc4_state->crtc_h == state->crtc->mode.vdisplay; | |
917 | /* Background fill might be necessary when the plane has per-pixel | |
22445f03 SS |
918 | * alpha content or a non-opaque plane alpha and could blend from the |
919 | * background or does not cover the entire screen. | |
3d67b68a | 920 | */ |
22445f03 SS |
921 | vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen || |
922 | state->alpha != DRM_BLEND_ALPHA_OPAQUE; | |
3d67b68a | 923 | |
8d938449 BB |
924 | /* Flag the dlist as initialized to avoid checking it twice in case |
925 | * the async update check already called vc4_plane_mode_set() and | |
926 | * decided to fallback to sync update because async update was not | |
927 | * possible. | |
928 | */ | |
929 | vc4_state->dlist_initialized = 1; | |
930 | ||
4686da83 BB |
931 | vc4_plane_calc_load(state); |
932 | ||
c8b75bca EA |
933 | return 0; |
934 | } | |
935 | ||
936 | /* If a modeset involves changing the setup of a plane, the atomic | |
937 | * infrastructure will call this to validate a proposed plane setup. | |
938 | * However, if a plane isn't getting updated, this (and the | |
939 | * corresponding vc4_plane_atomic_update) won't get called. Thus, we | |
940 | * compute the dlist here and have all active plane dlists get updated | |
941 | * in the CRTC's flush. | |
942 | */ | |
943 | static int vc4_plane_atomic_check(struct drm_plane *plane, | |
944 | struct drm_plane_state *state) | |
945 | { | |
946 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); | |
0a038c1c | 947 | int ret; |
c8b75bca EA |
948 | |
949 | vc4_state->dlist_count = 0; | |
950 | ||
0a038c1c | 951 | if (!plane_enabled(state)) |
c8b75bca | 952 | return 0; |
0a038c1c BB |
953 | |
954 | ret = vc4_plane_mode_set(plane, state); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | return vc4_plane_allocate_lbm(state); | |
c8b75bca EA |
959 | } |
960 | ||
961 | static void vc4_plane_atomic_update(struct drm_plane *plane, | |
962 | struct drm_plane_state *old_state) | |
963 | { | |
964 | /* No contents here. Since we don't know where in the CRTC's | |
965 | * dlist we should be stored, our dlist is uploaded to the | |
966 | * hardware with vc4_plane_write_dlist() at CRTC atomic_flush | |
967 | * time. | |
968 | */ | |
969 | } | |
970 | ||
971 | u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) | |
972 | { | |
973 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); | |
974 | int i; | |
975 | ||
b501bacc EA |
976 | vc4_state->hw_dlist = dlist; |
977 | ||
c8b75bca EA |
978 | /* Can't memcpy_toio() because it needs to be 32-bit writes. */ |
979 | for (i = 0; i < vc4_state->dlist_count; i++) | |
980 | writel(vc4_state->dlist[i], &dlist[i]); | |
981 | ||
982 | return vc4_state->dlist_count; | |
983 | } | |
984 | ||
2f196b7c | 985 | u32 vc4_plane_dlist_size(const struct drm_plane_state *state) |
c8b75bca | 986 | { |
2f196b7c DV |
987 | const struct vc4_plane_state *vc4_state = |
988 | container_of(state, typeof(*vc4_state), base); | |
c8b75bca EA |
989 | |
990 | return vc4_state->dlist_count; | |
991 | } | |
992 | ||
b501bacc EA |
993 | /* Updates the plane to immediately (well, once the FIFO needs |
994 | * refilling) scan out from at a new framebuffer. | |
995 | */ | |
996 | void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) | |
997 | { | |
998 | struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); | |
999 | struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); | |
1000 | uint32_t addr; | |
1001 | ||
1002 | /* We're skipping the address adjustment for negative origin, | |
1003 | * because this is only called on the primary plane. | |
1004 | */ | |
1005 | WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0); | |
1006 | addr = bo->paddr + fb->offsets[0]; | |
1007 | ||
1008 | /* Write the new address into the hardware immediately. The | |
1009 | * scanout will start from this address as soon as the FIFO | |
1010 | * needs to refill with pixels. | |
1011 | */ | |
6674a904 | 1012 | writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]); |
b501bacc EA |
1013 | |
1014 | /* Also update the CPU-side dlist copy, so that any later | |
1015 | * atomic updates that don't do a new modeset on our plane | |
1016 | * also use our updated address. | |
1017 | */ | |
6674a904 | 1018 | vc4_state->dlist[vc4_state->ptr0_offset] = addr; |
b501bacc EA |
1019 | } |
1020 | ||
539c320b GP |
1021 | static void vc4_plane_atomic_async_update(struct drm_plane *plane, |
1022 | struct drm_plane_state *state) | |
1023 | { | |
5a43911f | 1024 | struct vc4_plane_state *vc4_state, *new_vc4_state; |
539c320b | 1025 | |
c16b8555 | 1026 | swap(plane->state->fb, state->fb); |
539c320b GP |
1027 | plane->state->crtc_x = state->crtc_x; |
1028 | plane->state->crtc_y = state->crtc_y; | |
1d4118ca BB |
1029 | plane->state->crtc_w = state->crtc_w; |
1030 | plane->state->crtc_h = state->crtc_h; | |
539c320b GP |
1031 | plane->state->src_x = state->src_x; |
1032 | plane->state->src_y = state->src_y; | |
1d4118ca BB |
1033 | plane->state->src_w = state->src_w; |
1034 | plane->state->src_h = state->src_h; | |
1035 | plane->state->src_h = state->src_h; | |
1036 | plane->state->alpha = state->alpha; | |
1037 | plane->state->pixel_blend_mode = state->pixel_blend_mode; | |
1038 | plane->state->rotation = state->rotation; | |
1039 | plane->state->zpos = state->zpos; | |
1040 | plane->state->normalized_zpos = state->normalized_zpos; | |
1041 | plane->state->color_encoding = state->color_encoding; | |
1042 | plane->state->color_range = state->color_range; | |
1043 | plane->state->src = state->src; | |
1044 | plane->state->dst = state->dst; | |
1045 | plane->state->visible = state->visible; | |
5a43911f BB |
1046 | |
1047 | new_vc4_state = to_vc4_plane_state(state); | |
1048 | vc4_state = to_vc4_plane_state(plane->state); | |
1049 | ||
1d4118ca BB |
1050 | vc4_state->crtc_x = new_vc4_state->crtc_x; |
1051 | vc4_state->crtc_y = new_vc4_state->crtc_y; | |
1052 | vc4_state->crtc_h = new_vc4_state->crtc_h; | |
1053 | vc4_state->crtc_w = new_vc4_state->crtc_w; | |
1054 | vc4_state->src_x = new_vc4_state->src_x; | |
1055 | vc4_state->src_y = new_vc4_state->src_y; | |
1056 | memcpy(vc4_state->src_w, new_vc4_state->src_w, | |
1057 | sizeof(vc4_state->src_w)); | |
1058 | memcpy(vc4_state->src_h, new_vc4_state->src_h, | |
1059 | sizeof(vc4_state->src_h)); | |
1060 | memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling, | |
1061 | sizeof(vc4_state->x_scaling)); | |
1062 | memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling, | |
1063 | sizeof(vc4_state->y_scaling)); | |
1064 | vc4_state->is_unity = new_vc4_state->is_unity; | |
1065 | vc4_state->is_yuv = new_vc4_state->is_yuv; | |
1066 | memcpy(vc4_state->offsets, new_vc4_state->offsets, | |
1067 | sizeof(vc4_state->offsets)); | |
1068 | vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill; | |
1069 | ||
5a43911f BB |
1070 | /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */ |
1071 | vc4_state->dlist[vc4_state->pos0_offset] = | |
1072 | new_vc4_state->dlist[vc4_state->pos0_offset]; | |
1073 | vc4_state->dlist[vc4_state->pos2_offset] = | |
1074 | new_vc4_state->dlist[vc4_state->pos2_offset]; | |
1075 | vc4_state->dlist[vc4_state->ptr0_offset] = | |
1076 | new_vc4_state->dlist[vc4_state->ptr0_offset]; | |
539c320b GP |
1077 | |
1078 | /* Note that we can't just call vc4_plane_write_dlist() | |
1079 | * because that would smash the context data that the HVS is | |
1080 | * currently using. | |
1081 | */ | |
1082 | writel(vc4_state->dlist[vc4_state->pos0_offset], | |
1083 | &vc4_state->hw_dlist[vc4_state->pos0_offset]); | |
1084 | writel(vc4_state->dlist[vc4_state->pos2_offset], | |
1085 | &vc4_state->hw_dlist[vc4_state->pos2_offset]); | |
1086 | writel(vc4_state->dlist[vc4_state->ptr0_offset], | |
1087 | &vc4_state->hw_dlist[vc4_state->ptr0_offset]); | |
1088 | } | |
1089 | ||
1090 | static int vc4_plane_atomic_async_check(struct drm_plane *plane, | |
1091 | struct drm_plane_state *state) | |
1092 | { | |
1d4118ca BB |
1093 | struct vc4_plane_state *old_vc4_state, *new_vc4_state; |
1094 | int ret; | |
1095 | u32 i; | |
1096 | ||
1097 | ret = vc4_plane_mode_set(plane, state); | |
1098 | if (ret) | |
1099 | return ret; | |
1100 | ||
1101 | old_vc4_state = to_vc4_plane_state(plane->state); | |
1102 | new_vc4_state = to_vc4_plane_state(state); | |
1103 | if (old_vc4_state->dlist_count != new_vc4_state->dlist_count || | |
1104 | old_vc4_state->pos0_offset != new_vc4_state->pos0_offset || | |
1105 | old_vc4_state->pos2_offset != new_vc4_state->pos2_offset || | |
1106 | old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset || | |
1107 | vc4_lbm_size(plane->state) != vc4_lbm_size(state)) | |
539c320b GP |
1108 | return -EINVAL; |
1109 | ||
1d4118ca BB |
1110 | /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update |
1111 | * if anything else has changed, fallback to a sync update. | |
1112 | */ | |
1113 | for (i = 0; i < new_vc4_state->dlist_count; i++) { | |
1114 | if (i == new_vc4_state->pos0_offset || | |
1115 | i == new_vc4_state->pos2_offset || | |
1116 | i == new_vc4_state->ptr0_offset || | |
1117 | (new_vc4_state->lbm_offset && | |
1118 | i == new_vc4_state->lbm_offset)) | |
1119 | continue; | |
1120 | ||
1121 | if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i]) | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | ||
539c320b GP |
1125 | return 0; |
1126 | } | |
1127 | ||
334dbd69 EA |
1128 | static int vc4_prepare_fb(struct drm_plane *plane, |
1129 | struct drm_plane_state *state) | |
1130 | { | |
1131 | struct vc4_bo *bo; | |
b9f19259 | 1132 | int ret; |
334dbd69 | 1133 | |
2227a7a2 | 1134 | if (!state->fb) |
334dbd69 EA |
1135 | return 0; |
1136 | ||
1137 | bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); | |
b9f19259 | 1138 | |
66ab7005 | 1139 | drm_gem_fb_prepare_fb(plane, state); |
2227a7a2 DV |
1140 | |
1141 | if (plane->state->fb == state->fb) | |
1142 | return 0; | |
1143 | ||
b9f19259 BB |
1144 | ret = vc4_bo_inc_usecnt(bo); |
1145 | if (ret) | |
1146 | return ret; | |
1147 | ||
334dbd69 EA |
1148 | return 0; |
1149 | } | |
1150 | ||
b9f19259 BB |
1151 | static void vc4_cleanup_fb(struct drm_plane *plane, |
1152 | struct drm_plane_state *state) | |
1153 | { | |
1154 | struct vc4_bo *bo; | |
1155 | ||
1156 | if (plane->state->fb == state->fb || !state->fb) | |
1157 | return; | |
1158 | ||
1159 | bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); | |
1160 | vc4_bo_dec_usecnt(bo); | |
1161 | } | |
1162 | ||
c8b75bca | 1163 | static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { |
c8b75bca EA |
1164 | .atomic_check = vc4_plane_atomic_check, |
1165 | .atomic_update = vc4_plane_atomic_update, | |
334dbd69 | 1166 | .prepare_fb = vc4_prepare_fb, |
b9f19259 | 1167 | .cleanup_fb = vc4_cleanup_fb, |
539c320b GP |
1168 | .atomic_async_check = vc4_plane_atomic_async_check, |
1169 | .atomic_async_update = vc4_plane_atomic_async_update, | |
c8b75bca EA |
1170 | }; |
1171 | ||
1172 | static void vc4_plane_destroy(struct drm_plane *plane) | |
1173 | { | |
c8b75bca EA |
1174 | drm_plane_cleanup(plane); |
1175 | } | |
1176 | ||
423ad7b3 DS |
1177 | static bool vc4_format_mod_supported(struct drm_plane *plane, |
1178 | uint32_t format, | |
1179 | uint64_t modifier) | |
1180 | { | |
1181 | /* Support T_TILING for RGB formats only. */ | |
1182 | switch (format) { | |
1183 | case DRM_FORMAT_XRGB8888: | |
1184 | case DRM_FORMAT_ARGB8888: | |
1185 | case DRM_FORMAT_ABGR8888: | |
1186 | case DRM_FORMAT_XBGR8888: | |
1187 | case DRM_FORMAT_RGB565: | |
1188 | case DRM_FORMAT_BGR565: | |
1189 | case DRM_FORMAT_ARGB1555: | |
1190 | case DRM_FORMAT_XRGB1555: | |
e065a8dd DS |
1191 | switch (fourcc_mod_broadcom_mod(modifier)) { |
1192 | case DRM_FORMAT_MOD_LINEAR: | |
1193 | case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: | |
e065a8dd DS |
1194 | return true; |
1195 | default: | |
1196 | return false; | |
1197 | } | |
1198 | case DRM_FORMAT_NV12: | |
1199 | case DRM_FORMAT_NV21: | |
1200 | switch (fourcc_mod_broadcom_mod(modifier)) { | |
1201 | case DRM_FORMAT_MOD_LINEAR: | |
1202 | case DRM_FORMAT_MOD_BROADCOM_SAND64: | |
1203 | case DRM_FORMAT_MOD_BROADCOM_SAND128: | |
1204 | case DRM_FORMAT_MOD_BROADCOM_SAND256: | |
1205 | return true; | |
1206 | default: | |
1207 | return false; | |
1208 | } | |
423ad7b3 DS |
1209 | case DRM_FORMAT_YUV422: |
1210 | case DRM_FORMAT_YVU422: | |
1211 | case DRM_FORMAT_YUV420: | |
1212 | case DRM_FORMAT_YVU420: | |
423ad7b3 | 1213 | case DRM_FORMAT_NV16: |
1e871d65 | 1214 | case DRM_FORMAT_NV61: |
423ad7b3 DS |
1215 | default: |
1216 | return (modifier == DRM_FORMAT_MOD_LINEAR); | |
1217 | } | |
1218 | } | |
1219 | ||
c8b75bca | 1220 | static const struct drm_plane_funcs vc4_plane_funcs = { |
539c320b | 1221 | .update_plane = drm_atomic_helper_update_plane, |
c8b75bca EA |
1222 | .disable_plane = drm_atomic_helper_disable_plane, |
1223 | .destroy = vc4_plane_destroy, | |
1224 | .set_property = NULL, | |
1225 | .reset = vc4_plane_reset, | |
1226 | .atomic_duplicate_state = vc4_plane_duplicate_state, | |
1227 | .atomic_destroy_state = vc4_plane_destroy_state, | |
423ad7b3 | 1228 | .format_mod_supported = vc4_format_mod_supported, |
c8b75bca EA |
1229 | }; |
1230 | ||
1231 | struct drm_plane *vc4_plane_init(struct drm_device *dev, | |
1232 | enum drm_plane_type type) | |
1233 | { | |
1234 | struct drm_plane *plane = NULL; | |
1235 | struct vc4_plane *vc4_plane; | |
1236 | u32 formats[ARRAY_SIZE(hvs_formats)]; | |
1237 | int ret = 0; | |
1238 | unsigned i; | |
423ad7b3 DS |
1239 | static const uint64_t modifiers[] = { |
1240 | DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, | |
e065a8dd DS |
1241 | DRM_FORMAT_MOD_BROADCOM_SAND128, |
1242 | DRM_FORMAT_MOD_BROADCOM_SAND64, | |
1243 | DRM_FORMAT_MOD_BROADCOM_SAND256, | |
423ad7b3 DS |
1244 | DRM_FORMAT_MOD_LINEAR, |
1245 | DRM_FORMAT_MOD_INVALID | |
1246 | }; | |
c8b75bca EA |
1247 | |
1248 | vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane), | |
1249 | GFP_KERNEL); | |
7b347348 CIK |
1250 | if (!vc4_plane) |
1251 | return ERR_PTR(-ENOMEM); | |
c8b75bca | 1252 | |
2c2853f7 BB |
1253 | for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) |
1254 | formats[i] = hvs_formats[i].drm; | |
1255 | ||
c8b75bca | 1256 | plane = &vc4_plane->base; |
49d29a07 | 1257 | ret = drm_universal_plane_init(dev, plane, 0, |
c8b75bca | 1258 | &vc4_plane_funcs, |
2c2853f7 | 1259 | formats, ARRAY_SIZE(formats), |
423ad7b3 | 1260 | modifiers, type, NULL); |
c8b75bca EA |
1261 | |
1262 | drm_plane_helper_add(plane, &vc4_plane_helper_funcs); | |
1263 | ||
22445f03 | 1264 | drm_plane_create_alpha_property(plane); |
7cd3cf35 BB |
1265 | drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, |
1266 | DRM_MODE_ROTATE_0 | | |
1267 | DRM_MODE_ROTATE_180 | | |
1268 | DRM_MODE_REFLECT_X | | |
1269 | DRM_MODE_REFLECT_Y); | |
22445f03 | 1270 | |
c8b75bca | 1271 | return plane; |
c8b75bca | 1272 | } |