[mirror_ubuntu-kernels.git] / drivers / gpu / drm / vc4 / vc4_txp.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright © 2018 Broadcom
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Boris Brezillon <boris.brezillon@bootlin.com>
 */

#include <linux/clk.h>
#include <linux/component.h>
#include <linux/of_graph.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_writeback.h>

#include "vc4_drv.h"
#include "vc4_regs.h"

/* Base address of the output.  Raster formats must be 4-byte aligned,
 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
 * inconsistent, but probably utile).
 */
#define TXP_DST_PTR		0x00

/* Pitch in bytes for raster images, 16-byte aligned.  For tiled, it's
 * the width in tiles.
 */
#define TXP_DST_PITCH		0x04
/* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
 * shifted up.
 */
# define TXP_T_TILE_WIDTH_SHIFT		7
/* For LT-tiled images, DST_PITCH should be the number of utiles wide,
 * shifted up.
 */
# define TXP_LT_TILE_WIDTH_SHIFT	4

/* Pre-rotation width/height of the image.  Must match HVS config.
 *
 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
 * and width/height must be tile or utile-aligned as appropriate.  If
 * transposing (rotating), width is limited to 1920.
 *
 * Height is limited to various numbers between 4088 and 4095.  I'd
 * just use 4088 to be safe.
 */
#define TXP_DIM			0x08
# define TXP_HEIGHT_SHIFT		16
# define TXP_HEIGHT_MASK		GENMASK(31, 16)
# define TXP_WIDTH_SHIFT		0
# define TXP_WIDTH_MASK			GENMASK(15, 0)

#define TXP_DST_CTRL		0x0c
/* These bits are set to 0x54 */
#define TXP_PILOT_SHIFT			24
#define TXP_PILOT_MASK			GENMASK(31, 24)
/* Bits 22-23 are set to 0x01 */
#define TXP_VERSION_SHIFT		22
#define TXP_VERSION_MASK		GENMASK(23, 22)

/* Powers down the internal memory. */
# define TXP_POWERDOWN			BIT(21)

/* Enables storing the alpha component in 8888/4444, instead of
 * filling with ~ALPHA_INVERT.
 */
# define TXP_ALPHA_ENABLE		BIT(20)

/* 4 bits, each enables stores for a channel in each set of 4 bytes.
 * Set to 0xf for normal operation.
 */
# define TXP_BYTE_ENABLE_SHIFT		16
# define TXP_BYTE_ENABLE_MASK		GENMASK(19, 16)

/* Debug: Generate VSTART again at EOF. */
# define TXP_VSTART_AT_EOF		BIT(15)

/* Debug: Terminate the current frame immediately.  Stops AXI
 * writes.
 */
# define TXP_ABORT			BIT(14)

# define TXP_DITHER			BIT(13)

/* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
 * !TXP_ALPHA_ENABLE.
 */
# define TXP_ALPHA_INVERT		BIT(12)

/* Note: I've listed the channels here in high bit (in byte 3/2/1) to
 * low bit (in byte 0) order.
 */
# define TXP_FORMAT_SHIFT		8
# define TXP_FORMAT_MASK		GENMASK(11, 8)
# define TXP_FORMAT_ABGR4444		0
# define TXP_FORMAT_ARGB4444		1
# define TXP_FORMAT_BGRA4444		2
# define TXP_FORMAT_RGBA4444		3
# define TXP_FORMAT_BGR565		6
# define TXP_FORMAT_RGB565		7
/* 888s are non-rotated, raster-only */
# define TXP_FORMAT_BGR888		8
# define TXP_FORMAT_RGB888		9
# define TXP_FORMAT_ABGR8888		12
# define TXP_FORMAT_ARGB8888		13
# define TXP_FORMAT_BGRA8888		14
# define TXP_FORMAT_RGBA8888		15

/* If TFORMAT is set, generates LT instead of T format. */
# define TXP_LINEAR_UTILE		BIT(7)

/* Rotate output by 90 degrees. */
# define TXP_TRANSPOSE			BIT(6)

/* Generate a tiled format for V3D. */
# define TXP_TFORMAT			BIT(5)

/* Generates some undefined test mode output. */
# define TXP_TEST_MODE			BIT(4)

/* Request odd field from HVS. */
# define TXP_FIELD			BIT(3)

/* Raise interrupt when idle. */
# define TXP_EI				BIT(2)

/* Set when generating a frame, clears when idle. */
# define TXP_BUSY			BIT(1)

/* Starts a frame.  Self-clearing. */
# define TXP_GO				BIT(0)

/* Number of lines received and committed to memory. */
#define TXP_PROGRESS		0x10

#define TXP_READ(offset) readl(txp->regs + (offset))
#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))

struct vc4_txp {
	struct platform_device *pdev;

	struct drm_writeback_connector connector;

	void __iomem *regs;
	struct debugfs_regset32 regset;
};

static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
{
	return container_of(encoder, struct vc4_txp, connector.encoder);
}

static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
{
	return container_of(conn, struct vc4_txp, connector.base);
}

static const struct debugfs_reg32 txp_regs[] = {
	VC4_REG32(TXP_DST_PTR),
	VC4_REG32(TXP_DST_PITCH),
	VC4_REG32(TXP_DIM),
	VC4_REG32(TXP_DST_CTRL),
	VC4_REG32(TXP_PROGRESS),
};

static int vc4_txp_connector_get_modes(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;

	return drm_add_modes_noedid(connector, dev->mode_config.max_width,
				    dev->mode_config.max_height);
}

static enum drm_mode_status
vc4_txp_connector_mode_valid(struct drm_connector *connector,
			     struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	int w = mode->hdisplay, h = mode->vdisplay;

	if (w < mode_config->min_width || w > mode_config->max_width)
		return MODE_BAD_HVALUE;

	if (h < mode_config->min_height || h > mode_config->max_height)
		return MODE_BAD_VVALUE;

	return MODE_OK;
}

static const u32 drm_fmts[] = {
	DRM_FORMAT_RGB888,
	DRM_FORMAT_BGR888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_RGBX8888,
	DRM_FORMAT_BGRX8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_BGRA8888,
};

static const u32 txp_fmts[] = {
	TXP_FORMAT_RGB888,
	TXP_FORMAT_BGR888,
	TXP_FORMAT_ARGB8888,
	TXP_FORMAT_ABGR8888,
	TXP_FORMAT_ARGB8888,
	TXP_FORMAT_ABGR8888,
	TXP_FORMAT_RGBA8888,
	TXP_FORMAT_BGRA8888,
	TXP_FORMAT_RGBA8888,
	TXP_FORMAT_BGRA8888,
};

static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
					  struct drm_atomic_state *state)
{
	struct drm_connector_state *conn_state;
	struct drm_crtc_state *crtc_state;
	struct drm_framebuffer *fb;
	int i;

	conn_state = drm_atomic_get_new_connector_state(state, conn);
	if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
		return 0;

	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);

	fb = conn_state->writeback_job->fb;
	if (fb->width != crtc_state->mode.hdisplay ||
	    fb->height != crtc_state->mode.vdisplay) {
		DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
			      fb->width, fb->height);
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
		if (fb->format->format == drm_fmts[i])
			break;
	}

	if (i == ARRAY_SIZE(drm_fmts))
		return -EINVAL;

	/* Pitch must be aligned on 16 bytes. */
	if (fb->pitches[0] & GENMASK(3, 0))
		return -EINVAL;

	vc4_crtc_txp_armed(crtc_state);

	return 0;
}

static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
					struct drm_connector_state *conn_state)
{
	struct vc4_txp *txp = connector_to_vc4_txp(conn);
	struct drm_gem_cma_object *gem;
	struct drm_display_mode *mode;
	struct drm_framebuffer *fb;
	u32 ctrl;
	int i;

	if (WARN_ON(!conn_state->writeback_job ||
		    !conn_state->writeback_job->fb))
		return;

	mode = &conn_state->crtc->state->adjusted_mode;
	fb = conn_state->writeback_job->fb;

	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
		if (fb->format->format == drm_fmts[i])
			break;
	}

	if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
		return;

	ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI |
	       VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
	       VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);

	if (fb->format->has_alpha)
		ctrl |= TXP_ALPHA_ENABLE;

	gem = drm_fb_cma_get_gem_obj(fb, 0);
	TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
	TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
	TXP_WRITE(TXP_DIM,
		  VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
		  VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));

	TXP_WRITE(TXP_DST_CTRL, ctrl);

	drm_writeback_queue_job(&txp->connector, conn_state);
}

static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
	.get_modes = vc4_txp_connector_get_modes,
	.mode_valid = vc4_txp_connector_mode_valid,
	.atomic_check = vc4_txp_connector_atomic_check,
	.atomic_commit = vc4_txp_connector_atomic_commit,
};

static enum drm_connector_status
vc4_txp_connector_detect(struct drm_connector *connector, bool force)
{
	return connector_status_connected;
}

static void vc4_txp_connector_destroy(struct drm_connector *connector)
{
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);
}

static const struct drm_connector_funcs vc4_txp_connector_funcs = {
	.detect = vc4_txp_connector_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = vc4_txp_connector_destroy,
	.reset = drm_atomic_helper_connector_reset,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};

static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
{
	struct vc4_txp *txp = encoder_to_vc4_txp(encoder);

	if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
		unsigned long timeout = jiffies + msecs_to_jiffies(1000);

		TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);

		while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
		       time_before(jiffies, timeout))
			;

		WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
	}

	TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
}

static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
	.disable = vc4_txp_encoder_disable,
};

static irqreturn_t vc4_txp_interrupt(int irq, void *data)
{
	struct vc4_txp *txp = data;

	TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
	vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc));
	drm_writeback_signal_completion(&txp->connector, 0);

	return IRQ_HANDLED;
}

static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct drm_device *drm = dev_get_drvdata(master);
	struct vc4_dev *vc4 = to_vc4_dev(drm);
	struct vc4_txp *txp;
	int ret, irq;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL);
	if (!txp)
		return -ENOMEM;

	txp->pdev = pdev;

	txp->regs = vc4_ioremap_regs(pdev, 0);
	if (IS_ERR(txp->regs))
		return PTR_ERR(txp->regs);
	txp->regset.base = txp->regs;
	txp->regset.regs = txp_regs;
	txp->regset.nregs = ARRAY_SIZE(txp_regs);

	drm_connector_helper_add(&txp->connector.base,
				 &vc4_txp_connector_helper_funcs);
	ret = drm_writeback_connector_init(drm, &txp->connector,
					   &vc4_txp_connector_funcs,
					   &vc4_txp_encoder_helper_funcs,
					   drm_fmts, ARRAY_SIZE(drm_fmts));
	if (ret)
		return ret;

	ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
			       dev_name(dev), txp);
	if (ret)
		return ret;

	dev_set_drvdata(dev, txp);
	vc4->txp = txp;

	vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset);

	return 0;
}

static void vc4_txp_unbind(struct device *dev, struct device *master,
			   void *data)
{
	struct drm_device *drm = dev_get_drvdata(master);
	struct vc4_dev *vc4 = to_vc4_dev(drm);
	struct vc4_txp *txp = dev_get_drvdata(dev);

	vc4_txp_connector_destroy(&txp->connector.base);

	vc4->txp = NULL;
}

static const struct component_ops vc4_txp_ops = {
	.bind   = vc4_txp_bind,
	.unbind = vc4_txp_unbind,
};

static int vc4_txp_probe(struct platform_device *pdev)
{
	return component_add(&pdev->dev, &vc4_txp_ops);
}

static int vc4_txp_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &vc4_txp_ops);
	return 0;
}

static const struct of_device_id vc4_txp_dt_match[] = {
	{ .compatible = "brcm,bcm2835-txp" },
	{ /* sentinel */ },
};

struct platform_driver vc4_txp_driver = {
	.probe = vc4_txp_probe,
	.remove = vc4_txp_remove,
	.driver = {
		.name = "vc4_txp",
		.of_match_table = vc4_txp_dt_match,
	},
};
Commit	Line	Data
008095e0 BB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright © 2018 Broadcom
	4	*
	5	* Authors:
	6	* Eric Anholt <eric@anholt.net>
	7	* Boris Brezillon <boris.brezillon@bootlin.com>
	8	*/
	9
008095e0 BB	10	#include <linux/clk.h>
	11	#include <linux/component.h>
	12	#include <linux/of_graph.h>
	13	#include <linux/of_platform.h>
	14	#include <linux/pm_runtime.h>
	15
fd6d6d80 SR	16	#include <drm/drm_atomic_helper.h>
	17	#include <drm/drm_edid.h>
	18	#include <drm/drm_fb_cma_helper.h>
	19	#include <drm/drm_fourcc.h>
	20	#include <drm/drm_panel.h>
	21	#include <drm/drm_probe_helper.h>
	22	#include <drm/drm_writeback.h>
	23
008095e0 BB	24	#include "vc4_drv.h"
	25	#include "vc4_regs.h"
	26
	27	/* Base address of the output. Raster formats must be 4-byte aligned,
	28	* T and LT must be 16-byte aligned or maybe utile-aligned (docs are
	29	* inconsistent, but probably utile).
	30	*/
	31	#define TXP_DST_PTR 0x00
	32
	33	/* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
	34	* the width in tiles.
	35	*/
	36	#define TXP_DST_PITCH 0x04
	37	/* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
	38	* shifted up.
	39	*/
	40	# define TXP_T_TILE_WIDTH_SHIFT 7
	41	/* For LT-tiled images, DST_PITCH should be the number of utiles wide,
	42	* shifted up.
	43	*/
	44	# define TXP_LT_TILE_WIDTH_SHIFT 4
	45
	46	/* Pre-rotation width/height of the image. Must match HVS config.
	47	*
	48	* If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
	49	* and width/height must be tile or utile-aligned as appropriate. If
	50	* transposing (rotating), width is limited to 1920.
	51	*
	52	* Height is limited to various numbers between 4088 and 4095. I'd
	53	* just use 4088 to be safe.
	54	*/
	55	#define TXP_DIM 0x08
	56	# define TXP_HEIGHT_SHIFT 16
	57	# define TXP_HEIGHT_MASK GENMASK(31, 16)
	58	# define TXP_WIDTH_SHIFT 0
	59	# define TXP_WIDTH_MASK GENMASK(15, 0)
	60
	61	#define TXP_DST_CTRL 0x0c
	62	/* These bits are set to 0x54 */
	63	#define TXP_PILOT_SHIFT 24
	64	#define TXP_PILOT_MASK GENMASK(31, 24)
	65	/* Bits 22-23 are set to 0x01 */
	66	#define TXP_VERSION_SHIFT 22
	67	#define TXP_VERSION_MASK GENMASK(23, 22)
	68
	69	/* Powers down the internal memory. */
	70	# define TXP_POWERDOWN BIT(21)
	71
	72	/* Enables storing the alpha component in 8888/4444, instead of
	73	* filling with ~ALPHA_INVERT.
	74	*/
	75	# define TXP_ALPHA_ENABLE BIT(20)
	76
	77	/* 4 bits, each enables stores for a channel in each set of 4 bytes.
	78	* Set to 0xf for normal operation.
	79	*/
	80	# define TXP_BYTE_ENABLE_SHIFT 16
	81	# define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
	82
	83	/* Debug: Generate VSTART again at EOF. */
	84	# define TXP_VSTART_AT_EOF BIT(15)
	85
	86	/* Debug: Terminate the current frame immediately. Stops AXI
	87	* writes.
88	*/
89	# define TXP_ABORT BIT(14)
90
91	# define TXP_DITHER BIT(13)
92
93	/* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
94	* !TXP_ALPHA_ENABLE.
95	*/
96	# define TXP_ALPHA_INVERT BIT(12)
97
98	/* Note: I've listed the channels here in high bit (in byte 3/2/1) to
99	* low bit (in byte 0) order.
100	*/
101	# define TXP_FORMAT_SHIFT 8
102	# define TXP_FORMAT_MASK GENMASK(11, 8)
103	# define TXP_FORMAT_ABGR4444 0
104	# define TXP_FORMAT_ARGB4444 1
105	# define TXP_FORMAT_BGRA4444 2
106	# define TXP_FORMAT_RGBA4444 3
107	# define TXP_FORMAT_BGR565 6
108	# define TXP_FORMAT_RGB565 7
109	/* 888s are non-rotated, raster-only */
110	# define TXP_FORMAT_BGR888 8
111	# define TXP_FORMAT_RGB888 9
112	# define TXP_FORMAT_ABGR8888 12
113	# define TXP_FORMAT_ARGB8888 13
114	# define TXP_FORMAT_BGRA8888 14
115	# define TXP_FORMAT_RGBA8888 15
116
117	/* If TFORMAT is set, generates LT instead of T format. */
118	# define TXP_LINEAR_UTILE BIT(7)
119
120	/* Rotate output by 90 degrees. */
121	# define TXP_TRANSPOSE BIT(6)
122
123	/* Generate a tiled format for V3D. */
124	# define TXP_TFORMAT BIT(5)
125
126	/* Generates some undefined test mode output. */
127	# define TXP_TEST_MODE BIT(4)
128
129	/* Request odd field from HVS. */
130	# define TXP_FIELD BIT(3)
131
132	/* Raise interrupt when idle. */
133	# define TXP_EI BIT(2)
134
135	/* Set when generating a frame, clears when idle. */
136	# define TXP_BUSY BIT(1)
137
138	/* Starts a frame. Self-clearing. */
139	# define TXP_GO BIT(0)
140
141	/* Number of lines received and committed to memory. */
142	#define TXP_PROGRESS 0x10
143
144	#define TXP_READ(offset) readl(txp->regs + (offset))
145	#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
146
147	struct vc4_txp {
148	struct platform_device *pdev;
149
150	struct drm_writeback_connector connector;
151
152	void __iomem *regs;
3051719a	153	struct debugfs_regset32 regset;
008095e0 BB	154	};
	155
	156	static inline struct vc4_txp encoder_to_vc4_txp(struct drm_encoder encoder)
	157	{
	158	return container_of(encoder, struct vc4_txp, connector.encoder);
	159	}
	160
	161	static inline struct vc4_txp connector_to_vc4_txp(struct drm_connector conn)
	162	{
	163	return container_of(conn, struct vc4_txp, connector.base);
	164	}
	165
3051719a EA	166	static const struct debugfs_reg32 txp_regs[] = {
	167	VC4_REG32(TXP_DST_PTR),
	168	VC4_REG32(TXP_DST_PITCH),
	169	VC4_REG32(TXP_DIM),
	170	VC4_REG32(TXP_DST_CTRL),
	171	VC4_REG32(TXP_PROGRESS),
008095e0 BB	172	};
008095e0 BB	173
008095e0 BB	174	static int vc4_txp_connector_get_modes(struct drm_connector *connector)
	175	{
	176	struct drm_device *dev = connector->dev;
	177
	178	return drm_add_modes_noedid(connector, dev->mode_config.max_width,
	179	dev->mode_config.max_height);
	180	}
	181
	182	static enum drm_mode_status
	183	vc4_txp_connector_mode_valid(struct drm_connector *connector,
	184	struct drm_display_mode *mode)
	185	{
	186	struct drm_device *dev = connector->dev;
	187	struct drm_mode_config *mode_config = &dev->mode_config;
	188	int w = mode->hdisplay, h = mode->vdisplay;
	189
	190	if (w < mode_config->min_width \|\| w > mode_config->max_width)
	191	return MODE_BAD_HVALUE;
	192
	193	if (h < mode_config->min_height \|\| h > mode_config->max_height)
	194	return MODE_BAD_VVALUE;
	195
	196	return MODE_OK;
	197	}
	198
	199	static const u32 drm_fmts[] = {
	200	DRM_FORMAT_RGB888,
	201	DRM_FORMAT_BGR888,
	202	DRM_FORMAT_XRGB8888,
	203	DRM_FORMAT_XBGR8888,
	204	DRM_FORMAT_ARGB8888,
	205	DRM_FORMAT_ABGR8888,
	206	DRM_FORMAT_RGBX8888,
	207	DRM_FORMAT_BGRX8888,
	208	DRM_FORMAT_RGBA8888,
	209	DRM_FORMAT_BGRA8888,
	210	};
	211
	212	static const u32 txp_fmts[] = {
	213	TXP_FORMAT_RGB888,
	214	TXP_FORMAT_BGR888,
	215	TXP_FORMAT_ARGB8888,
	216	TXP_FORMAT_ABGR8888,
	217	TXP_FORMAT_ARGB8888,
	218	TXP_FORMAT_ABGR8888,
	219	TXP_FORMAT_RGBA8888,
	220	TXP_FORMAT_BGRA8888,
	221	TXP_FORMAT_RGBA8888,
	222	TXP_FORMAT_BGRA8888,
	223	};
	224
	225	static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
6f3b6278	226	struct drm_atomic_state *state)
008095e0	227	{
6f3b6278	228	struct drm_connector_state *conn_state;
008095e0	229	struct drm_crtc_state *crtc_state;
008095e0 BB	230	struct drm_framebuffer *fb;
	231	int i;
	232
6f3b6278	233	conn_state = drm_atomic_get_new_connector_state(state, conn);
008095e0 BB	234	if (!conn_state->writeback_job \|\| !conn_state->writeback_job->fb)
	235	return 0;
	236
6f3b6278	237	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
008095e0 BB	238
	239	fb = conn_state->writeback_job->fb;
	240	if (fb->width != crtc_state->mode.hdisplay \|\|
	241	fb->height != crtc_state->mode.vdisplay) {
	242	DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
	243	fb->width, fb->height);
	244	return -EINVAL;
	245	}
	246
	247	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
	248	if (fb->format->format == drm_fmts[i])
	249	break;
	250	}
	251
	252	if (i == ARRAY_SIZE(drm_fmts))
	253	return -EINVAL;
	254
008095e0 BB	255	/* Pitch must be aligned on 16 bytes. */
	256	if (fb->pitches[0] & GENMASK(3, 0))
	257	return -EINVAL;
	258
	259	vc4_crtc_txp_armed(crtc_state);
	260
	261	return 0;
	262	}
	263
	264	static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
	265	struct drm_connector_state *conn_state)
	266	{
	267	struct vc4_txp *txp = connector_to_vc4_txp(conn);
	268	struct drm_gem_cma_object *gem;
	269	struct drm_display_mode *mode;
	270	struct drm_framebuffer *fb;
	271	u32 ctrl;
	272	int i;
	273
	274	if (WARN_ON(!conn_state->writeback_job \|\|
	275	!conn_state->writeback_job->fb))
	276	return;
	277
	278	mode = &conn_state->crtc->state->adjusted_mode;
	279	fb = conn_state->writeback_job->fb;
	280
	281	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
	282	if (fb->format->format == drm_fmts[i])
	283	break;
	284	}
	285
	286	if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
	287	return;
	288
	289	ctrl = TXP_GO \| TXP_VSTART_AT_EOF \| TXP_EI \|
	290	VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) \|
	291	VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
	292
	293	if (fb->format->has_alpha)
	294	ctrl \|= TXP_ALPHA_ENABLE;
	295
	296	gem = drm_fb_cma_get_gem_obj(fb, 0);
	297	TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
	298	TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
	299	TXP_WRITE(TXP_DIM,
	300	VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) \|
	301	VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
	302
	303	TXP_WRITE(TXP_DST_CTRL, ctrl);
	304
97eb9eae	305	drm_writeback_queue_job(&txp->connector, conn_state);
008095e0 BB	306	}
	307
	308	static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
	309	.get_modes = vc4_txp_connector_get_modes,
	310	.mode_valid = vc4_txp_connector_mode_valid,
	311	.atomic_check = vc4_txp_connector_atomic_check,
	312	.atomic_commit = vc4_txp_connector_atomic_commit,
	313	};
	314
	315	static enum drm_connector_status
	316	vc4_txp_connector_detect(struct drm_connector *connector, bool force)
	317	{
	318	return connector_status_connected;
	319	}
	320
	321	static void vc4_txp_connector_destroy(struct drm_connector *connector)
	322	{
	323	drm_connector_unregister(connector);
	324	drm_connector_cleanup(connector);
	325	}
	326
	327	static const struct drm_connector_funcs vc4_txp_connector_funcs = {
	328	.detect = vc4_txp_connector_detect,
	329	.fill_modes = drm_helper_probe_single_connector_modes,
	330	.destroy = vc4_txp_connector_destroy,
	331	.reset = drm_atomic_helper_connector_reset,
	332	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
	333	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	334	};
	335
	336	static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
	337	{
	338	struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
	339
	340	if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
	341	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
	342
	343	TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
	344
	345	while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
	346	time_before(jiffies, timeout))
	347	;
	348
	349	WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
	350	}
	351
	352	TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
	353	}
	354
	355	static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
	356	.disable = vc4_txp_encoder_disable,
	357	};
	358
	359	static irqreturn_t vc4_txp_interrupt(int irq, void *data)
	360	{
	361	struct vc4_txp *txp = data;
	362
	363	TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
	364	vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc));
	365	drm_writeback_signal_completion(&txp->connector, 0);
	366
	367	return IRQ_HANDLED;
	368	}
	369
370	static int vc4_txp_bind(struct device dev, struct device master, void *data)
371	{
372	struct platform_device *pdev = to_platform_device(dev);
373	struct drm_device *drm = dev_get_drvdata(master);
374	struct vc4_dev *vc4 = to_vc4_dev(drm);
375	struct vc4_txp *txp;
376	int ret, irq;
377
378	irq = platform_get_irq(pdev, 0);
379	if (irq < 0)
380	return irq;
381
382	txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL);
383	if (!txp)
384	return -ENOMEM;
385
386	txp->pdev = pdev;
387
388	txp->regs = vc4_ioremap_regs(pdev, 0);
389	if (IS_ERR(txp->regs))
390	return PTR_ERR(txp->regs);
3051719a EA	391	txp->regset.base = txp->regs;
	392	txp->regset.regs = txp_regs;
	393	txp->regset.nregs = ARRAY_SIZE(txp_regs);
008095e0 BB	394
	395	drm_connector_helper_add(&txp->connector.base,
	396	&vc4_txp_connector_helper_funcs);
	397	ret = drm_writeback_connector_init(drm, &txp->connector,
	398	&vc4_txp_connector_funcs,
	399	&vc4_txp_encoder_helper_funcs,
	400	drm_fmts, ARRAY_SIZE(drm_fmts));
	401	if (ret)
	402	return ret;
	403
	404	ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
	405	dev_name(dev), txp);
	406	if (ret)
	407	return ret;
	408
	409	dev_set_drvdata(dev, txp);
	410	vc4->txp = txp;
	411
c9be804c EA	412	vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset);
c9be804c EA	413
008095e0 BB	414	return 0;
	415	}
	416
	417	static void vc4_txp_unbind(struct device dev, struct device master,
	418	void *data)
	419	{
	420	struct drm_device *drm = dev_get_drvdata(master);
	421	struct vc4_dev *vc4 = to_vc4_dev(drm);
	422	struct vc4_txp *txp = dev_get_drvdata(dev);
	423
	424	vc4_txp_connector_destroy(&txp->connector.base);
	425
	426	vc4->txp = NULL;
	427	}
	428
	429	static const struct component_ops vc4_txp_ops = {
	430	.bind = vc4_txp_bind,
	431	.unbind = vc4_txp_unbind,
	432	};
	433
	434	static int vc4_txp_probe(struct platform_device *pdev)
	435	{
	436	return component_add(&pdev->dev, &vc4_txp_ops);
	437	}
	438
	439	static int vc4_txp_remove(struct platform_device *pdev)
	440	{
	441	component_del(&pdev->dev, &vc4_txp_ops);
	442	return 0;
	443	}
	444
	445	static const struct of_device_id vc4_txp_dt_match[] = {
	446	{ .compatible = "brcm,bcm2835-txp" },
	447	{ /* sentinel */ },
	448	};
	449
	450	struct platform_driver vc4_txp_driver = {
	451	.probe = vc4_txp_probe,
	452	.remove = vc4_txp_remove,
	453	.driver = {
	454	.name = "vc4_txp",
	455	.of_match_table = vc4_txp_dt_match,
	456	},
	457	};