[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / via / via_irq.c

/* via_irq.c
 *
 * Copyright 2004 BEAM Ltd.
 * Copyright 2002 Tungsten Graphics, Inc.
 * Copyright 2005 Thomas Hellstrom.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * BEAM LTD, TUNGSTEN GRAPHICS  AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Terry Barnaby <terry1@beam.ltd.uk>
 *    Keith Whitwell <keith@tungstengraphics.com>
 *    Thomas Hellstrom <unichrome@shipmail.org>
 *
 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
 * The refresh rate is also calculated for video playback sync purposes.
 */

#include <drm/drm_device.h>
#include <drm/drm_vblank.h>
#include <drm/via_drm.h>

#include "via_drv.h"

#define VIA_REG_INTERRUPT       0x200

/* VIA_REG_INTERRUPT */
#define VIA_IRQ_GLOBAL	  (1 << 31)
#define VIA_IRQ_VBLANK_ENABLE   (1 << 19)
#define VIA_IRQ_VBLANK_PENDING  (1 << 3)
#define VIA_IRQ_HQV0_ENABLE     (1 << 11)
#define VIA_IRQ_HQV1_ENABLE     (1 << 25)
#define VIA_IRQ_HQV0_PENDING    (1 << 9)
#define VIA_IRQ_HQV1_PENDING    (1 << 10)
#define VIA_IRQ_DMA0_DD_ENABLE  (1 << 20)
#define VIA_IRQ_DMA0_TD_ENABLE  (1 << 21)
#define VIA_IRQ_DMA1_DD_ENABLE  (1 << 22)
#define VIA_IRQ_DMA1_TD_ENABLE  (1 << 23)
#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)


/*
 * Device-specific IRQs go here. This type might need to be extended with
 * the register if there are multiple IRQ control registers.
 * Currently we activate the HQV interrupts of  Unichrome Pro group A.
 */

static maskarray_t via_pro_group_a_irqs[] = {
	{VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
	 0x00000000 },
	{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
	 0x00000000 },
	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
};
static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};

static maskarray_t via_unichrome_irqs[] = {
	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	 VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
};
static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};


u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;

	if (pipe != 0)
		return 0;

	return atomic_read(&dev_priv->vbl_received);
}

irqreturn_t via_driver_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;
	int handled = 0;
	ktime_t cur_vblank;
	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	int i;

	status = via_read(dev_priv, VIA_REG_INTERRUPT);
	if (status & VIA_IRQ_VBLANK_PENDING) {
		atomic_inc(&dev_priv->vbl_received);
		if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
			cur_vblank = ktime_get();
			if (dev_priv->last_vblank_valid) {
				dev_priv->nsec_per_vblank =
					ktime_sub(cur_vblank,
						dev_priv->last_vblank) >> 4;
			}
			dev_priv->last_vblank = cur_vblank;
			dev_priv->last_vblank_valid = 1;
		}
		if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
			DRM_DEBUG("nsec per vblank is: %llu\n",
				  ktime_to_ns(dev_priv->nsec_per_vblank));
		}
		drm_handle_vblank(dev, 0);
		handled = 1;
	}

	for (i = 0; i < dev_priv->num_irqs; ++i) {
		if (status & cur_irq->pending_mask) {
			atomic_inc(&cur_irq->irq_received);
			wake_up(&cur_irq->irq_queue);
			handled = 1;
			if (dev_priv->irq_map[drm_via_irq_dma0_td] == i)
				via_dmablit_handler(dev, 0, 1);
			else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i)
				via_dmablit_handler(dev, 1, 1);
		}
		cur_irq++;
	}

	/* Acknowledge interrupts */
	via_write(dev_priv, VIA_REG_INTERRUPT, status);


	if (handled)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
{
	u32 status;

	if (dev_priv) {
		/* Acknowledge interrupts */
		status = via_read(dev_priv, VIA_REG_INTERRUPT);
		via_write(dev_priv, VIA_REG_INTERRUPT, status |
			  dev_priv->irq_pending_mask);
	}
}

int via_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;
	u32 status;

	if (pipe != 0) {
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
		return -EINVAL;
	}

	status = via_read(dev_priv, VIA_REG_INTERRUPT);
	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);

	via_write8(dev_priv, 0x83d4, 0x11);
	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);

	return 0;
}

void via_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
	drm_via_private_t *dev_priv = dev->dev_private;
	u32 status;

	status = via_read(dev_priv, VIA_REG_INTERRUPT);
	via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);

	via_write8(dev_priv, 0x83d4, 0x11);
	via_write8_mask(dev_priv, 0x83d5, 0x30, 0);

	if (pipe != 0)
		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
}

static int
via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence,
		    unsigned int *sequence)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	unsigned int cur_irq_sequence;
	drm_via_irq_t *cur_irq;
	int ret = 0;
	maskarray_t *masks;
	int real_irq;

	DRM_DEBUG("\n");

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	if (irq >= drm_via_irq_num) {
		DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
		return -EINVAL;
	}

	real_irq = dev_priv->irq_map[irq];

	if (real_irq < 0) {
		DRM_ERROR("Video IRQ %d not available on this hardware.\n",
			  irq);
		return -EINVAL;
	}

	masks = dev_priv->irq_masks;
	cur_irq = dev_priv->via_irqs + real_irq;

	if (masks[real_irq][2] && !force_sequence) {
		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
			    ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
			     masks[irq][4]));
		cur_irq_sequence = atomic_read(&cur_irq->irq_received);
	} else {
		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
			    (((cur_irq_sequence =
			       atomic_read(&cur_irq->irq_received)) -
			      *sequence) <= (1 << 23)));
	}
	*sequence = cur_irq_sequence;
	return ret;
}


/*
 * drm_dma.h hooks
 */

void via_driver_irq_preinstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;
	drm_via_irq_t *cur_irq;
	int i;

	DRM_DEBUG("dev_priv: %p\n", dev_priv);
	if (dev_priv) {
		cur_irq = dev_priv->via_irqs;

		dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
		dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;

		if (dev_priv->chipset == VIA_PRO_GROUP_A ||
		    dev_priv->chipset == VIA_DX9_0) {
			dev_priv->irq_masks = via_pro_group_a_irqs;
			dev_priv->num_irqs = via_num_pro_group_a;
			dev_priv->irq_map = via_irqmap_pro_group_a;
		} else {
			dev_priv->irq_masks = via_unichrome_irqs;
			dev_priv->num_irqs = via_num_unichrome;
			dev_priv->irq_map = via_irqmap_unichrome;
		}

		for (i = 0; i < dev_priv->num_irqs; ++i) {
			atomic_set(&cur_irq->irq_received, 0);
			cur_irq->enable_mask = dev_priv->irq_masks[i][0];
			cur_irq->pending_mask = dev_priv->irq_masks[i][1];
			init_waitqueue_head(&cur_irq->irq_queue);
			dev_priv->irq_enable_mask |= cur_irq->enable_mask;
			dev_priv->irq_pending_mask |= cur_irq->pending_mask;
			cur_irq++;

			DRM_DEBUG("Initializing IRQ %d\n", i);
		}

		dev_priv->last_vblank_valid = 0;

		/* Clear VSync interrupt regs */
		status = via_read(dev_priv, VIA_REG_INTERRUPT);
		via_write(dev_priv, VIA_REG_INTERRUPT, status &
			  ~(dev_priv->irq_enable_mask));

		/* Clear bits if they're already high */
		viadrv_acknowledge_irqs(dev_priv);
	}
}

int via_driver_irq_postinstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;

	DRM_DEBUG("via_driver_irq_postinstall\n");
	if (!dev_priv)
		return -EINVAL;

	status = via_read(dev_priv, VIA_REG_INTERRUPT);
	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
		  | dev_priv->irq_enable_mask);

	/* Some magic, oh for some data sheets ! */
	via_write8(dev_priv, 0x83d4, 0x11);
	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);

	return 0;
}

void via_driver_irq_uninstall(struct drm_device *dev)
{
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	u32 status;

	DRM_DEBUG("\n");
	if (dev_priv) {

		/* Some more magic, oh for some data sheets ! */

		via_write8(dev_priv, 0x83d4, 0x11);
		via_write8_mask(dev_priv, 0x83d5, 0x30, 0);

		status = via_read(dev_priv, VIA_REG_INTERRUPT);
		via_write(dev_priv, VIA_REG_INTERRUPT, status &
			  ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
	}
}

int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
	drm_via_irqwait_t *irqwait = data;
	struct timespec64 now;
	int ret = 0;
	drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	int force_sequence;

	if (irqwait->request.irq >= dev_priv->num_irqs) {
		DRM_ERROR("Trying to wait on unknown irq %d\n",
			  irqwait->request.irq);
		return -EINVAL;
	}

	cur_irq += irqwait->request.irq;

	switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
	case VIA_IRQ_RELATIVE:
		irqwait->request.sequence +=
			atomic_read(&cur_irq->irq_received);
		irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
	case VIA_IRQ_ABSOLUTE:
		break;
	default:
		return -EINVAL;
	}

	if (irqwait->request.type & VIA_IRQ_SIGNAL) {
		DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
		return -EINVAL;
	}

	force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);

	ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
				  &irqwait->request.sequence);
	ktime_get_ts64(&now);
	irqwait->reply.tval_sec = now.tv_sec;
	irqwait->reply.tval_usec = now.tv_nsec / NSEC_PER_USEC;

	return ret;
}
Commit	Line	Data
22f579c6 DA	1	/* via_irq.c
	2	*
	3	* Copyright 2004 BEAM Ltd.
	4	* Copyright 2002 Tungsten Graphics, Inc.
	5	* Copyright 2005 Thomas Hellstrom.
	6	* All Rights Reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice (including the next
	16	* paragraph) shall be included in all copies or substantial portions of the
	17	* Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	23	* DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Terry Barnaby <terry1@beam.ltd.uk>
	30	* Keith Whitwell <keith@tungstengraphics.com>
	31	* Thomas Hellstrom <unichrome@shipmail.org>
	32	*
	33	* This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
	34	* interrupt, as well as an infrastructure to handle other interrupts of the chip.
	35	* The refresh rate is also calculated for video playback sync purposes.
	36	*/
	37
0005cbda SR	38	#include <drm/drm_device.h>
0005cbda SR	39	#include <drm/drm_vblank.h>
760285e7	40	#include <drm/via_drm.h>
0005cbda	41
22f579c6 DA	42	#include "via_drv.h"
	43
	44	#define VIA_REG_INTERRUPT 0x200
	45
	46	/* VIA_REG_INTERRUPT */
0a3e67a4	47	#define VIA_IRQ_GLOBAL (1 << 31)
22f579c6 DA	48	#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
	49	#define VIA_IRQ_VBLANK_PENDING (1 << 3)
	50	#define VIA_IRQ_HQV0_ENABLE (1 << 11)
	51	#define VIA_IRQ_HQV1_ENABLE (1 << 25)
	52	#define VIA_IRQ_HQV0_PENDING (1 << 9)
	53	#define VIA_IRQ_HQV1_PENDING (1 << 10)
92514243 DA	54	#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
	55	#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
	56	#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
	57	#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
	58	#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
	59	#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
	60	#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
	61	#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
	62
22f579c6 DA	63
	64	/*
	65	* Device-specific IRQs go here. This type might need to be extended with
	66	* the register if there are multiple IRQ control registers.
b5e89ed5	67	* Currently we activate the HQV interrupts of Unichrome Pro group A.
22f579c6 DA	68	*/
	69
	70	static maskarray_t via_pro_group_a_irqs[] = {
b5e89ed5	71	{VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
0a3e67a4	72	0x00000000 },
b5e89ed5	73	{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
0a3e67a4	74	0x00000000 },
92514243 DA	75	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	76	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
	77	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	78	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
b5e89ed5	79	};
0a3e67a4	80	static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
92514243	81	static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
b5e89ed5	82
92514243 DA	83	static maskarray_t via_unichrome_irqs[] = {
	84	{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
	85	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008},
	86	{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
	87	VIA_DMA_CSR_TA \| VIA_DMA_CSR_TD, 0x00000008}
	88	};
0a3e67a4	89	static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
92514243	90	static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
b5e89ed5	91
0a3e67a4	92
88e72717	93	u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
0a3e67a4 JB	94	{
0a3e67a4 JB	95	drm_via_private_t *dev_priv = dev->dev_private;
88e72717 TR	96
88e72717 TR	97	if (pipe != 0)
0a3e67a4 JB	98	return 0;
	99
	100	return atomic_read(&dev_priv->vbl_received);
22f579c6 DA	101	}
22f579c6 DA	102
e9f0d76f	103	irqreturn_t via_driver_irq_handler(int irq, void *arg)
22f579c6	104	{
84b1fd10	105	struct drm_device dev = (struct drm_device ) arg;
22f579c6 DA	106	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	107	u32 status;
	108	int handled = 0;
de7e8bd0	109	ktime_t cur_vblank;
22f579c6 DA	110	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	111	int i;
	112
3bf2a06e	113	status = via_read(dev_priv, VIA_REG_INTERRUPT);
22f579c6	114	if (status & VIA_IRQ_VBLANK_PENDING) {
0a3e67a4 JB	115	atomic_inc(&dev_priv->vbl_received);
0a3e67a4 JB	116	if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
de7e8bd0	117	cur_vblank = ktime_get();
b5e89ed5	118	if (dev_priv->last_vblank_valid) {
de7e8bd0 AB	119	dev_priv->nsec_per_vblank =
	120	ktime_sub(cur_vblank,
	121	dev_priv->last_vblank) >> 4;
22f579c6 DA	122	}
	123	dev_priv->last_vblank = cur_vblank;
	124	dev_priv->last_vblank_valid = 1;
b5e89ed5	125	}
0a3e67a4	126	if (!(atomic_read(&dev_priv->vbl_received) & 0xFF)) {
de7e8bd0 AB	127	DRM_DEBUG("nsec per vblank is: %llu\n",
de7e8bd0 AB	128	ktime_to_ns(dev_priv->nsec_per_vblank));
22f579c6	129	}
0a3e67a4	130	drm_handle_vblank(dev, 0);
22f579c6 DA	131	handled = 1;
22f579c6 DA	132	}
22f579c6	133
b5e89ed5	134	for (i = 0; i < dev_priv->num_irqs; ++i) {
22f579c6	135	if (status & cur_irq->pending_mask) {
b5e89ed5	136	atomic_inc(&cur_irq->irq_received);
57ed0f7b	137	wake_up(&cur_irq->irq_queue);
22f579c6	138	handled = 1;
58c1e85a	139	if (dev_priv->irq_map[drm_via_irq_dma0_td] == i)
92514243	140	via_dmablit_handler(dev, 0, 1);
58c1e85a	141	else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i)
92514243	142	via_dmablit_handler(dev, 1, 1);
22f579c6 DA	143	}
	144	cur_irq++;
	145	}
b5e89ed5	146
3ad2f3fb	147	/* Acknowledge interrupts */
3bf2a06e	148	via_write(dev_priv, VIA_REG_INTERRUPT, status);
22f579c6	149
0a3e67a4	150
22f579c6 DA	151	if (handled)
	152	return IRQ_HANDLED;
	153	else
	154	return IRQ_NONE;
	155	}
	156
58c1e85a	157	static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv)
22f579c6 DA	158	{
	159	u32 status;
	160
	161	if (dev_priv) {
3ad2f3fb	162	/* Acknowledge interrupts */
3bf2a06e SR	163	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	164	via_write(dev_priv, VIA_REG_INTERRUPT, status \|
22f579c6 DA	165	dev_priv->irq_pending_mask);
	166	}
	167	}
	168
88e72717	169	int via_enable_vblank(struct drm_device *dev, unsigned int pipe)
22f579c6	170	{
0a3e67a4 JB	171	drm_via_private_t *dev_priv = dev->dev_private;
0a3e67a4 JB	172	u32 status;
22f579c6	173
88e72717 TR	174	if (pipe != 0) {
88e72717 TR	175	DRM_ERROR("%s: bad crtc %u\n", __func__, pipe);
22f579c6 DA	176	return -EINVAL;
	177	}
	178
3bf2a06e SR	179	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	180	via_write(dev_priv, VIA_REG_INTERRUPT, status \| VIA_IRQ_VBLANK_ENABLE);
0a3e67a4	181
3bf2a06e SR	182	via_write8(dev_priv, 0x83d4, 0x11);
3bf2a06e SR	183	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
22f579c6	184
0a3e67a4 JB	185	return 0;
0a3e67a4 JB	186	}
22f579c6	187
88e72717	188	void via_disable_vblank(struct drm_device *dev, unsigned int pipe)
0a3e67a4 JB	189	{
0a3e67a4 JB	190	drm_via_private_t *dev_priv = dev->dev_private;
42dd8619 SF	191	u32 status;
42dd8619 SF	192
3bf2a06e SR	193	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	194	via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
b5e89ed5	195
3bf2a06e SR	196	via_write8(dev_priv, 0x83d4, 0x11);
3bf2a06e SR	197	via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
0a3e67a4	198
88e72717 TR	199	if (pipe != 0)
88e72717 TR	200	DRM_ERROR("%s: bad crtc %u\n", __func__, pipe);
22f579c6 DA	201	}
22f579c6 DA	202
ce60fe02	203	static int
58c1e85a	204	via_driver_irq_wait(struct drm_device *dev, unsigned int irq, int force_sequence,
22f579c6 DA	205	unsigned int *sequence)
	206	{
	207	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	208	unsigned int cur_irq_sequence;
d253258c	209	drm_via_irq_t *cur_irq;
22f579c6	210	int ret = 0;
86678dfd	211	maskarray_t *masks;
92514243	212	int real_irq;
22f579c6	213
3e684eae	214	DRM_DEBUG("\n");
22f579c6 DA	215
22f579c6 DA	216	if (!dev_priv) {
3e684eae	217	DRM_ERROR("called with no initialization\n");
20caafa6	218	return -EINVAL;
22f579c6 DA	219	}
22f579c6 DA	220
92514243	221	if (irq >= drm_via_irq_num) {
3e684eae	222	DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
20caafa6	223	return -EINVAL;
22f579c6	224	}
b5e89ed5	225
92514243 DA	226	real_irq = dev_priv->irq_map[irq];
	227
	228	if (real_irq < 0) {
3e684eae MN	229	DRM_ERROR("Video IRQ %d not available on this hardware.\n",
3e684eae MN	230	irq);
20caafa6	231	return -EINVAL;
92514243	232	}
86678dfd DA	233
86678dfd DA	234	masks = dev_priv->irq_masks;
d253258c	235	cur_irq = dev_priv->via_irqs + real_irq;
22f579c6	236
92514243	237	if (masks[real_irq][2] && !force_sequence) {
9154e60c	238	VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
3bf2a06e	239	((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
b5e89ed5	240	masks[irq][4]));
22f579c6 DA	241	cur_irq_sequence = atomic_read(&cur_irq->irq_received);
22f579c6 DA	242	} else {
9154e60c	243	VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
b5e89ed5 DA	244	(((cur_irq_sequence =
	245	atomic_read(&cur_irq->irq_received)) -
	246	*sequence) <= (1 << 23)));
22f579c6 DA	247	}
	248	*sequence = cur_irq_sequence;
	249	return ret;
	250	}
	251
0a3e67a4	252
22f579c6 DA	253	/*
	254	* drm_dma.h hooks
	255	*/
	256
58c1e85a	257	void via_driver_irq_preinstall(struct drm_device *dev)
22f579c6 DA	258	{
	259	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	260	u32 status;
d253258c	261	drm_via_irq_t *cur_irq;
22f579c6 DA	262	int i;
22f579c6 DA	263
3e684eae	264	DRM_DEBUG("dev_priv: %p\n", dev_priv);
22f579c6	265	if (dev_priv) {
d253258c	266	cur_irq = dev_priv->via_irqs;
22f579c6 DA	267
	268	dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
	269	dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
	270
689692e7 TH	271	if (dev_priv->chipset == VIA_PRO_GROUP_A \|\|
	272	dev_priv->chipset == VIA_DX9_0) {
	273	dev_priv->irq_masks = via_pro_group_a_irqs;
	274	dev_priv->num_irqs = via_num_pro_group_a;
	275	dev_priv->irq_map = via_irqmap_pro_group_a;
	276	} else {
	277	dev_priv->irq_masks = via_unichrome_irqs;
	278	dev_priv->num_irqs = via_num_unichrome;
	279	dev_priv->irq_map = via_irqmap_unichrome;
	280	}
b5e89ed5 DA	281
b5e89ed5 DA	282	for (i = 0; i < dev_priv->num_irqs; ++i) {
22f579c6	283	atomic_set(&cur_irq->irq_received, 0);
b5e89ed5	284	cur_irq->enable_mask = dev_priv->irq_masks[i][0];
22f579c6	285	cur_irq->pending_mask = dev_priv->irq_masks[i][1];
57ed0f7b	286	init_waitqueue_head(&cur_irq->irq_queue);
22f579c6 DA	287	dev_priv->irq_enable_mask \|= cur_irq->enable_mask;
	288	dev_priv->irq_pending_mask \|= cur_irq->pending_mask;
	289	cur_irq++;
b5e89ed5	290
22f579c6 DA	291	DRM_DEBUG("Initializing IRQ %d\n", i);
22f579c6 DA	292	}
b5e89ed5 DA	293
b5e89ed5 DA	294	dev_priv->last_vblank_valid = 0;
22f579c6	295
92514243	296	/* Clear VSync interrupt regs */
3bf2a06e SR	297	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	298	via_write(dev_priv, VIA_REG_INTERRUPT, status &
22f579c6	299	~(dev_priv->irq_enable_mask));
b5e89ed5	300
22f579c6 DA	301	/* Clear bits if they're already high */
	302	viadrv_acknowledge_irqs(dev_priv);
	303	}
	304	}
	305
0a3e67a4	306	int via_driver_irq_postinstall(struct drm_device *dev)
22f579c6 DA	307	{
	308	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	309	u32 status;
	310
0a3e67a4 JB	311	DRM_DEBUG("via_driver_irq_postinstall\n");
	312	if (!dev_priv)
	313	return -EINVAL;
22f579c6	314
3bf2a06e SR	315	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	316	via_write(dev_priv, VIA_REG_INTERRUPT, status \| VIA_IRQ_GLOBAL
0a3e67a4	317	\| dev_priv->irq_enable_mask);
22f579c6	318
0a3e67a4	319	/* Some magic, oh for some data sheets ! */
3bf2a06e SR	320	via_write8(dev_priv, 0x83d4, 0x11);
3bf2a06e SR	321	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
b5e89ed5	322
0a3e67a4	323	return 0;
22f579c6 DA	324	}
22f579c6 DA	325
58c1e85a	326	void via_driver_irq_uninstall(struct drm_device *dev)
22f579c6 DA	327	{
	328	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	329	u32 status;
	330
3e684eae	331	DRM_DEBUG("\n");
22f579c6 DA	332	if (dev_priv) {
	333
	334	/* Some more magic, oh for some data sheets ! */
	335
3bf2a06e SR	336	via_write8(dev_priv, 0x83d4, 0x11);
3bf2a06e SR	337	via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
22f579c6	338
3bf2a06e SR	339	status = via_read(dev_priv, VIA_REG_INTERRUPT);
3bf2a06e SR	340	via_write(dev_priv, VIA_REG_INTERRUPT, status &
22f579c6 DA	341	~(VIA_IRQ_VBLANK_ENABLE \| dev_priv->irq_enable_mask));
	342	}
	343	}
	344
c153f45f	345	int via_wait_irq(struct drm_device dev, void data, struct drm_file *file_priv)
22f579c6	346	{
c153f45f	347	drm_via_irqwait_t *irqwait = data;
44a2d564	348	struct timespec64 now;
22f579c6 DA	349	int ret = 0;
	350	drm_via_private_t dev_priv = (drm_via_private_t ) dev->dev_private;
	351	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
	352	int force_sequence;
	353
c153f45f	354	if (irqwait->request.irq >= dev_priv->num_irqs) {
3e684eae	355	DRM_ERROR("Trying to wait on unknown irq %d\n",
c153f45f	356	irqwait->request.irq);
20caafa6	357	return -EINVAL;
22f579c6 DA	358	}
22f579c6 DA	359
c153f45f	360	cur_irq += irqwait->request.irq;
22f579c6	361
c153f45f	362	switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
22f579c6	363	case VIA_IRQ_RELATIVE:
0a3e67a4 JB	364	irqwait->request.sequence +=
0a3e67a4 JB	365	atomic_read(&cur_irq->irq_received);
c153f45f	366	irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
22f579c6 DA	367	case VIA_IRQ_ABSOLUTE:
	368	break;
	369	default:
20caafa6	370	return -EINVAL;
22f579c6 DA	371	}
22f579c6 DA	372
c153f45f	373	if (irqwait->request.type & VIA_IRQ_SIGNAL) {
3e684eae	374	DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
20caafa6	375	return -EINVAL;
22f579c6 DA	376	}
22f579c6 DA	377
c153f45f	378	force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
22f579c6	379
c153f45f EA	380	ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
c153f45f EA	381	&irqwait->request.sequence);
44a2d564	382	ktime_get_ts64(&now);
c153f45f	383	irqwait->reply.tval_sec = now.tv_sec;
44a2d564	384	irqwait->reply.tval_usec = now.tv_nsec / NSEC_PER_USEC;
22f579c6 DA	385
	386	return ret;
	387	}