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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
fb1d9738 | 28 | |
760285e7 | 29 | #include <drm/drmP.h> |
fb1d9738 | 30 | #include "vmwgfx_drv.h" |
760285e7 DH |
31 | #include <drm/ttm/ttm_placement.h> |
32 | #include <drm/ttm/ttm_bo_driver.h> | |
33 | #include <drm/ttm/ttm_object.h> | |
34 | #include <drm/ttm/ttm_module.h> | |
d92d9851 | 35 | #include <linux/dma_remapping.h> |
fb1d9738 JB |
36 | |
37 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
38 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
39 | #define VMWGFX_CHIP_SVGAII 0 | |
40 | #define VMW_FB_RESERVATION 0 | |
41 | ||
eb4f923b JB |
42 | #define VMW_MIN_INITIAL_WIDTH 800 |
43 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
44 | ||
45 | ||
fb1d9738 JB |
46 | /** |
47 | * Fully encoded drm commands. Might move to vmw_drm.h | |
48 | */ | |
49 | ||
50 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
51 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
52 | struct drm_vmw_getparam_arg) | |
53 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
54 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
55 | union drm_vmw_alloc_dmabuf_arg) | |
56 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
57 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
58 | struct drm_vmw_unref_dmabuf_arg) | |
59 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
60 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
61 | struct drm_vmw_cursor_bypass_arg) | |
62 | ||
63 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
65 | struct drm_vmw_control_stream_arg) | |
66 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
67 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
68 | struct drm_vmw_stream_arg) | |
69 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
70 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
71 | struct drm_vmw_stream_arg) | |
72 | ||
73 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
74 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
75 | struct drm_vmw_context_arg) | |
76 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
78 | struct drm_vmw_context_arg) | |
79 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
81 | union drm_vmw_surface_create_arg) | |
82 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
84 | struct drm_vmw_surface_arg) | |
85 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
86 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
87 | union drm_vmw_surface_reference_arg) | |
88 | #define DRM_IOCTL_VMW_EXECBUF \ | |
89 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
90 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
91 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
92 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
93 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
94 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
95 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
96 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
97 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
98 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
99 | struct drm_vmw_fence_signaled_arg) | |
100 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
101 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
102 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
103 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
104 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
105 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
106 | #define DRM_IOCTL_VMW_PRESENT \ |
107 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
108 | struct drm_vmw_present_arg) | |
109 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
110 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
111 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
112 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
113 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
114 | struct drm_vmw_update_layout_arg) | |
c74c162f TH |
115 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
116 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ | |
117 | struct drm_vmw_shader_create_arg) | |
118 | #define DRM_IOCTL_VMW_UNREF_SHADER \ | |
119 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ | |
120 | struct drm_vmw_shader_arg) | |
a97e2192 TH |
121 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
122 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ | |
123 | union drm_vmw_gb_surface_create_arg) | |
124 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ | |
125 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ | |
126 | union drm_vmw_gb_surface_reference_arg) | |
1d7a5cbf TH |
127 | #define DRM_IOCTL_VMW_SYNCCPU \ |
128 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ | |
129 | struct drm_vmw_synccpu_arg) | |
fb1d9738 JB |
130 | |
131 | /** | |
132 | * The core DRM version of this macro doesn't account for | |
133 | * DRM_COMMAND_BASE. | |
134 | */ | |
135 | ||
136 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 137 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
138 | |
139 | /** | |
140 | * Ioctl definitions. | |
141 | */ | |
142 | ||
baa70943 | 143 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
1b2f1489 | 144 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 145 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 146 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 147 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 148 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 149 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 150 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
151 | vmw_kms_cursor_bypass_ioctl, |
152 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 153 | |
1b2f1489 | 154 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 155 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 156 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 157 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 158 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 159 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 160 | |
1b2f1489 | 161 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 162 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 163 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 164 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 165 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 166 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 167 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 168 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 169 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 170 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 171 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 172 | DRM_AUTH | DRM_UNLOCKED), |
ae2a1040 TH |
173 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
174 | DRM_AUTH | DRM_UNLOCKED), | |
175 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, | |
176 | vmw_fence_obj_signaled_ioctl, | |
177 | DRM_AUTH | DRM_UNLOCKED), | |
178 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, | |
d8bd19d2 | 179 | DRM_AUTH | DRM_UNLOCKED), |
57c5ee79 TH |
180 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
181 | vmw_fence_event_ioctl, | |
182 | DRM_AUTH | DRM_UNLOCKED), | |
f63f6a59 TH |
183 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
184 | DRM_AUTH | DRM_UNLOCKED), | |
2fcd5a73 JB |
185 | |
186 | /* these allow direct access to the framebuffers mark as master only */ | |
187 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
188 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
189 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, | |
190 | vmw_present_readback_ioctl, | |
191 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
cd2b89e7 TH |
192 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
193 | vmw_kms_update_layout_ioctl, | |
194 | DRM_MASTER | DRM_UNLOCKED), | |
c74c162f TH |
195 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
196 | vmw_shader_define_ioctl, | |
197 | DRM_AUTH | DRM_UNLOCKED), | |
198 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, | |
199 | vmw_shader_destroy_ioctl, | |
200 | DRM_AUTH | DRM_UNLOCKED), | |
a97e2192 TH |
201 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
202 | vmw_gb_surface_define_ioctl, | |
203 | DRM_AUTH | DRM_UNLOCKED), | |
204 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, | |
205 | vmw_gb_surface_reference_ioctl, | |
206 | DRM_AUTH | DRM_UNLOCKED), | |
1d7a5cbf TH |
207 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
208 | vmw_user_dmabuf_synccpu_ioctl, | |
209 | DRM_AUTH | DRM_UNLOCKED), | |
fb1d9738 JB |
210 | }; |
211 | ||
212 | static struct pci_device_id vmw_pci_id_list[] = { | |
213 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
214 | {0, 0, 0} | |
215 | }; | |
c4903429 | 216 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 217 | |
5d2afab9 | 218 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
d92d9851 TH |
219 | static int vmw_force_iommu; |
220 | static int vmw_restrict_iommu; | |
221 | static int vmw_force_coherent; | |
0d00c488 | 222 | static int vmw_restrict_dma_mask; |
fb1d9738 JB |
223 | |
224 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
225 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
226 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
227 | void *ptr); | |
fb1d9738 | 228 | |
30c78bb8 TH |
229 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
230 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
d92d9851 TH |
231 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
232 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); | |
233 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); | |
234 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); | |
235 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); | |
236 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); | |
0d00c488 TH |
237 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
238 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); | |
d92d9851 | 239 | |
30c78bb8 | 240 | |
fb1d9738 JB |
241 | static void vmw_print_capabilities(uint32_t capabilities) |
242 | { | |
243 | DRM_INFO("Capabilities:\n"); | |
244 | if (capabilities & SVGA_CAP_RECT_COPY) | |
245 | DRM_INFO(" Rect copy.\n"); | |
246 | if (capabilities & SVGA_CAP_CURSOR) | |
247 | DRM_INFO(" Cursor.\n"); | |
248 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
249 | DRM_INFO(" Cursor bypass.\n"); | |
250 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
251 | DRM_INFO(" Cursor bypass 2.\n"); | |
252 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
253 | DRM_INFO(" 8bit emulation.\n"); | |
254 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
255 | DRM_INFO(" Alpha cursor.\n"); | |
256 | if (capabilities & SVGA_CAP_3D) | |
257 | DRM_INFO(" 3D.\n"); | |
258 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
259 | DRM_INFO(" Extended Fifo.\n"); | |
260 | if (capabilities & SVGA_CAP_MULTIMON) | |
261 | DRM_INFO(" Multimon.\n"); | |
262 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
263 | DRM_INFO(" Pitchlock.\n"); | |
264 | if (capabilities & SVGA_CAP_IRQMASK) | |
265 | DRM_INFO(" Irq mask.\n"); | |
266 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
267 | DRM_INFO(" Display Topology.\n"); | |
268 | if (capabilities & SVGA_CAP_GMR) | |
269 | DRM_INFO(" GMR.\n"); | |
270 | if (capabilities & SVGA_CAP_TRACES) | |
271 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
272 | if (capabilities & SVGA_CAP_GMR2) |
273 | DRM_INFO(" GMR2.\n"); | |
274 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
275 | DRM_INFO(" Screen Object 2.\n"); | |
c1234db7 TH |
276 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
277 | DRM_INFO(" Command Buffers.\n"); | |
278 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) | |
279 | DRM_INFO(" Command Buffers 2.\n"); | |
280 | if (capabilities & SVGA_CAP_GBOBJECTS) | |
281 | DRM_INFO(" Guest Backed Resources.\n"); | |
fb1d9738 JB |
282 | } |
283 | ||
e2fa3a76 | 284 | /** |
4b9e45e6 | 285 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
e2fa3a76 | 286 | * |
4b9e45e6 | 287 | * @dev_priv: A device private structure. |
e2fa3a76 | 288 | * |
4b9e45e6 TH |
289 | * This function creates a small buffer object that holds the query |
290 | * result for dummy queries emitted as query barriers. | |
291 | * The function will then map the first page and initialize a pending | |
292 | * occlusion query result structure, Finally it will unmap the buffer. | |
293 | * No interruptible waits are done within this function. | |
e2fa3a76 | 294 | * |
4b9e45e6 | 295 | * Returns an error if bo creation or initialization fails. |
e2fa3a76 | 296 | */ |
4b9e45e6 | 297 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
e2fa3a76 | 298 | { |
4b9e45e6 TH |
299 | int ret; |
300 | struct ttm_buffer_object *bo; | |
e2fa3a76 TH |
301 | struct ttm_bo_kmap_obj map; |
302 | volatile SVGA3dQueryResult *result; | |
303 | bool dummy; | |
e2fa3a76 | 304 | |
4b9e45e6 TH |
305 | /* |
306 | * Create the bo as pinned, so that a tryreserve will | |
307 | * immediately succeed. This is because we're the only | |
308 | * user of the bo currently. | |
309 | */ | |
310 | ret = ttm_bo_create(&dev_priv->bdev, | |
311 | PAGE_SIZE, | |
312 | ttm_bo_type_device, | |
313 | &vmw_sys_ne_placement, | |
314 | 0, false, NULL, | |
315 | &bo); | |
316 | ||
e2fa3a76 | 317 | if (unlikely(ret != 0)) |
4b9e45e6 TH |
318 | return ret; |
319 | ||
320 | ret = ttm_bo_reserve(bo, false, true, false, 0); | |
321 | BUG_ON(ret != 0); | |
e2fa3a76 TH |
322 | |
323 | ret = ttm_bo_kmap(bo, 0, 1, &map); | |
324 | if (likely(ret == 0)) { | |
325 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
326 | result->totalSize = sizeof(*result); | |
327 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
328 | result->result32 = 0xff; | |
329 | ttm_bo_kunmap(&map); | |
4b9e45e6 TH |
330 | } |
331 | vmw_bo_pin(bo, false); | |
e2fa3a76 | 332 | ttm_bo_unreserve(bo); |
e2fa3a76 | 333 | |
4b9e45e6 TH |
334 | if (unlikely(ret != 0)) { |
335 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
336 | ttm_bo_unref(&bo); | |
337 | } else | |
338 | dev_priv->dummy_query_bo = bo; | |
e2fa3a76 | 339 | |
4b9e45e6 | 340 | return ret; |
e2fa3a76 TH |
341 | } |
342 | ||
fb1d9738 JB |
343 | static int vmw_request_device(struct vmw_private *dev_priv) |
344 | { | |
345 | int ret; | |
346 | ||
fb1d9738 JB |
347 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
348 | if (unlikely(ret != 0)) { | |
349 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
350 | return ret; | |
351 | } | |
ae2a1040 | 352 | vmw_fence_fifo_up(dev_priv->fman); |
3530bdc3 TH |
353 | if (dev_priv->has_mob) { |
354 | ret = vmw_otables_setup(dev_priv); | |
355 | if (unlikely(ret != 0)) { | |
356 | DRM_ERROR("Unable to initialize " | |
357 | "guest Memory OBjects.\n"); | |
358 | goto out_no_mob; | |
359 | } | |
360 | } | |
e2fa3a76 TH |
361 | ret = vmw_dummy_query_bo_create(dev_priv); |
362 | if (unlikely(ret != 0)) | |
363 | goto out_no_query_bo; | |
fb1d9738 JB |
364 | |
365 | return 0; | |
e2fa3a76 TH |
366 | |
367 | out_no_query_bo: | |
3530bdc3 TH |
368 | if (dev_priv->has_mob) |
369 | vmw_otables_takedown(dev_priv); | |
370 | out_no_mob: | |
e2fa3a76 TH |
371 | vmw_fence_fifo_down(dev_priv->fman); |
372 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
373 | return ret; | |
fb1d9738 JB |
374 | } |
375 | ||
376 | static void vmw_release_device(struct vmw_private *dev_priv) | |
377 | { | |
e2fa3a76 TH |
378 | /* |
379 | * Previous destructions should've released | |
380 | * the pinned bo. | |
381 | */ | |
382 | ||
383 | BUG_ON(dev_priv->pinned_bo != NULL); | |
384 | ||
385 | ttm_bo_unref(&dev_priv->dummy_query_bo); | |
3530bdc3 TH |
386 | if (dev_priv->has_mob) |
387 | vmw_otables_takedown(dev_priv); | |
ae2a1040 | 388 | vmw_fence_fifo_down(dev_priv->fman); |
fb1d9738 | 389 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
390 | } |
391 | ||
3530bdc3 | 392 | |
05730b32 TH |
393 | /** |
394 | * Increase the 3d resource refcount. | |
395 | * If the count was prevously zero, initialize the fifo, switching to svga | |
396 | * mode. Note that the master holds a ref as well, and may request an | |
397 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
398 | */ | |
399 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
400 | bool unhide_svga) | |
30c78bb8 TH |
401 | { |
402 | int ret = 0; | |
403 | ||
404 | mutex_lock(&dev_priv->release_mutex); | |
405 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
406 | ret = vmw_request_device(dev_priv); | |
407 | if (unlikely(ret != 0)) | |
408 | --dev_priv->num_3d_resources; | |
05730b32 TH |
409 | } else if (unhide_svga) { |
410 | mutex_lock(&dev_priv->hw_mutex); | |
411 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
412 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
413 | ~SVGA_REG_ENABLE_HIDE); | |
414 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 415 | } |
05730b32 | 416 | |
30c78bb8 TH |
417 | mutex_unlock(&dev_priv->release_mutex); |
418 | return ret; | |
fb1d9738 JB |
419 | } |
420 | ||
05730b32 TH |
421 | /** |
422 | * Decrease the 3d resource refcount. | |
423 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
424 | * Note that the master holds a refcount as well, and may request an | |
425 | * explicit switch to vga mode when it releases its refcount to account | |
426 | * for the situation of an X server vt switch to VGA with 3d resources | |
427 | * active. | |
428 | */ | |
429 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
430 | bool hide_svga) | |
30c78bb8 TH |
431 | { |
432 | int32_t n3d; | |
433 | ||
434 | mutex_lock(&dev_priv->release_mutex); | |
435 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
436 | vmw_release_device(dev_priv); | |
05730b32 TH |
437 | else if (hide_svga) { |
438 | mutex_lock(&dev_priv->hw_mutex); | |
439 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
440 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
441 | SVGA_REG_ENABLE_HIDE); | |
442 | mutex_unlock(&dev_priv->hw_mutex); | |
443 | } | |
444 | ||
30c78bb8 TH |
445 | n3d = (int32_t) dev_priv->num_3d_resources; |
446 | mutex_unlock(&dev_priv->release_mutex); | |
447 | ||
448 | BUG_ON(n3d < 0); | |
449 | } | |
450 | ||
eb4f923b JB |
451 | /** |
452 | * Sets the initial_[width|height] fields on the given vmw_private. | |
453 | * | |
454 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
455 | * clamping the value to fb_max_[width|height] fields and the |
456 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
457 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
458 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
459 | */ | |
460 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
461 | { | |
462 | uint32_t width; | |
463 | uint32_t height; | |
464 | ||
465 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
466 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
467 | ||
468 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 469 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
470 | |
471 | if (width > dev_priv->fb_max_width || | |
472 | height > dev_priv->fb_max_height) { | |
473 | ||
474 | /* | |
475 | * This is a host error and shouldn't occur. | |
476 | */ | |
477 | ||
478 | width = VMW_MIN_INITIAL_WIDTH; | |
479 | height = VMW_MIN_INITIAL_HEIGHT; | |
480 | } | |
eb4f923b JB |
481 | |
482 | dev_priv->initial_width = width; | |
483 | dev_priv->initial_height = height; | |
484 | } | |
485 | ||
d92d9851 TH |
486 | /** |
487 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this | |
488 | * system. | |
489 | * | |
490 | * @dev_priv: Pointer to a struct vmw_private | |
491 | * | |
492 | * This functions tries to determine the IOMMU setup and what actions | |
493 | * need to be taken by the driver to make system pages visible to the | |
494 | * device. | |
495 | * If this function decides that DMA is not possible, it returns -EINVAL. | |
496 | * The driver may then try to disable features of the device that require | |
497 | * DMA. | |
498 | */ | |
499 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) | |
500 | { | |
d92d9851 TH |
501 | static const char *names[vmw_dma_map_max] = { |
502 | [vmw_dma_phys] = "Using physical TTM page addresses.", | |
503 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", | |
504 | [vmw_dma_map_populate] = "Keeping DMA mappings.", | |
505 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; | |
e14cd953 TH |
506 | #ifdef CONFIG_X86 |
507 | const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); | |
d92d9851 TH |
508 | |
509 | #ifdef CONFIG_INTEL_IOMMU | |
510 | if (intel_iommu_enabled) { | |
511 | dev_priv->map_mode = vmw_dma_map_populate; | |
512 | goto out_fixup; | |
513 | } | |
514 | #endif | |
515 | ||
516 | if (!(vmw_force_iommu || vmw_force_coherent)) { | |
517 | dev_priv->map_mode = vmw_dma_phys; | |
518 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); | |
519 | return 0; | |
520 | } | |
521 | ||
522 | dev_priv->map_mode = vmw_dma_map_populate; | |
523 | ||
524 | if (dma_ops->sync_single_for_cpu) | |
525 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
526 | #ifdef CONFIG_SWIOTLB | |
527 | if (swiotlb_nr_tbl() == 0) | |
528 | dev_priv->map_mode = vmw_dma_map_populate; | |
529 | #endif | |
530 | ||
21136946 | 531 | #ifdef CONFIG_INTEL_IOMMU |
d92d9851 | 532 | out_fixup: |
21136946 | 533 | #endif |
d92d9851 TH |
534 | if (dev_priv->map_mode == vmw_dma_map_populate && |
535 | vmw_restrict_iommu) | |
536 | dev_priv->map_mode = vmw_dma_map_bind; | |
537 | ||
538 | if (vmw_force_coherent) | |
539 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
540 | ||
541 | #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) | |
542 | /* | |
543 | * No coherent page pool | |
544 | */ | |
545 | if (dev_priv->map_mode == vmw_dma_alloc_coherent) | |
546 | return -EINVAL; | |
547 | #endif | |
548 | ||
e14cd953 TH |
549 | #else /* CONFIG_X86 */ |
550 | dev_priv->map_mode = vmw_dma_map_populate; | |
551 | #endif /* CONFIG_X86 */ | |
552 | ||
d92d9851 TH |
553 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
0d00c488 TH |
558 | /** |
559 | * vmw_dma_masks - set required page- and dma masks | |
560 | * | |
561 | * @dev: Pointer to struct drm-device | |
562 | * | |
563 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that | |
564 | * restriction also for 64-bit systems. | |
565 | */ | |
566 | #ifdef CONFIG_INTEL_IOMMU | |
567 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
568 | { | |
569 | struct drm_device *dev = dev_priv->dev; | |
570 | ||
571 | if (intel_iommu_enabled && | |
572 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { | |
573 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); | |
574 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); | |
575 | } | |
576 | return 0; | |
577 | } | |
578 | #else | |
579 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
580 | { | |
581 | return 0; | |
582 | } | |
583 | #endif | |
584 | ||
fb1d9738 JB |
585 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
586 | { | |
587 | struct vmw_private *dev_priv; | |
588 | int ret; | |
c188660f | 589 | uint32_t svga_id; |
c0951b79 | 590 | enum vmw_res_type i; |
d92d9851 | 591 | bool refuse_dma = false; |
fb1d9738 JB |
592 | |
593 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
594 | if (unlikely(dev_priv == NULL)) { | |
595 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
596 | return -ENOMEM; | |
597 | } | |
fb1d9738 | 598 | |
466e69b8 DA |
599 | pci_set_master(dev->pdev); |
600 | ||
fb1d9738 JB |
601 | dev_priv->dev = dev; |
602 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 603 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 JB |
604 | mutex_init(&dev_priv->hw_mutex); |
605 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 606 | mutex_init(&dev_priv->release_mutex); |
173fb7d4 | 607 | mutex_init(&dev_priv->binding_mutex); |
fb1d9738 | 608 | rwlock_init(&dev_priv->resource_lock); |
c0951b79 TH |
609 | |
610 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
611 | idr_init(&dev_priv->res_idr[i]); | |
612 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
613 | } | |
614 | ||
fb1d9738 JB |
615 | mutex_init(&dev_priv->init_mutex); |
616 | init_waitqueue_head(&dev_priv->fence_queue); | |
617 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 618 | dev_priv->fence_queue_waiters = 0; |
fb1d9738 | 619 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
c0951b79 | 620 | |
5bb39e81 | 621 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
622 | |
623 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
624 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
625 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
626 | ||
30c78bb8 TH |
627 | dev_priv->enable_fb = enable_fbdev; |
628 | ||
fb1d9738 | 629 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
630 | |
631 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
632 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
633 | if (svga_id != SVGA_ID_2) { | |
634 | ret = -ENOSYS; | |
49625904 | 635 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
636 | mutex_unlock(&dev_priv->hw_mutex); |
637 | goto out_err0; | |
638 | } | |
639 | ||
fb1d9738 | 640 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
d92d9851 TH |
641 | ret = vmw_dma_select_mode(dev_priv); |
642 | if (unlikely(ret != 0)) { | |
643 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); | |
644 | refuse_dma = true; | |
645 | } | |
fb1d9738 | 646 | |
5bb39e81 TH |
647 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
648 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
649 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
650 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
651 | |
652 | vmw_get_initial_size(dev_priv); | |
653 | ||
0d00c488 | 654 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
655 | dev_priv->max_gmr_ids = |
656 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
fb17f189 TH |
657 | dev_priv->max_gmr_pages = |
658 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
659 | dev_priv->memory_size = | |
660 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
661 | dev_priv->memory_size -= dev_priv->vram_size; |
662 | } else { | |
663 | /* | |
664 | * An arbitrary limit of 512MiB on surface | |
665 | * memory. But all HWV8 hardware supports GMR2. | |
666 | */ | |
667 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 668 | } |
6da768aa | 669 | dev_priv->max_mob_pages = 0; |
857aea1c | 670 | dev_priv->max_mob_size = 0; |
6da768aa TH |
671 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
672 | uint64_t mem_size = | |
673 | vmw_read(dev_priv, | |
674 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); | |
675 | ||
676 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; | |
afb0e50f TH |
677 | dev_priv->prim_bb_mem = |
678 | vmw_read(dev_priv, | |
679 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); | |
857aea1c CL |
680 | dev_priv->max_mob_size = |
681 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); | |
afb0e50f TH |
682 | } else |
683 | dev_priv->prim_bb_mem = dev_priv->vram_size; | |
fb1d9738 | 684 | |
0d00c488 | 685 | ret = vmw_dma_masks(dev_priv); |
3e894a62 TH |
686 | if (unlikely(ret != 0)) { |
687 | mutex_unlock(&dev_priv->hw_mutex); | |
0d00c488 | 688 | goto out_err0; |
3e894a62 | 689 | } |
0d00c488 | 690 | |
afb0e50f TH |
691 | if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size)) |
692 | dev_priv->prim_bb_mem = dev_priv->vram_size; | |
bc2d6508 | 693 | |
fb1d9738 JB |
694 | mutex_unlock(&dev_priv->hw_mutex); |
695 | ||
696 | vmw_print_capabilities(dev_priv->capabilities); | |
697 | ||
0d00c488 | 698 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
699 | DRM_INFO("Max GMR ids is %u\n", |
700 | (unsigned)dev_priv->max_gmr_ids); | |
fb17f189 TH |
701 | DRM_INFO("Max number of GMR pages is %u\n", |
702 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
703 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
704 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 705 | } |
bc2d6508 TH |
706 | DRM_INFO("Maximum display memory size is %u kiB\n", |
707 | dev_priv->prim_bb_mem / 1024); | |
fb1d9738 JB |
708 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
709 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
710 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
711 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
712 | ||
713 | ret = vmw_ttm_global_init(dev_priv); | |
714 | if (unlikely(ret != 0)) | |
715 | goto out_err0; | |
716 | ||
717 | ||
718 | vmw_master_init(&dev_priv->fbdev_master); | |
719 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
720 | dev_priv->active_master = &dev_priv->fbdev_master; | |
721 | ||
a2c06ee2 | 722 | |
fb1d9738 JB |
723 | ret = ttm_bo_device_init(&dev_priv->bdev, |
724 | dev_priv->bo_global_ref.ref.object, | |
44d847b7 DH |
725 | &vmw_bo_driver, |
726 | dev->anon_inode->i_mapping, | |
727 | VMWGFX_FILE_PAGE_OFFSET, | |
fb1d9738 JB |
728 | false); |
729 | if (unlikely(ret != 0)) { | |
730 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
731 | goto out_err1; | |
732 | } | |
733 | ||
734 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
735 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
736 | if (unlikely(ret != 0)) { | |
737 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
738 | goto out_err2; | |
739 | } | |
740 | ||
135cba0d | 741 | dev_priv->has_gmr = true; |
d92d9851 TH |
742 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || |
743 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
6da768aa | 744 | VMW_PL_GMR) != 0) { |
135cba0d TH |
745 | DRM_INFO("No GMR memory available. " |
746 | "Graphics memory resources are very limited.\n"); | |
747 | dev_priv->has_gmr = false; | |
748 | } | |
749 | ||
6da768aa | 750 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
3530bdc3 | 751 | dev_priv->has_mob = true; |
6da768aa TH |
752 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, |
753 | VMW_PL_MOB) != 0) { | |
754 | DRM_INFO("No MOB memory available. " | |
755 | "3D will be disabled.\n"); | |
756 | dev_priv->has_mob = false; | |
757 | } | |
758 | } | |
3530bdc3 | 759 | |
247d36d7 AL |
760 | dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, |
761 | dev_priv->mmio_size); | |
fb1d9738 JB |
762 | |
763 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
764 | dev_priv->mmio_size); | |
765 | ||
766 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
767 | ret = -ENOMEM; | |
768 | DRM_ERROR("Failed mapping MMIO.\n"); | |
769 | goto out_err3; | |
770 | } | |
771 | ||
d7e1958d JB |
772 | /* Need mmio memory to check for fifo pitchlock cap. */ |
773 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
774 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
775 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
776 | ret = -ENOSYS; | |
777 | DRM_ERROR("Hardware has no pitchlock\n"); | |
778 | goto out_err4; | |
779 | } | |
780 | ||
fb1d9738 | 781 | dev_priv->tdev = ttm_object_device_init |
69977ff5 | 782 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
fb1d9738 JB |
783 | |
784 | if (unlikely(dev_priv->tdev == NULL)) { | |
785 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
786 | ret = -ENOMEM; | |
787 | goto out_err4; | |
788 | } | |
789 | ||
790 | dev->dev_private = dev_priv; | |
791 | ||
fb1d9738 JB |
792 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
793 | dev_priv->stealth = (ret != 0); | |
794 | if (dev_priv->stealth) { | |
795 | /** | |
796 | * Request at least the mmio PCI resource. | |
797 | */ | |
798 | ||
799 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 800 | "Ignore above error if any.\n"); |
fb1d9738 JB |
801 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
802 | if (unlikely(ret != 0)) { | |
803 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
804 | goto out_no_device; | |
805 | } | |
fb1d9738 | 806 | } |
ae2a1040 | 807 | |
506ff75c TH |
808 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
809 | ret = drm_irq_install(dev); | |
810 | if (ret != 0) { | |
811 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
812 | goto out_no_irq; | |
813 | } | |
814 | } | |
815 | ||
ae2a1040 | 816 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
14bbf20c WY |
817 | if (unlikely(dev_priv->fman == NULL)) { |
818 | ret = -ENOMEM; | |
ae2a1040 | 819 | goto out_no_fman; |
14bbf20c | 820 | } |
56d1c78d | 821 | |
56d1c78d | 822 | vmw_kms_save_vga(dev_priv); |
56d1c78d JB |
823 | |
824 | /* Start kms and overlay systems, needs fifo. */ | |
7a1c2f6c TH |
825 | ret = vmw_kms_init(dev_priv); |
826 | if (unlikely(ret != 0)) | |
827 | goto out_no_kms; | |
f2d12b8e | 828 | vmw_overlay_init(dev_priv); |
56d1c78d | 829 | |
30c78bb8 | 830 | if (dev_priv->enable_fb) { |
506ff75c TH |
831 | ret = vmw_3d_resource_inc(dev_priv, true); |
832 | if (unlikely(ret != 0)) | |
833 | goto out_no_fifo; | |
30c78bb8 | 834 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
835 | } |
836 | ||
d9f36a00 TH |
837 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
838 | register_pm_notifier(&dev_priv->pm_nb); | |
839 | ||
fb1d9738 JB |
840 | return 0; |
841 | ||
506ff75c | 842 | out_no_fifo: |
56d1c78d JB |
843 | vmw_overlay_close(dev_priv); |
844 | vmw_kms_close(dev_priv); | |
845 | out_no_kms: | |
506ff75c | 846 | vmw_kms_restore_vga(dev_priv); |
ae2a1040 TH |
847 | vmw_fence_manager_takedown(dev_priv->fman); |
848 | out_no_fman: | |
506ff75c TH |
849 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
850 | drm_irq_uninstall(dev_priv->dev); | |
851 | out_no_irq: | |
30c78bb8 TH |
852 | if (dev_priv->stealth) |
853 | pci_release_region(dev->pdev, 2); | |
854 | else | |
855 | pci_release_regions(dev->pdev); | |
fb1d9738 | 856 | out_no_device: |
fb1d9738 JB |
857 | ttm_object_device_release(&dev_priv->tdev); |
858 | out_err4: | |
859 | iounmap(dev_priv->mmio_virt); | |
860 | out_err3: | |
247d36d7 | 861 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
6da768aa TH |
862 | if (dev_priv->has_mob) |
863 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
135cba0d TH |
864 | if (dev_priv->has_gmr) |
865 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
866 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
867 | out_err2: | |
868 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
869 | out_err1: | |
870 | vmw_ttm_global_release(dev_priv); | |
871 | out_err0: | |
c0951b79 TH |
872 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
873 | idr_destroy(&dev_priv->res_idr[i]); | |
874 | ||
fb1d9738 JB |
875 | kfree(dev_priv); |
876 | return ret; | |
877 | } | |
878 | ||
879 | static int vmw_driver_unload(struct drm_device *dev) | |
880 | { | |
881 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 882 | enum vmw_res_type i; |
fb1d9738 | 883 | |
d9f36a00 TH |
884 | unregister_pm_notifier(&dev_priv->pm_nb); |
885 | ||
c0951b79 TH |
886 | if (dev_priv->ctx.res_ht_initialized) |
887 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
be38ab6e TH |
888 | if (dev_priv->ctx.cmd_bounce) |
889 | vfree(dev_priv->ctx.cmd_bounce); | |
30c78bb8 TH |
890 | if (dev_priv->enable_fb) { |
891 | vmw_fb_close(dev_priv); | |
892 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 893 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 894 | } |
f2d12b8e TH |
895 | vmw_kms_close(dev_priv); |
896 | vmw_overlay_close(dev_priv); | |
ae2a1040 | 897 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c TH |
898 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
899 | drm_irq_uninstall(dev_priv->dev); | |
f2d12b8e | 900 | if (dev_priv->stealth) |
fb1d9738 | 901 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
902 | else |
903 | pci_release_regions(dev->pdev); | |
904 | ||
fb1d9738 JB |
905 | ttm_object_device_release(&dev_priv->tdev); |
906 | iounmap(dev_priv->mmio_virt); | |
247d36d7 | 907 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
6da768aa TH |
908 | if (dev_priv->has_mob) |
909 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
135cba0d TH |
910 | if (dev_priv->has_gmr) |
911 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
912 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
913 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
914 | vmw_ttm_global_release(dev_priv); | |
c0951b79 TH |
915 | |
916 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
917 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
918 | |
919 | kfree(dev_priv); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
6b82ef50 TH |
924 | static void vmw_preclose(struct drm_device *dev, |
925 | struct drm_file *file_priv) | |
926 | { | |
927 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
928 | struct vmw_private *dev_priv = vmw_priv(dev); | |
929 | ||
930 | vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); | |
931 | } | |
932 | ||
fb1d9738 JB |
933 | static void vmw_postclose(struct drm_device *dev, |
934 | struct drm_file *file_priv) | |
935 | { | |
936 | struct vmw_fpriv *vmw_fp; | |
937 | ||
938 | vmw_fp = vmw_fpriv(file_priv); | |
c4249855 TH |
939 | |
940 | if (vmw_fp->locked_master) { | |
941 | struct vmw_master *vmaster = | |
942 | vmw_master(vmw_fp->locked_master); | |
943 | ||
944 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
945 | ttm_vt_unlock(&vmaster->lock); | |
fb1d9738 | 946 | drm_master_put(&vmw_fp->locked_master); |
c4249855 TH |
947 | } |
948 | ||
d5bde956 | 949 | vmw_compat_shader_man_destroy(vmw_fp->shman); |
c4249855 | 950 | ttm_object_file_release(&vmw_fp->tfile); |
fb1d9738 JB |
951 | kfree(vmw_fp); |
952 | } | |
953 | ||
954 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
955 | { | |
956 | struct vmw_private *dev_priv = vmw_priv(dev); | |
957 | struct vmw_fpriv *vmw_fp; | |
958 | int ret = -ENOMEM; | |
959 | ||
960 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
961 | if (unlikely(vmw_fp == NULL)) | |
962 | return ret; | |
963 | ||
6b82ef50 | 964 | INIT_LIST_HEAD(&vmw_fp->fence_events); |
fb1d9738 JB |
965 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
966 | if (unlikely(vmw_fp->tfile == NULL)) | |
967 | goto out_no_tfile; | |
968 | ||
d5bde956 TH |
969 | vmw_fp->shman = vmw_compat_shader_man_create(dev_priv); |
970 | if (IS_ERR(vmw_fp->shman)) | |
971 | goto out_no_shman; | |
972 | ||
fb1d9738 | 973 | file_priv->driver_priv = vmw_fp; |
fb1d9738 JB |
974 | |
975 | return 0; | |
976 | ||
d5bde956 TH |
977 | out_no_shman: |
978 | ttm_object_file_release(&vmw_fp->tfile); | |
fb1d9738 JB |
979 | out_no_tfile: |
980 | kfree(vmw_fp); | |
981 | return ret; | |
982 | } | |
983 | ||
984 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
985 | unsigned long arg) | |
986 | { | |
987 | struct drm_file *file_priv = filp->private_data; | |
988 | struct drm_device *dev = file_priv->minor->dev; | |
989 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
990 | |
991 | /* | |
e1f78003 | 992 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
993 | */ |
994 | ||
995 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
996 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
baa70943 | 997 | const struct drm_ioctl_desc *ioctl = |
fb1d9738 JB |
998 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
999 | ||
2854eeda | 1000 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
1001 | DRM_ERROR("Invalid command format, ioctl %d\n", |
1002 | nr - DRM_COMMAND_BASE); | |
1003 | return -EINVAL; | |
1004 | } | |
fb1d9738 JB |
1005 | } |
1006 | ||
e1f78003 | 1007 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
1008 | } |
1009 | ||
fb1d9738 JB |
1010 | static void vmw_lastclose(struct drm_device *dev) |
1011 | { | |
fb1d9738 JB |
1012 | struct drm_crtc *crtc; |
1013 | struct drm_mode_set set; | |
1014 | int ret; | |
1015 | ||
fb1d9738 JB |
1016 | set.x = 0; |
1017 | set.y = 0; | |
1018 | set.fb = NULL; | |
1019 | set.mode = NULL; | |
1020 | set.connectors = NULL; | |
1021 | set.num_connectors = 0; | |
1022 | ||
1023 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1024 | set.crtc = crtc; | |
2d13b679 | 1025 | ret = drm_mode_set_config_internal(&set); |
fb1d9738 JB |
1026 | WARN_ON(ret != 0); |
1027 | } | |
1028 | ||
1029 | } | |
1030 | ||
1031 | static void vmw_master_init(struct vmw_master *vmaster) | |
1032 | { | |
1033 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
1034 | INIT_LIST_HEAD(&vmaster->fb_surf); |
1035 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
1036 | } |
1037 | ||
1038 | static int vmw_master_create(struct drm_device *dev, | |
1039 | struct drm_master *master) | |
1040 | { | |
1041 | struct vmw_master *vmaster; | |
1042 | ||
fb1d9738 JB |
1043 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
1044 | if (unlikely(vmaster == NULL)) | |
1045 | return -ENOMEM; | |
1046 | ||
3a939a5e | 1047 | vmw_master_init(vmaster); |
fb1d9738 JB |
1048 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
1049 | master->driver_priv = vmaster; | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static void vmw_master_destroy(struct drm_device *dev, | |
1055 | struct drm_master *master) | |
1056 | { | |
1057 | struct vmw_master *vmaster = vmw_master(master); | |
1058 | ||
fb1d9738 JB |
1059 | master->driver_priv = NULL; |
1060 | kfree(vmaster); | |
1061 | } | |
1062 | ||
1063 | ||
1064 | static int vmw_master_set(struct drm_device *dev, | |
1065 | struct drm_file *file_priv, | |
1066 | bool from_open) | |
1067 | { | |
1068 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1069 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1070 | struct vmw_master *active = dev_priv->active_master; | |
1071 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1072 | int ret = 0; | |
1073 | ||
30c78bb8 | 1074 | if (!dev_priv->enable_fb) { |
05730b32 | 1075 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
1076 | if (unlikely(ret != 0)) |
1077 | return ret; | |
1078 | vmw_kms_save_vga(dev_priv); | |
1079 | mutex_lock(&dev_priv->hw_mutex); | |
1080 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
1081 | mutex_unlock(&dev_priv->hw_mutex); | |
1082 | } | |
1083 | ||
fb1d9738 JB |
1084 | if (active) { |
1085 | BUG_ON(active != &dev_priv->fbdev_master); | |
1086 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
1087 | if (unlikely(ret != 0)) | |
1088 | goto out_no_active_lock; | |
1089 | ||
1090 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
1091 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
1092 | if (unlikely(ret != 0)) { | |
1093 | DRM_ERROR("Unable to clean VRAM on " | |
1094 | "master drop.\n"); | |
1095 | } | |
1096 | ||
1097 | dev_priv->active_master = NULL; | |
1098 | } | |
1099 | ||
1100 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
1101 | if (!from_open) { | |
1102 | ttm_vt_unlock(&vmaster->lock); | |
1103 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
1104 | drm_master_put(&vmw_fp->locked_master); | |
1105 | } | |
1106 | ||
1107 | dev_priv->active_master = vmaster; | |
1108 | ||
1109 | return 0; | |
1110 | ||
1111 | out_no_active_lock: | |
30c78bb8 | 1112 | if (!dev_priv->enable_fb) { |
ba723fe8 TH |
1113 | vmw_kms_restore_vga(dev_priv); |
1114 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
1115 | mutex_lock(&dev_priv->hw_mutex); |
1116 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
1117 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 1118 | } |
fb1d9738 JB |
1119 | return ret; |
1120 | } | |
1121 | ||
1122 | static void vmw_master_drop(struct drm_device *dev, | |
1123 | struct drm_file *file_priv, | |
1124 | bool from_release) | |
1125 | { | |
1126 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1127 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1128 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1129 | int ret; | |
1130 | ||
fb1d9738 JB |
1131 | /** |
1132 | * Make sure the master doesn't disappear while we have | |
1133 | * it locked. | |
1134 | */ | |
1135 | ||
1136 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
1137 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
fb1d9738 JB |
1138 | if (unlikely((ret != 0))) { |
1139 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
1140 | drm_master_put(&vmw_fp->locked_master); | |
1141 | } | |
1142 | ||
c4249855 TH |
1143 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
1144 | vmw_execbuf_release_pinned_bo(dev_priv); | |
fb1d9738 | 1145 | |
30c78bb8 TH |
1146 | if (!dev_priv->enable_fb) { |
1147 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
1148 | if (unlikely(ret != 0)) | |
1149 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
ba723fe8 TH |
1150 | vmw_kms_restore_vga(dev_priv); |
1151 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
1152 | mutex_lock(&dev_priv->hw_mutex); |
1153 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
1154 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 TH |
1155 | } |
1156 | ||
fb1d9738 JB |
1157 | dev_priv->active_master = &dev_priv->fbdev_master; |
1158 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
1159 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
1160 | ||
30c78bb8 TH |
1161 | if (dev_priv->enable_fb) |
1162 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
1163 | } |
1164 | ||
1165 | ||
1166 | static void vmw_remove(struct pci_dev *pdev) | |
1167 | { | |
1168 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1169 | ||
1170 | drm_put_dev(dev); | |
1171 | } | |
1172 | ||
d9f36a00 TH |
1173 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1174 | void *ptr) | |
1175 | { | |
1176 | struct vmw_private *dev_priv = | |
1177 | container_of(nb, struct vmw_private, pm_nb); | |
1178 | struct vmw_master *vmaster = dev_priv->active_master; | |
1179 | ||
1180 | switch (val) { | |
1181 | case PM_HIBERNATION_PREPARE: | |
1182 | case PM_SUSPEND_PREPARE: | |
1183 | ttm_suspend_lock(&vmaster->lock); | |
1184 | ||
1185 | /** | |
1186 | * This empties VRAM and unbinds all GMR bindings. | |
1187 | * Buffer contents is moved to swappable memory. | |
1188 | */ | |
c0951b79 TH |
1189 | vmw_execbuf_release_pinned_bo(dev_priv); |
1190 | vmw_resource_evict_all(dev_priv); | |
d9f36a00 | 1191 | ttm_bo_swapout_all(&dev_priv->bdev); |
094e0fa8 | 1192 | |
d9f36a00 TH |
1193 | break; |
1194 | case PM_POST_HIBERNATION: | |
1195 | case PM_POST_SUSPEND: | |
094e0fa8 | 1196 | case PM_POST_RESTORE: |
d9f36a00 | 1197 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 1198 | |
d9f36a00 TH |
1199 | break; |
1200 | case PM_RESTORE_PREPARE: | |
1201 | break; | |
d9f36a00 TH |
1202 | default: |
1203 | break; | |
1204 | } | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | /** | |
1209 | * These might not be needed with the virtual SVGA device. | |
1210 | */ | |
1211 | ||
7fbd721a | 1212 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1213 | { |
094e0fa8 TH |
1214 | struct drm_device *dev = pci_get_drvdata(pdev); |
1215 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1216 | ||
1217 | if (dev_priv->num_3d_resources != 0) { | |
1218 | DRM_INFO("Can't suspend or hibernate " | |
1219 | "while 3D resources are active.\n"); | |
1220 | return -EBUSY; | |
1221 | } | |
1222 | ||
d9f36a00 TH |
1223 | pci_save_state(pdev); |
1224 | pci_disable_device(pdev); | |
1225 | pci_set_power_state(pdev, PCI_D3hot); | |
1226 | return 0; | |
1227 | } | |
1228 | ||
7fbd721a | 1229 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1230 | { |
1231 | pci_set_power_state(pdev, PCI_D0); | |
1232 | pci_restore_state(pdev); | |
1233 | return pci_enable_device(pdev); | |
1234 | } | |
1235 | ||
7fbd721a TH |
1236 | static int vmw_pm_suspend(struct device *kdev) |
1237 | { | |
1238 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1239 | struct pm_message dummy; | |
1240 | ||
1241 | dummy.event = 0; | |
1242 | ||
1243 | return vmw_pci_suspend(pdev, dummy); | |
1244 | } | |
1245 | ||
1246 | static int vmw_pm_resume(struct device *kdev) | |
1247 | { | |
1248 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1249 | ||
1250 | return vmw_pci_resume(pdev); | |
1251 | } | |
1252 | ||
1253 | static int vmw_pm_prepare(struct device *kdev) | |
1254 | { | |
1255 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1256 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1257 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1258 | ||
1259 | /** | |
1260 | * Release 3d reference held by fbdev and potentially | |
1261 | * stop fifo. | |
1262 | */ | |
1263 | dev_priv->suspended = true; | |
1264 | if (dev_priv->enable_fb) | |
05730b32 | 1265 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
1266 | |
1267 | if (dev_priv->num_3d_resources != 0) { | |
1268 | ||
1269 | DRM_INFO("Can't suspend or hibernate " | |
1270 | "while 3D resources are active.\n"); | |
1271 | ||
1272 | if (dev_priv->enable_fb) | |
05730b32 | 1273 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
1274 | dev_priv->suspended = false; |
1275 | return -EBUSY; | |
1276 | } | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | static void vmw_pm_complete(struct device *kdev) | |
1282 | { | |
1283 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1284 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1285 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1286 | ||
95e8f6a2 TH |
1287 | mutex_lock(&dev_priv->hw_mutex); |
1288 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
1289 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
1290 | mutex_unlock(&dev_priv->hw_mutex); | |
1291 | ||
7fbd721a TH |
1292 | /** |
1293 | * Reclaim 3d reference held by fbdev and potentially | |
1294 | * start fifo. | |
1295 | */ | |
1296 | if (dev_priv->enable_fb) | |
05730b32 | 1297 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
1298 | |
1299 | dev_priv->suspended = false; | |
1300 | } | |
1301 | ||
1302 | static const struct dev_pm_ops vmw_pm_ops = { | |
1303 | .prepare = vmw_pm_prepare, | |
1304 | .complete = vmw_pm_complete, | |
1305 | .suspend = vmw_pm_suspend, | |
1306 | .resume = vmw_pm_resume, | |
1307 | }; | |
1308 | ||
e08e96de AV |
1309 | static const struct file_operations vmwgfx_driver_fops = { |
1310 | .owner = THIS_MODULE, | |
1311 | .open = drm_open, | |
1312 | .release = drm_release, | |
1313 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1314 | .mmap = vmw_mmap, | |
1315 | .poll = vmw_fops_poll, | |
1316 | .read = vmw_fops_read, | |
e08e96de AV |
1317 | #if defined(CONFIG_COMPAT) |
1318 | .compat_ioctl = drm_compat_ioctl, | |
1319 | #endif | |
1320 | .llseek = noop_llseek, | |
1321 | }; | |
1322 | ||
fb1d9738 JB |
1323 | static struct drm_driver driver = { |
1324 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
69977ff5 | 1325 | DRIVER_MODESET | DRIVER_PRIME, |
fb1d9738 JB |
1326 | .load = vmw_driver_load, |
1327 | .unload = vmw_driver_unload, | |
fb1d9738 JB |
1328 | .lastclose = vmw_lastclose, |
1329 | .irq_preinstall = vmw_irq_preinstall, | |
1330 | .irq_postinstall = vmw_irq_postinstall, | |
1331 | .irq_uninstall = vmw_irq_uninstall, | |
1332 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1333 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1334 | .enable_vblank = vmw_enable_vblank, |
1335 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 JB |
1336 | .ioctls = vmw_ioctls, |
1337 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
fb1d9738 JB |
1338 | .master_create = vmw_master_create, |
1339 | .master_destroy = vmw_master_destroy, | |
1340 | .master_set = vmw_master_set, | |
1341 | .master_drop = vmw_master_drop, | |
1342 | .open = vmw_driver_open, | |
6b82ef50 | 1343 | .preclose = vmw_preclose, |
fb1d9738 | 1344 | .postclose = vmw_postclose, |
5e1782d2 DA |
1345 | |
1346 | .dumb_create = vmw_dumb_create, | |
1347 | .dumb_map_offset = vmw_dumb_map_offset, | |
1348 | .dumb_destroy = vmw_dumb_destroy, | |
1349 | ||
69977ff5 TH |
1350 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1351 | .prime_handle_to_fd = vmw_prime_handle_to_fd, | |
1352 | ||
e08e96de | 1353 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1354 | .name = VMWGFX_DRIVER_NAME, |
1355 | .desc = VMWGFX_DRIVER_DESC, | |
1356 | .date = VMWGFX_DRIVER_DATE, | |
1357 | .major = VMWGFX_DRIVER_MAJOR, | |
1358 | .minor = VMWGFX_DRIVER_MINOR, | |
1359 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1360 | }; | |
1361 | ||
8410ea3b DA |
1362 | static struct pci_driver vmw_pci_driver = { |
1363 | .name = VMWGFX_DRIVER_NAME, | |
1364 | .id_table = vmw_pci_id_list, | |
1365 | .probe = vmw_probe, | |
1366 | .remove = vmw_remove, | |
1367 | .driver = { | |
1368 | .pm = &vmw_pm_ops | |
1369 | } | |
1370 | }; | |
1371 | ||
fb1d9738 JB |
1372 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1373 | { | |
dcdb1674 | 1374 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1375 | } |
1376 | ||
1377 | static int __init vmwgfx_init(void) | |
1378 | { | |
1379 | int ret; | |
8410ea3b | 1380 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1381 | if (ret) |
1382 | DRM_ERROR("Failed initializing DRM.\n"); | |
1383 | return ret; | |
1384 | } | |
1385 | ||
1386 | static void __exit vmwgfx_exit(void) | |
1387 | { | |
8410ea3b | 1388 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1389 | } |
1390 | ||
1391 | module_init(vmwgfx_init); | |
1392 | module_exit(vmwgfx_exit); | |
1393 | ||
1394 | MODULE_AUTHOR("VMware Inc. and others"); | |
1395 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1396 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1397 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1398 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1399 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1400 | "0"); |