]>
Commit | Line | Data |
---|---|---|
dff96888 | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
fb1d9738 JB |
2 | /************************************************************************** |
3 | * | |
dff96888 | 4 | * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA |
fb1d9738 JB |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
96c5d076 | 28 | #include <linux/console.h> |
fb1d9738 | 29 | |
760285e7 | 30 | #include <drm/drmP.h> |
fb1d9738 | 31 | #include "vmwgfx_drv.h" |
d80efd5c | 32 | #include "vmwgfx_binding.h" |
0b8762e9 | 33 | #include "ttm_object.h" |
760285e7 DH |
34 | #include <drm/ttm/ttm_placement.h> |
35 | #include <drm/ttm/ttm_bo_driver.h> | |
760285e7 | 36 | #include <drm/ttm/ttm_module.h> |
daedaa33 | 37 | #include <linux/intel-iommu.h> |
fb1d9738 | 38 | |
fb1d9738 JB |
39 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" |
40 | #define VMWGFX_CHIP_SVGAII 0 | |
41 | #define VMW_FB_RESERVATION 0 | |
42 | ||
eb4f923b JB |
43 | #define VMW_MIN_INITIAL_WIDTH 800 |
44 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
45 | ||
f9217913 SY |
46 | #ifndef VMWGFX_GIT_VERSION |
47 | #define VMWGFX_GIT_VERSION "Unknown" | |
48 | #endif | |
49 | ||
50 | #define VMWGFX_REPO "In Tree" | |
51 | ||
fd567467 TH |
52 | #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) |
53 | ||
eb4f923b | 54 | |
fb1d9738 JB |
55 | /** |
56 | * Fully encoded drm commands. Might move to vmw_drm.h | |
57 | */ | |
58 | ||
59 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
60 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
61 | struct drm_vmw_getparam_arg) | |
62 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
63 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
64 | union drm_vmw_alloc_dmabuf_arg) | |
65 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
66 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
67 | struct drm_vmw_unref_dmabuf_arg) | |
68 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
69 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
70 | struct drm_vmw_cursor_bypass_arg) | |
71 | ||
72 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
73 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
74 | struct drm_vmw_control_stream_arg) | |
75 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
76 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
77 | struct drm_vmw_stream_arg) | |
78 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
79 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
80 | struct drm_vmw_stream_arg) | |
81 | ||
82 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
83 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
84 | struct drm_vmw_context_arg) | |
85 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
86 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
87 | struct drm_vmw_context_arg) | |
88 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
89 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
90 | union drm_vmw_surface_create_arg) | |
91 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
92 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
93 | struct drm_vmw_surface_arg) | |
94 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
95 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
96 | union drm_vmw_surface_reference_arg) | |
97 | #define DRM_IOCTL_VMW_EXECBUF \ | |
98 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
99 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
100 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
101 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
102 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
103 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
104 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
105 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
106 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
107 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
108 | struct drm_vmw_fence_signaled_arg) | |
109 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
110 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
111 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
112 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
113 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
114 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
115 | #define DRM_IOCTL_VMW_PRESENT \ |
116 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
117 | struct drm_vmw_present_arg) | |
118 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
119 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
120 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
121 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
122 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
123 | struct drm_vmw_update_layout_arg) | |
c74c162f TH |
124 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
125 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ | |
126 | struct drm_vmw_shader_create_arg) | |
127 | #define DRM_IOCTL_VMW_UNREF_SHADER \ | |
128 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ | |
129 | struct drm_vmw_shader_arg) | |
a97e2192 TH |
130 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
131 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ | |
132 | union drm_vmw_gb_surface_create_arg) | |
133 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ | |
134 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ | |
135 | union drm_vmw_gb_surface_reference_arg) | |
1d7a5cbf TH |
136 | #define DRM_IOCTL_VMW_SYNCCPU \ |
137 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ | |
138 | struct drm_vmw_synccpu_arg) | |
d80efd5c TH |
139 | #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ |
140 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ | |
141 | struct drm_vmw_context_arg) | |
14b1c33e DR |
142 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ |
143 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ | |
144 | union drm_vmw_gb_surface_create_ext_arg) | |
145 | #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ | |
146 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ | |
147 | union drm_vmw_gb_surface_reference_ext_arg) | |
fb1d9738 JB |
148 | |
149 | /** | |
150 | * The core DRM version of this macro doesn't account for | |
151 | * DRM_COMMAND_BASE. | |
152 | */ | |
153 | ||
154 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
7e7392a6 | 155 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} |
fb1d9738 JB |
156 | |
157 | /** | |
158 | * Ioctl definitions. | |
159 | */ | |
160 | ||
baa70943 | 161 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
1b2f1489 | 162 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
f8c47144 | 163 | DRM_AUTH | DRM_RENDER_ALLOW), |
f1d34bfd | 164 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, |
f8c47144 | 165 | DRM_AUTH | DRM_RENDER_ALLOW), |
f1d34bfd | 166 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, |
f8c47144 | 167 | DRM_RENDER_ALLOW), |
1b2f1489 | 168 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 | 169 | vmw_kms_cursor_bypass_ioctl, |
190c462d | 170 | DRM_MASTER), |
fb1d9738 | 171 | |
1b2f1489 | 172 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
190c462d | 173 | DRM_MASTER), |
1b2f1489 | 174 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
190c462d | 175 | DRM_MASTER), |
1b2f1489 | 176 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
190c462d | 177 | DRM_MASTER), |
fb1d9738 | 178 | |
1b2f1489 | 179 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
f8c47144 | 180 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 181 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
f8c47144 | 182 | DRM_RENDER_ALLOW), |
1b2f1489 | 183 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
f8c47144 | 184 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 185 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
f8c47144 | 186 | DRM_RENDER_ALLOW), |
1b2f1489 | 187 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
f8c47144 DV |
188 | DRM_AUTH | DRM_RENDER_ALLOW), |
189 | VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | | |
d80efd5c | 190 | DRM_RENDER_ALLOW), |
ae2a1040 | 191 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
f8c47144 | 192 | DRM_RENDER_ALLOW), |
ae2a1040 TH |
193 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
194 | vmw_fence_obj_signaled_ioctl, | |
f8c47144 | 195 | DRM_RENDER_ALLOW), |
ae2a1040 | 196 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
f8c47144 | 197 | DRM_RENDER_ALLOW), |
03f80263 | 198 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
f8c47144 | 199 | DRM_AUTH | DRM_RENDER_ALLOW), |
f63f6a59 | 200 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
f8c47144 | 201 | DRM_AUTH | DRM_RENDER_ALLOW), |
2fcd5a73 JB |
202 | |
203 | /* these allow direct access to the framebuffers mark as master only */ | |
204 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
f8c47144 | 205 | DRM_MASTER | DRM_AUTH), |
2fcd5a73 JB |
206 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, |
207 | vmw_present_readback_ioctl, | |
f8c47144 | 208 | DRM_MASTER | DRM_AUTH), |
31788ca8 TH |
209 | /* |
210 | * The permissions of the below ioctl are overridden in | |
211 | * vmw_generic_ioctl(). We require either | |
212 | * DRM_MASTER or capable(CAP_SYS_ADMIN). | |
213 | */ | |
cd2b89e7 TH |
214 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
215 | vmw_kms_update_layout_ioctl, | |
31788ca8 | 216 | DRM_RENDER_ALLOW), |
c74c162f TH |
217 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
218 | vmw_shader_define_ioctl, | |
f8c47144 | 219 | DRM_AUTH | DRM_RENDER_ALLOW), |
c74c162f TH |
220 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
221 | vmw_shader_destroy_ioctl, | |
f8c47144 | 222 | DRM_RENDER_ALLOW), |
a97e2192 TH |
223 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
224 | vmw_gb_surface_define_ioctl, | |
f8c47144 | 225 | DRM_AUTH | DRM_RENDER_ALLOW), |
a97e2192 TH |
226 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
227 | vmw_gb_surface_reference_ioctl, | |
f8c47144 | 228 | DRM_AUTH | DRM_RENDER_ALLOW), |
1d7a5cbf | 229 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
f1d34bfd | 230 | vmw_user_bo_synccpu_ioctl, |
f8c47144 | 231 | DRM_RENDER_ALLOW), |
d80efd5c TH |
232 | VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, |
233 | vmw_extended_context_define_ioctl, | |
f8c47144 | 234 | DRM_AUTH | DRM_RENDER_ALLOW), |
14b1c33e DR |
235 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, |
236 | vmw_gb_surface_define_ext_ioctl, | |
237 | DRM_AUTH | DRM_RENDER_ALLOW), | |
238 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, | |
239 | vmw_gb_surface_reference_ext_ioctl, | |
240 | DRM_AUTH | DRM_RENDER_ALLOW), | |
fb1d9738 JB |
241 | }; |
242 | ||
8046306f | 243 | static const struct pci_device_id vmw_pci_id_list[] = { |
fb1d9738 JB |
244 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, |
245 | {0, 0, 0} | |
246 | }; | |
c4903429 | 247 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 248 | |
5d2afab9 | 249 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
d92d9851 TH |
250 | static int vmw_force_iommu; |
251 | static int vmw_restrict_iommu; | |
252 | static int vmw_force_coherent; | |
0d00c488 | 253 | static int vmw_restrict_dma_mask; |
04319d89 | 254 | static int vmw_assume_16bpp; |
fb1d9738 JB |
255 | |
256 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
257 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
258 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
259 | void *ptr); | |
fb1d9738 | 260 | |
30c78bb8 | 261 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
50f83737 | 262 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); |
d92d9851 | 263 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
50f83737 | 264 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); |
d92d9851 | 265 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); |
50f83737 | 266 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); |
d92d9851 | 267 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); |
50f83737 | 268 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); |
0d00c488 | 269 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
7a9d2001 | 270 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); |
04319d89 SY |
271 | MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); |
272 | module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); | |
d92d9851 | 273 | |
30c78bb8 | 274 | |
3b4c2511 NB |
275 | static void vmw_print_capabilities2(uint32_t capabilities2) |
276 | { | |
277 | DRM_INFO("Capabilities2:\n"); | |
278 | if (capabilities2 & SVGA_CAP2_GROW_OTABLE) | |
279 | DRM_INFO(" Grow oTable.\n"); | |
280 | if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) | |
281 | DRM_INFO(" IntraSurface copy.\n"); | |
282 | } | |
283 | ||
fb1d9738 JB |
284 | static void vmw_print_capabilities(uint32_t capabilities) |
285 | { | |
286 | DRM_INFO("Capabilities:\n"); | |
287 | if (capabilities & SVGA_CAP_RECT_COPY) | |
288 | DRM_INFO(" Rect copy.\n"); | |
289 | if (capabilities & SVGA_CAP_CURSOR) | |
290 | DRM_INFO(" Cursor.\n"); | |
291 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
292 | DRM_INFO(" Cursor bypass.\n"); | |
293 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
294 | DRM_INFO(" Cursor bypass 2.\n"); | |
295 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
296 | DRM_INFO(" 8bit emulation.\n"); | |
297 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
298 | DRM_INFO(" Alpha cursor.\n"); | |
299 | if (capabilities & SVGA_CAP_3D) | |
300 | DRM_INFO(" 3D.\n"); | |
301 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
302 | DRM_INFO(" Extended Fifo.\n"); | |
303 | if (capabilities & SVGA_CAP_MULTIMON) | |
304 | DRM_INFO(" Multimon.\n"); | |
305 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
306 | DRM_INFO(" Pitchlock.\n"); | |
307 | if (capabilities & SVGA_CAP_IRQMASK) | |
308 | DRM_INFO(" Irq mask.\n"); | |
309 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
310 | DRM_INFO(" Display Topology.\n"); | |
311 | if (capabilities & SVGA_CAP_GMR) | |
312 | DRM_INFO(" GMR.\n"); | |
313 | if (capabilities & SVGA_CAP_TRACES) | |
314 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
315 | if (capabilities & SVGA_CAP_GMR2) |
316 | DRM_INFO(" GMR2.\n"); | |
317 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
318 | DRM_INFO(" Screen Object 2.\n"); | |
c1234db7 TH |
319 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
320 | DRM_INFO(" Command Buffers.\n"); | |
321 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) | |
322 | DRM_INFO(" Command Buffers 2.\n"); | |
323 | if (capabilities & SVGA_CAP_GBOBJECTS) | |
324 | DRM_INFO(" Guest Backed Resources.\n"); | |
8ce75f8a SY |
325 | if (capabilities & SVGA_CAP_DX) |
326 | DRM_INFO(" DX Features.\n"); | |
dc366364 TH |
327 | if (capabilities & SVGA_CAP_HP_CMD_QUEUE) |
328 | DRM_INFO(" HP Command Queue.\n"); | |
fb1d9738 JB |
329 | } |
330 | ||
e2fa3a76 | 331 | /** |
4b9e45e6 | 332 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
e2fa3a76 | 333 | * |
4b9e45e6 | 334 | * @dev_priv: A device private structure. |
e2fa3a76 | 335 | * |
4b9e45e6 TH |
336 | * This function creates a small buffer object that holds the query |
337 | * result for dummy queries emitted as query barriers. | |
338 | * The function will then map the first page and initialize a pending | |
339 | * occlusion query result structure, Finally it will unmap the buffer. | |
340 | * No interruptible waits are done within this function. | |
e2fa3a76 | 341 | * |
4b9e45e6 | 342 | * Returns an error if bo creation or initialization fails. |
e2fa3a76 | 343 | */ |
4b9e45e6 | 344 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
e2fa3a76 | 345 | { |
4b9e45e6 | 346 | int ret; |
f1d34bfd | 347 | struct vmw_buffer_object *vbo; |
e2fa3a76 TH |
348 | struct ttm_bo_kmap_obj map; |
349 | volatile SVGA3dQueryResult *result; | |
350 | bool dummy; | |
e2fa3a76 | 351 | |
4b9e45e6 | 352 | /* |
459d0fa7 | 353 | * Create the vbo as pinned, so that a tryreserve will |
4b9e45e6 TH |
354 | * immediately succeed. This is because we're the only |
355 | * user of the bo currently. | |
356 | */ | |
459d0fa7 TH |
357 | vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); |
358 | if (!vbo) | |
359 | return -ENOMEM; | |
4b9e45e6 | 360 | |
f1d34bfd TH |
361 | ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, |
362 | &vmw_sys_ne_placement, false, | |
363 | &vmw_bo_bo_free); | |
e2fa3a76 | 364 | if (unlikely(ret != 0)) |
4b9e45e6 TH |
365 | return ret; |
366 | ||
dfd5e50e | 367 | ret = ttm_bo_reserve(&vbo->base, false, true, NULL); |
4b9e45e6 | 368 | BUG_ON(ret != 0); |
459d0fa7 | 369 | vmw_bo_pin_reserved(vbo, true); |
e2fa3a76 | 370 | |
459d0fa7 | 371 | ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); |
e2fa3a76 TH |
372 | if (likely(ret == 0)) { |
373 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
374 | result->totalSize = sizeof(*result); | |
375 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
376 | result->result32 = 0xff; | |
377 | ttm_bo_kunmap(&map); | |
4b9e45e6 | 378 | } |
459d0fa7 TH |
379 | vmw_bo_pin_reserved(vbo, false); |
380 | ttm_bo_unreserve(&vbo->base); | |
e2fa3a76 | 381 | |
4b9e45e6 TH |
382 | if (unlikely(ret != 0)) { |
383 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
f1d34bfd | 384 | vmw_bo_unreference(&vbo); |
4b9e45e6 | 385 | } else |
459d0fa7 | 386 | dev_priv->dummy_query_bo = vbo; |
e2fa3a76 | 387 | |
4b9e45e6 | 388 | return ret; |
e2fa3a76 TH |
389 | } |
390 | ||
153b3d5b TH |
391 | /** |
392 | * vmw_request_device_late - Perform late device setup | |
393 | * | |
394 | * @dev_priv: Pointer to device private. | |
395 | * | |
396 | * This function performs setup of otables and enables large command | |
397 | * buffer submission. These tasks are split out to a separate function | |
398 | * because it reverts vmw_release_device_early and is intended to be used | |
399 | * by an error path in the hibernation code. | |
400 | */ | |
401 | static int vmw_request_device_late(struct vmw_private *dev_priv) | |
fb1d9738 JB |
402 | { |
403 | int ret; | |
404 | ||
3530bdc3 TH |
405 | if (dev_priv->has_mob) { |
406 | ret = vmw_otables_setup(dev_priv); | |
407 | if (unlikely(ret != 0)) { | |
408 | DRM_ERROR("Unable to initialize " | |
409 | "guest Memory OBjects.\n"); | |
153b3d5b | 410 | return ret; |
3530bdc3 TH |
411 | } |
412 | } | |
153b3d5b | 413 | |
3eab3d9e TH |
414 | if (dev_priv->cman) { |
415 | ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, | |
416 | 256*4096, 2*4096); | |
417 | if (ret) { | |
418 | struct vmw_cmdbuf_man *man = dev_priv->cman; | |
419 | ||
420 | dev_priv->cman = NULL; | |
421 | vmw_cmdbuf_man_destroy(man); | |
422 | } | |
423 | } | |
424 | ||
153b3d5b TH |
425 | return 0; |
426 | } | |
427 | ||
fb1d9738 JB |
428 | static int vmw_request_device(struct vmw_private *dev_priv) |
429 | { | |
430 | int ret; | |
431 | ||
fb1d9738 JB |
432 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
433 | if (unlikely(ret != 0)) { | |
434 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
435 | return ret; | |
436 | } | |
ae2a1040 | 437 | vmw_fence_fifo_up(dev_priv->fman); |
3eab3d9e | 438 | dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); |
d80efd5c | 439 | if (IS_ERR(dev_priv->cman)) { |
3eab3d9e | 440 | dev_priv->cman = NULL; |
d80efd5c | 441 | dev_priv->has_dx = false; |
3530bdc3 | 442 | } |
153b3d5b TH |
443 | |
444 | ret = vmw_request_device_late(dev_priv); | |
445 | if (ret) | |
446 | goto out_no_mob; | |
447 | ||
e2fa3a76 TH |
448 | ret = vmw_dummy_query_bo_create(dev_priv); |
449 | if (unlikely(ret != 0)) | |
450 | goto out_no_query_bo; | |
fb1d9738 JB |
451 | |
452 | return 0; | |
e2fa3a76 TH |
453 | |
454 | out_no_query_bo: | |
3eab3d9e TH |
455 | if (dev_priv->cman) |
456 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
153b3d5b TH |
457 | if (dev_priv->has_mob) { |
458 | (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 459 | vmw_otables_takedown(dev_priv); |
153b3d5b | 460 | } |
3eab3d9e TH |
461 | if (dev_priv->cman) |
462 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
3530bdc3 | 463 | out_no_mob: |
e2fa3a76 TH |
464 | vmw_fence_fifo_down(dev_priv->fman); |
465 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
466 | return ret; | |
fb1d9738 JB |
467 | } |
468 | ||
153b3d5b TH |
469 | /** |
470 | * vmw_release_device_early - Early part of fifo takedown. | |
471 | * | |
472 | * @dev_priv: Pointer to device private struct. | |
473 | * | |
474 | * This is the first part of command submission takedown, to be called before | |
475 | * buffer management is taken down. | |
476 | */ | |
477 | static void vmw_release_device_early(struct vmw_private *dev_priv) | |
fb1d9738 | 478 | { |
e2fa3a76 TH |
479 | /* |
480 | * Previous destructions should've released | |
481 | * the pinned bo. | |
482 | */ | |
483 | ||
484 | BUG_ON(dev_priv->pinned_bo != NULL); | |
485 | ||
f1d34bfd | 486 | vmw_bo_unreference(&dev_priv->dummy_query_bo); |
3eab3d9e TH |
487 | if (dev_priv->cman) |
488 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
30c78bb8 | 489 | |
153b3d5b TH |
490 | if (dev_priv->has_mob) { |
491 | ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 492 | vmw_otables_takedown(dev_priv); |
30c78bb8 | 493 | } |
fb1d9738 JB |
494 | } |
495 | ||
05730b32 | 496 | /** |
153b3d5b TH |
497 | * vmw_release_device_late - Late part of fifo takedown. |
498 | * | |
499 | * @dev_priv: Pointer to device private struct. | |
500 | * | |
501 | * This is the last part of the command submission takedown, to be called when | |
502 | * command submission is no longer needed. It may wait on pending fences. | |
05730b32 | 503 | */ |
153b3d5b | 504 | static void vmw_release_device_late(struct vmw_private *dev_priv) |
30c78bb8 | 505 | { |
153b3d5b | 506 | vmw_fence_fifo_down(dev_priv->fman); |
3eab3d9e TH |
507 | if (dev_priv->cman) |
508 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
30c78bb8 | 509 | |
153b3d5b | 510 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
511 | } |
512 | ||
eb4f923b JB |
513 | /** |
514 | * Sets the initial_[width|height] fields on the given vmw_private. | |
515 | * | |
516 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
517 | * clamping the value to fb_max_[width|height] fields and the |
518 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
519 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
520 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
521 | */ | |
522 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
523 | { | |
524 | uint32_t width; | |
525 | uint32_t height; | |
526 | ||
527 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
528 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
529 | ||
530 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 531 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
532 | |
533 | if (width > dev_priv->fb_max_width || | |
534 | height > dev_priv->fb_max_height) { | |
535 | ||
536 | /* | |
537 | * This is a host error and shouldn't occur. | |
538 | */ | |
539 | ||
540 | width = VMW_MIN_INITIAL_WIDTH; | |
541 | height = VMW_MIN_INITIAL_HEIGHT; | |
542 | } | |
eb4f923b JB |
543 | |
544 | dev_priv->initial_width = width; | |
545 | dev_priv->initial_height = height; | |
546 | } | |
547 | ||
d92d9851 TH |
548 | /** |
549 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this | |
550 | * system. | |
551 | * | |
552 | * @dev_priv: Pointer to a struct vmw_private | |
553 | * | |
554 | * This functions tries to determine the IOMMU setup and what actions | |
555 | * need to be taken by the driver to make system pages visible to the | |
556 | * device. | |
557 | * If this function decides that DMA is not possible, it returns -EINVAL. | |
558 | * The driver may then try to disable features of the device that require | |
559 | * DMA. | |
560 | */ | |
561 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) | |
562 | { | |
d92d9851 TH |
563 | static const char *names[vmw_dma_map_max] = { |
564 | [vmw_dma_phys] = "Using physical TTM page addresses.", | |
565 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", | |
566 | [vmw_dma_map_populate] = "Keeping DMA mappings.", | |
567 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; | |
568 | ||
05f9467e CH |
569 | if (vmw_force_coherent) |
570 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
571 | else if (intel_iommu_enabled) | |
d92d9851 | 572 | dev_priv->map_mode = vmw_dma_map_populate; |
05f9467e | 573 | else if (!vmw_force_iommu) |
d92d9851 | 574 | dev_priv->map_mode = vmw_dma_phys; |
05f9467e | 575 | else if (IS_ENABLED(CONFIG_SWIOTLB) && swiotlb_nr_tbl()) |
2b3cd624 CH |
576 | dev_priv->map_mode = vmw_dma_alloc_coherent; |
577 | else | |
2b3cd624 | 578 | dev_priv->map_mode = vmw_dma_map_populate; |
d92d9851 | 579 | |
05f9467e | 580 | if (dev_priv->map_mode == vmw_dma_map_populate && vmw_restrict_iommu) |
d92d9851 TH |
581 | dev_priv->map_mode = vmw_dma_map_bind; |
582 | ||
9b5bf242 CH |
583 | /* No TTM coherent page pool? FIXME: Ask TTM instead! */ |
584 | if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) && | |
585 | (dev_priv->map_mode == vmw_dma_alloc_coherent)) | |
d92d9851 | 586 | return -EINVAL; |
9b5bf242 | 587 | |
d92d9851 | 588 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
d92d9851 TH |
589 | return 0; |
590 | } | |
591 | ||
0d00c488 TH |
592 | /** |
593 | * vmw_dma_masks - set required page- and dma masks | |
594 | * | |
595 | * @dev: Pointer to struct drm-device | |
596 | * | |
597 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that | |
598 | * restriction also for 64-bit systems. | |
599 | */ | |
0d00c488 TH |
600 | static int vmw_dma_masks(struct vmw_private *dev_priv) |
601 | { | |
602 | struct drm_device *dev = dev_priv->dev; | |
603 | ||
604 | if (intel_iommu_enabled && | |
605 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { | |
606 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); | |
607 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); | |
608 | } | |
609 | return 0; | |
610 | } | |
0d00c488 | 611 | |
fb1d9738 JB |
612 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
613 | { | |
614 | struct vmw_private *dev_priv; | |
615 | int ret; | |
c188660f | 616 | uint32_t svga_id; |
c0951b79 | 617 | enum vmw_res_type i; |
d92d9851 | 618 | bool refuse_dma = false; |
f9217913 | 619 | char host_log[100] = {0}; |
fb1d9738 JB |
620 | |
621 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
1a4adb05 | 622 | if (unlikely(!dev_priv)) { |
fb1d9738 JB |
623 | DRM_ERROR("Failed allocating a device private struct.\n"); |
624 | return -ENOMEM; | |
625 | } | |
fb1d9738 | 626 | |
466e69b8 DA |
627 | pci_set_master(dev->pdev); |
628 | ||
fb1d9738 JB |
629 | dev_priv->dev = dev; |
630 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 631 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 | 632 | mutex_init(&dev_priv->cmdbuf_mutex); |
30c78bb8 | 633 | mutex_init(&dev_priv->release_mutex); |
173fb7d4 | 634 | mutex_init(&dev_priv->binding_mutex); |
93cd1681 | 635 | mutex_init(&dev_priv->global_kms_state_mutex); |
294adf7d | 636 | ttm_lock_init(&dev_priv->reservation_sem); |
13289241 | 637 | spin_lock_init(&dev_priv->resource_lock); |
496eb6fd TH |
638 | spin_lock_init(&dev_priv->hw_lock); |
639 | spin_lock_init(&dev_priv->waiter_lock); | |
640 | spin_lock_init(&dev_priv->cap_lock); | |
153b3d5b | 641 | spin_lock_init(&dev_priv->svga_lock); |
36cc79bc | 642 | spin_lock_init(&dev_priv->cursor_lock); |
c0951b79 TH |
643 | |
644 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
645 | idr_init(&dev_priv->res_idr[i]); | |
646 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
647 | } | |
648 | ||
fb1d9738 JB |
649 | mutex_init(&dev_priv->init_mutex); |
650 | init_waitqueue_head(&dev_priv->fence_queue); | |
651 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 652 | dev_priv->fence_queue_waiters = 0; |
d2e8851a | 653 | dev_priv->fifo_queue_waiters = 0; |
c0951b79 | 654 | |
5bb39e81 | 655 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
656 | |
657 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
658 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
659 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
660 | ||
04319d89 SY |
661 | dev_priv->assume_16bpp = !!vmw_assume_16bpp; |
662 | ||
30c78bb8 TH |
663 | dev_priv->enable_fb = enable_fbdev; |
664 | ||
c188660f PH |
665 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
666 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
667 | if (svga_id != SVGA_ID_2) { | |
668 | ret = -ENOSYS; | |
49625904 | 669 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
670 | goto out_err0; |
671 | } | |
672 | ||
fb1d9738 | 673 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
3b4c2511 NB |
674 | |
675 | if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { | |
676 | dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); | |
677 | } | |
678 | ||
679 | ||
d92d9851 TH |
680 | ret = vmw_dma_select_mode(dev_priv); |
681 | if (unlikely(ret != 0)) { | |
682 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); | |
683 | refuse_dma = true; | |
684 | } | |
fb1d9738 | 685 | |
5bb39e81 TH |
686 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
687 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
688 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
689 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
690 | |
691 | vmw_get_initial_size(dev_priv); | |
692 | ||
0d00c488 | 693 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
694 | dev_priv->max_gmr_ids = |
695 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
fb17f189 TH |
696 | dev_priv->max_gmr_pages = |
697 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
698 | dev_priv->memory_size = | |
699 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
700 | dev_priv->memory_size -= dev_priv->vram_size; |
701 | } else { | |
702 | /* | |
703 | * An arbitrary limit of 512MiB on surface | |
704 | * memory. But all HWV8 hardware supports GMR2. | |
705 | */ | |
706 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 707 | } |
6da768aa | 708 | dev_priv->max_mob_pages = 0; |
857aea1c | 709 | dev_priv->max_mob_size = 0; |
6da768aa TH |
710 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
711 | uint64_t mem_size = | |
712 | vmw_read(dev_priv, | |
713 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); | |
714 | ||
7c20d213 SY |
715 | /* |
716 | * Workaround for low memory 2D VMs to compensate for the | |
717 | * allocation taken by fbdev | |
718 | */ | |
719 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) | |
cef75036 | 720 | mem_size *= 3; |
7c20d213 | 721 | |
6da768aa | 722 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
afb0e50f TH |
723 | dev_priv->prim_bb_mem = |
724 | vmw_read(dev_priv, | |
725 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); | |
857aea1c CL |
726 | dev_priv->max_mob_size = |
727 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); | |
35c05125 SY |
728 | dev_priv->stdu_max_width = |
729 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); | |
730 | dev_priv->stdu_max_height = | |
731 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); | |
732 | ||
733 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
734 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); | |
735 | dev_priv->texture_max_width = vmw_read(dev_priv, | |
736 | SVGA_REG_DEV_CAP); | |
737 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
738 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); | |
739 | dev_priv->texture_max_height = vmw_read(dev_priv, | |
740 | SVGA_REG_DEV_CAP); | |
df45e9d4 TH |
741 | } else { |
742 | dev_priv->texture_max_width = 8192; | |
743 | dev_priv->texture_max_height = 8192; | |
afb0e50f | 744 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
df45e9d4 TH |
745 | } |
746 | ||
35c05125 | 747 | vmw_print_capabilities(dev_priv->capabilities); |
3b4c2511 NB |
748 | if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) |
749 | vmw_print_capabilities2(dev_priv->capabilities2); | |
fb1d9738 | 750 | |
0d00c488 | 751 | ret = vmw_dma_masks(dev_priv); |
496eb6fd | 752 | if (unlikely(ret != 0)) |
0d00c488 TH |
753 | goto out_err0; |
754 | ||
0d00c488 | 755 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
756 | DRM_INFO("Max GMR ids is %u\n", |
757 | (unsigned)dev_priv->max_gmr_ids); | |
fb17f189 TH |
758 | DRM_INFO("Max number of GMR pages is %u\n", |
759 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
760 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
761 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 762 | } |
bc2d6508 TH |
763 | DRM_INFO("Maximum display memory size is %u kiB\n", |
764 | dev_priv->prim_bb_mem / 1024); | |
fb1d9738 JB |
765 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
766 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
767 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
768 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
769 | ||
fb1d9738 JB |
770 | vmw_master_init(&dev_priv->fbdev_master); |
771 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
772 | dev_priv->active_master = &dev_priv->fbdev_master; | |
773 | ||
b76ff5ea TH |
774 | dev_priv->mmio_virt = memremap(dev_priv->mmio_start, |
775 | dev_priv->mmio_size, MEMREMAP_WB); | |
fb1d9738 JB |
776 | |
777 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
778 | ret = -ENOMEM; | |
779 | DRM_ERROR("Failed mapping MMIO.\n"); | |
a64f784b | 780 | goto out_err0; |
fb1d9738 JB |
781 | } |
782 | ||
d7e1958d JB |
783 | /* Need mmio memory to check for fifo pitchlock cap. */ |
784 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
785 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
786 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
787 | ret = -ENOSYS; | |
788 | DRM_ERROR("Hardware has no pitchlock\n"); | |
789 | goto out_err4; | |
790 | } | |
791 | ||
27eb1fa9 CK |
792 | dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, |
793 | &vmw_prime_dmabuf_ops); | |
fb1d9738 JB |
794 | |
795 | if (unlikely(dev_priv->tdev == NULL)) { | |
796 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
797 | ret = -ENOMEM; | |
798 | goto out_err4; | |
799 | } | |
800 | ||
801 | dev->dev_private = dev_priv; | |
802 | ||
fb1d9738 JB |
803 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
804 | dev_priv->stealth = (ret != 0); | |
805 | if (dev_priv->stealth) { | |
806 | /** | |
807 | * Request at least the mmio PCI resource. | |
808 | */ | |
809 | ||
810 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 811 | "Ignore above error if any.\n"); |
fb1d9738 JB |
812 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
813 | if (unlikely(ret != 0)) { | |
814 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
815 | goto out_no_device; | |
816 | } | |
fb1d9738 | 817 | } |
ae2a1040 | 818 | |
506ff75c | 819 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
e300173f | 820 | ret = vmw_irq_install(dev, dev->pdev->irq); |
506ff75c TH |
821 | if (ret != 0) { |
822 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
823 | goto out_no_irq; | |
824 | } | |
825 | } | |
826 | ||
ae2a1040 | 827 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
14bbf20c WY |
828 | if (unlikely(dev_priv->fman == NULL)) { |
829 | ret = -ENOMEM; | |
ae2a1040 | 830 | goto out_no_fman; |
14bbf20c | 831 | } |
56d1c78d | 832 | |
153b3d5b | 833 | ret = ttm_bo_device_init(&dev_priv->bdev, |
153b3d5b TH |
834 | &vmw_bo_driver, |
835 | dev->anon_inode->i_mapping, | |
836 | VMWGFX_FILE_PAGE_OFFSET, | |
837 | false); | |
838 | if (unlikely(ret != 0)) { | |
839 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
840 | goto out_no_bdev; | |
841 | } | |
3458390b | 842 | |
153b3d5b TH |
843 | /* |
844 | * Enable VRAM, but initially don't use it until SVGA is enabled and | |
845 | * unhidden. | |
846 | */ | |
3458390b TH |
847 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, |
848 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
849 | if (unlikely(ret != 0)) { | |
850 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
851 | goto out_no_vram; | |
852 | } | |
153b3d5b | 853 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; |
3458390b TH |
854 | |
855 | dev_priv->has_gmr = true; | |
856 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || | |
857 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
858 | VMW_PL_GMR) != 0) { | |
859 | DRM_INFO("No GMR memory available. " | |
860 | "Graphics memory resources are very limited.\n"); | |
861 | dev_priv->has_gmr = false; | |
862 | } | |
863 | ||
864 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | |
865 | dev_priv->has_mob = true; | |
866 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, | |
867 | VMW_PL_MOB) != 0) { | |
868 | DRM_INFO("No MOB memory available. " | |
869 | "3D will be disabled.\n"); | |
870 | dev_priv->has_mob = false; | |
871 | } | |
872 | } | |
873 | ||
d80efd5c TH |
874 | if (dev_priv->has_mob) { |
875 | spin_lock(&dev_priv->cap_lock); | |
dc75e733 | 876 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); |
d80efd5c TH |
877 | dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); |
878 | spin_unlock(&dev_priv->cap_lock); | |
879 | } | |
880 | ||
fd567467 | 881 | vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); |
7a1c2f6c TH |
882 | ret = vmw_kms_init(dev_priv); |
883 | if (unlikely(ret != 0)) | |
884 | goto out_no_kms; | |
f2d12b8e | 885 | vmw_overlay_init(dev_priv); |
56d1c78d | 886 | |
153b3d5b TH |
887 | ret = vmw_request_device(dev_priv); |
888 | if (ret) | |
889 | goto out_no_fifo; | |
890 | ||
30aeee67 DR |
891 | if (dev_priv->has_dx) { |
892 | /* | |
893 | * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 | |
894 | * support | |
895 | */ | |
896 | if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { | |
897 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
898 | SVGA3D_DEVCAP_SM41); | |
899 | dev_priv->has_sm4_1 = vmw_read(dev_priv, | |
900 | SVGA_REG_DEV_CAP); | |
901 | } | |
902 | } | |
903 | ||
d80efd5c | 904 | DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); |
30aeee67 DR |
905 | DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) |
906 | ? "yes." : "no."); | |
907 | DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); | |
d80efd5c | 908 | |
f9217913 SY |
909 | snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", |
910 | VMWGFX_REPO, VMWGFX_GIT_VERSION); | |
911 | vmw_host_log(host_log); | |
912 | ||
913 | memset(host_log, 0, sizeof(host_log)); | |
914 | snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", | |
915 | VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, | |
916 | VMWGFX_DRIVER_PATCHLEVEL); | |
917 | vmw_host_log(host_log); | |
918 | ||
30c78bb8 | 919 | if (dev_priv->enable_fb) { |
153b3d5b TH |
920 | vmw_fifo_resource_inc(dev_priv); |
921 | vmw_svga_enable(dev_priv); | |
30c78bb8 | 922 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
923 | } |
924 | ||
d9f36a00 TH |
925 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
926 | register_pm_notifier(&dev_priv->pm_nb); | |
927 | ||
fb1d9738 JB |
928 | return 0; |
929 | ||
506ff75c | 930 | out_no_fifo: |
56d1c78d JB |
931 | vmw_overlay_close(dev_priv); |
932 | vmw_kms_close(dev_priv); | |
933 | out_no_kms: | |
3458390b TH |
934 | if (dev_priv->has_mob) |
935 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
936 | if (dev_priv->has_gmr) | |
937 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
938 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
939 | out_no_vram: | |
153b3d5b TH |
940 | (void)ttm_bo_device_release(&dev_priv->bdev); |
941 | out_no_bdev: | |
ae2a1040 TH |
942 | vmw_fence_manager_takedown(dev_priv->fman); |
943 | out_no_fman: | |
506ff75c | 944 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
e300173f | 945 | vmw_irq_uninstall(dev_priv->dev); |
506ff75c | 946 | out_no_irq: |
30c78bb8 TH |
947 | if (dev_priv->stealth) |
948 | pci_release_region(dev->pdev, 2); | |
949 | else | |
950 | pci_release_regions(dev->pdev); | |
fb1d9738 | 951 | out_no_device: |
fb1d9738 JB |
952 | ttm_object_device_release(&dev_priv->tdev); |
953 | out_err4: | |
b76ff5ea | 954 | memunmap(dev_priv->mmio_virt); |
fb1d9738 | 955 | out_err0: |
c0951b79 TH |
956 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
957 | idr_destroy(&dev_priv->res_idr[i]); | |
958 | ||
d80efd5c TH |
959 | if (dev_priv->ctx.staged_bindings) |
960 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
fb1d9738 JB |
961 | kfree(dev_priv); |
962 | return ret; | |
963 | } | |
964 | ||
11b3c20b | 965 | static void vmw_driver_unload(struct drm_device *dev) |
fb1d9738 JB |
966 | { |
967 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 968 | enum vmw_res_type i; |
fb1d9738 | 969 | |
d9f36a00 TH |
970 | unregister_pm_notifier(&dev_priv->pm_nb); |
971 | ||
c0951b79 TH |
972 | if (dev_priv->ctx.res_ht_initialized) |
973 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
a3a1a667 | 974 | vfree(dev_priv->ctx.cmd_bounce); |
30c78bb8 | 975 | if (dev_priv->enable_fb) { |
05c95018 | 976 | vmw_fb_off(dev_priv); |
30c78bb8 | 977 | vmw_fb_close(dev_priv); |
153b3d5b TH |
978 | vmw_fifo_resource_dec(dev_priv); |
979 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 980 | } |
153b3d5b | 981 | |
f2d12b8e TH |
982 | vmw_kms_close(dev_priv); |
983 | vmw_overlay_close(dev_priv); | |
3458390b | 984 | |
3458390b TH |
985 | if (dev_priv->has_gmr) |
986 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
987 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
988 | ||
153b3d5b TH |
989 | vmw_release_device_early(dev_priv); |
990 | if (dev_priv->has_mob) | |
991 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
992 | (void) ttm_bo_device_release(&dev_priv->bdev); | |
993 | vmw_release_device_late(dev_priv); | |
ae2a1040 | 994 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c | 995 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
e300173f | 996 | vmw_irq_uninstall(dev_priv->dev); |
f2d12b8e | 997 | if (dev_priv->stealth) |
fb1d9738 | 998 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
999 | else |
1000 | pci_release_regions(dev->pdev); | |
1001 | ||
fb1d9738 | 1002 | ttm_object_device_release(&dev_priv->tdev); |
b76ff5ea | 1003 | memunmap(dev_priv->mmio_virt); |
d80efd5c TH |
1004 | if (dev_priv->ctx.staged_bindings) |
1005 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
c0951b79 TH |
1006 | |
1007 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
1008 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
1009 | |
1010 | kfree(dev_priv); | |
fb1d9738 JB |
1011 | } |
1012 | ||
1013 | static void vmw_postclose(struct drm_device *dev, | |
1014 | struct drm_file *file_priv) | |
1015 | { | |
1016 | struct vmw_fpriv *vmw_fp; | |
1017 | ||
1018 | vmw_fp = vmw_fpriv(file_priv); | |
c4249855 TH |
1019 | |
1020 | if (vmw_fp->locked_master) { | |
1021 | struct vmw_master *vmaster = | |
1022 | vmw_master(vmw_fp->locked_master); | |
1023 | ||
1024 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
1025 | ttm_vt_unlock(&vmaster->lock); | |
fb1d9738 | 1026 | drm_master_put(&vmw_fp->locked_master); |
c4249855 TH |
1027 | } |
1028 | ||
1029 | ttm_object_file_release(&vmw_fp->tfile); | |
fb1d9738 JB |
1030 | kfree(vmw_fp); |
1031 | } | |
1032 | ||
1033 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
1034 | { | |
1035 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1036 | struct vmw_fpriv *vmw_fp; | |
1037 | int ret = -ENOMEM; | |
1038 | ||
1039 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
1a4adb05 | 1040 | if (unlikely(!vmw_fp)) |
fb1d9738 JB |
1041 | return ret; |
1042 | ||
1043 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
1044 | if (unlikely(vmw_fp->tfile == NULL)) | |
1045 | goto out_no_tfile; | |
1046 | ||
1047 | file_priv->driver_priv = vmw_fp; | |
fb1d9738 JB |
1048 | |
1049 | return 0; | |
1050 | ||
1051 | out_no_tfile: | |
1052 | kfree(vmw_fp); | |
1053 | return ret; | |
1054 | } | |
1055 | ||
64190bde TH |
1056 | static struct vmw_master *vmw_master_check(struct drm_device *dev, |
1057 | struct drm_file *file_priv, | |
1058 | unsigned int flags) | |
1059 | { | |
1060 | int ret; | |
1061 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1062 | struct vmw_master *vmaster; | |
1063 | ||
0d02c4a1 | 1064 | if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) |
64190bde TH |
1065 | return NULL; |
1066 | ||
1067 | ret = mutex_lock_interruptible(&dev->master_mutex); | |
1068 | if (unlikely(ret != 0)) | |
1069 | return ERR_PTR(-ERESTARTSYS); | |
1070 | ||
b3ac9f25 | 1071 | if (drm_is_current_master(file_priv)) { |
64190bde TH |
1072 | mutex_unlock(&dev->master_mutex); |
1073 | return NULL; | |
1074 | } | |
1075 | ||
1076 | /* | |
aa3469ce TH |
1077 | * Check if we were previously master, but now dropped. In that |
1078 | * case, allow at least render node functionality. | |
64190bde TH |
1079 | */ |
1080 | if (vmw_fp->locked_master) { | |
1081 | mutex_unlock(&dev->master_mutex); | |
aa3469ce TH |
1082 | |
1083 | if (flags & DRM_RENDER_ALLOW) | |
1084 | return NULL; | |
1085 | ||
64190bde TH |
1086 | DRM_ERROR("Dropped master trying to access ioctl that " |
1087 | "requires authentication.\n"); | |
1088 | return ERR_PTR(-EACCES); | |
1089 | } | |
1090 | mutex_unlock(&dev->master_mutex); | |
1091 | ||
64190bde TH |
1092 | /* |
1093 | * Take the TTM lock. Possibly sleep waiting for the authenticating | |
1094 | * master to become master again, or for a SIGTERM if the | |
1095 | * authenticating master exits. | |
1096 | */ | |
1097 | vmaster = vmw_master(file_priv->master); | |
1098 | ret = ttm_read_lock(&vmaster->lock, true); | |
1099 | if (unlikely(ret != 0)) | |
1100 | vmaster = ERR_PTR(ret); | |
1101 | ||
1102 | return vmaster; | |
1103 | } | |
1104 | ||
1105 | static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, | |
1106 | unsigned long arg, | |
1107 | long (*ioctl_func)(struct file *, unsigned int, | |
1108 | unsigned long)) | |
fb1d9738 JB |
1109 | { |
1110 | struct drm_file *file_priv = filp->private_data; | |
1111 | struct drm_device *dev = file_priv->minor->dev; | |
1112 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
64190bde TH |
1113 | struct vmw_master *vmaster; |
1114 | unsigned int flags; | |
1115 | long ret; | |
fb1d9738 JB |
1116 | |
1117 | /* | |
e1f78003 | 1118 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
1119 | */ |
1120 | ||
1121 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
1122 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
baa70943 | 1123 | const struct drm_ioctl_desc *ioctl = |
64190bde | 1124 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
fb1d9738 | 1125 | |
d80efd5c TH |
1126 | if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { |
1127 | ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); | |
1128 | if (unlikely(ret != 0)) | |
1129 | return ret; | |
1130 | ||
1131 | if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) | |
1132 | goto out_io_encoding; | |
1133 | ||
1134 | return (long) vmw_execbuf_ioctl(dev, arg, file_priv, | |
1135 | _IOC_SIZE(cmd)); | |
31788ca8 TH |
1136 | } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { |
1137 | if (!drm_is_current_master(file_priv) && | |
1138 | !capable(CAP_SYS_ADMIN)) | |
1139 | return -EACCES; | |
fb1d9738 | 1140 | } |
d80efd5c TH |
1141 | |
1142 | if (unlikely(ioctl->cmd != cmd)) | |
1143 | goto out_io_encoding; | |
1144 | ||
64190bde TH |
1145 | flags = ioctl->flags; |
1146 | } else if (!drm_ioctl_flags(nr, &flags)) | |
1147 | return -EINVAL; | |
1148 | ||
1149 | vmaster = vmw_master_check(dev, file_priv, flags); | |
55579cfe | 1150 | if (IS_ERR(vmaster)) { |
e338c4c2 TH |
1151 | ret = PTR_ERR(vmaster); |
1152 | ||
1153 | if (ret != -ERESTARTSYS) | |
1154 | DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", | |
1155 | nr, ret); | |
1156 | return ret; | |
fb1d9738 JB |
1157 | } |
1158 | ||
64190bde TH |
1159 | ret = ioctl_func(filp, cmd, arg); |
1160 | if (vmaster) | |
1161 | ttm_read_unlock(&vmaster->lock); | |
1162 | ||
1163 | return ret; | |
d80efd5c TH |
1164 | |
1165 | out_io_encoding: | |
1166 | DRM_ERROR("Invalid command format, ioctl %d\n", | |
1167 | nr - DRM_COMMAND_BASE); | |
1168 | ||
1169 | return -EINVAL; | |
64190bde TH |
1170 | } |
1171 | ||
1172 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
1173 | unsigned long arg) | |
1174 | { | |
1175 | return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); | |
fb1d9738 JB |
1176 | } |
1177 | ||
64190bde TH |
1178 | #ifdef CONFIG_COMPAT |
1179 | static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, | |
1180 | unsigned long arg) | |
1181 | { | |
1182 | return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); | |
1183 | } | |
1184 | #endif | |
1185 | ||
fb1d9738 JB |
1186 | static void vmw_lastclose(struct drm_device *dev) |
1187 | { | |
fb1d9738 JB |
1188 | } |
1189 | ||
1190 | static void vmw_master_init(struct vmw_master *vmaster) | |
1191 | { | |
1192 | ttm_lock_init(&vmaster->lock); | |
1193 | } | |
1194 | ||
1195 | static int vmw_master_create(struct drm_device *dev, | |
1196 | struct drm_master *master) | |
1197 | { | |
1198 | struct vmw_master *vmaster; | |
1199 | ||
fb1d9738 | 1200 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
1a4adb05 | 1201 | if (unlikely(!vmaster)) |
fb1d9738 JB |
1202 | return -ENOMEM; |
1203 | ||
3a939a5e | 1204 | vmw_master_init(vmaster); |
fb1d9738 JB |
1205 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
1206 | master->driver_priv = vmaster; | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | static void vmw_master_destroy(struct drm_device *dev, | |
1212 | struct drm_master *master) | |
1213 | { | |
1214 | struct vmw_master *vmaster = vmw_master(master); | |
1215 | ||
fb1d9738 JB |
1216 | master->driver_priv = NULL; |
1217 | kfree(vmaster); | |
1218 | } | |
1219 | ||
fb1d9738 JB |
1220 | static int vmw_master_set(struct drm_device *dev, |
1221 | struct drm_file *file_priv, | |
1222 | bool from_open) | |
1223 | { | |
1224 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1225 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1226 | struct vmw_master *active = dev_priv->active_master; | |
1227 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1228 | int ret = 0; | |
1229 | ||
fb1d9738 JB |
1230 | if (active) { |
1231 | BUG_ON(active != &dev_priv->fbdev_master); | |
1232 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
1233 | if (unlikely(ret != 0)) | |
153b3d5b | 1234 | return ret; |
fb1d9738 JB |
1235 | |
1236 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
fb1d9738 JB |
1237 | dev_priv->active_master = NULL; |
1238 | } | |
1239 | ||
1240 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
1241 | if (!from_open) { | |
1242 | ttm_vt_unlock(&vmaster->lock); | |
1243 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
1244 | drm_master_put(&vmw_fp->locked_master); | |
1245 | } | |
1246 | ||
1247 | dev_priv->active_master = vmaster; | |
5ea17348 | 1248 | drm_sysfs_hotplug_event(dev); |
fb1d9738 JB |
1249 | |
1250 | return 0; | |
fb1d9738 JB |
1251 | } |
1252 | ||
1253 | static void vmw_master_drop(struct drm_device *dev, | |
d6ed682e | 1254 | struct drm_file *file_priv) |
fb1d9738 JB |
1255 | { |
1256 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1257 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1258 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1259 | int ret; | |
1260 | ||
fb1d9738 JB |
1261 | /** |
1262 | * Make sure the master doesn't disappear while we have | |
1263 | * it locked. | |
1264 | */ | |
1265 | ||
1266 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
1267 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
8fbf9d92 | 1268 | vmw_kms_legacy_hotspot_clear(dev_priv); |
fb1d9738 JB |
1269 | if (unlikely((ret != 0))) { |
1270 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
1271 | drm_master_put(&vmw_fp->locked_master); | |
1272 | } | |
1273 | ||
c4249855 | 1274 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
fb1d9738 | 1275 | |
153b3d5b TH |
1276 | if (!dev_priv->enable_fb) |
1277 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 1278 | |
fb1d9738 JB |
1279 | dev_priv->active_master = &dev_priv->fbdev_master; |
1280 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
1281 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
fb1d9738 JB |
1282 | } |
1283 | ||
153b3d5b TH |
1284 | /** |
1285 | * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1286 | * | |
1287 | * @dev_priv: Pointer to device private struct. | |
1288 | * Needs the reservation sem to be held in non-exclusive mode. | |
1289 | */ | |
b9eb1a61 | 1290 | static void __vmw_svga_enable(struct vmw_private *dev_priv) |
153b3d5b TH |
1291 | { |
1292 | spin_lock(&dev_priv->svga_lock); | |
1293 | if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1294 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); | |
1295 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; | |
1296 | } | |
1297 | spin_unlock(&dev_priv->svga_lock); | |
1298 | } | |
1299 | ||
1300 | /** | |
1301 | * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1302 | * | |
1303 | * @dev_priv: Pointer to device private struct. | |
1304 | */ | |
1305 | void vmw_svga_enable(struct vmw_private *dev_priv) | |
1306 | { | |
f08c86c3 | 1307 | (void) ttm_read_lock(&dev_priv->reservation_sem, false); |
153b3d5b TH |
1308 | __vmw_svga_enable(dev_priv); |
1309 | ttm_read_unlock(&dev_priv->reservation_sem); | |
1310 | } | |
1311 | ||
1312 | /** | |
1313 | * __vmw_svga_disable - Disable SVGA mode and use of VRAM. | |
1314 | * | |
1315 | * @dev_priv: Pointer to device private struct. | |
1316 | * Needs the reservation sem to be held in exclusive mode. | |
1317 | * Will not empty VRAM. VRAM must be emptied by caller. | |
1318 | */ | |
b9eb1a61 | 1319 | static void __vmw_svga_disable(struct vmw_private *dev_priv) |
153b3d5b TH |
1320 | { |
1321 | spin_lock(&dev_priv->svga_lock); | |
1322 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1323 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
1324 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
8ce75f8a SY |
1325 | SVGA_REG_ENABLE_HIDE | |
1326 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1327 | } |
1328 | spin_unlock(&dev_priv->svga_lock); | |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo | |
1333 | * running. | |
1334 | * | |
1335 | * @dev_priv: Pointer to device private struct. | |
1336 | * Will empty VRAM. | |
1337 | */ | |
1338 | void vmw_svga_disable(struct vmw_private *dev_priv) | |
1339 | { | |
140bcaa2 TH |
1340 | /* |
1341 | * Disabling SVGA will turn off device modesetting capabilities, so | |
1342 | * notify KMS about that so that it doesn't cache atomic state that | |
1343 | * isn't valid anymore, for example crtcs turned on. | |
1344 | * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), | |
1345 | * but vmw_kms_lost_device() takes the reservation sem and thus we'll | |
1346 | * end up with lock order reversal. Thus, a master may actually perform | |
1347 | * a new modeset just after we call vmw_kms_lost_device() and race with | |
1348 | * vmw_svga_disable(), but that should at worst cause atomic KMS state | |
1349 | * to be inconsistent with the device, causing modesetting problems. | |
1350 | * | |
1351 | */ | |
1352 | vmw_kms_lost_device(dev_priv->dev); | |
153b3d5b TH |
1353 | ttm_write_lock(&dev_priv->reservation_sem, false); |
1354 | spin_lock(&dev_priv->svga_lock); | |
1355 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1356 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
153b3d5b TH |
1357 | spin_unlock(&dev_priv->svga_lock); |
1358 | if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) | |
1359 | DRM_ERROR("Failed evicting VRAM buffers.\n"); | |
8ce75f8a SY |
1360 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
1361 | SVGA_REG_ENABLE_HIDE | | |
1362 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1363 | } else |
1364 | spin_unlock(&dev_priv->svga_lock); | |
1365 | ttm_write_unlock(&dev_priv->reservation_sem); | |
1366 | } | |
fb1d9738 JB |
1367 | |
1368 | static void vmw_remove(struct pci_dev *pdev) | |
1369 | { | |
1370 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1371 | ||
fd3e4d6e | 1372 | pci_disable_device(pdev); |
fb1d9738 JB |
1373 | drm_put_dev(dev); |
1374 | } | |
1375 | ||
d9f36a00 TH |
1376 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1377 | void *ptr) | |
1378 | { | |
1379 | struct vmw_private *dev_priv = | |
1380 | container_of(nb, struct vmw_private, pm_nb); | |
d9f36a00 TH |
1381 | |
1382 | switch (val) { | |
1383 | case PM_HIBERNATION_PREPARE: | |
153b3d5b | 1384 | /* |
c3b9b165 TH |
1385 | * Take the reservation sem in write mode, which will make sure |
1386 | * there are no other processes holding a buffer object | |
1387 | * reservation, meaning we should be able to evict all buffer | |
1388 | * objects if needed. | |
1389 | * Once user-space processes have been frozen, we can release | |
1390 | * the lock again. | |
d9f36a00 | 1391 | */ |
c3b9b165 TH |
1392 | ttm_suspend_lock(&dev_priv->reservation_sem); |
1393 | dev_priv->suspend_locked = true; | |
d9f36a00 TH |
1394 | break; |
1395 | case PM_POST_HIBERNATION: | |
094e0fa8 | 1396 | case PM_POST_RESTORE: |
c3b9b165 TH |
1397 | if (READ_ONCE(dev_priv->suspend_locked)) { |
1398 | dev_priv->suspend_locked = false; | |
1399 | ttm_suspend_unlock(&dev_priv->reservation_sem); | |
1400 | } | |
d9f36a00 | 1401 | break; |
d9f36a00 TH |
1402 | default: |
1403 | break; | |
1404 | } | |
1405 | return 0; | |
1406 | } | |
1407 | ||
7fbd721a | 1408 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1409 | { |
094e0fa8 TH |
1410 | struct drm_device *dev = pci_get_drvdata(pdev); |
1411 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1412 | ||
153b3d5b | 1413 | if (dev_priv->refuse_hibernation) |
094e0fa8 | 1414 | return -EBUSY; |
094e0fa8 | 1415 | |
d9f36a00 TH |
1416 | pci_save_state(pdev); |
1417 | pci_disable_device(pdev); | |
1418 | pci_set_power_state(pdev, PCI_D3hot); | |
1419 | return 0; | |
1420 | } | |
1421 | ||
7fbd721a | 1422 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1423 | { |
1424 | pci_set_power_state(pdev, PCI_D0); | |
1425 | pci_restore_state(pdev); | |
1426 | return pci_enable_device(pdev); | |
1427 | } | |
1428 | ||
7fbd721a TH |
1429 | static int vmw_pm_suspend(struct device *kdev) |
1430 | { | |
1431 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1432 | struct pm_message dummy; | |
1433 | ||
1434 | dummy.event = 0; | |
1435 | ||
1436 | return vmw_pci_suspend(pdev, dummy); | |
1437 | } | |
1438 | ||
1439 | static int vmw_pm_resume(struct device *kdev) | |
1440 | { | |
1441 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1442 | ||
1443 | return vmw_pci_resume(pdev); | |
1444 | } | |
1445 | ||
153b3d5b | 1446 | static int vmw_pm_freeze(struct device *kdev) |
7fbd721a TH |
1447 | { |
1448 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1449 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1450 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c3b9b165 | 1451 | int ret; |
7fbd721a | 1452 | |
c3b9b165 TH |
1453 | /* |
1454 | * Unlock for vmw_kms_suspend. | |
1455 | * No user-space processes should be running now. | |
1456 | */ | |
1457 | ttm_suspend_unlock(&dev_priv->reservation_sem); | |
1458 | ret = vmw_kms_suspend(dev_priv->dev); | |
1459 | if (ret) { | |
1460 | ttm_suspend_lock(&dev_priv->reservation_sem); | |
1461 | DRM_ERROR("Failed to freeze modesetting.\n"); | |
1462 | return ret; | |
1463 | } | |
7fbd721a | 1464 | if (dev_priv->enable_fb) |
c3b9b165 | 1465 | vmw_fb_off(dev_priv); |
7fbd721a | 1466 | |
c3b9b165 TH |
1467 | ttm_suspend_lock(&dev_priv->reservation_sem); |
1468 | vmw_execbuf_release_pinned_bo(dev_priv); | |
1469 | vmw_resource_evict_all(dev_priv); | |
1470 | vmw_release_device_early(dev_priv); | |
1471 | ttm_bo_swapout_all(&dev_priv->bdev); | |
1472 | if (dev_priv->enable_fb) | |
1473 | vmw_fifo_resource_dec(dev_priv); | |
153b3d5b TH |
1474 | if (atomic_read(&dev_priv->num_fifo_resources) != 0) { |
1475 | DRM_ERROR("Can't hibernate while 3D resources are active.\n"); | |
7fbd721a | 1476 | if (dev_priv->enable_fb) |
153b3d5b TH |
1477 | vmw_fifo_resource_inc(dev_priv); |
1478 | WARN_ON(vmw_request_device_late(dev_priv)); | |
c3b9b165 TH |
1479 | dev_priv->suspend_locked = false; |
1480 | ttm_suspend_unlock(&dev_priv->reservation_sem); | |
1481 | if (dev_priv->suspend_state) | |
1482 | vmw_kms_resume(dev); | |
1483 | if (dev_priv->enable_fb) | |
1484 | vmw_fb_on(dev_priv); | |
7fbd721a TH |
1485 | return -EBUSY; |
1486 | } | |
1487 | ||
c3b9b165 TH |
1488 | vmw_fence_fifo_down(dev_priv->fman); |
1489 | __vmw_svga_disable(dev_priv); | |
153b3d5b TH |
1490 | |
1491 | vmw_release_device_late(dev_priv); | |
7fbd721a TH |
1492 | return 0; |
1493 | } | |
1494 | ||
153b3d5b | 1495 | static int vmw_pm_restore(struct device *kdev) |
7fbd721a TH |
1496 | { |
1497 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1498 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1499 | struct vmw_private *dev_priv = vmw_priv(dev); | |
153b3d5b | 1500 | int ret; |
7fbd721a | 1501 | |
95e8f6a2 TH |
1502 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
1503 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
95e8f6a2 | 1504 | |
7fbd721a | 1505 | if (dev_priv->enable_fb) |
153b3d5b TH |
1506 | vmw_fifo_resource_inc(dev_priv); |
1507 | ||
1508 | ret = vmw_request_device(dev_priv); | |
1509 | if (ret) | |
1510 | return ret; | |
1511 | ||
1512 | if (dev_priv->enable_fb) | |
1513 | __vmw_svga_enable(dev_priv); | |
7fbd721a | 1514 | |
c3b9b165 TH |
1515 | vmw_fence_fifo_up(dev_priv->fman); |
1516 | dev_priv->suspend_locked = false; | |
1517 | ttm_suspend_unlock(&dev_priv->reservation_sem); | |
1518 | if (dev_priv->suspend_state) | |
1519 | vmw_kms_resume(dev_priv->dev); | |
1520 | ||
1521 | if (dev_priv->enable_fb) | |
1522 | vmw_fb_on(dev_priv); | |
1523 | ||
153b3d5b | 1524 | return 0; |
7fbd721a TH |
1525 | } |
1526 | ||
1527 | static const struct dev_pm_ops vmw_pm_ops = { | |
153b3d5b TH |
1528 | .freeze = vmw_pm_freeze, |
1529 | .thaw = vmw_pm_restore, | |
1530 | .restore = vmw_pm_restore, | |
7fbd721a TH |
1531 | .suspend = vmw_pm_suspend, |
1532 | .resume = vmw_pm_resume, | |
1533 | }; | |
1534 | ||
e08e96de AV |
1535 | static const struct file_operations vmwgfx_driver_fops = { |
1536 | .owner = THIS_MODULE, | |
1537 | .open = drm_open, | |
1538 | .release = drm_release, | |
1539 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1540 | .mmap = vmw_mmap, | |
1541 | .poll = vmw_fops_poll, | |
1542 | .read = vmw_fops_read, | |
e08e96de | 1543 | #if defined(CONFIG_COMPAT) |
64190bde | 1544 | .compat_ioctl = vmw_compat_ioctl, |
e08e96de AV |
1545 | #endif |
1546 | .llseek = noop_llseek, | |
1547 | }; | |
1548 | ||
fb1d9738 JB |
1549 | static struct drm_driver driver = { |
1550 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
f7c478be | 1551 | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, |
fb1d9738 JB |
1552 | .load = vmw_driver_load, |
1553 | .unload = vmw_driver_unload, | |
fb1d9738 | 1554 | .lastclose = vmw_lastclose, |
7a1c2f6c | 1555 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1556 | .enable_vblank = vmw_enable_vblank, |
1557 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 | 1558 | .ioctls = vmw_ioctls, |
f95aeb17 | 1559 | .num_ioctls = ARRAY_SIZE(vmw_ioctls), |
fb1d9738 JB |
1560 | .master_create = vmw_master_create, |
1561 | .master_destroy = vmw_master_destroy, | |
1562 | .master_set = vmw_master_set, | |
1563 | .master_drop = vmw_master_drop, | |
1564 | .open = vmw_driver_open, | |
1565 | .postclose = vmw_postclose, | |
5e1782d2 DA |
1566 | |
1567 | .dumb_create = vmw_dumb_create, | |
1568 | .dumb_map_offset = vmw_dumb_map_offset, | |
1569 | .dumb_destroy = vmw_dumb_destroy, | |
1570 | ||
69977ff5 TH |
1571 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1572 | .prime_handle_to_fd = vmw_prime_handle_to_fd, | |
1573 | ||
e08e96de | 1574 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1575 | .name = VMWGFX_DRIVER_NAME, |
1576 | .desc = VMWGFX_DRIVER_DESC, | |
1577 | .date = VMWGFX_DRIVER_DATE, | |
1578 | .major = VMWGFX_DRIVER_MAJOR, | |
1579 | .minor = VMWGFX_DRIVER_MINOR, | |
1580 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1581 | }; | |
1582 | ||
8410ea3b DA |
1583 | static struct pci_driver vmw_pci_driver = { |
1584 | .name = VMWGFX_DRIVER_NAME, | |
1585 | .id_table = vmw_pci_id_list, | |
1586 | .probe = vmw_probe, | |
1587 | .remove = vmw_remove, | |
1588 | .driver = { | |
1589 | .pm = &vmw_pm_ops | |
1590 | } | |
1591 | }; | |
1592 | ||
fb1d9738 JB |
1593 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1594 | { | |
dcdb1674 | 1595 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1596 | } |
1597 | ||
1598 | static int __init vmwgfx_init(void) | |
1599 | { | |
1600 | int ret; | |
96c5d076 | 1601 | |
96c5d076 RC |
1602 | if (vgacon_text_force()) |
1603 | return -EINVAL; | |
96c5d076 | 1604 | |
10631d72 | 1605 | ret = pci_register_driver(&vmw_pci_driver); |
fb1d9738 JB |
1606 | if (ret) |
1607 | DRM_ERROR("Failed initializing DRM.\n"); | |
1608 | return ret; | |
1609 | } | |
1610 | ||
1611 | static void __exit vmwgfx_exit(void) | |
1612 | { | |
10631d72 | 1613 | pci_unregister_driver(&vmw_pci_driver); |
fb1d9738 JB |
1614 | } |
1615 | ||
1616 | module_init(vmwgfx_init); | |
1617 | module_exit(vmwgfx_exit); | |
1618 | ||
1619 | MODULE_AUTHOR("VMware Inc. and others"); | |
1620 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1621 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1622 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1623 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1624 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1625 | "0"); |