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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "vmwgfx_drv.h" | |
30 | #include "ttm/ttm_placement.h" | |
31 | #include "ttm/ttm_bo_driver.h" | |
32 | #include "ttm/ttm_object.h" | |
33 | #include "ttm/ttm_module.h" | |
34 | ||
35 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
36 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
37 | #define VMWGFX_CHIP_SVGAII 0 | |
38 | #define VMW_FB_RESERVATION 0 | |
39 | ||
40 | /** | |
41 | * Fully encoded drm commands. Might move to vmw_drm.h | |
42 | */ | |
43 | ||
44 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
45 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
46 | struct drm_vmw_getparam_arg) | |
47 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
48 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
49 | union drm_vmw_alloc_dmabuf_arg) | |
50 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
51 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
52 | struct drm_vmw_unref_dmabuf_arg) | |
53 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
54 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
55 | struct drm_vmw_cursor_bypass_arg) | |
56 | ||
57 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
58 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
59 | struct drm_vmw_control_stream_arg) | |
60 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
61 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
62 | struct drm_vmw_stream_arg) | |
63 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
65 | struct drm_vmw_stream_arg) | |
66 | ||
67 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
68 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
69 | struct drm_vmw_context_arg) | |
70 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
71 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
72 | struct drm_vmw_context_arg) | |
73 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
74 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
75 | union drm_vmw_surface_create_arg) | |
76 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
78 | struct drm_vmw_surface_arg) | |
79 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
81 | union drm_vmw_surface_reference_arg) | |
82 | #define DRM_IOCTL_VMW_EXECBUF \ | |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
84 | struct drm_vmw_execbuf_arg) | |
fb1d9738 JB |
85 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
86 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
87 | struct drm_vmw_fence_wait_arg) | |
f63f6a59 TH |
88 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
89 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
90 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
91 | |
92 | /** | |
93 | * The core DRM version of this macro doesn't account for | |
94 | * DRM_COMMAND_BASE. | |
95 | */ | |
96 | ||
97 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 98 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
99 | |
100 | /** | |
101 | * Ioctl definitions. | |
102 | */ | |
103 | ||
104 | static struct drm_ioctl_desc vmw_ioctls[] = { | |
1b2f1489 | 105 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 106 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 107 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 108 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 109 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 110 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 111 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
112 | vmw_kms_cursor_bypass_ioctl, |
113 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 114 | |
1b2f1489 | 115 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 116 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 117 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 118 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 119 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 120 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 121 | |
1b2f1489 | 122 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 123 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 124 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 125 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 126 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 127 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 128 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 129 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 130 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 131 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 132 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 133 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 134 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl, |
d8bd19d2 | 135 | DRM_AUTH | DRM_UNLOCKED), |
f63f6a59 TH |
136 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
137 | DRM_AUTH | DRM_UNLOCKED), | |
fb1d9738 JB |
138 | }; |
139 | ||
140 | static struct pci_device_id vmw_pci_id_list[] = { | |
141 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
142 | {0, 0, 0} | |
143 | }; | |
144 | ||
30c78bb8 | 145 | static int enable_fbdev; |
fb1d9738 JB |
146 | |
147 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
148 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
149 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
150 | void *ptr); | |
fb1d9738 | 151 | |
30c78bb8 TH |
152 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
153 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
154 | ||
fb1d9738 JB |
155 | static void vmw_print_capabilities(uint32_t capabilities) |
156 | { | |
157 | DRM_INFO("Capabilities:\n"); | |
158 | if (capabilities & SVGA_CAP_RECT_COPY) | |
159 | DRM_INFO(" Rect copy.\n"); | |
160 | if (capabilities & SVGA_CAP_CURSOR) | |
161 | DRM_INFO(" Cursor.\n"); | |
162 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
163 | DRM_INFO(" Cursor bypass.\n"); | |
164 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
165 | DRM_INFO(" Cursor bypass 2.\n"); | |
166 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
167 | DRM_INFO(" 8bit emulation.\n"); | |
168 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
169 | DRM_INFO(" Alpha cursor.\n"); | |
170 | if (capabilities & SVGA_CAP_3D) | |
171 | DRM_INFO(" 3D.\n"); | |
172 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
173 | DRM_INFO(" Extended Fifo.\n"); | |
174 | if (capabilities & SVGA_CAP_MULTIMON) | |
175 | DRM_INFO(" Multimon.\n"); | |
176 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
177 | DRM_INFO(" Pitchlock.\n"); | |
178 | if (capabilities & SVGA_CAP_IRQMASK) | |
179 | DRM_INFO(" Irq mask.\n"); | |
180 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
181 | DRM_INFO(" Display Topology.\n"); | |
182 | if (capabilities & SVGA_CAP_GMR) | |
183 | DRM_INFO(" GMR.\n"); | |
184 | if (capabilities & SVGA_CAP_TRACES) | |
185 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
186 | if (capabilities & SVGA_CAP_GMR2) |
187 | DRM_INFO(" GMR2.\n"); | |
188 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
189 | DRM_INFO(" Screen Object 2.\n"); | |
fb1d9738 JB |
190 | } |
191 | ||
192 | static int vmw_request_device(struct vmw_private *dev_priv) | |
193 | { | |
194 | int ret; | |
195 | ||
fb1d9738 JB |
196 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
197 | if (unlikely(ret != 0)) { | |
198 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
199 | return ret; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static void vmw_release_device(struct vmw_private *dev_priv) | |
206 | { | |
207 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
30c78bb8 TH |
208 | } |
209 | ||
05730b32 TH |
210 | /** |
211 | * Increase the 3d resource refcount. | |
212 | * If the count was prevously zero, initialize the fifo, switching to svga | |
213 | * mode. Note that the master holds a ref as well, and may request an | |
214 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
215 | */ | |
216 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
217 | bool unhide_svga) | |
30c78bb8 TH |
218 | { |
219 | int ret = 0; | |
220 | ||
221 | mutex_lock(&dev_priv->release_mutex); | |
222 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
223 | ret = vmw_request_device(dev_priv); | |
224 | if (unlikely(ret != 0)) | |
225 | --dev_priv->num_3d_resources; | |
05730b32 TH |
226 | } else if (unhide_svga) { |
227 | mutex_lock(&dev_priv->hw_mutex); | |
228 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
229 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
230 | ~SVGA_REG_ENABLE_HIDE); | |
231 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 232 | } |
05730b32 | 233 | |
30c78bb8 TH |
234 | mutex_unlock(&dev_priv->release_mutex); |
235 | return ret; | |
fb1d9738 JB |
236 | } |
237 | ||
05730b32 TH |
238 | /** |
239 | * Decrease the 3d resource refcount. | |
240 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
241 | * Note that the master holds a refcount as well, and may request an | |
242 | * explicit switch to vga mode when it releases its refcount to account | |
243 | * for the situation of an X server vt switch to VGA with 3d resources | |
244 | * active. | |
245 | */ | |
246 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
247 | bool hide_svga) | |
30c78bb8 TH |
248 | { |
249 | int32_t n3d; | |
250 | ||
251 | mutex_lock(&dev_priv->release_mutex); | |
252 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
253 | vmw_release_device(dev_priv); | |
05730b32 TH |
254 | else if (hide_svga) { |
255 | mutex_lock(&dev_priv->hw_mutex); | |
256 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
257 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
258 | SVGA_REG_ENABLE_HIDE); | |
259 | mutex_unlock(&dev_priv->hw_mutex); | |
260 | } | |
261 | ||
30c78bb8 TH |
262 | n3d = (int32_t) dev_priv->num_3d_resources; |
263 | mutex_unlock(&dev_priv->release_mutex); | |
264 | ||
265 | BUG_ON(n3d < 0); | |
266 | } | |
267 | ||
fb1d9738 JB |
268 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
269 | { | |
270 | struct vmw_private *dev_priv; | |
271 | int ret; | |
c188660f | 272 | uint32_t svga_id; |
fb1d9738 JB |
273 | |
274 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
275 | if (unlikely(dev_priv == NULL)) { | |
276 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
277 | return -ENOMEM; | |
278 | } | |
279 | memset(dev_priv, 0, sizeof(*dev_priv)); | |
280 | ||
281 | dev_priv->dev = dev; | |
282 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 283 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 JB |
284 | mutex_init(&dev_priv->hw_mutex); |
285 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 286 | mutex_init(&dev_priv->release_mutex); |
fb1d9738 JB |
287 | rwlock_init(&dev_priv->resource_lock); |
288 | idr_init(&dev_priv->context_idr); | |
289 | idr_init(&dev_priv->surface_idr); | |
290 | idr_init(&dev_priv->stream_idr); | |
fb1d9738 JB |
291 | mutex_init(&dev_priv->init_mutex); |
292 | init_waitqueue_head(&dev_priv->fence_queue); | |
293 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 294 | dev_priv->fence_queue_waiters = 0; |
fb1d9738 | 295 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
fb1d9738 JB |
296 | |
297 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
298 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
299 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
300 | ||
30c78bb8 TH |
301 | dev_priv->enable_fb = enable_fbdev; |
302 | ||
fb1d9738 | 303 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
304 | |
305 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
306 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
307 | if (svga_id != SVGA_ID_2) { | |
308 | ret = -ENOSYS; | |
309 | DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id); | |
310 | mutex_unlock(&dev_priv->hw_mutex); | |
311 | goto out_err0; | |
312 | } | |
313 | ||
fb1d9738 JB |
314 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
315 | ||
316 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
317 | dev_priv->max_gmr_descriptors = | |
318 | vmw_read(dev_priv, | |
319 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); | |
320 | dev_priv->max_gmr_ids = | |
321 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
322 | } | |
fb17f189 TH |
323 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
324 | dev_priv->max_gmr_pages = | |
325 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
326 | dev_priv->memory_size = | |
327 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
328 | } | |
fb1d9738 JB |
329 | |
330 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); | |
331 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
332 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
333 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
334 | ||
335 | mutex_unlock(&dev_priv->hw_mutex); | |
336 | ||
337 | vmw_print_capabilities(dev_priv->capabilities); | |
338 | ||
339 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
340 | DRM_INFO("Max GMR ids is %u\n", | |
341 | (unsigned)dev_priv->max_gmr_ids); | |
342 | DRM_INFO("Max GMR descriptors is %u\n", | |
343 | (unsigned)dev_priv->max_gmr_descriptors); | |
344 | } | |
fb17f189 TH |
345 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
346 | DRM_INFO("Max number of GMR pages is %u\n", | |
347 | (unsigned)dev_priv->max_gmr_pages); | |
348 | DRM_INFO("Max dedicated hypervisor graphics memory is %u\n", | |
349 | (unsigned)dev_priv->memory_size); | |
350 | } | |
fb1d9738 JB |
351 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
352 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
353 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
354 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
355 | ||
356 | ret = vmw_ttm_global_init(dev_priv); | |
357 | if (unlikely(ret != 0)) | |
358 | goto out_err0; | |
359 | ||
360 | ||
361 | vmw_master_init(&dev_priv->fbdev_master); | |
362 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
363 | dev_priv->active_master = &dev_priv->fbdev_master; | |
364 | ||
a2c06ee2 | 365 | |
fb1d9738 JB |
366 | ret = ttm_bo_device_init(&dev_priv->bdev, |
367 | dev_priv->bo_global_ref.ref.object, | |
368 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, | |
369 | false); | |
370 | if (unlikely(ret != 0)) { | |
371 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
372 | goto out_err1; | |
373 | } | |
374 | ||
375 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
376 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
377 | if (unlikely(ret != 0)) { | |
378 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
379 | goto out_err2; | |
380 | } | |
381 | ||
135cba0d TH |
382 | dev_priv->has_gmr = true; |
383 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
384 | dev_priv->max_gmr_ids) != 0) { | |
385 | DRM_INFO("No GMR memory available. " | |
386 | "Graphics memory resources are very limited.\n"); | |
387 | dev_priv->has_gmr = false; | |
388 | } | |
389 | ||
fb1d9738 JB |
390 | dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start, |
391 | dev_priv->mmio_size, DRM_MTRR_WC); | |
392 | ||
393 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
394 | dev_priv->mmio_size); | |
395 | ||
396 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
397 | ret = -ENOMEM; | |
398 | DRM_ERROR("Failed mapping MMIO.\n"); | |
399 | goto out_err3; | |
400 | } | |
401 | ||
d7e1958d JB |
402 | /* Need mmio memory to check for fifo pitchlock cap. */ |
403 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
404 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
405 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
406 | ret = -ENOSYS; | |
407 | DRM_ERROR("Hardware has no pitchlock\n"); | |
408 | goto out_err4; | |
409 | } | |
410 | ||
fb1d9738 JB |
411 | dev_priv->tdev = ttm_object_device_init |
412 | (dev_priv->mem_global_ref.object, 12); | |
413 | ||
414 | if (unlikely(dev_priv->tdev == NULL)) { | |
415 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
416 | ret = -ENOMEM; | |
417 | goto out_err4; | |
418 | } | |
419 | ||
420 | dev->dev_private = dev_priv; | |
421 | ||
fb1d9738 JB |
422 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
423 | dev_priv->stealth = (ret != 0); | |
424 | if (dev_priv->stealth) { | |
425 | /** | |
426 | * Request at least the mmio PCI resource. | |
427 | */ | |
428 | ||
429 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 430 | "Ignore above error if any.\n"); |
fb1d9738 JB |
431 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
432 | if (unlikely(ret != 0)) { | |
433 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
434 | goto out_no_device; | |
435 | } | |
fb1d9738 | 436 | } |
7a1c2f6c TH |
437 | ret = vmw_kms_init(dev_priv); |
438 | if (unlikely(ret != 0)) | |
439 | goto out_no_kms; | |
f2d12b8e | 440 | vmw_overlay_init(dev_priv); |
30c78bb8 | 441 | if (dev_priv->enable_fb) { |
05730b32 | 442 | ret = vmw_3d_resource_inc(dev_priv, false); |
30c78bb8 TH |
443 | if (unlikely(ret != 0)) |
444 | goto out_no_fifo; | |
445 | vmw_kms_save_vga(dev_priv); | |
446 | vmw_fb_init(dev_priv); | |
447 | DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? | |
448 | "Detected device 3D availability.\n" : | |
449 | "Detected no device 3D availability.\n"); | |
450 | } else { | |
451 | DRM_INFO("Delayed 3D detection since we're not " | |
452 | "running the device in SVGA mode yet.\n"); | |
453 | } | |
fb1d9738 | 454 | |
7a1c2f6c TH |
455 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
456 | ret = drm_irq_install(dev); | |
457 | if (unlikely(ret != 0)) { | |
458 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
459 | goto out_no_irq; | |
460 | } | |
461 | } | |
462 | ||
d9f36a00 TH |
463 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
464 | register_pm_notifier(&dev_priv->pm_nb); | |
465 | ||
fb1d9738 JB |
466 | return 0; |
467 | ||
7a1c2f6c TH |
468 | out_no_irq: |
469 | if (dev_priv->enable_fb) { | |
470 | vmw_fb_close(dev_priv); | |
471 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 472 | vmw_3d_resource_dec(dev_priv, false); |
7a1c2f6c | 473 | } |
30c78bb8 TH |
474 | out_no_fifo: |
475 | vmw_overlay_close(dev_priv); | |
476 | vmw_kms_close(dev_priv); | |
7a1c2f6c | 477 | out_no_kms: |
30c78bb8 TH |
478 | if (dev_priv->stealth) |
479 | pci_release_region(dev->pdev, 2); | |
480 | else | |
481 | pci_release_regions(dev->pdev); | |
fb1d9738 | 482 | out_no_device: |
fb1d9738 JB |
483 | ttm_object_device_release(&dev_priv->tdev); |
484 | out_err4: | |
485 | iounmap(dev_priv->mmio_virt); | |
486 | out_err3: | |
487 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
488 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
489 | if (dev_priv->has_gmr) |
490 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
491 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
492 | out_err2: | |
493 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
494 | out_err1: | |
495 | vmw_ttm_global_release(dev_priv); | |
496 | out_err0: | |
fb1d9738 JB |
497 | idr_destroy(&dev_priv->surface_idr); |
498 | idr_destroy(&dev_priv->context_idr); | |
499 | idr_destroy(&dev_priv->stream_idr); | |
500 | kfree(dev_priv); | |
501 | return ret; | |
502 | } | |
503 | ||
504 | static int vmw_driver_unload(struct drm_device *dev) | |
505 | { | |
506 | struct vmw_private *dev_priv = vmw_priv(dev); | |
507 | ||
d9f36a00 TH |
508 | unregister_pm_notifier(&dev_priv->pm_nb); |
509 | ||
be38ab6e TH |
510 | if (dev_priv->ctx.cmd_bounce) |
511 | vfree(dev_priv->ctx.cmd_bounce); | |
7a1c2f6c TH |
512 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
513 | drm_irq_uninstall(dev_priv->dev); | |
30c78bb8 TH |
514 | if (dev_priv->enable_fb) { |
515 | vmw_fb_close(dev_priv); | |
516 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 517 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 518 | } |
f2d12b8e TH |
519 | vmw_kms_close(dev_priv); |
520 | vmw_overlay_close(dev_priv); | |
f2d12b8e | 521 | if (dev_priv->stealth) |
fb1d9738 | 522 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
523 | else |
524 | pci_release_regions(dev->pdev); | |
525 | ||
fb1d9738 JB |
526 | ttm_object_device_release(&dev_priv->tdev); |
527 | iounmap(dev_priv->mmio_virt); | |
528 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
529 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
530 | if (dev_priv->has_gmr) |
531 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
532 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
533 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
534 | vmw_ttm_global_release(dev_priv); | |
fb1d9738 JB |
535 | idr_destroy(&dev_priv->surface_idr); |
536 | idr_destroy(&dev_priv->context_idr); | |
537 | idr_destroy(&dev_priv->stream_idr); | |
538 | ||
539 | kfree(dev_priv); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | static void vmw_postclose(struct drm_device *dev, | |
545 | struct drm_file *file_priv) | |
546 | { | |
547 | struct vmw_fpriv *vmw_fp; | |
548 | ||
549 | vmw_fp = vmw_fpriv(file_priv); | |
550 | ttm_object_file_release(&vmw_fp->tfile); | |
551 | if (vmw_fp->locked_master) | |
552 | drm_master_put(&vmw_fp->locked_master); | |
553 | kfree(vmw_fp); | |
554 | } | |
555 | ||
556 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
557 | { | |
558 | struct vmw_private *dev_priv = vmw_priv(dev); | |
559 | struct vmw_fpriv *vmw_fp; | |
560 | int ret = -ENOMEM; | |
561 | ||
562 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
563 | if (unlikely(vmw_fp == NULL)) | |
564 | return ret; | |
565 | ||
566 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
567 | if (unlikely(vmw_fp->tfile == NULL)) | |
568 | goto out_no_tfile; | |
569 | ||
570 | file_priv->driver_priv = vmw_fp; | |
571 | ||
572 | if (unlikely(dev_priv->bdev.dev_mapping == NULL)) | |
573 | dev_priv->bdev.dev_mapping = | |
574 | file_priv->filp->f_path.dentry->d_inode->i_mapping; | |
575 | ||
576 | return 0; | |
577 | ||
578 | out_no_tfile: | |
579 | kfree(vmw_fp); | |
580 | return ret; | |
581 | } | |
582 | ||
583 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
584 | unsigned long arg) | |
585 | { | |
586 | struct drm_file *file_priv = filp->private_data; | |
587 | struct drm_device *dev = file_priv->minor->dev; | |
588 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
589 | |
590 | /* | |
e1f78003 | 591 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
592 | */ |
593 | ||
594 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
595 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
596 | struct drm_ioctl_desc *ioctl = | |
597 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; | |
598 | ||
2854eeda | 599 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
600 | DRM_ERROR("Invalid command format, ioctl %d\n", |
601 | nr - DRM_COMMAND_BASE); | |
602 | return -EINVAL; | |
603 | } | |
fb1d9738 JB |
604 | } |
605 | ||
e1f78003 | 606 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
607 | } |
608 | ||
609 | static int vmw_firstopen(struct drm_device *dev) | |
610 | { | |
611 | struct vmw_private *dev_priv = vmw_priv(dev); | |
612 | dev_priv->is_opened = true; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | static void vmw_lastclose(struct drm_device *dev) | |
618 | { | |
619 | struct vmw_private *dev_priv = vmw_priv(dev); | |
620 | struct drm_crtc *crtc; | |
621 | struct drm_mode_set set; | |
622 | int ret; | |
623 | ||
624 | /** | |
625 | * Do nothing on the lastclose call from drm_unload. | |
626 | */ | |
627 | ||
628 | if (!dev_priv->is_opened) | |
629 | return; | |
630 | ||
631 | dev_priv->is_opened = false; | |
632 | set.x = 0; | |
633 | set.y = 0; | |
634 | set.fb = NULL; | |
635 | set.mode = NULL; | |
636 | set.connectors = NULL; | |
637 | set.num_connectors = 0; | |
638 | ||
639 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
640 | set.crtc = crtc; | |
641 | ret = crtc->funcs->set_config(&set); | |
642 | WARN_ON(ret != 0); | |
643 | } | |
644 | ||
645 | } | |
646 | ||
647 | static void vmw_master_init(struct vmw_master *vmaster) | |
648 | { | |
649 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
650 | INIT_LIST_HEAD(&vmaster->fb_surf); |
651 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
652 | } |
653 | ||
654 | static int vmw_master_create(struct drm_device *dev, | |
655 | struct drm_master *master) | |
656 | { | |
657 | struct vmw_master *vmaster; | |
658 | ||
fb1d9738 JB |
659 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
660 | if (unlikely(vmaster == NULL)) | |
661 | return -ENOMEM; | |
662 | ||
3a939a5e | 663 | vmw_master_init(vmaster); |
fb1d9738 JB |
664 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
665 | master->driver_priv = vmaster; | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static void vmw_master_destroy(struct drm_device *dev, | |
671 | struct drm_master *master) | |
672 | { | |
673 | struct vmw_master *vmaster = vmw_master(master); | |
674 | ||
fb1d9738 JB |
675 | master->driver_priv = NULL; |
676 | kfree(vmaster); | |
677 | } | |
678 | ||
679 | ||
680 | static int vmw_master_set(struct drm_device *dev, | |
681 | struct drm_file *file_priv, | |
682 | bool from_open) | |
683 | { | |
684 | struct vmw_private *dev_priv = vmw_priv(dev); | |
685 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
686 | struct vmw_master *active = dev_priv->active_master; | |
687 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
688 | int ret = 0; | |
689 | ||
30c78bb8 | 690 | if (!dev_priv->enable_fb) { |
05730b32 | 691 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
692 | if (unlikely(ret != 0)) |
693 | return ret; | |
694 | vmw_kms_save_vga(dev_priv); | |
695 | mutex_lock(&dev_priv->hw_mutex); | |
696 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
697 | mutex_unlock(&dev_priv->hw_mutex); | |
698 | } | |
699 | ||
fb1d9738 JB |
700 | if (active) { |
701 | BUG_ON(active != &dev_priv->fbdev_master); | |
702 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
703 | if (unlikely(ret != 0)) | |
704 | goto out_no_active_lock; | |
705 | ||
706 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
707 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
708 | if (unlikely(ret != 0)) { | |
709 | DRM_ERROR("Unable to clean VRAM on " | |
710 | "master drop.\n"); | |
711 | } | |
712 | ||
713 | dev_priv->active_master = NULL; | |
714 | } | |
715 | ||
716 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
717 | if (!from_open) { | |
718 | ttm_vt_unlock(&vmaster->lock); | |
719 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
720 | drm_master_put(&vmw_fp->locked_master); | |
721 | } | |
722 | ||
723 | dev_priv->active_master = vmaster; | |
724 | ||
725 | return 0; | |
726 | ||
727 | out_no_active_lock: | |
30c78bb8 TH |
728 | if (!dev_priv->enable_fb) { |
729 | mutex_lock(&dev_priv->hw_mutex); | |
730 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
731 | mutex_unlock(&dev_priv->hw_mutex); | |
732 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 733 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 | 734 | } |
fb1d9738 JB |
735 | return ret; |
736 | } | |
737 | ||
738 | static void vmw_master_drop(struct drm_device *dev, | |
739 | struct drm_file *file_priv, | |
740 | bool from_release) | |
741 | { | |
742 | struct vmw_private *dev_priv = vmw_priv(dev); | |
743 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
744 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
745 | int ret; | |
746 | ||
fb1d9738 JB |
747 | /** |
748 | * Make sure the master doesn't disappear while we have | |
749 | * it locked. | |
750 | */ | |
751 | ||
752 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
753 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
3a939a5e | 754 | vmw_kms_idle_workqueues(vmaster); |
fb1d9738 JB |
755 | |
756 | if (unlikely((ret != 0))) { | |
757 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
758 | drm_master_put(&vmw_fp->locked_master); | |
759 | } | |
760 | ||
761 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
762 | ||
30c78bb8 TH |
763 | if (!dev_priv->enable_fb) { |
764 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
765 | if (unlikely(ret != 0)) | |
766 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
767 | mutex_lock(&dev_priv->hw_mutex); | |
768 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
769 | mutex_unlock(&dev_priv->hw_mutex); | |
770 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 771 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 TH |
772 | } |
773 | ||
fb1d9738 JB |
774 | dev_priv->active_master = &dev_priv->fbdev_master; |
775 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
776 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
777 | ||
30c78bb8 TH |
778 | if (dev_priv->enable_fb) |
779 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
780 | } |
781 | ||
782 | ||
783 | static void vmw_remove(struct pci_dev *pdev) | |
784 | { | |
785 | struct drm_device *dev = pci_get_drvdata(pdev); | |
786 | ||
787 | drm_put_dev(dev); | |
788 | } | |
789 | ||
d9f36a00 TH |
790 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
791 | void *ptr) | |
792 | { | |
793 | struct vmw_private *dev_priv = | |
794 | container_of(nb, struct vmw_private, pm_nb); | |
795 | struct vmw_master *vmaster = dev_priv->active_master; | |
796 | ||
797 | switch (val) { | |
798 | case PM_HIBERNATION_PREPARE: | |
799 | case PM_SUSPEND_PREPARE: | |
800 | ttm_suspend_lock(&vmaster->lock); | |
801 | ||
802 | /** | |
803 | * This empties VRAM and unbinds all GMR bindings. | |
804 | * Buffer contents is moved to swappable memory. | |
805 | */ | |
806 | ttm_bo_swapout_all(&dev_priv->bdev); | |
094e0fa8 | 807 | |
d9f36a00 TH |
808 | break; |
809 | case PM_POST_HIBERNATION: | |
810 | case PM_POST_SUSPEND: | |
094e0fa8 | 811 | case PM_POST_RESTORE: |
d9f36a00 | 812 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 813 | |
d9f36a00 TH |
814 | break; |
815 | case PM_RESTORE_PREPARE: | |
816 | break; | |
d9f36a00 TH |
817 | default: |
818 | break; | |
819 | } | |
820 | return 0; | |
821 | } | |
822 | ||
823 | /** | |
824 | * These might not be needed with the virtual SVGA device. | |
825 | */ | |
826 | ||
7fbd721a | 827 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 828 | { |
094e0fa8 TH |
829 | struct drm_device *dev = pci_get_drvdata(pdev); |
830 | struct vmw_private *dev_priv = vmw_priv(dev); | |
831 | ||
832 | if (dev_priv->num_3d_resources != 0) { | |
833 | DRM_INFO("Can't suspend or hibernate " | |
834 | "while 3D resources are active.\n"); | |
835 | return -EBUSY; | |
836 | } | |
837 | ||
d9f36a00 TH |
838 | pci_save_state(pdev); |
839 | pci_disable_device(pdev); | |
840 | pci_set_power_state(pdev, PCI_D3hot); | |
841 | return 0; | |
842 | } | |
843 | ||
7fbd721a | 844 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
845 | { |
846 | pci_set_power_state(pdev, PCI_D0); | |
847 | pci_restore_state(pdev); | |
848 | return pci_enable_device(pdev); | |
849 | } | |
850 | ||
7fbd721a TH |
851 | static int vmw_pm_suspend(struct device *kdev) |
852 | { | |
853 | struct pci_dev *pdev = to_pci_dev(kdev); | |
854 | struct pm_message dummy; | |
855 | ||
856 | dummy.event = 0; | |
857 | ||
858 | return vmw_pci_suspend(pdev, dummy); | |
859 | } | |
860 | ||
861 | static int vmw_pm_resume(struct device *kdev) | |
862 | { | |
863 | struct pci_dev *pdev = to_pci_dev(kdev); | |
864 | ||
865 | return vmw_pci_resume(pdev); | |
866 | } | |
867 | ||
868 | static int vmw_pm_prepare(struct device *kdev) | |
869 | { | |
870 | struct pci_dev *pdev = to_pci_dev(kdev); | |
871 | struct drm_device *dev = pci_get_drvdata(pdev); | |
872 | struct vmw_private *dev_priv = vmw_priv(dev); | |
873 | ||
874 | /** | |
875 | * Release 3d reference held by fbdev and potentially | |
876 | * stop fifo. | |
877 | */ | |
878 | dev_priv->suspended = true; | |
879 | if (dev_priv->enable_fb) | |
05730b32 | 880 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
881 | |
882 | if (dev_priv->num_3d_resources != 0) { | |
883 | ||
884 | DRM_INFO("Can't suspend or hibernate " | |
885 | "while 3D resources are active.\n"); | |
886 | ||
887 | if (dev_priv->enable_fb) | |
05730b32 | 888 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
889 | dev_priv->suspended = false; |
890 | return -EBUSY; | |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | static void vmw_pm_complete(struct device *kdev) | |
897 | { | |
898 | struct pci_dev *pdev = to_pci_dev(kdev); | |
899 | struct drm_device *dev = pci_get_drvdata(pdev); | |
900 | struct vmw_private *dev_priv = vmw_priv(dev); | |
901 | ||
902 | /** | |
903 | * Reclaim 3d reference held by fbdev and potentially | |
904 | * start fifo. | |
905 | */ | |
906 | if (dev_priv->enable_fb) | |
05730b32 | 907 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
908 | |
909 | dev_priv->suspended = false; | |
910 | } | |
911 | ||
912 | static const struct dev_pm_ops vmw_pm_ops = { | |
913 | .prepare = vmw_pm_prepare, | |
914 | .complete = vmw_pm_complete, | |
915 | .suspend = vmw_pm_suspend, | |
916 | .resume = vmw_pm_resume, | |
917 | }; | |
918 | ||
fb1d9738 JB |
919 | static struct drm_driver driver = { |
920 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
921 | DRIVER_MODESET, | |
922 | .load = vmw_driver_load, | |
923 | .unload = vmw_driver_unload, | |
924 | .firstopen = vmw_firstopen, | |
925 | .lastclose = vmw_lastclose, | |
926 | .irq_preinstall = vmw_irq_preinstall, | |
927 | .irq_postinstall = vmw_irq_postinstall, | |
928 | .irq_uninstall = vmw_irq_uninstall, | |
929 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 930 | .get_vblank_counter = vmw_get_vblank_counter, |
fb1d9738 | 931 | .reclaim_buffers_locked = NULL, |
fb1d9738 JB |
932 | .ioctls = vmw_ioctls, |
933 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
934 | .dma_quiescent = NULL, /*vmw_dma_quiescent, */ | |
935 | .master_create = vmw_master_create, | |
936 | .master_destroy = vmw_master_destroy, | |
937 | .master_set = vmw_master_set, | |
938 | .master_drop = vmw_master_drop, | |
939 | .open = vmw_driver_open, | |
940 | .postclose = vmw_postclose, | |
941 | .fops = { | |
942 | .owner = THIS_MODULE, | |
943 | .open = drm_open, | |
944 | .release = drm_release, | |
945 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
946 | .mmap = vmw_mmap, | |
947 | .poll = drm_poll, | |
948 | .fasync = drm_fasync, | |
949 | #if defined(CONFIG_COMPAT) | |
950 | .compat_ioctl = drm_compat_ioctl, | |
951 | #endif | |
dc880abe | 952 | .llseek = noop_llseek, |
7fbd721a | 953 | }, |
fb1d9738 JB |
954 | .name = VMWGFX_DRIVER_NAME, |
955 | .desc = VMWGFX_DRIVER_DESC, | |
956 | .date = VMWGFX_DRIVER_DATE, | |
957 | .major = VMWGFX_DRIVER_MAJOR, | |
958 | .minor = VMWGFX_DRIVER_MINOR, | |
959 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
960 | }; | |
961 | ||
8410ea3b DA |
962 | static struct pci_driver vmw_pci_driver = { |
963 | .name = VMWGFX_DRIVER_NAME, | |
964 | .id_table = vmw_pci_id_list, | |
965 | .probe = vmw_probe, | |
966 | .remove = vmw_remove, | |
967 | .driver = { | |
968 | .pm = &vmw_pm_ops | |
969 | } | |
970 | }; | |
971 | ||
fb1d9738 JB |
972 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
973 | { | |
dcdb1674 | 974 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
975 | } |
976 | ||
977 | static int __init vmwgfx_init(void) | |
978 | { | |
979 | int ret; | |
8410ea3b | 980 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
981 | if (ret) |
982 | DRM_ERROR("Failed initializing DRM.\n"); | |
983 | return ret; | |
984 | } | |
985 | ||
986 | static void __exit vmwgfx_exit(void) | |
987 | { | |
8410ea3b | 988 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
989 | } |
990 | ||
991 | module_init(vmwgfx_init); | |
992 | module_exit(vmwgfx_exit); | |
993 | ||
994 | MODULE_AUTHOR("VMware Inc. and others"); | |
995 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
996 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
997 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
998 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
999 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1000 | "0"); |