]>
Commit | Line | Data |
---|---|---|
fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "vmwgfx_drv.h" | |
30 | #include "ttm/ttm_placement.h" | |
31 | #include "ttm/ttm_bo_driver.h" | |
32 | #include "ttm/ttm_object.h" | |
33 | #include "ttm/ttm_module.h" | |
34 | ||
35 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
36 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
37 | #define VMWGFX_CHIP_SVGAII 0 | |
38 | #define VMW_FB_RESERVATION 0 | |
39 | ||
40 | /** | |
41 | * Fully encoded drm commands. Might move to vmw_drm.h | |
42 | */ | |
43 | ||
44 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
45 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
46 | struct drm_vmw_getparam_arg) | |
47 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
48 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
49 | union drm_vmw_alloc_dmabuf_arg) | |
50 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
51 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
52 | struct drm_vmw_unref_dmabuf_arg) | |
53 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
54 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
55 | struct drm_vmw_cursor_bypass_arg) | |
56 | ||
57 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
58 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
59 | struct drm_vmw_control_stream_arg) | |
60 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
61 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
62 | struct drm_vmw_stream_arg) | |
63 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
65 | struct drm_vmw_stream_arg) | |
66 | ||
67 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
68 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
69 | struct drm_vmw_context_arg) | |
70 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
71 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
72 | struct drm_vmw_context_arg) | |
73 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
74 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
75 | union drm_vmw_surface_create_arg) | |
76 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
78 | struct drm_vmw_surface_arg) | |
79 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
81 | union drm_vmw_surface_reference_arg) | |
82 | #define DRM_IOCTL_VMW_EXECBUF \ | |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
84 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
85 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
86 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
87 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
88 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
89 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
90 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
91 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
92 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
93 | struct drm_vmw_fence_signaled_arg) | |
94 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
95 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
96 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
97 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
98 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
99 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
100 | #define DRM_IOCTL_VMW_PRESENT \ |
101 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
102 | struct drm_vmw_present_arg) | |
103 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
104 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
105 | struct drm_vmw_present_readback_arg) | |
fb1d9738 JB |
106 | |
107 | /** | |
108 | * The core DRM version of this macro doesn't account for | |
109 | * DRM_COMMAND_BASE. | |
110 | */ | |
111 | ||
112 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 113 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
114 | |
115 | /** | |
116 | * Ioctl definitions. | |
117 | */ | |
118 | ||
119 | static struct drm_ioctl_desc vmw_ioctls[] = { | |
1b2f1489 | 120 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 121 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 122 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 123 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 124 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 125 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 126 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
127 | vmw_kms_cursor_bypass_ioctl, |
128 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 129 | |
1b2f1489 | 130 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 131 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 132 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 133 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 134 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 135 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 136 | |
1b2f1489 | 137 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 138 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 139 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 140 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 141 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 142 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 143 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 144 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 145 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 146 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 147 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 148 | DRM_AUTH | DRM_UNLOCKED), |
ae2a1040 TH |
149 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
150 | DRM_AUTH | DRM_UNLOCKED), | |
151 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, | |
152 | vmw_fence_obj_signaled_ioctl, | |
153 | DRM_AUTH | DRM_UNLOCKED), | |
154 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, | |
d8bd19d2 | 155 | DRM_AUTH | DRM_UNLOCKED), |
57c5ee79 TH |
156 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
157 | vmw_fence_event_ioctl, | |
158 | DRM_AUTH | DRM_UNLOCKED), | |
f63f6a59 TH |
159 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
160 | DRM_AUTH | DRM_UNLOCKED), | |
2fcd5a73 JB |
161 | |
162 | /* these allow direct access to the framebuffers mark as master only */ | |
163 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
164 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
165 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, | |
166 | vmw_present_readback_ioctl, | |
167 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
fb1d9738 JB |
168 | }; |
169 | ||
170 | static struct pci_device_id vmw_pci_id_list[] = { | |
171 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
172 | {0, 0, 0} | |
173 | }; | |
174 | ||
30c78bb8 | 175 | static int enable_fbdev; |
fb1d9738 JB |
176 | |
177 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
178 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
179 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
180 | void *ptr); | |
fb1d9738 | 181 | |
30c78bb8 TH |
182 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
183 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
184 | ||
fb1d9738 JB |
185 | static void vmw_print_capabilities(uint32_t capabilities) |
186 | { | |
187 | DRM_INFO("Capabilities:\n"); | |
188 | if (capabilities & SVGA_CAP_RECT_COPY) | |
189 | DRM_INFO(" Rect copy.\n"); | |
190 | if (capabilities & SVGA_CAP_CURSOR) | |
191 | DRM_INFO(" Cursor.\n"); | |
192 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
193 | DRM_INFO(" Cursor bypass.\n"); | |
194 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
195 | DRM_INFO(" Cursor bypass 2.\n"); | |
196 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
197 | DRM_INFO(" 8bit emulation.\n"); | |
198 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
199 | DRM_INFO(" Alpha cursor.\n"); | |
200 | if (capabilities & SVGA_CAP_3D) | |
201 | DRM_INFO(" 3D.\n"); | |
202 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
203 | DRM_INFO(" Extended Fifo.\n"); | |
204 | if (capabilities & SVGA_CAP_MULTIMON) | |
205 | DRM_INFO(" Multimon.\n"); | |
206 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
207 | DRM_INFO(" Pitchlock.\n"); | |
208 | if (capabilities & SVGA_CAP_IRQMASK) | |
209 | DRM_INFO(" Irq mask.\n"); | |
210 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
211 | DRM_INFO(" Display Topology.\n"); | |
212 | if (capabilities & SVGA_CAP_GMR) | |
213 | DRM_INFO(" GMR.\n"); | |
214 | if (capabilities & SVGA_CAP_TRACES) | |
215 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
216 | if (capabilities & SVGA_CAP_GMR2) |
217 | DRM_INFO(" GMR2.\n"); | |
218 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
219 | DRM_INFO(" Screen Object 2.\n"); | |
fb1d9738 JB |
220 | } |
221 | ||
e2fa3a76 TH |
222 | |
223 | /** | |
224 | * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at | |
225 | * the start of a buffer object. | |
226 | * | |
227 | * @dev_priv: The device private structure. | |
228 | * | |
229 | * This function will idle the buffer using an uninterruptible wait, then | |
230 | * map the first page and initialize a pending occlusion query result structure, | |
231 | * Finally it will unmap the buffer. | |
232 | * | |
233 | * TODO: Since we're only mapping a single page, we should optimize the map | |
234 | * to use kmap_atomic / iomap_atomic. | |
235 | */ | |
236 | static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv) | |
237 | { | |
238 | struct ttm_bo_kmap_obj map; | |
239 | volatile SVGA3dQueryResult *result; | |
240 | bool dummy; | |
241 | int ret; | |
242 | struct ttm_bo_device *bdev = &dev_priv->bdev; | |
243 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; | |
244 | ||
245 | ttm_bo_reserve(bo, false, false, false, 0); | |
246 | spin_lock(&bdev->fence_lock); | |
247 | ret = ttm_bo_wait(bo, false, false, false, TTM_USAGE_READWRITE); | |
248 | spin_unlock(&bdev->fence_lock); | |
249 | if (unlikely(ret != 0)) | |
250 | (void) vmw_fallback_wait(dev_priv, false, true, 0, false, | |
251 | 10*HZ); | |
252 | ||
253 | ret = ttm_bo_kmap(bo, 0, 1, &map); | |
254 | if (likely(ret == 0)) { | |
255 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
256 | result->totalSize = sizeof(*result); | |
257 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
258 | result->result32 = 0xff; | |
259 | ttm_bo_kunmap(&map); | |
260 | } else | |
261 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
262 | ttm_bo_unreserve(bo); | |
263 | } | |
264 | ||
265 | ||
266 | /** | |
267 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result | |
268 | * | |
269 | * @dev_priv: A device private structure. | |
270 | * | |
271 | * This function creates a small buffer object that holds the query | |
272 | * result for dummy queries emitted as query barriers. | |
273 | * No interruptible waits are done within this function. | |
274 | * | |
275 | * Returns an error if bo creation fails. | |
276 | */ | |
277 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) | |
278 | { | |
279 | return ttm_bo_create(&dev_priv->bdev, | |
280 | PAGE_SIZE, | |
281 | ttm_bo_type_device, | |
282 | &vmw_vram_sys_placement, | |
283 | 0, 0, false, NULL, | |
284 | &dev_priv->dummy_query_bo); | |
285 | } | |
286 | ||
287 | ||
fb1d9738 JB |
288 | static int vmw_request_device(struct vmw_private *dev_priv) |
289 | { | |
290 | int ret; | |
291 | ||
fb1d9738 JB |
292 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
293 | if (unlikely(ret != 0)) { | |
294 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
295 | return ret; | |
296 | } | |
ae2a1040 | 297 | vmw_fence_fifo_up(dev_priv->fman); |
e2fa3a76 TH |
298 | ret = vmw_dummy_query_bo_create(dev_priv); |
299 | if (unlikely(ret != 0)) | |
300 | goto out_no_query_bo; | |
301 | vmw_dummy_query_bo_prepare(dev_priv); | |
fb1d9738 JB |
302 | |
303 | return 0; | |
e2fa3a76 TH |
304 | |
305 | out_no_query_bo: | |
306 | vmw_fence_fifo_down(dev_priv->fman); | |
307 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
308 | return ret; | |
fb1d9738 JB |
309 | } |
310 | ||
311 | static void vmw_release_device(struct vmw_private *dev_priv) | |
312 | { | |
e2fa3a76 TH |
313 | /* |
314 | * Previous destructions should've released | |
315 | * the pinned bo. | |
316 | */ | |
317 | ||
318 | BUG_ON(dev_priv->pinned_bo != NULL); | |
319 | ||
320 | ttm_bo_unref(&dev_priv->dummy_query_bo); | |
ae2a1040 | 321 | vmw_fence_fifo_down(dev_priv->fman); |
fb1d9738 | 322 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
323 | } |
324 | ||
05730b32 TH |
325 | /** |
326 | * Increase the 3d resource refcount. | |
327 | * If the count was prevously zero, initialize the fifo, switching to svga | |
328 | * mode. Note that the master holds a ref as well, and may request an | |
329 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
330 | */ | |
331 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
332 | bool unhide_svga) | |
30c78bb8 TH |
333 | { |
334 | int ret = 0; | |
335 | ||
336 | mutex_lock(&dev_priv->release_mutex); | |
337 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
338 | ret = vmw_request_device(dev_priv); | |
339 | if (unlikely(ret != 0)) | |
340 | --dev_priv->num_3d_resources; | |
05730b32 TH |
341 | } else if (unhide_svga) { |
342 | mutex_lock(&dev_priv->hw_mutex); | |
343 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
344 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
345 | ~SVGA_REG_ENABLE_HIDE); | |
346 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 347 | } |
05730b32 | 348 | |
30c78bb8 TH |
349 | mutex_unlock(&dev_priv->release_mutex); |
350 | return ret; | |
fb1d9738 JB |
351 | } |
352 | ||
05730b32 TH |
353 | /** |
354 | * Decrease the 3d resource refcount. | |
355 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
356 | * Note that the master holds a refcount as well, and may request an | |
357 | * explicit switch to vga mode when it releases its refcount to account | |
358 | * for the situation of an X server vt switch to VGA with 3d resources | |
359 | * active. | |
360 | */ | |
361 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
362 | bool hide_svga) | |
30c78bb8 TH |
363 | { |
364 | int32_t n3d; | |
365 | ||
366 | mutex_lock(&dev_priv->release_mutex); | |
367 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
368 | vmw_release_device(dev_priv); | |
05730b32 TH |
369 | else if (hide_svga) { |
370 | mutex_lock(&dev_priv->hw_mutex); | |
371 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
372 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
373 | SVGA_REG_ENABLE_HIDE); | |
374 | mutex_unlock(&dev_priv->hw_mutex); | |
375 | } | |
376 | ||
30c78bb8 TH |
377 | n3d = (int32_t) dev_priv->num_3d_resources; |
378 | mutex_unlock(&dev_priv->release_mutex); | |
379 | ||
380 | BUG_ON(n3d < 0); | |
381 | } | |
382 | ||
fb1d9738 JB |
383 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
384 | { | |
385 | struct vmw_private *dev_priv; | |
386 | int ret; | |
c188660f | 387 | uint32_t svga_id; |
fb1d9738 JB |
388 | |
389 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
390 | if (unlikely(dev_priv == NULL)) { | |
391 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
392 | return -ENOMEM; | |
393 | } | |
394 | memset(dev_priv, 0, sizeof(*dev_priv)); | |
395 | ||
396 | dev_priv->dev = dev; | |
397 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 398 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 JB |
399 | mutex_init(&dev_priv->hw_mutex); |
400 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 401 | mutex_init(&dev_priv->release_mutex); |
fb1d9738 JB |
402 | rwlock_init(&dev_priv->resource_lock); |
403 | idr_init(&dev_priv->context_idr); | |
404 | idr_init(&dev_priv->surface_idr); | |
405 | idr_init(&dev_priv->stream_idr); | |
fb1d9738 JB |
406 | mutex_init(&dev_priv->init_mutex); |
407 | init_waitqueue_head(&dev_priv->fence_queue); | |
408 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 409 | dev_priv->fence_queue_waiters = 0; |
fb1d9738 | 410 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
5bb39e81 TH |
411 | INIT_LIST_HEAD(&dev_priv->surface_lru); |
412 | dev_priv->used_memory_size = 0; | |
fb1d9738 JB |
413 | |
414 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
415 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
416 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
417 | ||
30c78bb8 TH |
418 | dev_priv->enable_fb = enable_fbdev; |
419 | ||
fb1d9738 | 420 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
421 | |
422 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
423 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
424 | if (svga_id != SVGA_ID_2) { | |
425 | ret = -ENOSYS; | |
426 | DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id); | |
427 | mutex_unlock(&dev_priv->hw_mutex); | |
428 | goto out_err0; | |
429 | } | |
430 | ||
fb1d9738 JB |
431 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
432 | ||
5bb39e81 TH |
433 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
434 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
435 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
436 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
fb1d9738 JB |
437 | if (dev_priv->capabilities & SVGA_CAP_GMR) { |
438 | dev_priv->max_gmr_descriptors = | |
439 | vmw_read(dev_priv, | |
440 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); | |
441 | dev_priv->max_gmr_ids = | |
442 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
443 | } | |
fb17f189 TH |
444 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
445 | dev_priv->max_gmr_pages = | |
446 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
447 | dev_priv->memory_size = | |
448 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
449 | dev_priv->memory_size -= dev_priv->vram_size; |
450 | } else { | |
451 | /* | |
452 | * An arbitrary limit of 512MiB on surface | |
453 | * memory. But all HWV8 hardware supports GMR2. | |
454 | */ | |
455 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 456 | } |
fb1d9738 | 457 | |
fb1d9738 JB |
458 | mutex_unlock(&dev_priv->hw_mutex); |
459 | ||
460 | vmw_print_capabilities(dev_priv->capabilities); | |
461 | ||
462 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
463 | DRM_INFO("Max GMR ids is %u\n", | |
464 | (unsigned)dev_priv->max_gmr_ids); | |
465 | DRM_INFO("Max GMR descriptors is %u\n", | |
466 | (unsigned)dev_priv->max_gmr_descriptors); | |
467 | } | |
fb17f189 TH |
468 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
469 | DRM_INFO("Max number of GMR pages is %u\n", | |
470 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
471 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
472 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 473 | } |
fb1d9738 JB |
474 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
475 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
476 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
477 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
478 | ||
479 | ret = vmw_ttm_global_init(dev_priv); | |
480 | if (unlikely(ret != 0)) | |
481 | goto out_err0; | |
482 | ||
483 | ||
484 | vmw_master_init(&dev_priv->fbdev_master); | |
485 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
486 | dev_priv->active_master = &dev_priv->fbdev_master; | |
487 | ||
a2c06ee2 | 488 | |
fb1d9738 JB |
489 | ret = ttm_bo_device_init(&dev_priv->bdev, |
490 | dev_priv->bo_global_ref.ref.object, | |
491 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, | |
492 | false); | |
493 | if (unlikely(ret != 0)) { | |
494 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
495 | goto out_err1; | |
496 | } | |
497 | ||
498 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
499 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
500 | if (unlikely(ret != 0)) { | |
501 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
502 | goto out_err2; | |
503 | } | |
504 | ||
135cba0d TH |
505 | dev_priv->has_gmr = true; |
506 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
507 | dev_priv->max_gmr_ids) != 0) { | |
508 | DRM_INFO("No GMR memory available. " | |
509 | "Graphics memory resources are very limited.\n"); | |
510 | dev_priv->has_gmr = false; | |
511 | } | |
512 | ||
fb1d9738 JB |
513 | dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start, |
514 | dev_priv->mmio_size, DRM_MTRR_WC); | |
515 | ||
516 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
517 | dev_priv->mmio_size); | |
518 | ||
519 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
520 | ret = -ENOMEM; | |
521 | DRM_ERROR("Failed mapping MMIO.\n"); | |
522 | goto out_err3; | |
523 | } | |
524 | ||
d7e1958d JB |
525 | /* Need mmio memory to check for fifo pitchlock cap. */ |
526 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
527 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
528 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
529 | ret = -ENOSYS; | |
530 | DRM_ERROR("Hardware has no pitchlock\n"); | |
531 | goto out_err4; | |
532 | } | |
533 | ||
fb1d9738 JB |
534 | dev_priv->tdev = ttm_object_device_init |
535 | (dev_priv->mem_global_ref.object, 12); | |
536 | ||
537 | if (unlikely(dev_priv->tdev == NULL)) { | |
538 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
539 | ret = -ENOMEM; | |
540 | goto out_err4; | |
541 | } | |
542 | ||
543 | dev->dev_private = dev_priv; | |
544 | ||
fb1d9738 JB |
545 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
546 | dev_priv->stealth = (ret != 0); | |
547 | if (dev_priv->stealth) { | |
548 | /** | |
549 | * Request at least the mmio PCI resource. | |
550 | */ | |
551 | ||
552 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 553 | "Ignore above error if any.\n"); |
fb1d9738 JB |
554 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
555 | if (unlikely(ret != 0)) { | |
556 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
557 | goto out_no_device; | |
558 | } | |
fb1d9738 | 559 | } |
ae2a1040 TH |
560 | |
561 | dev_priv->fman = vmw_fence_manager_init(dev_priv); | |
562 | if (unlikely(dev_priv->fman == NULL)) | |
563 | goto out_no_fman; | |
56d1c78d JB |
564 | |
565 | /* Need to start the fifo to check if we can do screen objects */ | |
566 | ret = vmw_3d_resource_inc(dev_priv, true); | |
567 | if (unlikely(ret != 0)) | |
568 | goto out_no_fifo; | |
569 | vmw_kms_save_vga(dev_priv); | |
56d1c78d JB |
570 | |
571 | /* Start kms and overlay systems, needs fifo. */ | |
7a1c2f6c TH |
572 | ret = vmw_kms_init(dev_priv); |
573 | if (unlikely(ret != 0)) | |
574 | goto out_no_kms; | |
f2d12b8e | 575 | vmw_overlay_init(dev_priv); |
56d1c78d | 576 | |
01e81419 | 577 | /* 3D Depends on Screen Objects being used. */ |
6ea77d13 TH |
578 | DRM_INFO("Detected %sdevice 3D availability.\n", |
579 | vmw_fifo_have_3d(dev_priv) ? | |
580 | "" : "no "); | |
01e81419 | 581 | |
56d1c78d | 582 | /* We might be done with the fifo now */ |
30c78bb8 | 583 | if (dev_priv->enable_fb) { |
30c78bb8 | 584 | vmw_fb_init(dev_priv); |
30c78bb8 | 585 | } else { |
56d1c78d JB |
586 | vmw_kms_restore_vga(dev_priv); |
587 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 | 588 | } |
fb1d9738 | 589 | |
7a1c2f6c TH |
590 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
591 | ret = drm_irq_install(dev); | |
592 | if (unlikely(ret != 0)) { | |
593 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
594 | goto out_no_irq; | |
595 | } | |
596 | } | |
597 | ||
d9f36a00 TH |
598 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
599 | register_pm_notifier(&dev_priv->pm_nb); | |
600 | ||
fb1d9738 JB |
601 | return 0; |
602 | ||
7a1c2f6c | 603 | out_no_irq: |
56d1c78d | 604 | if (dev_priv->enable_fb) |
7a1c2f6c | 605 | vmw_fb_close(dev_priv); |
56d1c78d JB |
606 | vmw_overlay_close(dev_priv); |
607 | vmw_kms_close(dev_priv); | |
608 | out_no_kms: | |
609 | /* We still have a 3D resource reference held */ | |
610 | if (dev_priv->enable_fb) { | |
7a1c2f6c | 611 | vmw_kms_restore_vga(dev_priv); |
05730b32 | 612 | vmw_3d_resource_dec(dev_priv, false); |
7a1c2f6c | 613 | } |
30c78bb8 | 614 | out_no_fifo: |
ae2a1040 TH |
615 | vmw_fence_manager_takedown(dev_priv->fman); |
616 | out_no_fman: | |
30c78bb8 TH |
617 | if (dev_priv->stealth) |
618 | pci_release_region(dev->pdev, 2); | |
619 | else | |
620 | pci_release_regions(dev->pdev); | |
fb1d9738 | 621 | out_no_device: |
fb1d9738 JB |
622 | ttm_object_device_release(&dev_priv->tdev); |
623 | out_err4: | |
624 | iounmap(dev_priv->mmio_virt); | |
625 | out_err3: | |
626 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
627 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
628 | if (dev_priv->has_gmr) |
629 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
630 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
631 | out_err2: | |
632 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
633 | out_err1: | |
634 | vmw_ttm_global_release(dev_priv); | |
635 | out_err0: | |
fb1d9738 JB |
636 | idr_destroy(&dev_priv->surface_idr); |
637 | idr_destroy(&dev_priv->context_idr); | |
638 | idr_destroy(&dev_priv->stream_idr); | |
639 | kfree(dev_priv); | |
640 | return ret; | |
641 | } | |
642 | ||
643 | static int vmw_driver_unload(struct drm_device *dev) | |
644 | { | |
645 | struct vmw_private *dev_priv = vmw_priv(dev); | |
646 | ||
d9f36a00 TH |
647 | unregister_pm_notifier(&dev_priv->pm_nb); |
648 | ||
be38ab6e TH |
649 | if (dev_priv->ctx.cmd_bounce) |
650 | vfree(dev_priv->ctx.cmd_bounce); | |
7a1c2f6c TH |
651 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
652 | drm_irq_uninstall(dev_priv->dev); | |
30c78bb8 TH |
653 | if (dev_priv->enable_fb) { |
654 | vmw_fb_close(dev_priv); | |
655 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 656 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 657 | } |
f2d12b8e TH |
658 | vmw_kms_close(dev_priv); |
659 | vmw_overlay_close(dev_priv); | |
ae2a1040 | 660 | vmw_fence_manager_takedown(dev_priv->fman); |
f2d12b8e | 661 | if (dev_priv->stealth) |
fb1d9738 | 662 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
663 | else |
664 | pci_release_regions(dev->pdev); | |
665 | ||
fb1d9738 JB |
666 | ttm_object_device_release(&dev_priv->tdev); |
667 | iounmap(dev_priv->mmio_virt); | |
668 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
669 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
670 | if (dev_priv->has_gmr) |
671 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
672 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
673 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
674 | vmw_ttm_global_release(dev_priv); | |
fb1d9738 JB |
675 | idr_destroy(&dev_priv->surface_idr); |
676 | idr_destroy(&dev_priv->context_idr); | |
677 | idr_destroy(&dev_priv->stream_idr); | |
678 | ||
679 | kfree(dev_priv); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static void vmw_postclose(struct drm_device *dev, | |
685 | struct drm_file *file_priv) | |
686 | { | |
687 | struct vmw_fpriv *vmw_fp; | |
688 | ||
689 | vmw_fp = vmw_fpriv(file_priv); | |
690 | ttm_object_file_release(&vmw_fp->tfile); | |
691 | if (vmw_fp->locked_master) | |
692 | drm_master_put(&vmw_fp->locked_master); | |
693 | kfree(vmw_fp); | |
694 | } | |
695 | ||
696 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
697 | { | |
698 | struct vmw_private *dev_priv = vmw_priv(dev); | |
699 | struct vmw_fpriv *vmw_fp; | |
700 | int ret = -ENOMEM; | |
701 | ||
702 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
703 | if (unlikely(vmw_fp == NULL)) | |
704 | return ret; | |
705 | ||
706 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
707 | if (unlikely(vmw_fp->tfile == NULL)) | |
708 | goto out_no_tfile; | |
709 | ||
710 | file_priv->driver_priv = vmw_fp; | |
711 | ||
712 | if (unlikely(dev_priv->bdev.dev_mapping == NULL)) | |
713 | dev_priv->bdev.dev_mapping = | |
714 | file_priv->filp->f_path.dentry->d_inode->i_mapping; | |
715 | ||
716 | return 0; | |
717 | ||
718 | out_no_tfile: | |
719 | kfree(vmw_fp); | |
720 | return ret; | |
721 | } | |
722 | ||
723 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
724 | unsigned long arg) | |
725 | { | |
726 | struct drm_file *file_priv = filp->private_data; | |
727 | struct drm_device *dev = file_priv->minor->dev; | |
728 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
729 | |
730 | /* | |
e1f78003 | 731 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
732 | */ |
733 | ||
734 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
735 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
736 | struct drm_ioctl_desc *ioctl = | |
737 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; | |
738 | ||
2854eeda | 739 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
740 | DRM_ERROR("Invalid command format, ioctl %d\n", |
741 | nr - DRM_COMMAND_BASE); | |
742 | return -EINVAL; | |
743 | } | |
fb1d9738 JB |
744 | } |
745 | ||
e1f78003 | 746 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
747 | } |
748 | ||
749 | static int vmw_firstopen(struct drm_device *dev) | |
750 | { | |
751 | struct vmw_private *dev_priv = vmw_priv(dev); | |
752 | dev_priv->is_opened = true; | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | static void vmw_lastclose(struct drm_device *dev) | |
758 | { | |
759 | struct vmw_private *dev_priv = vmw_priv(dev); | |
760 | struct drm_crtc *crtc; | |
761 | struct drm_mode_set set; | |
762 | int ret; | |
763 | ||
764 | /** | |
765 | * Do nothing on the lastclose call from drm_unload. | |
766 | */ | |
767 | ||
768 | if (!dev_priv->is_opened) | |
769 | return; | |
770 | ||
771 | dev_priv->is_opened = false; | |
772 | set.x = 0; | |
773 | set.y = 0; | |
774 | set.fb = NULL; | |
775 | set.mode = NULL; | |
776 | set.connectors = NULL; | |
777 | set.num_connectors = 0; | |
778 | ||
779 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
780 | set.crtc = crtc; | |
781 | ret = crtc->funcs->set_config(&set); | |
782 | WARN_ON(ret != 0); | |
783 | } | |
784 | ||
785 | } | |
786 | ||
787 | static void vmw_master_init(struct vmw_master *vmaster) | |
788 | { | |
789 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
790 | INIT_LIST_HEAD(&vmaster->fb_surf); |
791 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
792 | } |
793 | ||
794 | static int vmw_master_create(struct drm_device *dev, | |
795 | struct drm_master *master) | |
796 | { | |
797 | struct vmw_master *vmaster; | |
798 | ||
fb1d9738 JB |
799 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
800 | if (unlikely(vmaster == NULL)) | |
801 | return -ENOMEM; | |
802 | ||
3a939a5e | 803 | vmw_master_init(vmaster); |
fb1d9738 JB |
804 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
805 | master->driver_priv = vmaster; | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static void vmw_master_destroy(struct drm_device *dev, | |
811 | struct drm_master *master) | |
812 | { | |
813 | struct vmw_master *vmaster = vmw_master(master); | |
814 | ||
fb1d9738 JB |
815 | master->driver_priv = NULL; |
816 | kfree(vmaster); | |
817 | } | |
818 | ||
819 | ||
820 | static int vmw_master_set(struct drm_device *dev, | |
821 | struct drm_file *file_priv, | |
822 | bool from_open) | |
823 | { | |
824 | struct vmw_private *dev_priv = vmw_priv(dev); | |
825 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
826 | struct vmw_master *active = dev_priv->active_master; | |
827 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
828 | int ret = 0; | |
829 | ||
30c78bb8 | 830 | if (!dev_priv->enable_fb) { |
05730b32 | 831 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
832 | if (unlikely(ret != 0)) |
833 | return ret; | |
834 | vmw_kms_save_vga(dev_priv); | |
835 | mutex_lock(&dev_priv->hw_mutex); | |
836 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
837 | mutex_unlock(&dev_priv->hw_mutex); | |
838 | } | |
839 | ||
fb1d9738 JB |
840 | if (active) { |
841 | BUG_ON(active != &dev_priv->fbdev_master); | |
842 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
843 | if (unlikely(ret != 0)) | |
844 | goto out_no_active_lock; | |
845 | ||
846 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
847 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
848 | if (unlikely(ret != 0)) { | |
849 | DRM_ERROR("Unable to clean VRAM on " | |
850 | "master drop.\n"); | |
851 | } | |
852 | ||
853 | dev_priv->active_master = NULL; | |
854 | } | |
855 | ||
856 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
857 | if (!from_open) { | |
858 | ttm_vt_unlock(&vmaster->lock); | |
859 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
860 | drm_master_put(&vmw_fp->locked_master); | |
861 | } | |
862 | ||
863 | dev_priv->active_master = vmaster; | |
864 | ||
865 | return 0; | |
866 | ||
867 | out_no_active_lock: | |
30c78bb8 TH |
868 | if (!dev_priv->enable_fb) { |
869 | mutex_lock(&dev_priv->hw_mutex); | |
870 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
871 | mutex_unlock(&dev_priv->hw_mutex); | |
872 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 873 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 | 874 | } |
fb1d9738 JB |
875 | return ret; |
876 | } | |
877 | ||
878 | static void vmw_master_drop(struct drm_device *dev, | |
879 | struct drm_file *file_priv, | |
880 | bool from_release) | |
881 | { | |
882 | struct vmw_private *dev_priv = vmw_priv(dev); | |
883 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
884 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
885 | int ret; | |
886 | ||
fb1d9738 JB |
887 | /** |
888 | * Make sure the master doesn't disappear while we have | |
889 | * it locked. | |
890 | */ | |
891 | ||
892 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
893 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
e2fa3a76 TH |
894 | vmw_execbuf_release_pinned_bo(dev_priv, false, 0); |
895 | ||
fb1d9738 JB |
896 | if (unlikely((ret != 0))) { |
897 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
898 | drm_master_put(&vmw_fp->locked_master); | |
899 | } | |
900 | ||
901 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
902 | ||
30c78bb8 TH |
903 | if (!dev_priv->enable_fb) { |
904 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
905 | if (unlikely(ret != 0)) | |
906 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
907 | mutex_lock(&dev_priv->hw_mutex); | |
908 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
909 | mutex_unlock(&dev_priv->hw_mutex); | |
910 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 911 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 TH |
912 | } |
913 | ||
fb1d9738 JB |
914 | dev_priv->active_master = &dev_priv->fbdev_master; |
915 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
916 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
917 | ||
30c78bb8 TH |
918 | if (dev_priv->enable_fb) |
919 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
920 | } |
921 | ||
922 | ||
923 | static void vmw_remove(struct pci_dev *pdev) | |
924 | { | |
925 | struct drm_device *dev = pci_get_drvdata(pdev); | |
926 | ||
927 | drm_put_dev(dev); | |
928 | } | |
929 | ||
d9f36a00 TH |
930 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
931 | void *ptr) | |
932 | { | |
933 | struct vmw_private *dev_priv = | |
934 | container_of(nb, struct vmw_private, pm_nb); | |
935 | struct vmw_master *vmaster = dev_priv->active_master; | |
936 | ||
937 | switch (val) { | |
938 | case PM_HIBERNATION_PREPARE: | |
939 | case PM_SUSPEND_PREPARE: | |
940 | ttm_suspend_lock(&vmaster->lock); | |
941 | ||
942 | /** | |
943 | * This empties VRAM and unbinds all GMR bindings. | |
944 | * Buffer contents is moved to swappable memory. | |
945 | */ | |
e2fa3a76 | 946 | vmw_execbuf_release_pinned_bo(dev_priv, false, 0); |
d9f36a00 | 947 | ttm_bo_swapout_all(&dev_priv->bdev); |
094e0fa8 | 948 | |
d9f36a00 TH |
949 | break; |
950 | case PM_POST_HIBERNATION: | |
951 | case PM_POST_SUSPEND: | |
094e0fa8 | 952 | case PM_POST_RESTORE: |
d9f36a00 | 953 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 954 | |
d9f36a00 TH |
955 | break; |
956 | case PM_RESTORE_PREPARE: | |
957 | break; | |
d9f36a00 TH |
958 | default: |
959 | break; | |
960 | } | |
961 | return 0; | |
962 | } | |
963 | ||
964 | /** | |
965 | * These might not be needed with the virtual SVGA device. | |
966 | */ | |
967 | ||
7fbd721a | 968 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 969 | { |
094e0fa8 TH |
970 | struct drm_device *dev = pci_get_drvdata(pdev); |
971 | struct vmw_private *dev_priv = vmw_priv(dev); | |
972 | ||
973 | if (dev_priv->num_3d_resources != 0) { | |
974 | DRM_INFO("Can't suspend or hibernate " | |
975 | "while 3D resources are active.\n"); | |
976 | return -EBUSY; | |
977 | } | |
978 | ||
d9f36a00 TH |
979 | pci_save_state(pdev); |
980 | pci_disable_device(pdev); | |
981 | pci_set_power_state(pdev, PCI_D3hot); | |
982 | return 0; | |
983 | } | |
984 | ||
7fbd721a | 985 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
986 | { |
987 | pci_set_power_state(pdev, PCI_D0); | |
988 | pci_restore_state(pdev); | |
989 | return pci_enable_device(pdev); | |
990 | } | |
991 | ||
7fbd721a TH |
992 | static int vmw_pm_suspend(struct device *kdev) |
993 | { | |
994 | struct pci_dev *pdev = to_pci_dev(kdev); | |
995 | struct pm_message dummy; | |
996 | ||
997 | dummy.event = 0; | |
998 | ||
999 | return vmw_pci_suspend(pdev, dummy); | |
1000 | } | |
1001 | ||
1002 | static int vmw_pm_resume(struct device *kdev) | |
1003 | { | |
1004 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1005 | ||
1006 | return vmw_pci_resume(pdev); | |
1007 | } | |
1008 | ||
1009 | static int vmw_pm_prepare(struct device *kdev) | |
1010 | { | |
1011 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1012 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1013 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1014 | ||
1015 | /** | |
1016 | * Release 3d reference held by fbdev and potentially | |
1017 | * stop fifo. | |
1018 | */ | |
1019 | dev_priv->suspended = true; | |
1020 | if (dev_priv->enable_fb) | |
05730b32 | 1021 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
1022 | |
1023 | if (dev_priv->num_3d_resources != 0) { | |
1024 | ||
1025 | DRM_INFO("Can't suspend or hibernate " | |
1026 | "while 3D resources are active.\n"); | |
1027 | ||
1028 | if (dev_priv->enable_fb) | |
05730b32 | 1029 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
1030 | dev_priv->suspended = false; |
1031 | return -EBUSY; | |
1032 | } | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static void vmw_pm_complete(struct device *kdev) | |
1038 | { | |
1039 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1040 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1041 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1042 | ||
1043 | /** | |
1044 | * Reclaim 3d reference held by fbdev and potentially | |
1045 | * start fifo. | |
1046 | */ | |
1047 | if (dev_priv->enable_fb) | |
05730b32 | 1048 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
1049 | |
1050 | dev_priv->suspended = false; | |
1051 | } | |
1052 | ||
1053 | static const struct dev_pm_ops vmw_pm_ops = { | |
1054 | .prepare = vmw_pm_prepare, | |
1055 | .complete = vmw_pm_complete, | |
1056 | .suspend = vmw_pm_suspend, | |
1057 | .resume = vmw_pm_resume, | |
1058 | }; | |
1059 | ||
fb1d9738 JB |
1060 | static struct drm_driver driver = { |
1061 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
1062 | DRIVER_MODESET, | |
1063 | .load = vmw_driver_load, | |
1064 | .unload = vmw_driver_unload, | |
1065 | .firstopen = vmw_firstopen, | |
1066 | .lastclose = vmw_lastclose, | |
1067 | .irq_preinstall = vmw_irq_preinstall, | |
1068 | .irq_postinstall = vmw_irq_postinstall, | |
1069 | .irq_uninstall = vmw_irq_uninstall, | |
1070 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1071 | .get_vblank_counter = vmw_get_vblank_counter, |
fb1d9738 | 1072 | .reclaim_buffers_locked = NULL, |
fb1d9738 JB |
1073 | .ioctls = vmw_ioctls, |
1074 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
1075 | .dma_quiescent = NULL, /*vmw_dma_quiescent, */ | |
1076 | .master_create = vmw_master_create, | |
1077 | .master_destroy = vmw_master_destroy, | |
1078 | .master_set = vmw_master_set, | |
1079 | .master_drop = vmw_master_drop, | |
1080 | .open = vmw_driver_open, | |
1081 | .postclose = vmw_postclose, | |
1082 | .fops = { | |
1083 | .owner = THIS_MODULE, | |
1084 | .open = drm_open, | |
1085 | .release = drm_release, | |
1086 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1087 | .mmap = vmw_mmap, | |
5438ae88 TH |
1088 | .poll = vmw_fops_poll, |
1089 | .read = vmw_fops_read, | |
fb1d9738 JB |
1090 | .fasync = drm_fasync, |
1091 | #if defined(CONFIG_COMPAT) | |
1092 | .compat_ioctl = drm_compat_ioctl, | |
1093 | #endif | |
dc880abe | 1094 | .llseek = noop_llseek, |
7fbd721a | 1095 | }, |
fb1d9738 JB |
1096 | .name = VMWGFX_DRIVER_NAME, |
1097 | .desc = VMWGFX_DRIVER_DESC, | |
1098 | .date = VMWGFX_DRIVER_DATE, | |
1099 | .major = VMWGFX_DRIVER_MAJOR, | |
1100 | .minor = VMWGFX_DRIVER_MINOR, | |
1101 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1102 | }; | |
1103 | ||
8410ea3b DA |
1104 | static struct pci_driver vmw_pci_driver = { |
1105 | .name = VMWGFX_DRIVER_NAME, | |
1106 | .id_table = vmw_pci_id_list, | |
1107 | .probe = vmw_probe, | |
1108 | .remove = vmw_remove, | |
1109 | .driver = { | |
1110 | .pm = &vmw_pm_ops | |
1111 | } | |
1112 | }; | |
1113 | ||
fb1d9738 JB |
1114 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1115 | { | |
dcdb1674 | 1116 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1117 | } |
1118 | ||
1119 | static int __init vmwgfx_init(void) | |
1120 | { | |
1121 | int ret; | |
8410ea3b | 1122 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1123 | if (ret) |
1124 | DRM_ERROR("Failed initializing DRM.\n"); | |
1125 | return ret; | |
1126 | } | |
1127 | ||
1128 | static void __exit vmwgfx_exit(void) | |
1129 | { | |
8410ea3b | 1130 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1131 | } |
1132 | ||
1133 | module_init(vmwgfx_init); | |
1134 | module_exit(vmwgfx_exit); | |
1135 | ||
1136 | MODULE_AUTHOR("VMware Inc. and others"); | |
1137 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1138 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1139 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1140 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1141 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1142 | "0"); |