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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
54fbde8a | 3 | * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
fb1d9738 JB |
4 | * All Rights Reserved. |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
96c5d076 | 28 | #include <linux/console.h> |
fb1d9738 | 29 | |
760285e7 | 30 | #include <drm/drmP.h> |
fb1d9738 | 31 | #include "vmwgfx_drv.h" |
d80efd5c | 32 | #include "vmwgfx_binding.h" |
760285e7 DH |
33 | #include <drm/ttm/ttm_placement.h> |
34 | #include <drm/ttm/ttm_bo_driver.h> | |
35 | #include <drm/ttm/ttm_object.h> | |
36 | #include <drm/ttm/ttm_module.h> | |
d92d9851 | 37 | #include <linux/dma_remapping.h> |
fb1d9738 JB |
38 | |
39 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
40 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
41 | #define VMWGFX_CHIP_SVGAII 0 | |
42 | #define VMW_FB_RESERVATION 0 | |
43 | ||
eb4f923b JB |
44 | #define VMW_MIN_INITIAL_WIDTH 800 |
45 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
46 | ||
47 | ||
fb1d9738 JB |
48 | /** |
49 | * Fully encoded drm commands. Might move to vmw_drm.h | |
50 | */ | |
51 | ||
52 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
53 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
54 | struct drm_vmw_getparam_arg) | |
55 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
56 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
57 | union drm_vmw_alloc_dmabuf_arg) | |
58 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
59 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
60 | struct drm_vmw_unref_dmabuf_arg) | |
61 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
62 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
63 | struct drm_vmw_cursor_bypass_arg) | |
64 | ||
65 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
66 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
67 | struct drm_vmw_control_stream_arg) | |
68 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
69 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
70 | struct drm_vmw_stream_arg) | |
71 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
72 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
73 | struct drm_vmw_stream_arg) | |
74 | ||
75 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
76 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
77 | struct drm_vmw_context_arg) | |
78 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
79 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
80 | struct drm_vmw_context_arg) | |
81 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
82 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
83 | union drm_vmw_surface_create_arg) | |
84 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
85 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
86 | struct drm_vmw_surface_arg) | |
87 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
88 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
89 | union drm_vmw_surface_reference_arg) | |
90 | #define DRM_IOCTL_VMW_EXECBUF \ | |
91 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
92 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
93 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
94 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
95 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
96 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
97 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
98 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
99 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
100 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
101 | struct drm_vmw_fence_signaled_arg) | |
102 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
103 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
104 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
105 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
106 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
107 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
108 | #define DRM_IOCTL_VMW_PRESENT \ |
109 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
110 | struct drm_vmw_present_arg) | |
111 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
112 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
113 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
114 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
115 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
116 | struct drm_vmw_update_layout_arg) | |
c74c162f TH |
117 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
118 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ | |
119 | struct drm_vmw_shader_create_arg) | |
120 | #define DRM_IOCTL_VMW_UNREF_SHADER \ | |
121 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ | |
122 | struct drm_vmw_shader_arg) | |
a97e2192 TH |
123 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
124 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ | |
125 | union drm_vmw_gb_surface_create_arg) | |
126 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ | |
127 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ | |
128 | union drm_vmw_gb_surface_reference_arg) | |
1d7a5cbf TH |
129 | #define DRM_IOCTL_VMW_SYNCCPU \ |
130 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ | |
131 | struct drm_vmw_synccpu_arg) | |
d80efd5c TH |
132 | #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ |
133 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ | |
134 | struct drm_vmw_context_arg) | |
fb1d9738 JB |
135 | |
136 | /** | |
137 | * The core DRM version of this macro doesn't account for | |
138 | * DRM_COMMAND_BASE. | |
139 | */ | |
140 | ||
141 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
7e7392a6 | 142 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} |
fb1d9738 JB |
143 | |
144 | /** | |
145 | * Ioctl definitions. | |
146 | */ | |
147 | ||
baa70943 | 148 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
1b2f1489 | 149 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
f8c47144 | 150 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 151 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
f8c47144 | 152 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 153 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
f8c47144 | 154 | DRM_RENDER_ALLOW), |
1b2f1489 | 155 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 | 156 | vmw_kms_cursor_bypass_ioctl, |
f8c47144 | 157 | DRM_MASTER | DRM_CONTROL_ALLOW), |
fb1d9738 | 158 | |
1b2f1489 | 159 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
f8c47144 | 160 | DRM_MASTER | DRM_CONTROL_ALLOW), |
1b2f1489 | 161 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
f8c47144 | 162 | DRM_MASTER | DRM_CONTROL_ALLOW), |
1b2f1489 | 163 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
f8c47144 | 164 | DRM_MASTER | DRM_CONTROL_ALLOW), |
fb1d9738 | 165 | |
1b2f1489 | 166 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
f8c47144 | 167 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 168 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
f8c47144 | 169 | DRM_RENDER_ALLOW), |
1b2f1489 | 170 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
f8c47144 | 171 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 172 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
f8c47144 | 173 | DRM_RENDER_ALLOW), |
1b2f1489 | 174 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
f8c47144 DV |
175 | DRM_AUTH | DRM_RENDER_ALLOW), |
176 | VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | | |
d80efd5c | 177 | DRM_RENDER_ALLOW), |
ae2a1040 | 178 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
f8c47144 | 179 | DRM_RENDER_ALLOW), |
ae2a1040 TH |
180 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
181 | vmw_fence_obj_signaled_ioctl, | |
f8c47144 | 182 | DRM_RENDER_ALLOW), |
ae2a1040 | 183 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
f8c47144 | 184 | DRM_RENDER_ALLOW), |
03f80263 | 185 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
f8c47144 | 186 | DRM_AUTH | DRM_RENDER_ALLOW), |
f63f6a59 | 187 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
f8c47144 | 188 | DRM_AUTH | DRM_RENDER_ALLOW), |
2fcd5a73 JB |
189 | |
190 | /* these allow direct access to the framebuffers mark as master only */ | |
191 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
f8c47144 | 192 | DRM_MASTER | DRM_AUTH), |
2fcd5a73 JB |
193 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, |
194 | vmw_present_readback_ioctl, | |
f8c47144 | 195 | DRM_MASTER | DRM_AUTH), |
cd2b89e7 TH |
196 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
197 | vmw_kms_update_layout_ioctl, | |
b0dc6d43 | 198 | DRM_MASTER | DRM_CONTROL_ALLOW), |
c74c162f TH |
199 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
200 | vmw_shader_define_ioctl, | |
f8c47144 | 201 | DRM_AUTH | DRM_RENDER_ALLOW), |
c74c162f TH |
202 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
203 | vmw_shader_destroy_ioctl, | |
f8c47144 | 204 | DRM_RENDER_ALLOW), |
a97e2192 TH |
205 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
206 | vmw_gb_surface_define_ioctl, | |
f8c47144 | 207 | DRM_AUTH | DRM_RENDER_ALLOW), |
a97e2192 TH |
208 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
209 | vmw_gb_surface_reference_ioctl, | |
f8c47144 | 210 | DRM_AUTH | DRM_RENDER_ALLOW), |
1d7a5cbf TH |
211 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
212 | vmw_user_dmabuf_synccpu_ioctl, | |
f8c47144 | 213 | DRM_RENDER_ALLOW), |
d80efd5c TH |
214 | VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, |
215 | vmw_extended_context_define_ioctl, | |
f8c47144 | 216 | DRM_AUTH | DRM_RENDER_ALLOW), |
fb1d9738 JB |
217 | }; |
218 | ||
219 | static struct pci_device_id vmw_pci_id_list[] = { | |
220 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
221 | {0, 0, 0} | |
222 | }; | |
c4903429 | 223 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 224 | |
5d2afab9 | 225 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
d92d9851 TH |
226 | static int vmw_force_iommu; |
227 | static int vmw_restrict_iommu; | |
228 | static int vmw_force_coherent; | |
0d00c488 | 229 | static int vmw_restrict_dma_mask; |
fb1d9738 JB |
230 | |
231 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
232 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
233 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
234 | void *ptr); | |
fb1d9738 | 235 | |
30c78bb8 TH |
236 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
237 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
d92d9851 TH |
238 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
239 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); | |
240 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); | |
241 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); | |
242 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); | |
243 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); | |
0d00c488 TH |
244 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
245 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); | |
d92d9851 | 246 | |
30c78bb8 | 247 | |
fb1d9738 JB |
248 | static void vmw_print_capabilities(uint32_t capabilities) |
249 | { | |
250 | DRM_INFO("Capabilities:\n"); | |
251 | if (capabilities & SVGA_CAP_RECT_COPY) | |
252 | DRM_INFO(" Rect copy.\n"); | |
253 | if (capabilities & SVGA_CAP_CURSOR) | |
254 | DRM_INFO(" Cursor.\n"); | |
255 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
256 | DRM_INFO(" Cursor bypass.\n"); | |
257 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
258 | DRM_INFO(" Cursor bypass 2.\n"); | |
259 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
260 | DRM_INFO(" 8bit emulation.\n"); | |
261 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
262 | DRM_INFO(" Alpha cursor.\n"); | |
263 | if (capabilities & SVGA_CAP_3D) | |
264 | DRM_INFO(" 3D.\n"); | |
265 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
266 | DRM_INFO(" Extended Fifo.\n"); | |
267 | if (capabilities & SVGA_CAP_MULTIMON) | |
268 | DRM_INFO(" Multimon.\n"); | |
269 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
270 | DRM_INFO(" Pitchlock.\n"); | |
271 | if (capabilities & SVGA_CAP_IRQMASK) | |
272 | DRM_INFO(" Irq mask.\n"); | |
273 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
274 | DRM_INFO(" Display Topology.\n"); | |
275 | if (capabilities & SVGA_CAP_GMR) | |
276 | DRM_INFO(" GMR.\n"); | |
277 | if (capabilities & SVGA_CAP_TRACES) | |
278 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
279 | if (capabilities & SVGA_CAP_GMR2) |
280 | DRM_INFO(" GMR2.\n"); | |
281 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
282 | DRM_INFO(" Screen Object 2.\n"); | |
c1234db7 TH |
283 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
284 | DRM_INFO(" Command Buffers.\n"); | |
285 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) | |
286 | DRM_INFO(" Command Buffers 2.\n"); | |
287 | if (capabilities & SVGA_CAP_GBOBJECTS) | |
288 | DRM_INFO(" Guest Backed Resources.\n"); | |
8ce75f8a SY |
289 | if (capabilities & SVGA_CAP_DX) |
290 | DRM_INFO(" DX Features.\n"); | |
fb1d9738 JB |
291 | } |
292 | ||
e2fa3a76 | 293 | /** |
4b9e45e6 | 294 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
e2fa3a76 | 295 | * |
4b9e45e6 | 296 | * @dev_priv: A device private structure. |
e2fa3a76 | 297 | * |
4b9e45e6 TH |
298 | * This function creates a small buffer object that holds the query |
299 | * result for dummy queries emitted as query barriers. | |
300 | * The function will then map the first page and initialize a pending | |
301 | * occlusion query result structure, Finally it will unmap the buffer. | |
302 | * No interruptible waits are done within this function. | |
e2fa3a76 | 303 | * |
4b9e45e6 | 304 | * Returns an error if bo creation or initialization fails. |
e2fa3a76 | 305 | */ |
4b9e45e6 | 306 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
e2fa3a76 | 307 | { |
4b9e45e6 | 308 | int ret; |
459d0fa7 | 309 | struct vmw_dma_buffer *vbo; |
e2fa3a76 TH |
310 | struct ttm_bo_kmap_obj map; |
311 | volatile SVGA3dQueryResult *result; | |
312 | bool dummy; | |
e2fa3a76 | 313 | |
4b9e45e6 | 314 | /* |
459d0fa7 | 315 | * Create the vbo as pinned, so that a tryreserve will |
4b9e45e6 TH |
316 | * immediately succeed. This is because we're the only |
317 | * user of the bo currently. | |
318 | */ | |
459d0fa7 TH |
319 | vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); |
320 | if (!vbo) | |
321 | return -ENOMEM; | |
4b9e45e6 | 322 | |
459d0fa7 TH |
323 | ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, |
324 | &vmw_sys_ne_placement, false, | |
325 | &vmw_dmabuf_bo_free); | |
e2fa3a76 | 326 | if (unlikely(ret != 0)) |
4b9e45e6 TH |
327 | return ret; |
328 | ||
dfd5e50e | 329 | ret = ttm_bo_reserve(&vbo->base, false, true, NULL); |
4b9e45e6 | 330 | BUG_ON(ret != 0); |
459d0fa7 | 331 | vmw_bo_pin_reserved(vbo, true); |
e2fa3a76 | 332 | |
459d0fa7 | 333 | ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); |
e2fa3a76 TH |
334 | if (likely(ret == 0)) { |
335 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
336 | result->totalSize = sizeof(*result); | |
337 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
338 | result->result32 = 0xff; | |
339 | ttm_bo_kunmap(&map); | |
4b9e45e6 | 340 | } |
459d0fa7 TH |
341 | vmw_bo_pin_reserved(vbo, false); |
342 | ttm_bo_unreserve(&vbo->base); | |
e2fa3a76 | 343 | |
4b9e45e6 TH |
344 | if (unlikely(ret != 0)) { |
345 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
459d0fa7 | 346 | vmw_dmabuf_unreference(&vbo); |
4b9e45e6 | 347 | } else |
459d0fa7 | 348 | dev_priv->dummy_query_bo = vbo; |
e2fa3a76 | 349 | |
4b9e45e6 | 350 | return ret; |
e2fa3a76 TH |
351 | } |
352 | ||
153b3d5b TH |
353 | /** |
354 | * vmw_request_device_late - Perform late device setup | |
355 | * | |
356 | * @dev_priv: Pointer to device private. | |
357 | * | |
358 | * This function performs setup of otables and enables large command | |
359 | * buffer submission. These tasks are split out to a separate function | |
360 | * because it reverts vmw_release_device_early and is intended to be used | |
361 | * by an error path in the hibernation code. | |
362 | */ | |
363 | static int vmw_request_device_late(struct vmw_private *dev_priv) | |
fb1d9738 JB |
364 | { |
365 | int ret; | |
366 | ||
3530bdc3 TH |
367 | if (dev_priv->has_mob) { |
368 | ret = vmw_otables_setup(dev_priv); | |
369 | if (unlikely(ret != 0)) { | |
370 | DRM_ERROR("Unable to initialize " | |
371 | "guest Memory OBjects.\n"); | |
153b3d5b | 372 | return ret; |
3530bdc3 TH |
373 | } |
374 | } | |
153b3d5b | 375 | |
3eab3d9e TH |
376 | if (dev_priv->cman) { |
377 | ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, | |
378 | 256*4096, 2*4096); | |
379 | if (ret) { | |
380 | struct vmw_cmdbuf_man *man = dev_priv->cman; | |
381 | ||
382 | dev_priv->cman = NULL; | |
383 | vmw_cmdbuf_man_destroy(man); | |
384 | } | |
385 | } | |
386 | ||
153b3d5b TH |
387 | return 0; |
388 | } | |
389 | ||
fb1d9738 JB |
390 | static int vmw_request_device(struct vmw_private *dev_priv) |
391 | { | |
392 | int ret; | |
393 | ||
fb1d9738 JB |
394 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
395 | if (unlikely(ret != 0)) { | |
396 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
397 | return ret; | |
398 | } | |
ae2a1040 | 399 | vmw_fence_fifo_up(dev_priv->fman); |
3eab3d9e | 400 | dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); |
d80efd5c | 401 | if (IS_ERR(dev_priv->cman)) { |
3eab3d9e | 402 | dev_priv->cman = NULL; |
d80efd5c | 403 | dev_priv->has_dx = false; |
3530bdc3 | 404 | } |
153b3d5b TH |
405 | |
406 | ret = vmw_request_device_late(dev_priv); | |
407 | if (ret) | |
408 | goto out_no_mob; | |
409 | ||
e2fa3a76 TH |
410 | ret = vmw_dummy_query_bo_create(dev_priv); |
411 | if (unlikely(ret != 0)) | |
412 | goto out_no_query_bo; | |
fb1d9738 JB |
413 | |
414 | return 0; | |
e2fa3a76 TH |
415 | |
416 | out_no_query_bo: | |
3eab3d9e TH |
417 | if (dev_priv->cman) |
418 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
153b3d5b TH |
419 | if (dev_priv->has_mob) { |
420 | (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 421 | vmw_otables_takedown(dev_priv); |
153b3d5b | 422 | } |
3eab3d9e TH |
423 | if (dev_priv->cman) |
424 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
3530bdc3 | 425 | out_no_mob: |
e2fa3a76 TH |
426 | vmw_fence_fifo_down(dev_priv->fman); |
427 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
428 | return ret; | |
fb1d9738 JB |
429 | } |
430 | ||
153b3d5b TH |
431 | /** |
432 | * vmw_release_device_early - Early part of fifo takedown. | |
433 | * | |
434 | * @dev_priv: Pointer to device private struct. | |
435 | * | |
436 | * This is the first part of command submission takedown, to be called before | |
437 | * buffer management is taken down. | |
438 | */ | |
439 | static void vmw_release_device_early(struct vmw_private *dev_priv) | |
fb1d9738 | 440 | { |
e2fa3a76 TH |
441 | /* |
442 | * Previous destructions should've released | |
443 | * the pinned bo. | |
444 | */ | |
445 | ||
446 | BUG_ON(dev_priv->pinned_bo != NULL); | |
447 | ||
459d0fa7 | 448 | vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); |
3eab3d9e TH |
449 | if (dev_priv->cman) |
450 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
30c78bb8 | 451 | |
153b3d5b TH |
452 | if (dev_priv->has_mob) { |
453 | ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 454 | vmw_otables_takedown(dev_priv); |
30c78bb8 | 455 | } |
fb1d9738 JB |
456 | } |
457 | ||
05730b32 | 458 | /** |
153b3d5b TH |
459 | * vmw_release_device_late - Late part of fifo takedown. |
460 | * | |
461 | * @dev_priv: Pointer to device private struct. | |
462 | * | |
463 | * This is the last part of the command submission takedown, to be called when | |
464 | * command submission is no longer needed. It may wait on pending fences. | |
05730b32 | 465 | */ |
153b3d5b | 466 | static void vmw_release_device_late(struct vmw_private *dev_priv) |
30c78bb8 | 467 | { |
153b3d5b | 468 | vmw_fence_fifo_down(dev_priv->fman); |
3eab3d9e TH |
469 | if (dev_priv->cman) |
470 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
30c78bb8 | 471 | |
153b3d5b | 472 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
473 | } |
474 | ||
eb4f923b JB |
475 | /** |
476 | * Sets the initial_[width|height] fields on the given vmw_private. | |
477 | * | |
478 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
479 | * clamping the value to fb_max_[width|height] fields and the |
480 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
481 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
482 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
483 | */ | |
484 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
485 | { | |
486 | uint32_t width; | |
487 | uint32_t height; | |
488 | ||
489 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
490 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
491 | ||
492 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 493 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
494 | |
495 | if (width > dev_priv->fb_max_width || | |
496 | height > dev_priv->fb_max_height) { | |
497 | ||
498 | /* | |
499 | * This is a host error and shouldn't occur. | |
500 | */ | |
501 | ||
502 | width = VMW_MIN_INITIAL_WIDTH; | |
503 | height = VMW_MIN_INITIAL_HEIGHT; | |
504 | } | |
eb4f923b JB |
505 | |
506 | dev_priv->initial_width = width; | |
507 | dev_priv->initial_height = height; | |
508 | } | |
509 | ||
d92d9851 TH |
510 | /** |
511 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this | |
512 | * system. | |
513 | * | |
514 | * @dev_priv: Pointer to a struct vmw_private | |
515 | * | |
516 | * This functions tries to determine the IOMMU setup and what actions | |
517 | * need to be taken by the driver to make system pages visible to the | |
518 | * device. | |
519 | * If this function decides that DMA is not possible, it returns -EINVAL. | |
520 | * The driver may then try to disable features of the device that require | |
521 | * DMA. | |
522 | */ | |
523 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) | |
524 | { | |
d92d9851 TH |
525 | static const char *names[vmw_dma_map_max] = { |
526 | [vmw_dma_phys] = "Using physical TTM page addresses.", | |
527 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", | |
528 | [vmw_dma_map_populate] = "Keeping DMA mappings.", | |
529 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; | |
e14cd953 TH |
530 | #ifdef CONFIG_X86 |
531 | const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); | |
d92d9851 TH |
532 | |
533 | #ifdef CONFIG_INTEL_IOMMU | |
534 | if (intel_iommu_enabled) { | |
535 | dev_priv->map_mode = vmw_dma_map_populate; | |
536 | goto out_fixup; | |
537 | } | |
538 | #endif | |
539 | ||
540 | if (!(vmw_force_iommu || vmw_force_coherent)) { | |
541 | dev_priv->map_mode = vmw_dma_phys; | |
542 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); | |
543 | return 0; | |
544 | } | |
545 | ||
546 | dev_priv->map_mode = vmw_dma_map_populate; | |
547 | ||
548 | if (dma_ops->sync_single_for_cpu) | |
549 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
550 | #ifdef CONFIG_SWIOTLB | |
551 | if (swiotlb_nr_tbl() == 0) | |
552 | dev_priv->map_mode = vmw_dma_map_populate; | |
553 | #endif | |
554 | ||
21136946 | 555 | #ifdef CONFIG_INTEL_IOMMU |
d92d9851 | 556 | out_fixup: |
21136946 | 557 | #endif |
d92d9851 TH |
558 | if (dev_priv->map_mode == vmw_dma_map_populate && |
559 | vmw_restrict_iommu) | |
560 | dev_priv->map_mode = vmw_dma_map_bind; | |
561 | ||
562 | if (vmw_force_coherent) | |
563 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
564 | ||
565 | #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) | |
566 | /* | |
567 | * No coherent page pool | |
568 | */ | |
569 | if (dev_priv->map_mode == vmw_dma_alloc_coherent) | |
570 | return -EINVAL; | |
571 | #endif | |
572 | ||
e14cd953 TH |
573 | #else /* CONFIG_X86 */ |
574 | dev_priv->map_mode = vmw_dma_map_populate; | |
575 | #endif /* CONFIG_X86 */ | |
576 | ||
d92d9851 TH |
577 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
0d00c488 TH |
582 | /** |
583 | * vmw_dma_masks - set required page- and dma masks | |
584 | * | |
585 | * @dev: Pointer to struct drm-device | |
586 | * | |
587 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that | |
588 | * restriction also for 64-bit systems. | |
589 | */ | |
590 | #ifdef CONFIG_INTEL_IOMMU | |
591 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
592 | { | |
593 | struct drm_device *dev = dev_priv->dev; | |
594 | ||
595 | if (intel_iommu_enabled && | |
596 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { | |
597 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); | |
598 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); | |
599 | } | |
600 | return 0; | |
601 | } | |
602 | #else | |
603 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
604 | { | |
605 | return 0; | |
606 | } | |
607 | #endif | |
608 | ||
fb1d9738 JB |
609 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
610 | { | |
611 | struct vmw_private *dev_priv; | |
612 | int ret; | |
c188660f | 613 | uint32_t svga_id; |
c0951b79 | 614 | enum vmw_res_type i; |
d92d9851 | 615 | bool refuse_dma = false; |
fb1d9738 JB |
616 | |
617 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
618 | if (unlikely(dev_priv == NULL)) { | |
619 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
620 | return -ENOMEM; | |
621 | } | |
fb1d9738 | 622 | |
466e69b8 DA |
623 | pci_set_master(dev->pdev); |
624 | ||
fb1d9738 JB |
625 | dev_priv->dev = dev; |
626 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 627 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 | 628 | mutex_init(&dev_priv->cmdbuf_mutex); |
30c78bb8 | 629 | mutex_init(&dev_priv->release_mutex); |
173fb7d4 | 630 | mutex_init(&dev_priv->binding_mutex); |
93cd1681 | 631 | mutex_init(&dev_priv->global_kms_state_mutex); |
fb1d9738 | 632 | rwlock_init(&dev_priv->resource_lock); |
294adf7d | 633 | ttm_lock_init(&dev_priv->reservation_sem); |
496eb6fd TH |
634 | spin_lock_init(&dev_priv->hw_lock); |
635 | spin_lock_init(&dev_priv->waiter_lock); | |
636 | spin_lock_init(&dev_priv->cap_lock); | |
153b3d5b | 637 | spin_lock_init(&dev_priv->svga_lock); |
c0951b79 TH |
638 | |
639 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
640 | idr_init(&dev_priv->res_idr[i]); | |
641 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
642 | } | |
643 | ||
fb1d9738 JB |
644 | mutex_init(&dev_priv->init_mutex); |
645 | init_waitqueue_head(&dev_priv->fence_queue); | |
646 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 647 | dev_priv->fence_queue_waiters = 0; |
d2e8851a | 648 | dev_priv->fifo_queue_waiters = 0; |
c0951b79 | 649 | |
5bb39e81 | 650 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
651 | |
652 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
653 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
654 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
655 | ||
30c78bb8 TH |
656 | dev_priv->enable_fb = enable_fbdev; |
657 | ||
c188660f PH |
658 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
659 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
660 | if (svga_id != SVGA_ID_2) { | |
661 | ret = -ENOSYS; | |
49625904 | 662 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
663 | goto out_err0; |
664 | } | |
665 | ||
fb1d9738 | 666 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
d92d9851 TH |
667 | ret = vmw_dma_select_mode(dev_priv); |
668 | if (unlikely(ret != 0)) { | |
669 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); | |
670 | refuse_dma = true; | |
671 | } | |
fb1d9738 | 672 | |
5bb39e81 TH |
673 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
674 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
675 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
676 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
677 | |
678 | vmw_get_initial_size(dev_priv); | |
679 | ||
0d00c488 | 680 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
681 | dev_priv->max_gmr_ids = |
682 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
fb17f189 TH |
683 | dev_priv->max_gmr_pages = |
684 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
685 | dev_priv->memory_size = | |
686 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
687 | dev_priv->memory_size -= dev_priv->vram_size; |
688 | } else { | |
689 | /* | |
690 | * An arbitrary limit of 512MiB on surface | |
691 | * memory. But all HWV8 hardware supports GMR2. | |
692 | */ | |
693 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 694 | } |
6da768aa | 695 | dev_priv->max_mob_pages = 0; |
857aea1c | 696 | dev_priv->max_mob_size = 0; |
6da768aa TH |
697 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
698 | uint64_t mem_size = | |
699 | vmw_read(dev_priv, | |
700 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); | |
701 | ||
702 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; | |
afb0e50f TH |
703 | dev_priv->prim_bb_mem = |
704 | vmw_read(dev_priv, | |
705 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); | |
857aea1c CL |
706 | dev_priv->max_mob_size = |
707 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); | |
35c05125 SY |
708 | dev_priv->stdu_max_width = |
709 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); | |
710 | dev_priv->stdu_max_height = | |
711 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); | |
712 | ||
713 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
714 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); | |
715 | dev_priv->texture_max_width = vmw_read(dev_priv, | |
716 | SVGA_REG_DEV_CAP); | |
717 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
718 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); | |
719 | dev_priv->texture_max_height = vmw_read(dev_priv, | |
720 | SVGA_REG_DEV_CAP); | |
df45e9d4 TH |
721 | } else { |
722 | dev_priv->texture_max_width = 8192; | |
723 | dev_priv->texture_max_height = 8192; | |
afb0e50f | 724 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
df45e9d4 TH |
725 | } |
726 | ||
35c05125 | 727 | vmw_print_capabilities(dev_priv->capabilities); |
fb1d9738 | 728 | |
0d00c488 | 729 | ret = vmw_dma_masks(dev_priv); |
496eb6fd | 730 | if (unlikely(ret != 0)) |
0d00c488 TH |
731 | goto out_err0; |
732 | ||
0d00c488 | 733 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
734 | DRM_INFO("Max GMR ids is %u\n", |
735 | (unsigned)dev_priv->max_gmr_ids); | |
fb17f189 TH |
736 | DRM_INFO("Max number of GMR pages is %u\n", |
737 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
738 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
739 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 740 | } |
bc2d6508 TH |
741 | DRM_INFO("Maximum display memory size is %u kiB\n", |
742 | dev_priv->prim_bb_mem / 1024); | |
fb1d9738 JB |
743 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
744 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
745 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
746 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
747 | ||
748 | ret = vmw_ttm_global_init(dev_priv); | |
749 | if (unlikely(ret != 0)) | |
750 | goto out_err0; | |
751 | ||
752 | ||
753 | vmw_master_init(&dev_priv->fbdev_master); | |
754 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
755 | dev_priv->active_master = &dev_priv->fbdev_master; | |
756 | ||
b76ff5ea TH |
757 | dev_priv->mmio_virt = memremap(dev_priv->mmio_start, |
758 | dev_priv->mmio_size, MEMREMAP_WB); | |
fb1d9738 JB |
759 | |
760 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
761 | ret = -ENOMEM; | |
762 | DRM_ERROR("Failed mapping MMIO.\n"); | |
763 | goto out_err3; | |
764 | } | |
765 | ||
d7e1958d JB |
766 | /* Need mmio memory to check for fifo pitchlock cap. */ |
767 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
768 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
769 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
770 | ret = -ENOSYS; | |
771 | DRM_ERROR("Hardware has no pitchlock\n"); | |
772 | goto out_err4; | |
773 | } | |
774 | ||
fb1d9738 | 775 | dev_priv->tdev = ttm_object_device_init |
69977ff5 | 776 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
fb1d9738 JB |
777 | |
778 | if (unlikely(dev_priv->tdev == NULL)) { | |
779 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
780 | ret = -ENOMEM; | |
781 | goto out_err4; | |
782 | } | |
783 | ||
784 | dev->dev_private = dev_priv; | |
785 | ||
fb1d9738 JB |
786 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
787 | dev_priv->stealth = (ret != 0); | |
788 | if (dev_priv->stealth) { | |
789 | /** | |
790 | * Request at least the mmio PCI resource. | |
791 | */ | |
792 | ||
793 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 794 | "Ignore above error if any.\n"); |
fb1d9738 JB |
795 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
796 | if (unlikely(ret != 0)) { | |
797 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
798 | goto out_no_device; | |
799 | } | |
fb1d9738 | 800 | } |
ae2a1040 | 801 | |
506ff75c | 802 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
bb0f1b5c | 803 | ret = drm_irq_install(dev, dev->pdev->irq); |
506ff75c TH |
804 | if (ret != 0) { |
805 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
806 | goto out_no_irq; | |
807 | } | |
808 | } | |
809 | ||
ae2a1040 | 810 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
14bbf20c WY |
811 | if (unlikely(dev_priv->fman == NULL)) { |
812 | ret = -ENOMEM; | |
ae2a1040 | 813 | goto out_no_fman; |
14bbf20c | 814 | } |
56d1c78d | 815 | |
153b3d5b TH |
816 | ret = ttm_bo_device_init(&dev_priv->bdev, |
817 | dev_priv->bo_global_ref.ref.object, | |
818 | &vmw_bo_driver, | |
819 | dev->anon_inode->i_mapping, | |
820 | VMWGFX_FILE_PAGE_OFFSET, | |
821 | false); | |
822 | if (unlikely(ret != 0)) { | |
823 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
824 | goto out_no_bdev; | |
825 | } | |
3458390b | 826 | |
153b3d5b TH |
827 | /* |
828 | * Enable VRAM, but initially don't use it until SVGA is enabled and | |
829 | * unhidden. | |
830 | */ | |
3458390b TH |
831 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, |
832 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
833 | if (unlikely(ret != 0)) { | |
834 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
835 | goto out_no_vram; | |
836 | } | |
153b3d5b | 837 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; |
3458390b TH |
838 | |
839 | dev_priv->has_gmr = true; | |
840 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || | |
841 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
842 | VMW_PL_GMR) != 0) { | |
843 | DRM_INFO("No GMR memory available. " | |
844 | "Graphics memory resources are very limited.\n"); | |
845 | dev_priv->has_gmr = false; | |
846 | } | |
847 | ||
848 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | |
849 | dev_priv->has_mob = true; | |
850 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, | |
851 | VMW_PL_MOB) != 0) { | |
852 | DRM_INFO("No MOB memory available. " | |
853 | "3D will be disabled.\n"); | |
854 | dev_priv->has_mob = false; | |
855 | } | |
856 | } | |
857 | ||
d80efd5c TH |
858 | if (dev_priv->has_mob) { |
859 | spin_lock(&dev_priv->cap_lock); | |
860 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); | |
861 | dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); | |
862 | spin_unlock(&dev_priv->cap_lock); | |
863 | } | |
864 | ||
56d1c78d | 865 | |
7a1c2f6c TH |
866 | ret = vmw_kms_init(dev_priv); |
867 | if (unlikely(ret != 0)) | |
868 | goto out_no_kms; | |
f2d12b8e | 869 | vmw_overlay_init(dev_priv); |
56d1c78d | 870 | |
153b3d5b TH |
871 | ret = vmw_request_device(dev_priv); |
872 | if (ret) | |
873 | goto out_no_fifo; | |
874 | ||
d80efd5c TH |
875 | DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); |
876 | ||
30c78bb8 | 877 | if (dev_priv->enable_fb) { |
153b3d5b TH |
878 | vmw_fifo_resource_inc(dev_priv); |
879 | vmw_svga_enable(dev_priv); | |
30c78bb8 | 880 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
881 | } |
882 | ||
d9f36a00 TH |
883 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
884 | register_pm_notifier(&dev_priv->pm_nb); | |
885 | ||
fb1d9738 JB |
886 | return 0; |
887 | ||
506ff75c | 888 | out_no_fifo: |
56d1c78d JB |
889 | vmw_overlay_close(dev_priv); |
890 | vmw_kms_close(dev_priv); | |
891 | out_no_kms: | |
3458390b TH |
892 | if (dev_priv->has_mob) |
893 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
894 | if (dev_priv->has_gmr) | |
895 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
896 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
897 | out_no_vram: | |
153b3d5b TH |
898 | (void)ttm_bo_device_release(&dev_priv->bdev); |
899 | out_no_bdev: | |
ae2a1040 TH |
900 | vmw_fence_manager_takedown(dev_priv->fman); |
901 | out_no_fman: | |
506ff75c TH |
902 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
903 | drm_irq_uninstall(dev_priv->dev); | |
904 | out_no_irq: | |
30c78bb8 TH |
905 | if (dev_priv->stealth) |
906 | pci_release_region(dev->pdev, 2); | |
907 | else | |
908 | pci_release_regions(dev->pdev); | |
fb1d9738 | 909 | out_no_device: |
fb1d9738 JB |
910 | ttm_object_device_release(&dev_priv->tdev); |
911 | out_err4: | |
b76ff5ea | 912 | memunmap(dev_priv->mmio_virt); |
fb1d9738 | 913 | out_err3: |
fb1d9738 JB |
914 | vmw_ttm_global_release(dev_priv); |
915 | out_err0: | |
c0951b79 TH |
916 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
917 | idr_destroy(&dev_priv->res_idr[i]); | |
918 | ||
d80efd5c TH |
919 | if (dev_priv->ctx.staged_bindings) |
920 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
fb1d9738 JB |
921 | kfree(dev_priv); |
922 | return ret; | |
923 | } | |
924 | ||
925 | static int vmw_driver_unload(struct drm_device *dev) | |
926 | { | |
927 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 928 | enum vmw_res_type i; |
fb1d9738 | 929 | |
d9f36a00 TH |
930 | unregister_pm_notifier(&dev_priv->pm_nb); |
931 | ||
c0951b79 TH |
932 | if (dev_priv->ctx.res_ht_initialized) |
933 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
a3a1a667 | 934 | vfree(dev_priv->ctx.cmd_bounce); |
30c78bb8 | 935 | if (dev_priv->enable_fb) { |
05c95018 | 936 | vmw_fb_off(dev_priv); |
30c78bb8 | 937 | vmw_fb_close(dev_priv); |
153b3d5b TH |
938 | vmw_fifo_resource_dec(dev_priv); |
939 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 940 | } |
153b3d5b | 941 | |
f2d12b8e TH |
942 | vmw_kms_close(dev_priv); |
943 | vmw_overlay_close(dev_priv); | |
3458390b | 944 | |
3458390b TH |
945 | if (dev_priv->has_gmr) |
946 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
947 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
948 | ||
153b3d5b TH |
949 | vmw_release_device_early(dev_priv); |
950 | if (dev_priv->has_mob) | |
951 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
952 | (void) ttm_bo_device_release(&dev_priv->bdev); | |
953 | vmw_release_device_late(dev_priv); | |
ae2a1040 | 954 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c TH |
955 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
956 | drm_irq_uninstall(dev_priv->dev); | |
f2d12b8e | 957 | if (dev_priv->stealth) |
fb1d9738 | 958 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
959 | else |
960 | pci_release_regions(dev->pdev); | |
961 | ||
fb1d9738 | 962 | ttm_object_device_release(&dev_priv->tdev); |
b76ff5ea | 963 | memunmap(dev_priv->mmio_virt); |
d80efd5c TH |
964 | if (dev_priv->ctx.staged_bindings) |
965 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
fb1d9738 | 966 | vmw_ttm_global_release(dev_priv); |
c0951b79 TH |
967 | |
968 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
969 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
970 | |
971 | kfree(dev_priv); | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
976 | static void vmw_postclose(struct drm_device *dev, | |
977 | struct drm_file *file_priv) | |
978 | { | |
979 | struct vmw_fpriv *vmw_fp; | |
980 | ||
981 | vmw_fp = vmw_fpriv(file_priv); | |
c4249855 TH |
982 | |
983 | if (vmw_fp->locked_master) { | |
984 | struct vmw_master *vmaster = | |
985 | vmw_master(vmw_fp->locked_master); | |
986 | ||
987 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
988 | ttm_vt_unlock(&vmaster->lock); | |
fb1d9738 | 989 | drm_master_put(&vmw_fp->locked_master); |
c4249855 TH |
990 | } |
991 | ||
992 | ttm_object_file_release(&vmw_fp->tfile); | |
fb1d9738 JB |
993 | kfree(vmw_fp); |
994 | } | |
995 | ||
996 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
997 | { | |
998 | struct vmw_private *dev_priv = vmw_priv(dev); | |
999 | struct vmw_fpriv *vmw_fp; | |
1000 | int ret = -ENOMEM; | |
1001 | ||
1002 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
1003 | if (unlikely(vmw_fp == NULL)) | |
1004 | return ret; | |
1005 | ||
1006 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
1007 | if (unlikely(vmw_fp->tfile == NULL)) | |
1008 | goto out_no_tfile; | |
1009 | ||
1010 | file_priv->driver_priv = vmw_fp; | |
fb1d9738 JB |
1011 | |
1012 | return 0; | |
1013 | ||
1014 | out_no_tfile: | |
1015 | kfree(vmw_fp); | |
1016 | return ret; | |
1017 | } | |
1018 | ||
64190bde TH |
1019 | static struct vmw_master *vmw_master_check(struct drm_device *dev, |
1020 | struct drm_file *file_priv, | |
1021 | unsigned int flags) | |
1022 | { | |
1023 | int ret; | |
1024 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1025 | struct vmw_master *vmaster; | |
1026 | ||
1027 | if (file_priv->minor->type != DRM_MINOR_LEGACY || | |
1028 | !(flags & DRM_AUTH)) | |
1029 | return NULL; | |
1030 | ||
1031 | ret = mutex_lock_interruptible(&dev->master_mutex); | |
1032 | if (unlikely(ret != 0)) | |
1033 | return ERR_PTR(-ERESTARTSYS); | |
1034 | ||
7963e9db | 1035 | if (file_priv->is_master) { |
64190bde TH |
1036 | mutex_unlock(&dev->master_mutex); |
1037 | return NULL; | |
1038 | } | |
1039 | ||
1040 | /* | |
aa3469ce TH |
1041 | * Check if we were previously master, but now dropped. In that |
1042 | * case, allow at least render node functionality. | |
64190bde TH |
1043 | */ |
1044 | if (vmw_fp->locked_master) { | |
1045 | mutex_unlock(&dev->master_mutex); | |
aa3469ce TH |
1046 | |
1047 | if (flags & DRM_RENDER_ALLOW) | |
1048 | return NULL; | |
1049 | ||
64190bde TH |
1050 | DRM_ERROR("Dropped master trying to access ioctl that " |
1051 | "requires authentication.\n"); | |
1052 | return ERR_PTR(-EACCES); | |
1053 | } | |
1054 | mutex_unlock(&dev->master_mutex); | |
1055 | ||
64190bde TH |
1056 | /* |
1057 | * Take the TTM lock. Possibly sleep waiting for the authenticating | |
1058 | * master to become master again, or for a SIGTERM if the | |
1059 | * authenticating master exits. | |
1060 | */ | |
1061 | vmaster = vmw_master(file_priv->master); | |
1062 | ret = ttm_read_lock(&vmaster->lock, true); | |
1063 | if (unlikely(ret != 0)) | |
1064 | vmaster = ERR_PTR(ret); | |
1065 | ||
1066 | return vmaster; | |
1067 | } | |
1068 | ||
1069 | static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, | |
1070 | unsigned long arg, | |
1071 | long (*ioctl_func)(struct file *, unsigned int, | |
1072 | unsigned long)) | |
fb1d9738 JB |
1073 | { |
1074 | struct drm_file *file_priv = filp->private_data; | |
1075 | struct drm_device *dev = file_priv->minor->dev; | |
1076 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
64190bde TH |
1077 | struct vmw_master *vmaster; |
1078 | unsigned int flags; | |
1079 | long ret; | |
fb1d9738 JB |
1080 | |
1081 | /* | |
e1f78003 | 1082 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
1083 | */ |
1084 | ||
1085 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
1086 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
baa70943 | 1087 | const struct drm_ioctl_desc *ioctl = |
64190bde | 1088 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
fb1d9738 | 1089 | |
d80efd5c TH |
1090 | if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { |
1091 | ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); | |
1092 | if (unlikely(ret != 0)) | |
1093 | return ret; | |
1094 | ||
1095 | if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) | |
1096 | goto out_io_encoding; | |
1097 | ||
1098 | return (long) vmw_execbuf_ioctl(dev, arg, file_priv, | |
1099 | _IOC_SIZE(cmd)); | |
fb1d9738 | 1100 | } |
d80efd5c TH |
1101 | |
1102 | if (unlikely(ioctl->cmd != cmd)) | |
1103 | goto out_io_encoding; | |
1104 | ||
64190bde TH |
1105 | flags = ioctl->flags; |
1106 | } else if (!drm_ioctl_flags(nr, &flags)) | |
1107 | return -EINVAL; | |
1108 | ||
1109 | vmaster = vmw_master_check(dev, file_priv, flags); | |
55579cfe | 1110 | if (IS_ERR(vmaster)) { |
e338c4c2 TH |
1111 | ret = PTR_ERR(vmaster); |
1112 | ||
1113 | if (ret != -ERESTARTSYS) | |
1114 | DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", | |
1115 | nr, ret); | |
1116 | return ret; | |
fb1d9738 JB |
1117 | } |
1118 | ||
64190bde TH |
1119 | ret = ioctl_func(filp, cmd, arg); |
1120 | if (vmaster) | |
1121 | ttm_read_unlock(&vmaster->lock); | |
1122 | ||
1123 | return ret; | |
d80efd5c TH |
1124 | |
1125 | out_io_encoding: | |
1126 | DRM_ERROR("Invalid command format, ioctl %d\n", | |
1127 | nr - DRM_COMMAND_BASE); | |
1128 | ||
1129 | return -EINVAL; | |
64190bde TH |
1130 | } |
1131 | ||
1132 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
1133 | unsigned long arg) | |
1134 | { | |
1135 | return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); | |
fb1d9738 JB |
1136 | } |
1137 | ||
64190bde TH |
1138 | #ifdef CONFIG_COMPAT |
1139 | static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, | |
1140 | unsigned long arg) | |
1141 | { | |
1142 | return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); | |
1143 | } | |
1144 | #endif | |
1145 | ||
fb1d9738 JB |
1146 | static void vmw_lastclose(struct drm_device *dev) |
1147 | { | |
fb1d9738 JB |
1148 | } |
1149 | ||
1150 | static void vmw_master_init(struct vmw_master *vmaster) | |
1151 | { | |
1152 | ttm_lock_init(&vmaster->lock); | |
1153 | } | |
1154 | ||
1155 | static int vmw_master_create(struct drm_device *dev, | |
1156 | struct drm_master *master) | |
1157 | { | |
1158 | struct vmw_master *vmaster; | |
1159 | ||
fb1d9738 JB |
1160 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
1161 | if (unlikely(vmaster == NULL)) | |
1162 | return -ENOMEM; | |
1163 | ||
3a939a5e | 1164 | vmw_master_init(vmaster); |
fb1d9738 JB |
1165 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
1166 | master->driver_priv = vmaster; | |
1167 | ||
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | static void vmw_master_destroy(struct drm_device *dev, | |
1172 | struct drm_master *master) | |
1173 | { | |
1174 | struct vmw_master *vmaster = vmw_master(master); | |
1175 | ||
fb1d9738 JB |
1176 | master->driver_priv = NULL; |
1177 | kfree(vmaster); | |
1178 | } | |
1179 | ||
fb1d9738 JB |
1180 | static int vmw_master_set(struct drm_device *dev, |
1181 | struct drm_file *file_priv, | |
1182 | bool from_open) | |
1183 | { | |
1184 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1185 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1186 | struct vmw_master *active = dev_priv->active_master; | |
1187 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1188 | int ret = 0; | |
1189 | ||
fb1d9738 JB |
1190 | if (active) { |
1191 | BUG_ON(active != &dev_priv->fbdev_master); | |
1192 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
1193 | if (unlikely(ret != 0)) | |
153b3d5b | 1194 | return ret; |
fb1d9738 JB |
1195 | |
1196 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
fb1d9738 JB |
1197 | dev_priv->active_master = NULL; |
1198 | } | |
1199 | ||
1200 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
1201 | if (!from_open) { | |
1202 | ttm_vt_unlock(&vmaster->lock); | |
1203 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
1204 | drm_master_put(&vmw_fp->locked_master); | |
1205 | } | |
1206 | ||
1207 | dev_priv->active_master = vmaster; | |
5ea17348 | 1208 | drm_sysfs_hotplug_event(dev); |
fb1d9738 JB |
1209 | |
1210 | return 0; | |
fb1d9738 JB |
1211 | } |
1212 | ||
1213 | static void vmw_master_drop(struct drm_device *dev, | |
1214 | struct drm_file *file_priv, | |
1215 | bool from_release) | |
1216 | { | |
1217 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1218 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1219 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1220 | int ret; | |
1221 | ||
fb1d9738 JB |
1222 | /** |
1223 | * Make sure the master doesn't disappear while we have | |
1224 | * it locked. | |
1225 | */ | |
1226 | ||
1227 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
1228 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
8fbf9d92 | 1229 | vmw_kms_legacy_hotspot_clear(dev_priv); |
fb1d9738 JB |
1230 | if (unlikely((ret != 0))) { |
1231 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
1232 | drm_master_put(&vmw_fp->locked_master); | |
1233 | } | |
1234 | ||
c4249855 | 1235 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
fb1d9738 | 1236 | |
153b3d5b TH |
1237 | if (!dev_priv->enable_fb) |
1238 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 1239 | |
fb1d9738 JB |
1240 | dev_priv->active_master = &dev_priv->fbdev_master; |
1241 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
1242 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
1243 | ||
30c78bb8 TH |
1244 | if (dev_priv->enable_fb) |
1245 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
1246 | } |
1247 | ||
153b3d5b TH |
1248 | /** |
1249 | * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1250 | * | |
1251 | * @dev_priv: Pointer to device private struct. | |
1252 | * Needs the reservation sem to be held in non-exclusive mode. | |
1253 | */ | |
b9eb1a61 | 1254 | static void __vmw_svga_enable(struct vmw_private *dev_priv) |
153b3d5b TH |
1255 | { |
1256 | spin_lock(&dev_priv->svga_lock); | |
1257 | if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1258 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); | |
1259 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; | |
1260 | } | |
1261 | spin_unlock(&dev_priv->svga_lock); | |
1262 | } | |
1263 | ||
1264 | /** | |
1265 | * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1266 | * | |
1267 | * @dev_priv: Pointer to device private struct. | |
1268 | */ | |
1269 | void vmw_svga_enable(struct vmw_private *dev_priv) | |
1270 | { | |
1271 | ttm_read_lock(&dev_priv->reservation_sem, false); | |
1272 | __vmw_svga_enable(dev_priv); | |
1273 | ttm_read_unlock(&dev_priv->reservation_sem); | |
1274 | } | |
1275 | ||
1276 | /** | |
1277 | * __vmw_svga_disable - Disable SVGA mode and use of VRAM. | |
1278 | * | |
1279 | * @dev_priv: Pointer to device private struct. | |
1280 | * Needs the reservation sem to be held in exclusive mode. | |
1281 | * Will not empty VRAM. VRAM must be emptied by caller. | |
1282 | */ | |
b9eb1a61 | 1283 | static void __vmw_svga_disable(struct vmw_private *dev_priv) |
153b3d5b TH |
1284 | { |
1285 | spin_lock(&dev_priv->svga_lock); | |
1286 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1287 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
1288 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
8ce75f8a SY |
1289 | SVGA_REG_ENABLE_HIDE | |
1290 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1291 | } |
1292 | spin_unlock(&dev_priv->svga_lock); | |
1293 | } | |
1294 | ||
1295 | /** | |
1296 | * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo | |
1297 | * running. | |
1298 | * | |
1299 | * @dev_priv: Pointer to device private struct. | |
1300 | * Will empty VRAM. | |
1301 | */ | |
1302 | void vmw_svga_disable(struct vmw_private *dev_priv) | |
1303 | { | |
1304 | ttm_write_lock(&dev_priv->reservation_sem, false); | |
1305 | spin_lock(&dev_priv->svga_lock); | |
1306 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1307 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
153b3d5b TH |
1308 | spin_unlock(&dev_priv->svga_lock); |
1309 | if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) | |
1310 | DRM_ERROR("Failed evicting VRAM buffers.\n"); | |
8ce75f8a SY |
1311 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
1312 | SVGA_REG_ENABLE_HIDE | | |
1313 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1314 | } else |
1315 | spin_unlock(&dev_priv->svga_lock); | |
1316 | ttm_write_unlock(&dev_priv->reservation_sem); | |
1317 | } | |
fb1d9738 JB |
1318 | |
1319 | static void vmw_remove(struct pci_dev *pdev) | |
1320 | { | |
1321 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1322 | ||
fd3e4d6e | 1323 | pci_disable_device(pdev); |
fb1d9738 JB |
1324 | drm_put_dev(dev); |
1325 | } | |
1326 | ||
d9f36a00 TH |
1327 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1328 | void *ptr) | |
1329 | { | |
1330 | struct vmw_private *dev_priv = | |
1331 | container_of(nb, struct vmw_private, pm_nb); | |
d9f36a00 TH |
1332 | |
1333 | switch (val) { | |
1334 | case PM_HIBERNATION_PREPARE: | |
a278724a TH |
1335 | if (dev_priv->enable_fb) |
1336 | vmw_fb_off(dev_priv); | |
294adf7d | 1337 | ttm_suspend_lock(&dev_priv->reservation_sem); |
d9f36a00 | 1338 | |
153b3d5b | 1339 | /* |
d9f36a00 TH |
1340 | * This empties VRAM and unbinds all GMR bindings. |
1341 | * Buffer contents is moved to swappable memory. | |
1342 | */ | |
c0951b79 TH |
1343 | vmw_execbuf_release_pinned_bo(dev_priv); |
1344 | vmw_resource_evict_all(dev_priv); | |
153b3d5b | 1345 | vmw_release_device_early(dev_priv); |
d9f36a00 | 1346 | ttm_bo_swapout_all(&dev_priv->bdev); |
153b3d5b | 1347 | vmw_fence_fifo_down(dev_priv->fman); |
d9f36a00 TH |
1348 | break; |
1349 | case PM_POST_HIBERNATION: | |
094e0fa8 | 1350 | case PM_POST_RESTORE: |
153b3d5b | 1351 | vmw_fence_fifo_up(dev_priv->fman); |
294adf7d | 1352 | ttm_suspend_unlock(&dev_priv->reservation_sem); |
a278724a TH |
1353 | if (dev_priv->enable_fb) |
1354 | vmw_fb_on(dev_priv); | |
d9f36a00 TH |
1355 | break; |
1356 | case PM_RESTORE_PREPARE: | |
1357 | break; | |
d9f36a00 TH |
1358 | default: |
1359 | break; | |
1360 | } | |
1361 | return 0; | |
1362 | } | |
1363 | ||
7fbd721a | 1364 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1365 | { |
094e0fa8 TH |
1366 | struct drm_device *dev = pci_get_drvdata(pdev); |
1367 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1368 | ||
153b3d5b | 1369 | if (dev_priv->refuse_hibernation) |
094e0fa8 | 1370 | return -EBUSY; |
094e0fa8 | 1371 | |
d9f36a00 TH |
1372 | pci_save_state(pdev); |
1373 | pci_disable_device(pdev); | |
1374 | pci_set_power_state(pdev, PCI_D3hot); | |
1375 | return 0; | |
1376 | } | |
1377 | ||
7fbd721a | 1378 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1379 | { |
1380 | pci_set_power_state(pdev, PCI_D0); | |
1381 | pci_restore_state(pdev); | |
1382 | return pci_enable_device(pdev); | |
1383 | } | |
1384 | ||
7fbd721a TH |
1385 | static int vmw_pm_suspend(struct device *kdev) |
1386 | { | |
1387 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1388 | struct pm_message dummy; | |
1389 | ||
1390 | dummy.event = 0; | |
1391 | ||
1392 | return vmw_pci_suspend(pdev, dummy); | |
1393 | } | |
1394 | ||
1395 | static int vmw_pm_resume(struct device *kdev) | |
1396 | { | |
1397 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1398 | ||
1399 | return vmw_pci_resume(pdev); | |
1400 | } | |
1401 | ||
153b3d5b | 1402 | static int vmw_pm_freeze(struct device *kdev) |
7fbd721a TH |
1403 | { |
1404 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1405 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1406 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1407 | ||
7fbd721a TH |
1408 | dev_priv->suspended = true; |
1409 | if (dev_priv->enable_fb) | |
153b3d5b | 1410 | vmw_fifo_resource_dec(dev_priv); |
7fbd721a | 1411 | |
153b3d5b TH |
1412 | if (atomic_read(&dev_priv->num_fifo_resources) != 0) { |
1413 | DRM_ERROR("Can't hibernate while 3D resources are active.\n"); | |
7fbd721a | 1414 | if (dev_priv->enable_fb) |
153b3d5b TH |
1415 | vmw_fifo_resource_inc(dev_priv); |
1416 | WARN_ON(vmw_request_device_late(dev_priv)); | |
7fbd721a TH |
1417 | dev_priv->suspended = false; |
1418 | return -EBUSY; | |
1419 | } | |
1420 | ||
153b3d5b TH |
1421 | if (dev_priv->enable_fb) |
1422 | __vmw_svga_disable(dev_priv); | |
1423 | ||
1424 | vmw_release_device_late(dev_priv); | |
1425 | ||
7fbd721a TH |
1426 | return 0; |
1427 | } | |
1428 | ||
153b3d5b | 1429 | static int vmw_pm_restore(struct device *kdev) |
7fbd721a TH |
1430 | { |
1431 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1432 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1433 | struct vmw_private *dev_priv = vmw_priv(dev); | |
153b3d5b | 1434 | int ret; |
7fbd721a | 1435 | |
95e8f6a2 TH |
1436 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
1437 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
95e8f6a2 | 1438 | |
7fbd721a | 1439 | if (dev_priv->enable_fb) |
153b3d5b TH |
1440 | vmw_fifo_resource_inc(dev_priv); |
1441 | ||
1442 | ret = vmw_request_device(dev_priv); | |
1443 | if (ret) | |
1444 | return ret; | |
1445 | ||
1446 | if (dev_priv->enable_fb) | |
1447 | __vmw_svga_enable(dev_priv); | |
7fbd721a TH |
1448 | |
1449 | dev_priv->suspended = false; | |
153b3d5b TH |
1450 | |
1451 | return 0; | |
7fbd721a TH |
1452 | } |
1453 | ||
1454 | static const struct dev_pm_ops vmw_pm_ops = { | |
153b3d5b TH |
1455 | .freeze = vmw_pm_freeze, |
1456 | .thaw = vmw_pm_restore, | |
1457 | .restore = vmw_pm_restore, | |
7fbd721a TH |
1458 | .suspend = vmw_pm_suspend, |
1459 | .resume = vmw_pm_resume, | |
1460 | }; | |
1461 | ||
e08e96de AV |
1462 | static const struct file_operations vmwgfx_driver_fops = { |
1463 | .owner = THIS_MODULE, | |
1464 | .open = drm_open, | |
1465 | .release = drm_release, | |
1466 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1467 | .mmap = vmw_mmap, | |
1468 | .poll = vmw_fops_poll, | |
1469 | .read = vmw_fops_read, | |
e08e96de | 1470 | #if defined(CONFIG_COMPAT) |
64190bde | 1471 | .compat_ioctl = vmw_compat_ioctl, |
e08e96de AV |
1472 | #endif |
1473 | .llseek = noop_llseek, | |
1474 | }; | |
1475 | ||
fb1d9738 JB |
1476 | static struct drm_driver driver = { |
1477 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
03f80263 | 1478 | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, |
fb1d9738 JB |
1479 | .load = vmw_driver_load, |
1480 | .unload = vmw_driver_unload, | |
fb1d9738 JB |
1481 | .lastclose = vmw_lastclose, |
1482 | .irq_preinstall = vmw_irq_preinstall, | |
1483 | .irq_postinstall = vmw_irq_postinstall, | |
1484 | .irq_uninstall = vmw_irq_uninstall, | |
1485 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1486 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1487 | .enable_vblank = vmw_enable_vblank, |
1488 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 | 1489 | .ioctls = vmw_ioctls, |
f95aeb17 | 1490 | .num_ioctls = ARRAY_SIZE(vmw_ioctls), |
fb1d9738 JB |
1491 | .master_create = vmw_master_create, |
1492 | .master_destroy = vmw_master_destroy, | |
1493 | .master_set = vmw_master_set, | |
1494 | .master_drop = vmw_master_drop, | |
1495 | .open = vmw_driver_open, | |
1496 | .postclose = vmw_postclose, | |
915b4d11 | 1497 | .set_busid = drm_pci_set_busid, |
5e1782d2 DA |
1498 | |
1499 | .dumb_create = vmw_dumb_create, | |
1500 | .dumb_map_offset = vmw_dumb_map_offset, | |
1501 | .dumb_destroy = vmw_dumb_destroy, | |
1502 | ||
69977ff5 TH |
1503 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1504 | .prime_handle_to_fd = vmw_prime_handle_to_fd, | |
1505 | ||
e08e96de | 1506 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1507 | .name = VMWGFX_DRIVER_NAME, |
1508 | .desc = VMWGFX_DRIVER_DESC, | |
1509 | .date = VMWGFX_DRIVER_DATE, | |
1510 | .major = VMWGFX_DRIVER_MAJOR, | |
1511 | .minor = VMWGFX_DRIVER_MINOR, | |
1512 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1513 | }; | |
1514 | ||
8410ea3b DA |
1515 | static struct pci_driver vmw_pci_driver = { |
1516 | .name = VMWGFX_DRIVER_NAME, | |
1517 | .id_table = vmw_pci_id_list, | |
1518 | .probe = vmw_probe, | |
1519 | .remove = vmw_remove, | |
1520 | .driver = { | |
1521 | .pm = &vmw_pm_ops | |
1522 | } | |
1523 | }; | |
1524 | ||
fb1d9738 JB |
1525 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1526 | { | |
dcdb1674 | 1527 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1528 | } |
1529 | ||
1530 | static int __init vmwgfx_init(void) | |
1531 | { | |
1532 | int ret; | |
96c5d076 | 1533 | |
96c5d076 RC |
1534 | if (vgacon_text_force()) |
1535 | return -EINVAL; | |
96c5d076 | 1536 | |
8410ea3b | 1537 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1538 | if (ret) |
1539 | DRM_ERROR("Failed initializing DRM.\n"); | |
1540 | return ret; | |
1541 | } | |
1542 | ||
1543 | static void __exit vmwgfx_exit(void) | |
1544 | { | |
8410ea3b | 1545 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1546 | } |
1547 | ||
1548 | module_init(vmwgfx_init); | |
1549 | module_exit(vmwgfx_exit); | |
1550 | ||
1551 | MODULE_AUTHOR("VMware Inc. and others"); | |
1552 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1553 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1554 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1555 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1556 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1557 | "0"); |