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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
f9217913 | 3 | * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA |
fb1d9738 JB |
4 | * All Rights Reserved. |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
96c5d076 | 28 | #include <linux/console.h> |
fb1d9738 | 29 | |
760285e7 | 30 | #include <drm/drmP.h> |
fb1d9738 | 31 | #include "vmwgfx_drv.h" |
d80efd5c | 32 | #include "vmwgfx_binding.h" |
760285e7 DH |
33 | #include <drm/ttm/ttm_placement.h> |
34 | #include <drm/ttm/ttm_bo_driver.h> | |
35 | #include <drm/ttm/ttm_object.h> | |
36 | #include <drm/ttm/ttm_module.h> | |
d92d9851 | 37 | #include <linux/dma_remapping.h> |
fb1d9738 JB |
38 | |
39 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
40 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
41 | #define VMWGFX_CHIP_SVGAII 0 | |
42 | #define VMW_FB_RESERVATION 0 | |
43 | ||
eb4f923b JB |
44 | #define VMW_MIN_INITIAL_WIDTH 800 |
45 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
46 | ||
f9217913 SY |
47 | #ifndef VMWGFX_GIT_VERSION |
48 | #define VMWGFX_GIT_VERSION "Unknown" | |
49 | #endif | |
50 | ||
51 | #define VMWGFX_REPO "In Tree" | |
52 | ||
eb4f923b | 53 | |
fb1d9738 JB |
54 | /** |
55 | * Fully encoded drm commands. Might move to vmw_drm.h | |
56 | */ | |
57 | ||
58 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
59 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
60 | struct drm_vmw_getparam_arg) | |
61 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
62 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
63 | union drm_vmw_alloc_dmabuf_arg) | |
64 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
65 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
66 | struct drm_vmw_unref_dmabuf_arg) | |
67 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
68 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
69 | struct drm_vmw_cursor_bypass_arg) | |
70 | ||
71 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
72 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
73 | struct drm_vmw_control_stream_arg) | |
74 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
75 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
76 | struct drm_vmw_stream_arg) | |
77 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
78 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
79 | struct drm_vmw_stream_arg) | |
80 | ||
81 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
82 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
83 | struct drm_vmw_context_arg) | |
84 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
85 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
86 | struct drm_vmw_context_arg) | |
87 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
88 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
89 | union drm_vmw_surface_create_arg) | |
90 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
91 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
92 | struct drm_vmw_surface_arg) | |
93 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
94 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
95 | union drm_vmw_surface_reference_arg) | |
96 | #define DRM_IOCTL_VMW_EXECBUF \ | |
97 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
98 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
99 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
100 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
101 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
102 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
103 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
104 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
105 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
106 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
107 | struct drm_vmw_fence_signaled_arg) | |
108 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
109 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
110 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
111 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
112 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
113 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
114 | #define DRM_IOCTL_VMW_PRESENT \ |
115 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
116 | struct drm_vmw_present_arg) | |
117 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
118 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
119 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
120 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
121 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
122 | struct drm_vmw_update_layout_arg) | |
c74c162f TH |
123 | #define DRM_IOCTL_VMW_CREATE_SHADER \ |
124 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ | |
125 | struct drm_vmw_shader_create_arg) | |
126 | #define DRM_IOCTL_VMW_UNREF_SHADER \ | |
127 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ | |
128 | struct drm_vmw_shader_arg) | |
a97e2192 TH |
129 | #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ |
130 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ | |
131 | union drm_vmw_gb_surface_create_arg) | |
132 | #define DRM_IOCTL_VMW_GB_SURFACE_REF \ | |
133 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ | |
134 | union drm_vmw_gb_surface_reference_arg) | |
1d7a5cbf TH |
135 | #define DRM_IOCTL_VMW_SYNCCPU \ |
136 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ | |
137 | struct drm_vmw_synccpu_arg) | |
d80efd5c TH |
138 | #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ |
139 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ | |
140 | struct drm_vmw_context_arg) | |
fb1d9738 JB |
141 | |
142 | /** | |
143 | * The core DRM version of this macro doesn't account for | |
144 | * DRM_COMMAND_BASE. | |
145 | */ | |
146 | ||
147 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
7e7392a6 | 148 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} |
fb1d9738 JB |
149 | |
150 | /** | |
151 | * Ioctl definitions. | |
152 | */ | |
153 | ||
baa70943 | 154 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
1b2f1489 | 155 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
f8c47144 | 156 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 157 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
f8c47144 | 158 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 159 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
f8c47144 | 160 | DRM_RENDER_ALLOW), |
1b2f1489 | 161 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 | 162 | vmw_kms_cursor_bypass_ioctl, |
f8c47144 | 163 | DRM_MASTER | DRM_CONTROL_ALLOW), |
fb1d9738 | 164 | |
1b2f1489 | 165 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
f8c47144 | 166 | DRM_MASTER | DRM_CONTROL_ALLOW), |
1b2f1489 | 167 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
f8c47144 | 168 | DRM_MASTER | DRM_CONTROL_ALLOW), |
1b2f1489 | 169 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
f8c47144 | 170 | DRM_MASTER | DRM_CONTROL_ALLOW), |
fb1d9738 | 171 | |
1b2f1489 | 172 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
f8c47144 | 173 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 174 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
f8c47144 | 175 | DRM_RENDER_ALLOW), |
1b2f1489 | 176 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
f8c47144 | 177 | DRM_AUTH | DRM_RENDER_ALLOW), |
1b2f1489 | 178 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
f8c47144 | 179 | DRM_RENDER_ALLOW), |
1b2f1489 | 180 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
f8c47144 DV |
181 | DRM_AUTH | DRM_RENDER_ALLOW), |
182 | VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | | |
d80efd5c | 183 | DRM_RENDER_ALLOW), |
ae2a1040 | 184 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
f8c47144 | 185 | DRM_RENDER_ALLOW), |
ae2a1040 TH |
186 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, |
187 | vmw_fence_obj_signaled_ioctl, | |
f8c47144 | 188 | DRM_RENDER_ALLOW), |
ae2a1040 | 189 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, |
f8c47144 | 190 | DRM_RENDER_ALLOW), |
03f80263 | 191 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, |
f8c47144 | 192 | DRM_AUTH | DRM_RENDER_ALLOW), |
f63f6a59 | 193 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
f8c47144 | 194 | DRM_AUTH | DRM_RENDER_ALLOW), |
2fcd5a73 JB |
195 | |
196 | /* these allow direct access to the framebuffers mark as master only */ | |
197 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
f8c47144 | 198 | DRM_MASTER | DRM_AUTH), |
2fcd5a73 JB |
199 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, |
200 | vmw_present_readback_ioctl, | |
f8c47144 | 201 | DRM_MASTER | DRM_AUTH), |
31788ca8 TH |
202 | /* |
203 | * The permissions of the below ioctl are overridden in | |
204 | * vmw_generic_ioctl(). We require either | |
205 | * DRM_MASTER or capable(CAP_SYS_ADMIN). | |
206 | */ | |
cd2b89e7 TH |
207 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
208 | vmw_kms_update_layout_ioctl, | |
31788ca8 | 209 | DRM_RENDER_ALLOW), |
c74c162f TH |
210 | VMW_IOCTL_DEF(VMW_CREATE_SHADER, |
211 | vmw_shader_define_ioctl, | |
f8c47144 | 212 | DRM_AUTH | DRM_RENDER_ALLOW), |
c74c162f TH |
213 | VMW_IOCTL_DEF(VMW_UNREF_SHADER, |
214 | vmw_shader_destroy_ioctl, | |
f8c47144 | 215 | DRM_RENDER_ALLOW), |
a97e2192 TH |
216 | VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, |
217 | vmw_gb_surface_define_ioctl, | |
f8c47144 | 218 | DRM_AUTH | DRM_RENDER_ALLOW), |
a97e2192 TH |
219 | VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, |
220 | vmw_gb_surface_reference_ioctl, | |
f8c47144 | 221 | DRM_AUTH | DRM_RENDER_ALLOW), |
1d7a5cbf TH |
222 | VMW_IOCTL_DEF(VMW_SYNCCPU, |
223 | vmw_user_dmabuf_synccpu_ioctl, | |
f8c47144 | 224 | DRM_RENDER_ALLOW), |
d80efd5c TH |
225 | VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, |
226 | vmw_extended_context_define_ioctl, | |
f8c47144 | 227 | DRM_AUTH | DRM_RENDER_ALLOW), |
fb1d9738 JB |
228 | }; |
229 | ||
230 | static struct pci_device_id vmw_pci_id_list[] = { | |
231 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
232 | {0, 0, 0} | |
233 | }; | |
c4903429 | 234 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 235 | |
5d2afab9 | 236 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
d92d9851 TH |
237 | static int vmw_force_iommu; |
238 | static int vmw_restrict_iommu; | |
239 | static int vmw_force_coherent; | |
0d00c488 | 240 | static int vmw_restrict_dma_mask; |
04319d89 | 241 | static int vmw_assume_16bpp; |
fb1d9738 JB |
242 | |
243 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
244 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
245 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
246 | void *ptr); | |
fb1d9738 | 247 | |
30c78bb8 | 248 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
2d8e60e8 | 249 | module_param_named(enable_fbdev, enable_fbdev, int, S_IRUSR | S_IWUSR); |
d92d9851 | 250 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
2d8e60e8 | 251 | module_param_named(force_dma_api, vmw_force_iommu, int, S_IRUSR | S_IWUSR); |
d92d9851 | 252 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); |
2d8e60e8 | 253 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, S_IRUSR | S_IWUSR); |
d92d9851 | 254 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); |
2d8e60e8 | 255 | module_param_named(force_coherent, vmw_force_coherent, int, S_IRUSR | S_IWUSR); |
0d00c488 | 256 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
2d8e60e8 | 257 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, S_IRUSR | S_IWUSR); |
04319d89 SY |
258 | MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); |
259 | module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); | |
d92d9851 | 260 | |
30c78bb8 | 261 | |
fb1d9738 JB |
262 | static void vmw_print_capabilities(uint32_t capabilities) |
263 | { | |
264 | DRM_INFO("Capabilities:\n"); | |
265 | if (capabilities & SVGA_CAP_RECT_COPY) | |
266 | DRM_INFO(" Rect copy.\n"); | |
267 | if (capabilities & SVGA_CAP_CURSOR) | |
268 | DRM_INFO(" Cursor.\n"); | |
269 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
270 | DRM_INFO(" Cursor bypass.\n"); | |
271 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
272 | DRM_INFO(" Cursor bypass 2.\n"); | |
273 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
274 | DRM_INFO(" 8bit emulation.\n"); | |
275 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
276 | DRM_INFO(" Alpha cursor.\n"); | |
277 | if (capabilities & SVGA_CAP_3D) | |
278 | DRM_INFO(" 3D.\n"); | |
279 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
280 | DRM_INFO(" Extended Fifo.\n"); | |
281 | if (capabilities & SVGA_CAP_MULTIMON) | |
282 | DRM_INFO(" Multimon.\n"); | |
283 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
284 | DRM_INFO(" Pitchlock.\n"); | |
285 | if (capabilities & SVGA_CAP_IRQMASK) | |
286 | DRM_INFO(" Irq mask.\n"); | |
287 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
288 | DRM_INFO(" Display Topology.\n"); | |
289 | if (capabilities & SVGA_CAP_GMR) | |
290 | DRM_INFO(" GMR.\n"); | |
291 | if (capabilities & SVGA_CAP_TRACES) | |
292 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
293 | if (capabilities & SVGA_CAP_GMR2) |
294 | DRM_INFO(" GMR2.\n"); | |
295 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
296 | DRM_INFO(" Screen Object 2.\n"); | |
c1234db7 TH |
297 | if (capabilities & SVGA_CAP_COMMAND_BUFFERS) |
298 | DRM_INFO(" Command Buffers.\n"); | |
299 | if (capabilities & SVGA_CAP_CMD_BUFFERS_2) | |
300 | DRM_INFO(" Command Buffers 2.\n"); | |
301 | if (capabilities & SVGA_CAP_GBOBJECTS) | |
302 | DRM_INFO(" Guest Backed Resources.\n"); | |
8ce75f8a SY |
303 | if (capabilities & SVGA_CAP_DX) |
304 | DRM_INFO(" DX Features.\n"); | |
fb1d9738 JB |
305 | } |
306 | ||
e2fa3a76 | 307 | /** |
4b9e45e6 | 308 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result |
e2fa3a76 | 309 | * |
4b9e45e6 | 310 | * @dev_priv: A device private structure. |
e2fa3a76 | 311 | * |
4b9e45e6 TH |
312 | * This function creates a small buffer object that holds the query |
313 | * result for dummy queries emitted as query barriers. | |
314 | * The function will then map the first page and initialize a pending | |
315 | * occlusion query result structure, Finally it will unmap the buffer. | |
316 | * No interruptible waits are done within this function. | |
e2fa3a76 | 317 | * |
4b9e45e6 | 318 | * Returns an error if bo creation or initialization fails. |
e2fa3a76 | 319 | */ |
4b9e45e6 | 320 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) |
e2fa3a76 | 321 | { |
4b9e45e6 | 322 | int ret; |
459d0fa7 | 323 | struct vmw_dma_buffer *vbo; |
e2fa3a76 TH |
324 | struct ttm_bo_kmap_obj map; |
325 | volatile SVGA3dQueryResult *result; | |
326 | bool dummy; | |
e2fa3a76 | 327 | |
4b9e45e6 | 328 | /* |
459d0fa7 | 329 | * Create the vbo as pinned, so that a tryreserve will |
4b9e45e6 TH |
330 | * immediately succeed. This is because we're the only |
331 | * user of the bo currently. | |
332 | */ | |
459d0fa7 TH |
333 | vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); |
334 | if (!vbo) | |
335 | return -ENOMEM; | |
4b9e45e6 | 336 | |
459d0fa7 TH |
337 | ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, |
338 | &vmw_sys_ne_placement, false, | |
339 | &vmw_dmabuf_bo_free); | |
e2fa3a76 | 340 | if (unlikely(ret != 0)) |
4b9e45e6 TH |
341 | return ret; |
342 | ||
dfd5e50e | 343 | ret = ttm_bo_reserve(&vbo->base, false, true, NULL); |
4b9e45e6 | 344 | BUG_ON(ret != 0); |
459d0fa7 | 345 | vmw_bo_pin_reserved(vbo, true); |
e2fa3a76 | 346 | |
459d0fa7 | 347 | ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); |
e2fa3a76 TH |
348 | if (likely(ret == 0)) { |
349 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
350 | result->totalSize = sizeof(*result); | |
351 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
352 | result->result32 = 0xff; | |
353 | ttm_bo_kunmap(&map); | |
4b9e45e6 | 354 | } |
459d0fa7 TH |
355 | vmw_bo_pin_reserved(vbo, false); |
356 | ttm_bo_unreserve(&vbo->base); | |
e2fa3a76 | 357 | |
4b9e45e6 TH |
358 | if (unlikely(ret != 0)) { |
359 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
459d0fa7 | 360 | vmw_dmabuf_unreference(&vbo); |
4b9e45e6 | 361 | } else |
459d0fa7 | 362 | dev_priv->dummy_query_bo = vbo; |
e2fa3a76 | 363 | |
4b9e45e6 | 364 | return ret; |
e2fa3a76 TH |
365 | } |
366 | ||
153b3d5b TH |
367 | /** |
368 | * vmw_request_device_late - Perform late device setup | |
369 | * | |
370 | * @dev_priv: Pointer to device private. | |
371 | * | |
372 | * This function performs setup of otables and enables large command | |
373 | * buffer submission. These tasks are split out to a separate function | |
374 | * because it reverts vmw_release_device_early and is intended to be used | |
375 | * by an error path in the hibernation code. | |
376 | */ | |
377 | static int vmw_request_device_late(struct vmw_private *dev_priv) | |
fb1d9738 JB |
378 | { |
379 | int ret; | |
380 | ||
3530bdc3 TH |
381 | if (dev_priv->has_mob) { |
382 | ret = vmw_otables_setup(dev_priv); | |
383 | if (unlikely(ret != 0)) { | |
384 | DRM_ERROR("Unable to initialize " | |
385 | "guest Memory OBjects.\n"); | |
153b3d5b | 386 | return ret; |
3530bdc3 TH |
387 | } |
388 | } | |
153b3d5b | 389 | |
3eab3d9e TH |
390 | if (dev_priv->cman) { |
391 | ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, | |
392 | 256*4096, 2*4096); | |
393 | if (ret) { | |
394 | struct vmw_cmdbuf_man *man = dev_priv->cman; | |
395 | ||
396 | dev_priv->cman = NULL; | |
397 | vmw_cmdbuf_man_destroy(man); | |
398 | } | |
399 | } | |
400 | ||
153b3d5b TH |
401 | return 0; |
402 | } | |
403 | ||
fb1d9738 JB |
404 | static int vmw_request_device(struct vmw_private *dev_priv) |
405 | { | |
406 | int ret; | |
407 | ||
fb1d9738 JB |
408 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
409 | if (unlikely(ret != 0)) { | |
410 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
411 | return ret; | |
412 | } | |
ae2a1040 | 413 | vmw_fence_fifo_up(dev_priv->fman); |
3eab3d9e | 414 | dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); |
d80efd5c | 415 | if (IS_ERR(dev_priv->cman)) { |
3eab3d9e | 416 | dev_priv->cman = NULL; |
d80efd5c | 417 | dev_priv->has_dx = false; |
3530bdc3 | 418 | } |
153b3d5b TH |
419 | |
420 | ret = vmw_request_device_late(dev_priv); | |
421 | if (ret) | |
422 | goto out_no_mob; | |
423 | ||
e2fa3a76 TH |
424 | ret = vmw_dummy_query_bo_create(dev_priv); |
425 | if (unlikely(ret != 0)) | |
426 | goto out_no_query_bo; | |
fb1d9738 JB |
427 | |
428 | return 0; | |
e2fa3a76 TH |
429 | |
430 | out_no_query_bo: | |
3eab3d9e TH |
431 | if (dev_priv->cman) |
432 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
153b3d5b TH |
433 | if (dev_priv->has_mob) { |
434 | (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 435 | vmw_otables_takedown(dev_priv); |
153b3d5b | 436 | } |
3eab3d9e TH |
437 | if (dev_priv->cman) |
438 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
3530bdc3 | 439 | out_no_mob: |
e2fa3a76 TH |
440 | vmw_fence_fifo_down(dev_priv->fman); |
441 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
442 | return ret; | |
fb1d9738 JB |
443 | } |
444 | ||
153b3d5b TH |
445 | /** |
446 | * vmw_release_device_early - Early part of fifo takedown. | |
447 | * | |
448 | * @dev_priv: Pointer to device private struct. | |
449 | * | |
450 | * This is the first part of command submission takedown, to be called before | |
451 | * buffer management is taken down. | |
452 | */ | |
453 | static void vmw_release_device_early(struct vmw_private *dev_priv) | |
fb1d9738 | 454 | { |
e2fa3a76 TH |
455 | /* |
456 | * Previous destructions should've released | |
457 | * the pinned bo. | |
458 | */ | |
459 | ||
460 | BUG_ON(dev_priv->pinned_bo != NULL); | |
461 | ||
459d0fa7 | 462 | vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); |
3eab3d9e TH |
463 | if (dev_priv->cman) |
464 | vmw_cmdbuf_remove_pool(dev_priv->cman); | |
30c78bb8 | 465 | |
153b3d5b TH |
466 | if (dev_priv->has_mob) { |
467 | ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); | |
3530bdc3 | 468 | vmw_otables_takedown(dev_priv); |
30c78bb8 | 469 | } |
fb1d9738 JB |
470 | } |
471 | ||
05730b32 | 472 | /** |
153b3d5b TH |
473 | * vmw_release_device_late - Late part of fifo takedown. |
474 | * | |
475 | * @dev_priv: Pointer to device private struct. | |
476 | * | |
477 | * This is the last part of the command submission takedown, to be called when | |
478 | * command submission is no longer needed. It may wait on pending fences. | |
05730b32 | 479 | */ |
153b3d5b | 480 | static void vmw_release_device_late(struct vmw_private *dev_priv) |
30c78bb8 | 481 | { |
153b3d5b | 482 | vmw_fence_fifo_down(dev_priv->fman); |
3eab3d9e TH |
483 | if (dev_priv->cman) |
484 | vmw_cmdbuf_man_destroy(dev_priv->cman); | |
30c78bb8 | 485 | |
153b3d5b | 486 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
487 | } |
488 | ||
eb4f923b JB |
489 | /** |
490 | * Sets the initial_[width|height] fields on the given vmw_private. | |
491 | * | |
492 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
493 | * clamping the value to fb_max_[width|height] fields and the |
494 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
495 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
496 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
497 | */ | |
498 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
499 | { | |
500 | uint32_t width; | |
501 | uint32_t height; | |
502 | ||
503 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
504 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
505 | ||
506 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 507 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
508 | |
509 | if (width > dev_priv->fb_max_width || | |
510 | height > dev_priv->fb_max_height) { | |
511 | ||
512 | /* | |
513 | * This is a host error and shouldn't occur. | |
514 | */ | |
515 | ||
516 | width = VMW_MIN_INITIAL_WIDTH; | |
517 | height = VMW_MIN_INITIAL_HEIGHT; | |
518 | } | |
eb4f923b JB |
519 | |
520 | dev_priv->initial_width = width; | |
521 | dev_priv->initial_height = height; | |
522 | } | |
523 | ||
d92d9851 TH |
524 | /** |
525 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this | |
526 | * system. | |
527 | * | |
528 | * @dev_priv: Pointer to a struct vmw_private | |
529 | * | |
530 | * This functions tries to determine the IOMMU setup and what actions | |
531 | * need to be taken by the driver to make system pages visible to the | |
532 | * device. | |
533 | * If this function decides that DMA is not possible, it returns -EINVAL. | |
534 | * The driver may then try to disable features of the device that require | |
535 | * DMA. | |
536 | */ | |
537 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) | |
538 | { | |
d92d9851 TH |
539 | static const char *names[vmw_dma_map_max] = { |
540 | [vmw_dma_phys] = "Using physical TTM page addresses.", | |
541 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", | |
542 | [vmw_dma_map_populate] = "Keeping DMA mappings.", | |
543 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; | |
e14cd953 TH |
544 | #ifdef CONFIG_X86 |
545 | const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); | |
d92d9851 TH |
546 | |
547 | #ifdef CONFIG_INTEL_IOMMU | |
548 | if (intel_iommu_enabled) { | |
549 | dev_priv->map_mode = vmw_dma_map_populate; | |
550 | goto out_fixup; | |
551 | } | |
552 | #endif | |
553 | ||
554 | if (!(vmw_force_iommu || vmw_force_coherent)) { | |
555 | dev_priv->map_mode = vmw_dma_phys; | |
556 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); | |
557 | return 0; | |
558 | } | |
559 | ||
560 | dev_priv->map_mode = vmw_dma_map_populate; | |
561 | ||
562 | if (dma_ops->sync_single_for_cpu) | |
563 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
564 | #ifdef CONFIG_SWIOTLB | |
565 | if (swiotlb_nr_tbl() == 0) | |
566 | dev_priv->map_mode = vmw_dma_map_populate; | |
567 | #endif | |
568 | ||
21136946 | 569 | #ifdef CONFIG_INTEL_IOMMU |
d92d9851 | 570 | out_fixup: |
21136946 | 571 | #endif |
d92d9851 TH |
572 | if (dev_priv->map_mode == vmw_dma_map_populate && |
573 | vmw_restrict_iommu) | |
574 | dev_priv->map_mode = vmw_dma_map_bind; | |
575 | ||
576 | if (vmw_force_coherent) | |
577 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
578 | ||
579 | #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) | |
580 | /* | |
581 | * No coherent page pool | |
582 | */ | |
583 | if (dev_priv->map_mode == vmw_dma_alloc_coherent) | |
584 | return -EINVAL; | |
585 | #endif | |
586 | ||
e14cd953 TH |
587 | #else /* CONFIG_X86 */ |
588 | dev_priv->map_mode = vmw_dma_map_populate; | |
589 | #endif /* CONFIG_X86 */ | |
590 | ||
d92d9851 TH |
591 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
0d00c488 TH |
596 | /** |
597 | * vmw_dma_masks - set required page- and dma masks | |
598 | * | |
599 | * @dev: Pointer to struct drm-device | |
600 | * | |
601 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that | |
602 | * restriction also for 64-bit systems. | |
603 | */ | |
604 | #ifdef CONFIG_INTEL_IOMMU | |
605 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
606 | { | |
607 | struct drm_device *dev = dev_priv->dev; | |
608 | ||
609 | if (intel_iommu_enabled && | |
610 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { | |
611 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); | |
612 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | #else | |
617 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
618 | { | |
619 | return 0; | |
620 | } | |
621 | #endif | |
622 | ||
fb1d9738 JB |
623 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
624 | { | |
625 | struct vmw_private *dev_priv; | |
626 | int ret; | |
c188660f | 627 | uint32_t svga_id; |
c0951b79 | 628 | enum vmw_res_type i; |
d92d9851 | 629 | bool refuse_dma = false; |
f9217913 | 630 | char host_log[100] = {0}; |
fb1d9738 JB |
631 | |
632 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
633 | if (unlikely(dev_priv == NULL)) { | |
634 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
635 | return -ENOMEM; | |
636 | } | |
fb1d9738 | 637 | |
466e69b8 DA |
638 | pci_set_master(dev->pdev); |
639 | ||
fb1d9738 JB |
640 | dev_priv->dev = dev; |
641 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 642 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 | 643 | mutex_init(&dev_priv->cmdbuf_mutex); |
30c78bb8 | 644 | mutex_init(&dev_priv->release_mutex); |
173fb7d4 | 645 | mutex_init(&dev_priv->binding_mutex); |
93cd1681 | 646 | mutex_init(&dev_priv->global_kms_state_mutex); |
fb1d9738 | 647 | rwlock_init(&dev_priv->resource_lock); |
294adf7d | 648 | ttm_lock_init(&dev_priv->reservation_sem); |
496eb6fd TH |
649 | spin_lock_init(&dev_priv->hw_lock); |
650 | spin_lock_init(&dev_priv->waiter_lock); | |
651 | spin_lock_init(&dev_priv->cap_lock); | |
153b3d5b | 652 | spin_lock_init(&dev_priv->svga_lock); |
36cc79bc | 653 | spin_lock_init(&dev_priv->cursor_lock); |
c0951b79 TH |
654 | |
655 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
656 | idr_init(&dev_priv->res_idr[i]); | |
657 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
658 | } | |
659 | ||
fb1d9738 JB |
660 | mutex_init(&dev_priv->init_mutex); |
661 | init_waitqueue_head(&dev_priv->fence_queue); | |
662 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 663 | dev_priv->fence_queue_waiters = 0; |
d2e8851a | 664 | dev_priv->fifo_queue_waiters = 0; |
c0951b79 | 665 | |
5bb39e81 | 666 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
667 | |
668 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
669 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
670 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
671 | ||
04319d89 SY |
672 | dev_priv->assume_16bpp = !!vmw_assume_16bpp; |
673 | ||
30c78bb8 TH |
674 | dev_priv->enable_fb = enable_fbdev; |
675 | ||
c188660f PH |
676 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
677 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
678 | if (svga_id != SVGA_ID_2) { | |
679 | ret = -ENOSYS; | |
49625904 | 680 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
681 | goto out_err0; |
682 | } | |
683 | ||
fb1d9738 | 684 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
d92d9851 TH |
685 | ret = vmw_dma_select_mode(dev_priv); |
686 | if (unlikely(ret != 0)) { | |
687 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); | |
688 | refuse_dma = true; | |
689 | } | |
fb1d9738 | 690 | |
5bb39e81 TH |
691 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
692 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
693 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
694 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
695 | |
696 | vmw_get_initial_size(dev_priv); | |
697 | ||
0d00c488 | 698 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
699 | dev_priv->max_gmr_ids = |
700 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
fb17f189 TH |
701 | dev_priv->max_gmr_pages = |
702 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
703 | dev_priv->memory_size = | |
704 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
705 | dev_priv->memory_size -= dev_priv->vram_size; |
706 | } else { | |
707 | /* | |
708 | * An arbitrary limit of 512MiB on surface | |
709 | * memory. But all HWV8 hardware supports GMR2. | |
710 | */ | |
711 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 712 | } |
6da768aa | 713 | dev_priv->max_mob_pages = 0; |
857aea1c | 714 | dev_priv->max_mob_size = 0; |
6da768aa TH |
715 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { |
716 | uint64_t mem_size = | |
717 | vmw_read(dev_priv, | |
718 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); | |
719 | ||
7c20d213 SY |
720 | /* |
721 | * Workaround for low memory 2D VMs to compensate for the | |
722 | * allocation taken by fbdev | |
723 | */ | |
724 | if (!(dev_priv->capabilities & SVGA_CAP_3D)) | |
725 | mem_size *= 2; | |
726 | ||
6da768aa | 727 | dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; |
afb0e50f TH |
728 | dev_priv->prim_bb_mem = |
729 | vmw_read(dev_priv, | |
730 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); | |
857aea1c CL |
731 | dev_priv->max_mob_size = |
732 | vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); | |
35c05125 SY |
733 | dev_priv->stdu_max_width = |
734 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); | |
735 | dev_priv->stdu_max_height = | |
736 | vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); | |
737 | ||
738 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
739 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); | |
740 | dev_priv->texture_max_width = vmw_read(dev_priv, | |
741 | SVGA_REG_DEV_CAP); | |
742 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, | |
743 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); | |
744 | dev_priv->texture_max_height = vmw_read(dev_priv, | |
745 | SVGA_REG_DEV_CAP); | |
df45e9d4 TH |
746 | } else { |
747 | dev_priv->texture_max_width = 8192; | |
748 | dev_priv->texture_max_height = 8192; | |
afb0e50f | 749 | dev_priv->prim_bb_mem = dev_priv->vram_size; |
df45e9d4 TH |
750 | } |
751 | ||
35c05125 | 752 | vmw_print_capabilities(dev_priv->capabilities); |
fb1d9738 | 753 | |
0d00c488 | 754 | ret = vmw_dma_masks(dev_priv); |
496eb6fd | 755 | if (unlikely(ret != 0)) |
0d00c488 TH |
756 | goto out_err0; |
757 | ||
0d00c488 | 758 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
759 | DRM_INFO("Max GMR ids is %u\n", |
760 | (unsigned)dev_priv->max_gmr_ids); | |
fb17f189 TH |
761 | DRM_INFO("Max number of GMR pages is %u\n", |
762 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
763 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
764 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 765 | } |
bc2d6508 TH |
766 | DRM_INFO("Maximum display memory size is %u kiB\n", |
767 | dev_priv->prim_bb_mem / 1024); | |
fb1d9738 JB |
768 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
769 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
770 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
771 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
772 | ||
773 | ret = vmw_ttm_global_init(dev_priv); | |
774 | if (unlikely(ret != 0)) | |
775 | goto out_err0; | |
776 | ||
777 | ||
778 | vmw_master_init(&dev_priv->fbdev_master); | |
779 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
780 | dev_priv->active_master = &dev_priv->fbdev_master; | |
781 | ||
b76ff5ea TH |
782 | dev_priv->mmio_virt = memremap(dev_priv->mmio_start, |
783 | dev_priv->mmio_size, MEMREMAP_WB); | |
fb1d9738 JB |
784 | |
785 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
786 | ret = -ENOMEM; | |
787 | DRM_ERROR("Failed mapping MMIO.\n"); | |
788 | goto out_err3; | |
789 | } | |
790 | ||
d7e1958d JB |
791 | /* Need mmio memory to check for fifo pitchlock cap. */ |
792 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
793 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
794 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
795 | ret = -ENOSYS; | |
796 | DRM_ERROR("Hardware has no pitchlock\n"); | |
797 | goto out_err4; | |
798 | } | |
799 | ||
fb1d9738 | 800 | dev_priv->tdev = ttm_object_device_init |
69977ff5 | 801 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
fb1d9738 JB |
802 | |
803 | if (unlikely(dev_priv->tdev == NULL)) { | |
804 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
805 | ret = -ENOMEM; | |
806 | goto out_err4; | |
807 | } | |
808 | ||
809 | dev->dev_private = dev_priv; | |
810 | ||
fb1d9738 JB |
811 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
812 | dev_priv->stealth = (ret != 0); | |
813 | if (dev_priv->stealth) { | |
814 | /** | |
815 | * Request at least the mmio PCI resource. | |
816 | */ | |
817 | ||
818 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 819 | "Ignore above error if any.\n"); |
fb1d9738 JB |
820 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
821 | if (unlikely(ret != 0)) { | |
822 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
823 | goto out_no_device; | |
824 | } | |
fb1d9738 | 825 | } |
ae2a1040 | 826 | |
506ff75c | 827 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
bb0f1b5c | 828 | ret = drm_irq_install(dev, dev->pdev->irq); |
506ff75c TH |
829 | if (ret != 0) { |
830 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
831 | goto out_no_irq; | |
832 | } | |
833 | } | |
834 | ||
ae2a1040 | 835 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
14bbf20c WY |
836 | if (unlikely(dev_priv->fman == NULL)) { |
837 | ret = -ENOMEM; | |
ae2a1040 | 838 | goto out_no_fman; |
14bbf20c | 839 | } |
56d1c78d | 840 | |
153b3d5b TH |
841 | ret = ttm_bo_device_init(&dev_priv->bdev, |
842 | dev_priv->bo_global_ref.ref.object, | |
843 | &vmw_bo_driver, | |
844 | dev->anon_inode->i_mapping, | |
845 | VMWGFX_FILE_PAGE_OFFSET, | |
846 | false); | |
847 | if (unlikely(ret != 0)) { | |
848 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
849 | goto out_no_bdev; | |
850 | } | |
3458390b | 851 | |
153b3d5b TH |
852 | /* |
853 | * Enable VRAM, but initially don't use it until SVGA is enabled and | |
854 | * unhidden. | |
855 | */ | |
3458390b TH |
856 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, |
857 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
858 | if (unlikely(ret != 0)) { | |
859 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
860 | goto out_no_vram; | |
861 | } | |
153b3d5b | 862 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; |
3458390b TH |
863 | |
864 | dev_priv->has_gmr = true; | |
865 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || | |
866 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
867 | VMW_PL_GMR) != 0) { | |
868 | DRM_INFO("No GMR memory available. " | |
869 | "Graphics memory resources are very limited.\n"); | |
870 | dev_priv->has_gmr = false; | |
871 | } | |
872 | ||
873 | if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { | |
874 | dev_priv->has_mob = true; | |
875 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, | |
876 | VMW_PL_MOB) != 0) { | |
877 | DRM_INFO("No MOB memory available. " | |
878 | "3D will be disabled.\n"); | |
879 | dev_priv->has_mob = false; | |
880 | } | |
881 | } | |
882 | ||
d80efd5c TH |
883 | if (dev_priv->has_mob) { |
884 | spin_lock(&dev_priv->cap_lock); | |
885 | vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); | |
886 | dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); | |
887 | spin_unlock(&dev_priv->cap_lock); | |
888 | } | |
889 | ||
56d1c78d | 890 | |
7a1c2f6c TH |
891 | ret = vmw_kms_init(dev_priv); |
892 | if (unlikely(ret != 0)) | |
893 | goto out_no_kms; | |
f2d12b8e | 894 | vmw_overlay_init(dev_priv); |
56d1c78d | 895 | |
153b3d5b TH |
896 | ret = vmw_request_device(dev_priv); |
897 | if (ret) | |
898 | goto out_no_fifo; | |
899 | ||
d80efd5c TH |
900 | DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); |
901 | ||
f9217913 SY |
902 | snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", |
903 | VMWGFX_REPO, VMWGFX_GIT_VERSION); | |
904 | vmw_host_log(host_log); | |
905 | ||
906 | memset(host_log, 0, sizeof(host_log)); | |
907 | snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", | |
908 | VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, | |
909 | VMWGFX_DRIVER_PATCHLEVEL); | |
910 | vmw_host_log(host_log); | |
911 | ||
30c78bb8 | 912 | if (dev_priv->enable_fb) { |
153b3d5b TH |
913 | vmw_fifo_resource_inc(dev_priv); |
914 | vmw_svga_enable(dev_priv); | |
30c78bb8 | 915 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
916 | } |
917 | ||
d9f36a00 TH |
918 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
919 | register_pm_notifier(&dev_priv->pm_nb); | |
920 | ||
fb1d9738 JB |
921 | return 0; |
922 | ||
506ff75c | 923 | out_no_fifo: |
56d1c78d JB |
924 | vmw_overlay_close(dev_priv); |
925 | vmw_kms_close(dev_priv); | |
926 | out_no_kms: | |
3458390b TH |
927 | if (dev_priv->has_mob) |
928 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
929 | if (dev_priv->has_gmr) | |
930 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
931 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
932 | out_no_vram: | |
153b3d5b TH |
933 | (void)ttm_bo_device_release(&dev_priv->bdev); |
934 | out_no_bdev: | |
ae2a1040 TH |
935 | vmw_fence_manager_takedown(dev_priv->fman); |
936 | out_no_fman: | |
506ff75c TH |
937 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
938 | drm_irq_uninstall(dev_priv->dev); | |
939 | out_no_irq: | |
30c78bb8 TH |
940 | if (dev_priv->stealth) |
941 | pci_release_region(dev->pdev, 2); | |
942 | else | |
943 | pci_release_regions(dev->pdev); | |
fb1d9738 | 944 | out_no_device: |
fb1d9738 JB |
945 | ttm_object_device_release(&dev_priv->tdev); |
946 | out_err4: | |
b76ff5ea | 947 | memunmap(dev_priv->mmio_virt); |
fb1d9738 | 948 | out_err3: |
fb1d9738 JB |
949 | vmw_ttm_global_release(dev_priv); |
950 | out_err0: | |
c0951b79 TH |
951 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
952 | idr_destroy(&dev_priv->res_idr[i]); | |
953 | ||
d80efd5c TH |
954 | if (dev_priv->ctx.staged_bindings) |
955 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
fb1d9738 JB |
956 | kfree(dev_priv); |
957 | return ret; | |
958 | } | |
959 | ||
11b3c20b | 960 | static void vmw_driver_unload(struct drm_device *dev) |
fb1d9738 JB |
961 | { |
962 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 963 | enum vmw_res_type i; |
fb1d9738 | 964 | |
d9f36a00 TH |
965 | unregister_pm_notifier(&dev_priv->pm_nb); |
966 | ||
c0951b79 TH |
967 | if (dev_priv->ctx.res_ht_initialized) |
968 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
a3a1a667 | 969 | vfree(dev_priv->ctx.cmd_bounce); |
30c78bb8 | 970 | if (dev_priv->enable_fb) { |
05c95018 | 971 | vmw_fb_off(dev_priv); |
30c78bb8 | 972 | vmw_fb_close(dev_priv); |
153b3d5b TH |
973 | vmw_fifo_resource_dec(dev_priv); |
974 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 975 | } |
153b3d5b | 976 | |
f2d12b8e TH |
977 | vmw_kms_close(dev_priv); |
978 | vmw_overlay_close(dev_priv); | |
3458390b | 979 | |
3458390b TH |
980 | if (dev_priv->has_gmr) |
981 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
982 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
983 | ||
153b3d5b TH |
984 | vmw_release_device_early(dev_priv); |
985 | if (dev_priv->has_mob) | |
986 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); | |
987 | (void) ttm_bo_device_release(&dev_priv->bdev); | |
988 | vmw_release_device_late(dev_priv); | |
ae2a1040 | 989 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c TH |
990 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
991 | drm_irq_uninstall(dev_priv->dev); | |
f2d12b8e | 992 | if (dev_priv->stealth) |
fb1d9738 | 993 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
994 | else |
995 | pci_release_regions(dev->pdev); | |
996 | ||
fb1d9738 | 997 | ttm_object_device_release(&dev_priv->tdev); |
b76ff5ea | 998 | memunmap(dev_priv->mmio_virt); |
d80efd5c TH |
999 | if (dev_priv->ctx.staged_bindings) |
1000 | vmw_binding_state_free(dev_priv->ctx.staged_bindings); | |
fb1d9738 | 1001 | vmw_ttm_global_release(dev_priv); |
c0951b79 TH |
1002 | |
1003 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
1004 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
1005 | |
1006 | kfree(dev_priv); | |
fb1d9738 JB |
1007 | } |
1008 | ||
1009 | static void vmw_postclose(struct drm_device *dev, | |
1010 | struct drm_file *file_priv) | |
1011 | { | |
1012 | struct vmw_fpriv *vmw_fp; | |
1013 | ||
1014 | vmw_fp = vmw_fpriv(file_priv); | |
c4249855 TH |
1015 | |
1016 | if (vmw_fp->locked_master) { | |
1017 | struct vmw_master *vmaster = | |
1018 | vmw_master(vmw_fp->locked_master); | |
1019 | ||
1020 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
1021 | ttm_vt_unlock(&vmaster->lock); | |
fb1d9738 | 1022 | drm_master_put(&vmw_fp->locked_master); |
c4249855 TH |
1023 | } |
1024 | ||
1025 | ttm_object_file_release(&vmw_fp->tfile); | |
fb1d9738 JB |
1026 | kfree(vmw_fp); |
1027 | } | |
1028 | ||
1029 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
1030 | { | |
1031 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1032 | struct vmw_fpriv *vmw_fp; | |
1033 | int ret = -ENOMEM; | |
1034 | ||
1035 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
1036 | if (unlikely(vmw_fp == NULL)) | |
1037 | return ret; | |
1038 | ||
1039 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
1040 | if (unlikely(vmw_fp->tfile == NULL)) | |
1041 | goto out_no_tfile; | |
1042 | ||
1043 | file_priv->driver_priv = vmw_fp; | |
fb1d9738 JB |
1044 | |
1045 | return 0; | |
1046 | ||
1047 | out_no_tfile: | |
1048 | kfree(vmw_fp); | |
1049 | return ret; | |
1050 | } | |
1051 | ||
64190bde TH |
1052 | static struct vmw_master *vmw_master_check(struct drm_device *dev, |
1053 | struct drm_file *file_priv, | |
1054 | unsigned int flags) | |
1055 | { | |
1056 | int ret; | |
1057 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1058 | struct vmw_master *vmaster; | |
1059 | ||
0d02c4a1 | 1060 | if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) |
64190bde TH |
1061 | return NULL; |
1062 | ||
1063 | ret = mutex_lock_interruptible(&dev->master_mutex); | |
1064 | if (unlikely(ret != 0)) | |
1065 | return ERR_PTR(-ERESTARTSYS); | |
1066 | ||
b3ac9f25 | 1067 | if (drm_is_current_master(file_priv)) { |
64190bde TH |
1068 | mutex_unlock(&dev->master_mutex); |
1069 | return NULL; | |
1070 | } | |
1071 | ||
1072 | /* | |
aa3469ce TH |
1073 | * Check if we were previously master, but now dropped. In that |
1074 | * case, allow at least render node functionality. | |
64190bde TH |
1075 | */ |
1076 | if (vmw_fp->locked_master) { | |
1077 | mutex_unlock(&dev->master_mutex); | |
aa3469ce TH |
1078 | |
1079 | if (flags & DRM_RENDER_ALLOW) | |
1080 | return NULL; | |
1081 | ||
64190bde TH |
1082 | DRM_ERROR("Dropped master trying to access ioctl that " |
1083 | "requires authentication.\n"); | |
1084 | return ERR_PTR(-EACCES); | |
1085 | } | |
1086 | mutex_unlock(&dev->master_mutex); | |
1087 | ||
64190bde TH |
1088 | /* |
1089 | * Take the TTM lock. Possibly sleep waiting for the authenticating | |
1090 | * master to become master again, or for a SIGTERM if the | |
1091 | * authenticating master exits. | |
1092 | */ | |
1093 | vmaster = vmw_master(file_priv->master); | |
1094 | ret = ttm_read_lock(&vmaster->lock, true); | |
1095 | if (unlikely(ret != 0)) | |
1096 | vmaster = ERR_PTR(ret); | |
1097 | ||
1098 | return vmaster; | |
1099 | } | |
1100 | ||
1101 | static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, | |
1102 | unsigned long arg, | |
1103 | long (*ioctl_func)(struct file *, unsigned int, | |
1104 | unsigned long)) | |
fb1d9738 JB |
1105 | { |
1106 | struct drm_file *file_priv = filp->private_data; | |
1107 | struct drm_device *dev = file_priv->minor->dev; | |
1108 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
64190bde TH |
1109 | struct vmw_master *vmaster; |
1110 | unsigned int flags; | |
1111 | long ret; | |
fb1d9738 JB |
1112 | |
1113 | /* | |
e1f78003 | 1114 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
1115 | */ |
1116 | ||
1117 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
1118 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
baa70943 | 1119 | const struct drm_ioctl_desc *ioctl = |
64190bde | 1120 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
fb1d9738 | 1121 | |
d80efd5c TH |
1122 | if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { |
1123 | ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); | |
1124 | if (unlikely(ret != 0)) | |
1125 | return ret; | |
1126 | ||
1127 | if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) | |
1128 | goto out_io_encoding; | |
1129 | ||
1130 | return (long) vmw_execbuf_ioctl(dev, arg, file_priv, | |
1131 | _IOC_SIZE(cmd)); | |
31788ca8 TH |
1132 | } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { |
1133 | if (!drm_is_current_master(file_priv) && | |
1134 | !capable(CAP_SYS_ADMIN)) | |
1135 | return -EACCES; | |
fb1d9738 | 1136 | } |
d80efd5c TH |
1137 | |
1138 | if (unlikely(ioctl->cmd != cmd)) | |
1139 | goto out_io_encoding; | |
1140 | ||
64190bde TH |
1141 | flags = ioctl->flags; |
1142 | } else if (!drm_ioctl_flags(nr, &flags)) | |
1143 | return -EINVAL; | |
1144 | ||
1145 | vmaster = vmw_master_check(dev, file_priv, flags); | |
55579cfe | 1146 | if (IS_ERR(vmaster)) { |
e338c4c2 TH |
1147 | ret = PTR_ERR(vmaster); |
1148 | ||
1149 | if (ret != -ERESTARTSYS) | |
1150 | DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", | |
1151 | nr, ret); | |
1152 | return ret; | |
fb1d9738 JB |
1153 | } |
1154 | ||
64190bde TH |
1155 | ret = ioctl_func(filp, cmd, arg); |
1156 | if (vmaster) | |
1157 | ttm_read_unlock(&vmaster->lock); | |
1158 | ||
1159 | return ret; | |
d80efd5c TH |
1160 | |
1161 | out_io_encoding: | |
1162 | DRM_ERROR("Invalid command format, ioctl %d\n", | |
1163 | nr - DRM_COMMAND_BASE); | |
1164 | ||
1165 | return -EINVAL; | |
64190bde TH |
1166 | } |
1167 | ||
1168 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
1169 | unsigned long arg) | |
1170 | { | |
1171 | return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); | |
fb1d9738 JB |
1172 | } |
1173 | ||
64190bde TH |
1174 | #ifdef CONFIG_COMPAT |
1175 | static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, | |
1176 | unsigned long arg) | |
1177 | { | |
1178 | return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); | |
1179 | } | |
1180 | #endif | |
1181 | ||
fb1d9738 JB |
1182 | static void vmw_lastclose(struct drm_device *dev) |
1183 | { | |
fb1d9738 JB |
1184 | } |
1185 | ||
1186 | static void vmw_master_init(struct vmw_master *vmaster) | |
1187 | { | |
1188 | ttm_lock_init(&vmaster->lock); | |
1189 | } | |
1190 | ||
1191 | static int vmw_master_create(struct drm_device *dev, | |
1192 | struct drm_master *master) | |
1193 | { | |
1194 | struct vmw_master *vmaster; | |
1195 | ||
fb1d9738 JB |
1196 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
1197 | if (unlikely(vmaster == NULL)) | |
1198 | return -ENOMEM; | |
1199 | ||
3a939a5e | 1200 | vmw_master_init(vmaster); |
fb1d9738 JB |
1201 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
1202 | master->driver_priv = vmaster; | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static void vmw_master_destroy(struct drm_device *dev, | |
1208 | struct drm_master *master) | |
1209 | { | |
1210 | struct vmw_master *vmaster = vmw_master(master); | |
1211 | ||
fb1d9738 JB |
1212 | master->driver_priv = NULL; |
1213 | kfree(vmaster); | |
1214 | } | |
1215 | ||
fb1d9738 JB |
1216 | static int vmw_master_set(struct drm_device *dev, |
1217 | struct drm_file *file_priv, | |
1218 | bool from_open) | |
1219 | { | |
1220 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1221 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1222 | struct vmw_master *active = dev_priv->active_master; | |
1223 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1224 | int ret = 0; | |
1225 | ||
fb1d9738 JB |
1226 | if (active) { |
1227 | BUG_ON(active != &dev_priv->fbdev_master); | |
1228 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
1229 | if (unlikely(ret != 0)) | |
153b3d5b | 1230 | return ret; |
fb1d9738 JB |
1231 | |
1232 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
fb1d9738 JB |
1233 | dev_priv->active_master = NULL; |
1234 | } | |
1235 | ||
1236 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
1237 | if (!from_open) { | |
1238 | ttm_vt_unlock(&vmaster->lock); | |
1239 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
1240 | drm_master_put(&vmw_fp->locked_master); | |
1241 | } | |
1242 | ||
1243 | dev_priv->active_master = vmaster; | |
5ea17348 | 1244 | drm_sysfs_hotplug_event(dev); |
fb1d9738 JB |
1245 | |
1246 | return 0; | |
fb1d9738 JB |
1247 | } |
1248 | ||
1249 | static void vmw_master_drop(struct drm_device *dev, | |
d6ed682e | 1250 | struct drm_file *file_priv) |
fb1d9738 JB |
1251 | { |
1252 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1253 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1254 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1255 | int ret; | |
1256 | ||
fb1d9738 JB |
1257 | /** |
1258 | * Make sure the master doesn't disappear while we have | |
1259 | * it locked. | |
1260 | */ | |
1261 | ||
1262 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
1263 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
8fbf9d92 | 1264 | vmw_kms_legacy_hotspot_clear(dev_priv); |
fb1d9738 JB |
1265 | if (unlikely((ret != 0))) { |
1266 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
1267 | drm_master_put(&vmw_fp->locked_master); | |
1268 | } | |
1269 | ||
c4249855 | 1270 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
fb1d9738 | 1271 | |
153b3d5b TH |
1272 | if (!dev_priv->enable_fb) |
1273 | vmw_svga_disable(dev_priv); | |
30c78bb8 | 1274 | |
fb1d9738 JB |
1275 | dev_priv->active_master = &dev_priv->fbdev_master; |
1276 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
1277 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
1278 | ||
30c78bb8 TH |
1279 | if (dev_priv->enable_fb) |
1280 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
1281 | } |
1282 | ||
153b3d5b TH |
1283 | /** |
1284 | * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1285 | * | |
1286 | * @dev_priv: Pointer to device private struct. | |
1287 | * Needs the reservation sem to be held in non-exclusive mode. | |
1288 | */ | |
b9eb1a61 | 1289 | static void __vmw_svga_enable(struct vmw_private *dev_priv) |
153b3d5b TH |
1290 | { |
1291 | spin_lock(&dev_priv->svga_lock); | |
1292 | if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1293 | vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); | |
1294 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; | |
1295 | } | |
1296 | spin_unlock(&dev_priv->svga_lock); | |
1297 | } | |
1298 | ||
1299 | /** | |
1300 | * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. | |
1301 | * | |
1302 | * @dev_priv: Pointer to device private struct. | |
1303 | */ | |
1304 | void vmw_svga_enable(struct vmw_private *dev_priv) | |
1305 | { | |
f08c86c3 | 1306 | (void) ttm_read_lock(&dev_priv->reservation_sem, false); |
153b3d5b TH |
1307 | __vmw_svga_enable(dev_priv); |
1308 | ttm_read_unlock(&dev_priv->reservation_sem); | |
1309 | } | |
1310 | ||
1311 | /** | |
1312 | * __vmw_svga_disable - Disable SVGA mode and use of VRAM. | |
1313 | * | |
1314 | * @dev_priv: Pointer to device private struct. | |
1315 | * Needs the reservation sem to be held in exclusive mode. | |
1316 | * Will not empty VRAM. VRAM must be emptied by caller. | |
1317 | */ | |
b9eb1a61 | 1318 | static void __vmw_svga_disable(struct vmw_private *dev_priv) |
153b3d5b TH |
1319 | { |
1320 | spin_lock(&dev_priv->svga_lock); | |
1321 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1322 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
1323 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
8ce75f8a SY |
1324 | SVGA_REG_ENABLE_HIDE | |
1325 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1326 | } |
1327 | spin_unlock(&dev_priv->svga_lock); | |
1328 | } | |
1329 | ||
1330 | /** | |
1331 | * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo | |
1332 | * running. | |
1333 | * | |
1334 | * @dev_priv: Pointer to device private struct. | |
1335 | * Will empty VRAM. | |
1336 | */ | |
1337 | void vmw_svga_disable(struct vmw_private *dev_priv) | |
1338 | { | |
1339 | ttm_write_lock(&dev_priv->reservation_sem, false); | |
1340 | spin_lock(&dev_priv->svga_lock); | |
1341 | if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { | |
1342 | dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; | |
153b3d5b TH |
1343 | spin_unlock(&dev_priv->svga_lock); |
1344 | if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) | |
1345 | DRM_ERROR("Failed evicting VRAM buffers.\n"); | |
8ce75f8a SY |
1346 | vmw_write(dev_priv, SVGA_REG_ENABLE, |
1347 | SVGA_REG_ENABLE_HIDE | | |
1348 | SVGA_REG_ENABLE_ENABLE); | |
153b3d5b TH |
1349 | } else |
1350 | spin_unlock(&dev_priv->svga_lock); | |
1351 | ttm_write_unlock(&dev_priv->reservation_sem); | |
1352 | } | |
fb1d9738 JB |
1353 | |
1354 | static void vmw_remove(struct pci_dev *pdev) | |
1355 | { | |
1356 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1357 | ||
fd3e4d6e | 1358 | pci_disable_device(pdev); |
fb1d9738 JB |
1359 | drm_put_dev(dev); |
1360 | } | |
1361 | ||
d9f36a00 TH |
1362 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1363 | void *ptr) | |
1364 | { | |
1365 | struct vmw_private *dev_priv = | |
1366 | container_of(nb, struct vmw_private, pm_nb); | |
d9f36a00 TH |
1367 | |
1368 | switch (val) { | |
1369 | case PM_HIBERNATION_PREPARE: | |
a278724a TH |
1370 | if (dev_priv->enable_fb) |
1371 | vmw_fb_off(dev_priv); | |
294adf7d | 1372 | ttm_suspend_lock(&dev_priv->reservation_sem); |
d9f36a00 | 1373 | |
153b3d5b | 1374 | /* |
d9f36a00 TH |
1375 | * This empties VRAM and unbinds all GMR bindings. |
1376 | * Buffer contents is moved to swappable memory. | |
1377 | */ | |
c0951b79 TH |
1378 | vmw_execbuf_release_pinned_bo(dev_priv); |
1379 | vmw_resource_evict_all(dev_priv); | |
153b3d5b | 1380 | vmw_release_device_early(dev_priv); |
d9f36a00 | 1381 | ttm_bo_swapout_all(&dev_priv->bdev); |
153b3d5b | 1382 | vmw_fence_fifo_down(dev_priv->fman); |
d9f36a00 TH |
1383 | break; |
1384 | case PM_POST_HIBERNATION: | |
094e0fa8 | 1385 | case PM_POST_RESTORE: |
153b3d5b | 1386 | vmw_fence_fifo_up(dev_priv->fman); |
294adf7d | 1387 | ttm_suspend_unlock(&dev_priv->reservation_sem); |
a278724a TH |
1388 | if (dev_priv->enable_fb) |
1389 | vmw_fb_on(dev_priv); | |
d9f36a00 TH |
1390 | break; |
1391 | case PM_RESTORE_PREPARE: | |
1392 | break; | |
d9f36a00 TH |
1393 | default: |
1394 | break; | |
1395 | } | |
1396 | return 0; | |
1397 | } | |
1398 | ||
7fbd721a | 1399 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1400 | { |
094e0fa8 TH |
1401 | struct drm_device *dev = pci_get_drvdata(pdev); |
1402 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1403 | ||
153b3d5b | 1404 | if (dev_priv->refuse_hibernation) |
094e0fa8 | 1405 | return -EBUSY; |
094e0fa8 | 1406 | |
d9f36a00 TH |
1407 | pci_save_state(pdev); |
1408 | pci_disable_device(pdev); | |
1409 | pci_set_power_state(pdev, PCI_D3hot); | |
1410 | return 0; | |
1411 | } | |
1412 | ||
7fbd721a | 1413 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1414 | { |
1415 | pci_set_power_state(pdev, PCI_D0); | |
1416 | pci_restore_state(pdev); | |
1417 | return pci_enable_device(pdev); | |
1418 | } | |
1419 | ||
7fbd721a TH |
1420 | static int vmw_pm_suspend(struct device *kdev) |
1421 | { | |
1422 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1423 | struct pm_message dummy; | |
1424 | ||
1425 | dummy.event = 0; | |
1426 | ||
1427 | return vmw_pci_suspend(pdev, dummy); | |
1428 | } | |
1429 | ||
1430 | static int vmw_pm_resume(struct device *kdev) | |
1431 | { | |
1432 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1433 | ||
1434 | return vmw_pci_resume(pdev); | |
1435 | } | |
1436 | ||
153b3d5b | 1437 | static int vmw_pm_freeze(struct device *kdev) |
7fbd721a TH |
1438 | { |
1439 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1440 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1441 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1442 | ||
7fbd721a TH |
1443 | dev_priv->suspended = true; |
1444 | if (dev_priv->enable_fb) | |
153b3d5b | 1445 | vmw_fifo_resource_dec(dev_priv); |
7fbd721a | 1446 | |
153b3d5b TH |
1447 | if (atomic_read(&dev_priv->num_fifo_resources) != 0) { |
1448 | DRM_ERROR("Can't hibernate while 3D resources are active.\n"); | |
7fbd721a | 1449 | if (dev_priv->enable_fb) |
153b3d5b TH |
1450 | vmw_fifo_resource_inc(dev_priv); |
1451 | WARN_ON(vmw_request_device_late(dev_priv)); | |
7fbd721a TH |
1452 | dev_priv->suspended = false; |
1453 | return -EBUSY; | |
1454 | } | |
1455 | ||
153b3d5b TH |
1456 | if (dev_priv->enable_fb) |
1457 | __vmw_svga_disable(dev_priv); | |
1458 | ||
1459 | vmw_release_device_late(dev_priv); | |
1460 | ||
7fbd721a TH |
1461 | return 0; |
1462 | } | |
1463 | ||
153b3d5b | 1464 | static int vmw_pm_restore(struct device *kdev) |
7fbd721a TH |
1465 | { |
1466 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1467 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1468 | struct vmw_private *dev_priv = vmw_priv(dev); | |
153b3d5b | 1469 | int ret; |
7fbd721a | 1470 | |
95e8f6a2 TH |
1471 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); |
1472 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
95e8f6a2 | 1473 | |
7fbd721a | 1474 | if (dev_priv->enable_fb) |
153b3d5b TH |
1475 | vmw_fifo_resource_inc(dev_priv); |
1476 | ||
1477 | ret = vmw_request_device(dev_priv); | |
1478 | if (ret) | |
1479 | return ret; | |
1480 | ||
1481 | if (dev_priv->enable_fb) | |
1482 | __vmw_svga_enable(dev_priv); | |
7fbd721a TH |
1483 | |
1484 | dev_priv->suspended = false; | |
153b3d5b TH |
1485 | |
1486 | return 0; | |
7fbd721a TH |
1487 | } |
1488 | ||
1489 | static const struct dev_pm_ops vmw_pm_ops = { | |
153b3d5b TH |
1490 | .freeze = vmw_pm_freeze, |
1491 | .thaw = vmw_pm_restore, | |
1492 | .restore = vmw_pm_restore, | |
7fbd721a TH |
1493 | .suspend = vmw_pm_suspend, |
1494 | .resume = vmw_pm_resume, | |
1495 | }; | |
1496 | ||
e08e96de AV |
1497 | static const struct file_operations vmwgfx_driver_fops = { |
1498 | .owner = THIS_MODULE, | |
1499 | .open = drm_open, | |
1500 | .release = drm_release, | |
1501 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1502 | .mmap = vmw_mmap, | |
1503 | .poll = vmw_fops_poll, | |
1504 | .read = vmw_fops_read, | |
e08e96de | 1505 | #if defined(CONFIG_COMPAT) |
64190bde | 1506 | .compat_ioctl = vmw_compat_ioctl, |
e08e96de AV |
1507 | #endif |
1508 | .llseek = noop_llseek, | |
1509 | }; | |
1510 | ||
fb1d9738 JB |
1511 | static struct drm_driver driver = { |
1512 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
03f80263 | 1513 | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, |
fb1d9738 JB |
1514 | .load = vmw_driver_load, |
1515 | .unload = vmw_driver_unload, | |
fb1d9738 JB |
1516 | .lastclose = vmw_lastclose, |
1517 | .irq_preinstall = vmw_irq_preinstall, | |
1518 | .irq_postinstall = vmw_irq_postinstall, | |
1519 | .irq_uninstall = vmw_irq_uninstall, | |
1520 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1521 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1522 | .enable_vblank = vmw_enable_vblank, |
1523 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 | 1524 | .ioctls = vmw_ioctls, |
f95aeb17 | 1525 | .num_ioctls = ARRAY_SIZE(vmw_ioctls), |
fb1d9738 JB |
1526 | .master_create = vmw_master_create, |
1527 | .master_destroy = vmw_master_destroy, | |
1528 | .master_set = vmw_master_set, | |
1529 | .master_drop = vmw_master_drop, | |
1530 | .open = vmw_driver_open, | |
1531 | .postclose = vmw_postclose, | |
915b4d11 | 1532 | .set_busid = drm_pci_set_busid, |
5e1782d2 DA |
1533 | |
1534 | .dumb_create = vmw_dumb_create, | |
1535 | .dumb_map_offset = vmw_dumb_map_offset, | |
1536 | .dumb_destroy = vmw_dumb_destroy, | |
1537 | ||
69977ff5 TH |
1538 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1539 | .prime_handle_to_fd = vmw_prime_handle_to_fd, | |
1540 | ||
e08e96de | 1541 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1542 | .name = VMWGFX_DRIVER_NAME, |
1543 | .desc = VMWGFX_DRIVER_DESC, | |
1544 | .date = VMWGFX_DRIVER_DATE, | |
1545 | .major = VMWGFX_DRIVER_MAJOR, | |
1546 | .minor = VMWGFX_DRIVER_MINOR, | |
1547 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1548 | }; | |
1549 | ||
8410ea3b DA |
1550 | static struct pci_driver vmw_pci_driver = { |
1551 | .name = VMWGFX_DRIVER_NAME, | |
1552 | .id_table = vmw_pci_id_list, | |
1553 | .probe = vmw_probe, | |
1554 | .remove = vmw_remove, | |
1555 | .driver = { | |
1556 | .pm = &vmw_pm_ops | |
1557 | } | |
1558 | }; | |
1559 | ||
fb1d9738 JB |
1560 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1561 | { | |
dcdb1674 | 1562 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1563 | } |
1564 | ||
1565 | static int __init vmwgfx_init(void) | |
1566 | { | |
1567 | int ret; | |
96c5d076 | 1568 | |
96c5d076 RC |
1569 | if (vgacon_text_force()) |
1570 | return -EINVAL; | |
96c5d076 | 1571 | |
8410ea3b | 1572 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1573 | if (ret) |
1574 | DRM_ERROR("Failed initializing DRM.\n"); | |
1575 | return ret; | |
1576 | } | |
1577 | ||
1578 | static void __exit vmwgfx_exit(void) | |
1579 | { | |
8410ea3b | 1580 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1581 | } |
1582 | ||
1583 | module_init(vmwgfx_init); | |
1584 | module_exit(vmwgfx_exit); | |
1585 | ||
1586 | MODULE_AUTHOR("VMware Inc. and others"); | |
1587 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1588 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1589 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1590 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1591 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1592 | "0"); |