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fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
e0cd3608 | 27 | #include <linux/module.h> |
fb1d9738 | 28 | |
760285e7 | 29 | #include <drm/drmP.h> |
fb1d9738 | 30 | #include "vmwgfx_drv.h" |
760285e7 DH |
31 | #include <drm/ttm/ttm_placement.h> |
32 | #include <drm/ttm/ttm_bo_driver.h> | |
33 | #include <drm/ttm/ttm_object.h> | |
34 | #include <drm/ttm/ttm_module.h> | |
d92d9851 | 35 | #include <linux/dma_remapping.h> |
fb1d9738 JB |
36 | |
37 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
38 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
39 | #define VMWGFX_CHIP_SVGAII 0 | |
40 | #define VMW_FB_RESERVATION 0 | |
41 | ||
eb4f923b JB |
42 | #define VMW_MIN_INITIAL_WIDTH 800 |
43 | #define VMW_MIN_INITIAL_HEIGHT 600 | |
44 | ||
45 | ||
fb1d9738 JB |
46 | /** |
47 | * Fully encoded drm commands. Might move to vmw_drm.h | |
48 | */ | |
49 | ||
50 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
51 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
52 | struct drm_vmw_getparam_arg) | |
53 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
54 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
55 | union drm_vmw_alloc_dmabuf_arg) | |
56 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
57 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
58 | struct drm_vmw_unref_dmabuf_arg) | |
59 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
60 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
61 | struct drm_vmw_cursor_bypass_arg) | |
62 | ||
63 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
65 | struct drm_vmw_control_stream_arg) | |
66 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
67 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
68 | struct drm_vmw_stream_arg) | |
69 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
70 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
71 | struct drm_vmw_stream_arg) | |
72 | ||
73 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
74 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
75 | struct drm_vmw_context_arg) | |
76 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
78 | struct drm_vmw_context_arg) | |
79 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
81 | union drm_vmw_surface_create_arg) | |
82 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
84 | struct drm_vmw_surface_arg) | |
85 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
86 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
87 | union drm_vmw_surface_reference_arg) | |
88 | #define DRM_IOCTL_VMW_EXECBUF \ | |
89 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
90 | struct drm_vmw_execbuf_arg) | |
ae2a1040 TH |
91 | #define DRM_IOCTL_VMW_GET_3D_CAP \ |
92 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ | |
93 | struct drm_vmw_get_3d_cap_arg) | |
fb1d9738 JB |
94 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
95 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
96 | struct drm_vmw_fence_wait_arg) | |
ae2a1040 TH |
97 | #define DRM_IOCTL_VMW_FENCE_SIGNALED \ |
98 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ | |
99 | struct drm_vmw_fence_signaled_arg) | |
100 | #define DRM_IOCTL_VMW_FENCE_UNREF \ | |
101 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ | |
102 | struct drm_vmw_fence_arg) | |
57c5ee79 TH |
103 | #define DRM_IOCTL_VMW_FENCE_EVENT \ |
104 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ | |
105 | struct drm_vmw_fence_event_arg) | |
2fcd5a73 JB |
106 | #define DRM_IOCTL_VMW_PRESENT \ |
107 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ | |
108 | struct drm_vmw_present_arg) | |
109 | #define DRM_IOCTL_VMW_PRESENT_READBACK \ | |
110 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ | |
111 | struct drm_vmw_present_readback_arg) | |
cd2b89e7 TH |
112 | #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ |
113 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ | |
114 | struct drm_vmw_update_layout_arg) | |
fb1d9738 JB |
115 | |
116 | /** | |
117 | * The core DRM version of this macro doesn't account for | |
118 | * DRM_COMMAND_BASE. | |
119 | */ | |
120 | ||
121 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 122 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
123 | |
124 | /** | |
125 | * Ioctl definitions. | |
126 | */ | |
127 | ||
baa70943 | 128 | static const struct drm_ioctl_desc vmw_ioctls[] = { |
1b2f1489 | 129 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 130 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 131 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 132 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 133 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 134 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 135 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
136 | vmw_kms_cursor_bypass_ioctl, |
137 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 138 | |
1b2f1489 | 139 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 140 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 141 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 142 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 143 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 144 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 145 | |
1b2f1489 | 146 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 147 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 148 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 149 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 150 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 151 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 152 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 153 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 154 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 155 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 156 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 157 | DRM_AUTH | DRM_UNLOCKED), |
ae2a1040 TH |
158 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, |
159 | DRM_AUTH | DRM_UNLOCKED), | |
160 | VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, | |
161 | vmw_fence_obj_signaled_ioctl, | |
162 | DRM_AUTH | DRM_UNLOCKED), | |
163 | VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, | |
d8bd19d2 | 164 | DRM_AUTH | DRM_UNLOCKED), |
57c5ee79 TH |
165 | VMW_IOCTL_DEF(VMW_FENCE_EVENT, |
166 | vmw_fence_event_ioctl, | |
167 | DRM_AUTH | DRM_UNLOCKED), | |
f63f6a59 TH |
168 | VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, |
169 | DRM_AUTH | DRM_UNLOCKED), | |
2fcd5a73 JB |
170 | |
171 | /* these allow direct access to the framebuffers mark as master only */ | |
172 | VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, | |
173 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
174 | VMW_IOCTL_DEF(VMW_PRESENT_READBACK, | |
175 | vmw_present_readback_ioctl, | |
176 | DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), | |
cd2b89e7 TH |
177 | VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, |
178 | vmw_kms_update_layout_ioctl, | |
179 | DRM_MASTER | DRM_UNLOCKED), | |
fb1d9738 JB |
180 | }; |
181 | ||
182 | static struct pci_device_id vmw_pci_id_list[] = { | |
183 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
184 | {0, 0, 0} | |
185 | }; | |
c4903429 | 186 | MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); |
fb1d9738 | 187 | |
5d2afab9 | 188 | static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); |
d92d9851 TH |
189 | static int vmw_force_iommu; |
190 | static int vmw_restrict_iommu; | |
191 | static int vmw_force_coherent; | |
0d00c488 | 192 | static int vmw_restrict_dma_mask; |
fb1d9738 JB |
193 | |
194 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
195 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
196 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
197 | void *ptr); | |
fb1d9738 | 198 | |
30c78bb8 TH |
199 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
200 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
d92d9851 TH |
201 | MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); |
202 | module_param_named(force_dma_api, vmw_force_iommu, int, 0600); | |
203 | MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); | |
204 | module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); | |
205 | MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); | |
206 | module_param_named(force_coherent, vmw_force_coherent, int, 0600); | |
0d00c488 TH |
207 | MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); |
208 | module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); | |
d92d9851 | 209 | |
30c78bb8 | 210 | |
fb1d9738 JB |
211 | static void vmw_print_capabilities(uint32_t capabilities) |
212 | { | |
213 | DRM_INFO("Capabilities:\n"); | |
214 | if (capabilities & SVGA_CAP_RECT_COPY) | |
215 | DRM_INFO(" Rect copy.\n"); | |
216 | if (capabilities & SVGA_CAP_CURSOR) | |
217 | DRM_INFO(" Cursor.\n"); | |
218 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
219 | DRM_INFO(" Cursor bypass.\n"); | |
220 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
221 | DRM_INFO(" Cursor bypass 2.\n"); | |
222 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
223 | DRM_INFO(" 8bit emulation.\n"); | |
224 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
225 | DRM_INFO(" Alpha cursor.\n"); | |
226 | if (capabilities & SVGA_CAP_3D) | |
227 | DRM_INFO(" 3D.\n"); | |
228 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
229 | DRM_INFO(" Extended Fifo.\n"); | |
230 | if (capabilities & SVGA_CAP_MULTIMON) | |
231 | DRM_INFO(" Multimon.\n"); | |
232 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
233 | DRM_INFO(" Pitchlock.\n"); | |
234 | if (capabilities & SVGA_CAP_IRQMASK) | |
235 | DRM_INFO(" Irq mask.\n"); | |
236 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
237 | DRM_INFO(" Display Topology.\n"); | |
238 | if (capabilities & SVGA_CAP_GMR) | |
239 | DRM_INFO(" GMR.\n"); | |
240 | if (capabilities & SVGA_CAP_TRACES) | |
241 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
242 | if (capabilities & SVGA_CAP_GMR2) |
243 | DRM_INFO(" GMR2.\n"); | |
244 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
245 | DRM_INFO(" Screen Object 2.\n"); | |
fb1d9738 JB |
246 | } |
247 | ||
e2fa3a76 TH |
248 | |
249 | /** | |
250 | * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at | |
251 | * the start of a buffer object. | |
252 | * | |
253 | * @dev_priv: The device private structure. | |
254 | * | |
255 | * This function will idle the buffer using an uninterruptible wait, then | |
256 | * map the first page and initialize a pending occlusion query result structure, | |
257 | * Finally it will unmap the buffer. | |
258 | * | |
259 | * TODO: Since we're only mapping a single page, we should optimize the map | |
260 | * to use kmap_atomic / iomap_atomic. | |
261 | */ | |
262 | static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv) | |
263 | { | |
264 | struct ttm_bo_kmap_obj map; | |
265 | volatile SVGA3dQueryResult *result; | |
266 | bool dummy; | |
267 | int ret; | |
268 | struct ttm_bo_device *bdev = &dev_priv->bdev; | |
269 | struct ttm_buffer_object *bo = dev_priv->dummy_query_bo; | |
270 | ||
271 | ttm_bo_reserve(bo, false, false, false, 0); | |
272 | spin_lock(&bdev->fence_lock); | |
1717c0e2 | 273 | ret = ttm_bo_wait(bo, false, false, false); |
e2fa3a76 TH |
274 | spin_unlock(&bdev->fence_lock); |
275 | if (unlikely(ret != 0)) | |
276 | (void) vmw_fallback_wait(dev_priv, false, true, 0, false, | |
277 | 10*HZ); | |
278 | ||
279 | ret = ttm_bo_kmap(bo, 0, 1, &map); | |
280 | if (likely(ret == 0)) { | |
281 | result = ttm_kmap_obj_virtual(&map, &dummy); | |
282 | result->totalSize = sizeof(*result); | |
283 | result->state = SVGA3D_QUERYSTATE_PENDING; | |
284 | result->result32 = 0xff; | |
285 | ttm_bo_kunmap(&map); | |
286 | } else | |
287 | DRM_ERROR("Dummy query buffer map failed.\n"); | |
288 | ttm_bo_unreserve(bo); | |
289 | } | |
290 | ||
291 | ||
292 | /** | |
293 | * vmw_dummy_query_bo_create - create a bo to hold a dummy query result | |
294 | * | |
295 | * @dev_priv: A device private structure. | |
296 | * | |
297 | * This function creates a small buffer object that holds the query | |
298 | * result for dummy queries emitted as query barriers. | |
299 | * No interruptible waits are done within this function. | |
300 | * | |
301 | * Returns an error if bo creation fails. | |
302 | */ | |
303 | static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) | |
304 | { | |
305 | return ttm_bo_create(&dev_priv->bdev, | |
306 | PAGE_SIZE, | |
307 | ttm_bo_type_device, | |
308 | &vmw_vram_sys_placement, | |
0b91c4a1 | 309 | 0, false, NULL, |
e2fa3a76 TH |
310 | &dev_priv->dummy_query_bo); |
311 | } | |
312 | ||
313 | ||
fb1d9738 JB |
314 | static int vmw_request_device(struct vmw_private *dev_priv) |
315 | { | |
316 | int ret; | |
317 | ||
fb1d9738 JB |
318 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
319 | if (unlikely(ret != 0)) { | |
320 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
321 | return ret; | |
322 | } | |
ae2a1040 | 323 | vmw_fence_fifo_up(dev_priv->fman); |
e2fa3a76 TH |
324 | ret = vmw_dummy_query_bo_create(dev_priv); |
325 | if (unlikely(ret != 0)) | |
326 | goto out_no_query_bo; | |
327 | vmw_dummy_query_bo_prepare(dev_priv); | |
fb1d9738 JB |
328 | |
329 | return 0; | |
e2fa3a76 TH |
330 | |
331 | out_no_query_bo: | |
332 | vmw_fence_fifo_down(dev_priv->fman); | |
333 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
334 | return ret; | |
fb1d9738 JB |
335 | } |
336 | ||
337 | static void vmw_release_device(struct vmw_private *dev_priv) | |
338 | { | |
e2fa3a76 TH |
339 | /* |
340 | * Previous destructions should've released | |
341 | * the pinned bo. | |
342 | */ | |
343 | ||
344 | BUG_ON(dev_priv->pinned_bo != NULL); | |
345 | ||
346 | ttm_bo_unref(&dev_priv->dummy_query_bo); | |
ae2a1040 | 347 | vmw_fence_fifo_down(dev_priv->fman); |
fb1d9738 | 348 | vmw_fifo_release(dev_priv, &dev_priv->fifo); |
30c78bb8 TH |
349 | } |
350 | ||
05730b32 TH |
351 | /** |
352 | * Increase the 3d resource refcount. | |
353 | * If the count was prevously zero, initialize the fifo, switching to svga | |
354 | * mode. Note that the master holds a ref as well, and may request an | |
355 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
356 | */ | |
357 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
358 | bool unhide_svga) | |
30c78bb8 TH |
359 | { |
360 | int ret = 0; | |
361 | ||
362 | mutex_lock(&dev_priv->release_mutex); | |
363 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
364 | ret = vmw_request_device(dev_priv); | |
365 | if (unlikely(ret != 0)) | |
366 | --dev_priv->num_3d_resources; | |
05730b32 TH |
367 | } else if (unhide_svga) { |
368 | mutex_lock(&dev_priv->hw_mutex); | |
369 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
370 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
371 | ~SVGA_REG_ENABLE_HIDE); | |
372 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 373 | } |
05730b32 | 374 | |
30c78bb8 TH |
375 | mutex_unlock(&dev_priv->release_mutex); |
376 | return ret; | |
fb1d9738 JB |
377 | } |
378 | ||
05730b32 TH |
379 | /** |
380 | * Decrease the 3d resource refcount. | |
381 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
382 | * Note that the master holds a refcount as well, and may request an | |
383 | * explicit switch to vga mode when it releases its refcount to account | |
384 | * for the situation of an X server vt switch to VGA with 3d resources | |
385 | * active. | |
386 | */ | |
387 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
388 | bool hide_svga) | |
30c78bb8 TH |
389 | { |
390 | int32_t n3d; | |
391 | ||
392 | mutex_lock(&dev_priv->release_mutex); | |
393 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
394 | vmw_release_device(dev_priv); | |
05730b32 TH |
395 | else if (hide_svga) { |
396 | mutex_lock(&dev_priv->hw_mutex); | |
397 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
398 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
399 | SVGA_REG_ENABLE_HIDE); | |
400 | mutex_unlock(&dev_priv->hw_mutex); | |
401 | } | |
402 | ||
30c78bb8 TH |
403 | n3d = (int32_t) dev_priv->num_3d_resources; |
404 | mutex_unlock(&dev_priv->release_mutex); | |
405 | ||
406 | BUG_ON(n3d < 0); | |
407 | } | |
408 | ||
eb4f923b JB |
409 | /** |
410 | * Sets the initial_[width|height] fields on the given vmw_private. | |
411 | * | |
412 | * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then | |
67d4a87b TH |
413 | * clamping the value to fb_max_[width|height] fields and the |
414 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. | |
415 | * If the values appear to be invalid, set them to | |
eb4f923b JB |
416 | * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. |
417 | */ | |
418 | static void vmw_get_initial_size(struct vmw_private *dev_priv) | |
419 | { | |
420 | uint32_t width; | |
421 | uint32_t height; | |
422 | ||
423 | width = vmw_read(dev_priv, SVGA_REG_WIDTH); | |
424 | height = vmw_read(dev_priv, SVGA_REG_HEIGHT); | |
425 | ||
426 | width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); | |
eb4f923b | 427 | height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); |
67d4a87b TH |
428 | |
429 | if (width > dev_priv->fb_max_width || | |
430 | height > dev_priv->fb_max_height) { | |
431 | ||
432 | /* | |
433 | * This is a host error and shouldn't occur. | |
434 | */ | |
435 | ||
436 | width = VMW_MIN_INITIAL_WIDTH; | |
437 | height = VMW_MIN_INITIAL_HEIGHT; | |
438 | } | |
eb4f923b JB |
439 | |
440 | dev_priv->initial_width = width; | |
441 | dev_priv->initial_height = height; | |
442 | } | |
443 | ||
d92d9851 TH |
444 | /** |
445 | * vmw_dma_select_mode - Determine how DMA mappings should be set up for this | |
446 | * system. | |
447 | * | |
448 | * @dev_priv: Pointer to a struct vmw_private | |
449 | * | |
450 | * This functions tries to determine the IOMMU setup and what actions | |
451 | * need to be taken by the driver to make system pages visible to the | |
452 | * device. | |
453 | * If this function decides that DMA is not possible, it returns -EINVAL. | |
454 | * The driver may then try to disable features of the device that require | |
455 | * DMA. | |
456 | */ | |
457 | static int vmw_dma_select_mode(struct vmw_private *dev_priv) | |
458 | { | |
d92d9851 TH |
459 | static const char *names[vmw_dma_map_max] = { |
460 | [vmw_dma_phys] = "Using physical TTM page addresses.", | |
461 | [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", | |
462 | [vmw_dma_map_populate] = "Keeping DMA mappings.", | |
463 | [vmw_dma_map_bind] = "Giving up DMA mappings early."}; | |
e14cd953 TH |
464 | #ifdef CONFIG_X86 |
465 | const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); | |
d92d9851 TH |
466 | |
467 | #ifdef CONFIG_INTEL_IOMMU | |
468 | if (intel_iommu_enabled) { | |
469 | dev_priv->map_mode = vmw_dma_map_populate; | |
470 | goto out_fixup; | |
471 | } | |
472 | #endif | |
473 | ||
474 | if (!(vmw_force_iommu || vmw_force_coherent)) { | |
475 | dev_priv->map_mode = vmw_dma_phys; | |
476 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); | |
477 | return 0; | |
478 | } | |
479 | ||
480 | dev_priv->map_mode = vmw_dma_map_populate; | |
481 | ||
482 | if (dma_ops->sync_single_for_cpu) | |
483 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
484 | #ifdef CONFIG_SWIOTLB | |
485 | if (swiotlb_nr_tbl() == 0) | |
486 | dev_priv->map_mode = vmw_dma_map_populate; | |
487 | #endif | |
488 | ||
21136946 | 489 | #ifdef CONFIG_INTEL_IOMMU |
d92d9851 | 490 | out_fixup: |
21136946 | 491 | #endif |
d92d9851 TH |
492 | if (dev_priv->map_mode == vmw_dma_map_populate && |
493 | vmw_restrict_iommu) | |
494 | dev_priv->map_mode = vmw_dma_map_bind; | |
495 | ||
496 | if (vmw_force_coherent) | |
497 | dev_priv->map_mode = vmw_dma_alloc_coherent; | |
498 | ||
499 | #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) | |
500 | /* | |
501 | * No coherent page pool | |
502 | */ | |
503 | if (dev_priv->map_mode == vmw_dma_alloc_coherent) | |
504 | return -EINVAL; | |
505 | #endif | |
506 | ||
e14cd953 TH |
507 | #else /* CONFIG_X86 */ |
508 | dev_priv->map_mode = vmw_dma_map_populate; | |
509 | #endif /* CONFIG_X86 */ | |
510 | ||
d92d9851 TH |
511 | DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
0d00c488 TH |
516 | /** |
517 | * vmw_dma_masks - set required page- and dma masks | |
518 | * | |
519 | * @dev: Pointer to struct drm-device | |
520 | * | |
521 | * With 32-bit we can only handle 32 bit PFNs. Optionally set that | |
522 | * restriction also for 64-bit systems. | |
523 | */ | |
524 | #ifdef CONFIG_INTEL_IOMMU | |
525 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
526 | { | |
527 | struct drm_device *dev = dev_priv->dev; | |
528 | ||
529 | if (intel_iommu_enabled && | |
530 | (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { | |
531 | DRM_INFO("Restricting DMA addresses to 44 bits.\n"); | |
532 | return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); | |
533 | } | |
534 | return 0; | |
535 | } | |
536 | #else | |
537 | static int vmw_dma_masks(struct vmw_private *dev_priv) | |
538 | { | |
539 | return 0; | |
540 | } | |
541 | #endif | |
542 | ||
fb1d9738 JB |
543 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
544 | { | |
545 | struct vmw_private *dev_priv; | |
546 | int ret; | |
c188660f | 547 | uint32_t svga_id; |
c0951b79 | 548 | enum vmw_res_type i; |
d92d9851 | 549 | bool refuse_dma = false; |
fb1d9738 JB |
550 | |
551 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
552 | if (unlikely(dev_priv == NULL)) { | |
553 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
554 | return -ENOMEM; | |
555 | } | |
fb1d9738 | 556 | |
466e69b8 DA |
557 | pci_set_master(dev->pdev); |
558 | ||
fb1d9738 JB |
559 | dev_priv->dev = dev; |
560 | dev_priv->vmw_chipset = chipset; | |
6bcd8d3c | 561 | dev_priv->last_read_seqno = (uint32_t) -100; |
fb1d9738 JB |
562 | mutex_init(&dev_priv->hw_mutex); |
563 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 564 | mutex_init(&dev_priv->release_mutex); |
fb1d9738 | 565 | rwlock_init(&dev_priv->resource_lock); |
c0951b79 TH |
566 | |
567 | for (i = vmw_res_context; i < vmw_res_max; ++i) { | |
568 | idr_init(&dev_priv->res_idr[i]); | |
569 | INIT_LIST_HEAD(&dev_priv->res_lru[i]); | |
570 | } | |
571 | ||
fb1d9738 JB |
572 | mutex_init(&dev_priv->init_mutex); |
573 | init_waitqueue_head(&dev_priv->fence_queue); | |
574 | init_waitqueue_head(&dev_priv->fifo_queue); | |
4f73a96b | 575 | dev_priv->fence_queue_waiters = 0; |
fb1d9738 | 576 | atomic_set(&dev_priv->fifo_queue_waiters, 0); |
c0951b79 | 577 | |
5bb39e81 | 578 | dev_priv->used_memory_size = 0; |
fb1d9738 JB |
579 | |
580 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
581 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
582 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
583 | ||
30c78bb8 TH |
584 | dev_priv->enable_fb = enable_fbdev; |
585 | ||
fb1d9738 | 586 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
587 | |
588 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
589 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
590 | if (svga_id != SVGA_ID_2) { | |
591 | ret = -ENOSYS; | |
49625904 | 592 | DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); |
c188660f PH |
593 | mutex_unlock(&dev_priv->hw_mutex); |
594 | goto out_err0; | |
595 | } | |
596 | ||
fb1d9738 | 597 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
d92d9851 TH |
598 | ret = vmw_dma_select_mode(dev_priv); |
599 | if (unlikely(ret != 0)) { | |
600 | DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); | |
601 | refuse_dma = true; | |
602 | } | |
fb1d9738 | 603 | |
5bb39e81 TH |
604 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); |
605 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
606 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
607 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
eb4f923b JB |
608 | |
609 | vmw_get_initial_size(dev_priv); | |
610 | ||
0d00c488 | 611 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
612 | dev_priv->max_gmr_ids = |
613 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
fb17f189 TH |
614 | dev_priv->max_gmr_pages = |
615 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
616 | dev_priv->memory_size = | |
617 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
5bb39e81 TH |
618 | dev_priv->memory_size -= dev_priv->vram_size; |
619 | } else { | |
620 | /* | |
621 | * An arbitrary limit of 512MiB on surface | |
622 | * memory. But all HWV8 hardware supports GMR2. | |
623 | */ | |
624 | dev_priv->memory_size = 512*1024*1024; | |
fb17f189 | 625 | } |
fb1d9738 | 626 | |
0d00c488 TH |
627 | ret = vmw_dma_masks(dev_priv); |
628 | if (unlikely(ret != 0)) | |
629 | goto out_err0; | |
630 | ||
fb1d9738 JB |
631 | mutex_unlock(&dev_priv->hw_mutex); |
632 | ||
633 | vmw_print_capabilities(dev_priv->capabilities); | |
634 | ||
0d00c488 | 635 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
fb1d9738 JB |
636 | DRM_INFO("Max GMR ids is %u\n", |
637 | (unsigned)dev_priv->max_gmr_ids); | |
fb17f189 TH |
638 | DRM_INFO("Max number of GMR pages is %u\n", |
639 | (unsigned)dev_priv->max_gmr_pages); | |
5bb39e81 TH |
640 | DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", |
641 | (unsigned)dev_priv->memory_size / 1024); | |
fb17f189 | 642 | } |
fb1d9738 JB |
643 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
644 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
645 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
646 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
647 | ||
648 | ret = vmw_ttm_global_init(dev_priv); | |
649 | if (unlikely(ret != 0)) | |
650 | goto out_err0; | |
651 | ||
652 | ||
653 | vmw_master_init(&dev_priv->fbdev_master); | |
654 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
655 | dev_priv->active_master = &dev_priv->fbdev_master; | |
656 | ||
a2c06ee2 | 657 | |
fb1d9738 JB |
658 | ret = ttm_bo_device_init(&dev_priv->bdev, |
659 | dev_priv->bo_global_ref.ref.object, | |
660 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, | |
661 | false); | |
662 | if (unlikely(ret != 0)) { | |
663 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
664 | goto out_err1; | |
665 | } | |
666 | ||
667 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
668 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
669 | if (unlikely(ret != 0)) { | |
670 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
671 | goto out_err2; | |
672 | } | |
673 | ||
135cba0d | 674 | dev_priv->has_gmr = true; |
d92d9851 TH |
675 | if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || |
676 | refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
677 | dev_priv->max_gmr_ids) != 0) { | |
135cba0d TH |
678 | DRM_INFO("No GMR memory available. " |
679 | "Graphics memory resources are very limited.\n"); | |
680 | dev_priv->has_gmr = false; | |
681 | } | |
682 | ||
247d36d7 AL |
683 | dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, |
684 | dev_priv->mmio_size); | |
fb1d9738 JB |
685 | |
686 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
687 | dev_priv->mmio_size); | |
688 | ||
689 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
690 | ret = -ENOMEM; | |
691 | DRM_ERROR("Failed mapping MMIO.\n"); | |
692 | goto out_err3; | |
693 | } | |
694 | ||
d7e1958d JB |
695 | /* Need mmio memory to check for fifo pitchlock cap. */ |
696 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
697 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
698 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
699 | ret = -ENOSYS; | |
700 | DRM_ERROR("Hardware has no pitchlock\n"); | |
701 | goto out_err4; | |
702 | } | |
703 | ||
fb1d9738 | 704 | dev_priv->tdev = ttm_object_device_init |
69977ff5 | 705 | (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); |
fb1d9738 JB |
706 | |
707 | if (unlikely(dev_priv->tdev == NULL)) { | |
708 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
709 | ret = -ENOMEM; | |
710 | goto out_err4; | |
711 | } | |
712 | ||
713 | dev->dev_private = dev_priv; | |
714 | ||
fb1d9738 JB |
715 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
716 | dev_priv->stealth = (ret != 0); | |
717 | if (dev_priv->stealth) { | |
718 | /** | |
719 | * Request at least the mmio PCI resource. | |
720 | */ | |
721 | ||
722 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 723 | "Ignore above error if any.\n"); |
fb1d9738 JB |
724 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
725 | if (unlikely(ret != 0)) { | |
726 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
727 | goto out_no_device; | |
728 | } | |
fb1d9738 | 729 | } |
ae2a1040 | 730 | |
506ff75c TH |
731 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
732 | ret = drm_irq_install(dev); | |
733 | if (ret != 0) { | |
734 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
735 | goto out_no_irq; | |
736 | } | |
737 | } | |
738 | ||
ae2a1040 | 739 | dev_priv->fman = vmw_fence_manager_init(dev_priv); |
14bbf20c WY |
740 | if (unlikely(dev_priv->fman == NULL)) { |
741 | ret = -ENOMEM; | |
ae2a1040 | 742 | goto out_no_fman; |
14bbf20c | 743 | } |
56d1c78d | 744 | |
56d1c78d | 745 | vmw_kms_save_vga(dev_priv); |
56d1c78d JB |
746 | |
747 | /* Start kms and overlay systems, needs fifo. */ | |
7a1c2f6c TH |
748 | ret = vmw_kms_init(dev_priv); |
749 | if (unlikely(ret != 0)) | |
750 | goto out_no_kms; | |
f2d12b8e | 751 | vmw_overlay_init(dev_priv); |
56d1c78d | 752 | |
30c78bb8 | 753 | if (dev_priv->enable_fb) { |
506ff75c TH |
754 | ret = vmw_3d_resource_inc(dev_priv, true); |
755 | if (unlikely(ret != 0)) | |
756 | goto out_no_fifo; | |
30c78bb8 | 757 | vmw_fb_init(dev_priv); |
7a1c2f6c TH |
758 | } |
759 | ||
d9f36a00 TH |
760 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
761 | register_pm_notifier(&dev_priv->pm_nb); | |
762 | ||
fb1d9738 JB |
763 | return 0; |
764 | ||
506ff75c | 765 | out_no_fifo: |
56d1c78d JB |
766 | vmw_overlay_close(dev_priv); |
767 | vmw_kms_close(dev_priv); | |
768 | out_no_kms: | |
506ff75c | 769 | vmw_kms_restore_vga(dev_priv); |
ae2a1040 TH |
770 | vmw_fence_manager_takedown(dev_priv->fman); |
771 | out_no_fman: | |
506ff75c TH |
772 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
773 | drm_irq_uninstall(dev_priv->dev); | |
774 | out_no_irq: | |
30c78bb8 TH |
775 | if (dev_priv->stealth) |
776 | pci_release_region(dev->pdev, 2); | |
777 | else | |
778 | pci_release_regions(dev->pdev); | |
fb1d9738 | 779 | out_no_device: |
fb1d9738 JB |
780 | ttm_object_device_release(&dev_priv->tdev); |
781 | out_err4: | |
782 | iounmap(dev_priv->mmio_virt); | |
783 | out_err3: | |
247d36d7 | 784 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
135cba0d TH |
785 | if (dev_priv->has_gmr) |
786 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
787 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
788 | out_err2: | |
789 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
790 | out_err1: | |
791 | vmw_ttm_global_release(dev_priv); | |
792 | out_err0: | |
c0951b79 TH |
793 | for (i = vmw_res_context; i < vmw_res_max; ++i) |
794 | idr_destroy(&dev_priv->res_idr[i]); | |
795 | ||
fb1d9738 JB |
796 | kfree(dev_priv); |
797 | return ret; | |
798 | } | |
799 | ||
800 | static int vmw_driver_unload(struct drm_device *dev) | |
801 | { | |
802 | struct vmw_private *dev_priv = vmw_priv(dev); | |
c0951b79 | 803 | enum vmw_res_type i; |
fb1d9738 | 804 | |
d9f36a00 TH |
805 | unregister_pm_notifier(&dev_priv->pm_nb); |
806 | ||
c0951b79 TH |
807 | if (dev_priv->ctx.res_ht_initialized) |
808 | drm_ht_remove(&dev_priv->ctx.res_ht); | |
be38ab6e TH |
809 | if (dev_priv->ctx.cmd_bounce) |
810 | vfree(dev_priv->ctx.cmd_bounce); | |
30c78bb8 TH |
811 | if (dev_priv->enable_fb) { |
812 | vmw_fb_close(dev_priv); | |
813 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 814 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 815 | } |
f2d12b8e TH |
816 | vmw_kms_close(dev_priv); |
817 | vmw_overlay_close(dev_priv); | |
ae2a1040 | 818 | vmw_fence_manager_takedown(dev_priv->fman); |
506ff75c TH |
819 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
820 | drm_irq_uninstall(dev_priv->dev); | |
f2d12b8e | 821 | if (dev_priv->stealth) |
fb1d9738 | 822 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
823 | else |
824 | pci_release_regions(dev->pdev); | |
825 | ||
fb1d9738 JB |
826 | ttm_object_device_release(&dev_priv->tdev); |
827 | iounmap(dev_priv->mmio_virt); | |
247d36d7 | 828 | arch_phys_wc_del(dev_priv->mmio_mtrr); |
135cba0d TH |
829 | if (dev_priv->has_gmr) |
830 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
831 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
832 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
833 | vmw_ttm_global_release(dev_priv); | |
c0951b79 TH |
834 | |
835 | for (i = vmw_res_context; i < vmw_res_max; ++i) | |
836 | idr_destroy(&dev_priv->res_idr[i]); | |
fb1d9738 JB |
837 | |
838 | kfree(dev_priv); | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
6b82ef50 TH |
843 | static void vmw_preclose(struct drm_device *dev, |
844 | struct drm_file *file_priv) | |
845 | { | |
846 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
847 | struct vmw_private *dev_priv = vmw_priv(dev); | |
848 | ||
849 | vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); | |
850 | } | |
851 | ||
fb1d9738 JB |
852 | static void vmw_postclose(struct drm_device *dev, |
853 | struct drm_file *file_priv) | |
854 | { | |
855 | struct vmw_fpriv *vmw_fp; | |
856 | ||
857 | vmw_fp = vmw_fpriv(file_priv); | |
c4249855 TH |
858 | |
859 | if (vmw_fp->locked_master) { | |
860 | struct vmw_master *vmaster = | |
861 | vmw_master(vmw_fp->locked_master); | |
862 | ||
863 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
864 | ttm_vt_unlock(&vmaster->lock); | |
fb1d9738 | 865 | drm_master_put(&vmw_fp->locked_master); |
c4249855 TH |
866 | } |
867 | ||
868 | ttm_object_file_release(&vmw_fp->tfile); | |
fb1d9738 JB |
869 | kfree(vmw_fp); |
870 | } | |
871 | ||
872 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
873 | { | |
874 | struct vmw_private *dev_priv = vmw_priv(dev); | |
875 | struct vmw_fpriv *vmw_fp; | |
876 | int ret = -ENOMEM; | |
877 | ||
878 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
879 | if (unlikely(vmw_fp == NULL)) | |
880 | return ret; | |
881 | ||
6b82ef50 | 882 | INIT_LIST_HEAD(&vmw_fp->fence_events); |
fb1d9738 JB |
883 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); |
884 | if (unlikely(vmw_fp->tfile == NULL)) | |
885 | goto out_no_tfile; | |
886 | ||
887 | file_priv->driver_priv = vmw_fp; | |
949c4a34 | 888 | dev_priv->bdev.dev_mapping = dev->dev_mapping; |
fb1d9738 JB |
889 | |
890 | return 0; | |
891 | ||
892 | out_no_tfile: | |
893 | kfree(vmw_fp); | |
894 | return ret; | |
895 | } | |
896 | ||
897 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
898 | unsigned long arg) | |
899 | { | |
900 | struct drm_file *file_priv = filp->private_data; | |
901 | struct drm_device *dev = file_priv->minor->dev; | |
902 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
903 | |
904 | /* | |
e1f78003 | 905 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
906 | */ |
907 | ||
908 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
909 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
baa70943 | 910 | const struct drm_ioctl_desc *ioctl = |
fb1d9738 JB |
911 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; |
912 | ||
2854eeda | 913 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
914 | DRM_ERROR("Invalid command format, ioctl %d\n", |
915 | nr - DRM_COMMAND_BASE); | |
916 | return -EINVAL; | |
917 | } | |
fb1d9738 JB |
918 | } |
919 | ||
e1f78003 | 920 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
921 | } |
922 | ||
fb1d9738 JB |
923 | static void vmw_lastclose(struct drm_device *dev) |
924 | { | |
fb1d9738 JB |
925 | struct drm_crtc *crtc; |
926 | struct drm_mode_set set; | |
927 | int ret; | |
928 | ||
fb1d9738 JB |
929 | set.x = 0; |
930 | set.y = 0; | |
931 | set.fb = NULL; | |
932 | set.mode = NULL; | |
933 | set.connectors = NULL; | |
934 | set.num_connectors = 0; | |
935 | ||
936 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
937 | set.crtc = crtc; | |
2d13b679 | 938 | ret = drm_mode_set_config_internal(&set); |
fb1d9738 JB |
939 | WARN_ON(ret != 0); |
940 | } | |
941 | ||
942 | } | |
943 | ||
944 | static void vmw_master_init(struct vmw_master *vmaster) | |
945 | { | |
946 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
947 | INIT_LIST_HEAD(&vmaster->fb_surf); |
948 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
949 | } |
950 | ||
951 | static int vmw_master_create(struct drm_device *dev, | |
952 | struct drm_master *master) | |
953 | { | |
954 | struct vmw_master *vmaster; | |
955 | ||
fb1d9738 JB |
956 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
957 | if (unlikely(vmaster == NULL)) | |
958 | return -ENOMEM; | |
959 | ||
3a939a5e | 960 | vmw_master_init(vmaster); |
fb1d9738 JB |
961 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
962 | master->driver_priv = vmaster; | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | static void vmw_master_destroy(struct drm_device *dev, | |
968 | struct drm_master *master) | |
969 | { | |
970 | struct vmw_master *vmaster = vmw_master(master); | |
971 | ||
fb1d9738 JB |
972 | master->driver_priv = NULL; |
973 | kfree(vmaster); | |
974 | } | |
975 | ||
976 | ||
977 | static int vmw_master_set(struct drm_device *dev, | |
978 | struct drm_file *file_priv, | |
979 | bool from_open) | |
980 | { | |
981 | struct vmw_private *dev_priv = vmw_priv(dev); | |
982 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
983 | struct vmw_master *active = dev_priv->active_master; | |
984 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
985 | int ret = 0; | |
986 | ||
30c78bb8 | 987 | if (!dev_priv->enable_fb) { |
05730b32 | 988 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
989 | if (unlikely(ret != 0)) |
990 | return ret; | |
991 | vmw_kms_save_vga(dev_priv); | |
992 | mutex_lock(&dev_priv->hw_mutex); | |
993 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
994 | mutex_unlock(&dev_priv->hw_mutex); | |
995 | } | |
996 | ||
fb1d9738 JB |
997 | if (active) { |
998 | BUG_ON(active != &dev_priv->fbdev_master); | |
999 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
1000 | if (unlikely(ret != 0)) | |
1001 | goto out_no_active_lock; | |
1002 | ||
1003 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
1004 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
1005 | if (unlikely(ret != 0)) { | |
1006 | DRM_ERROR("Unable to clean VRAM on " | |
1007 | "master drop.\n"); | |
1008 | } | |
1009 | ||
1010 | dev_priv->active_master = NULL; | |
1011 | } | |
1012 | ||
1013 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
1014 | if (!from_open) { | |
1015 | ttm_vt_unlock(&vmaster->lock); | |
1016 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
1017 | drm_master_put(&vmw_fp->locked_master); | |
1018 | } | |
1019 | ||
1020 | dev_priv->active_master = vmaster; | |
1021 | ||
1022 | return 0; | |
1023 | ||
1024 | out_no_active_lock: | |
30c78bb8 | 1025 | if (!dev_priv->enable_fb) { |
ba723fe8 TH |
1026 | vmw_kms_restore_vga(dev_priv); |
1027 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
1028 | mutex_lock(&dev_priv->hw_mutex); |
1029 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
1030 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 1031 | } |
fb1d9738 JB |
1032 | return ret; |
1033 | } | |
1034 | ||
1035 | static void vmw_master_drop(struct drm_device *dev, | |
1036 | struct drm_file *file_priv, | |
1037 | bool from_release) | |
1038 | { | |
1039 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1040 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
1041 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
1042 | int ret; | |
1043 | ||
fb1d9738 JB |
1044 | /** |
1045 | * Make sure the master doesn't disappear while we have | |
1046 | * it locked. | |
1047 | */ | |
1048 | ||
1049 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
1050 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
fb1d9738 JB |
1051 | if (unlikely((ret != 0))) { |
1052 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
1053 | drm_master_put(&vmw_fp->locked_master); | |
1054 | } | |
1055 | ||
c4249855 TH |
1056 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); |
1057 | vmw_execbuf_release_pinned_bo(dev_priv); | |
fb1d9738 | 1058 | |
30c78bb8 TH |
1059 | if (!dev_priv->enable_fb) { |
1060 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
1061 | if (unlikely(ret != 0)) | |
1062 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
ba723fe8 TH |
1063 | vmw_kms_restore_vga(dev_priv); |
1064 | vmw_3d_resource_dec(dev_priv, true); | |
30c78bb8 TH |
1065 | mutex_lock(&dev_priv->hw_mutex); |
1066 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
1067 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 TH |
1068 | } |
1069 | ||
fb1d9738 JB |
1070 | dev_priv->active_master = &dev_priv->fbdev_master; |
1071 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
1072 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
1073 | ||
30c78bb8 TH |
1074 | if (dev_priv->enable_fb) |
1075 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
1076 | } |
1077 | ||
1078 | ||
1079 | static void vmw_remove(struct pci_dev *pdev) | |
1080 | { | |
1081 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1082 | ||
1083 | drm_put_dev(dev); | |
1084 | } | |
1085 | ||
d9f36a00 TH |
1086 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
1087 | void *ptr) | |
1088 | { | |
1089 | struct vmw_private *dev_priv = | |
1090 | container_of(nb, struct vmw_private, pm_nb); | |
1091 | struct vmw_master *vmaster = dev_priv->active_master; | |
1092 | ||
1093 | switch (val) { | |
1094 | case PM_HIBERNATION_PREPARE: | |
1095 | case PM_SUSPEND_PREPARE: | |
1096 | ttm_suspend_lock(&vmaster->lock); | |
1097 | ||
1098 | /** | |
1099 | * This empties VRAM and unbinds all GMR bindings. | |
1100 | * Buffer contents is moved to swappable memory. | |
1101 | */ | |
c0951b79 TH |
1102 | vmw_execbuf_release_pinned_bo(dev_priv); |
1103 | vmw_resource_evict_all(dev_priv); | |
d9f36a00 | 1104 | ttm_bo_swapout_all(&dev_priv->bdev); |
094e0fa8 | 1105 | |
d9f36a00 TH |
1106 | break; |
1107 | case PM_POST_HIBERNATION: | |
1108 | case PM_POST_SUSPEND: | |
094e0fa8 | 1109 | case PM_POST_RESTORE: |
d9f36a00 | 1110 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 1111 | |
d9f36a00 TH |
1112 | break; |
1113 | case PM_RESTORE_PREPARE: | |
1114 | break; | |
d9f36a00 TH |
1115 | default: |
1116 | break; | |
1117 | } | |
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | /** | |
1122 | * These might not be needed with the virtual SVGA device. | |
1123 | */ | |
1124 | ||
7fbd721a | 1125 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 1126 | { |
094e0fa8 TH |
1127 | struct drm_device *dev = pci_get_drvdata(pdev); |
1128 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1129 | ||
1130 | if (dev_priv->num_3d_resources != 0) { | |
1131 | DRM_INFO("Can't suspend or hibernate " | |
1132 | "while 3D resources are active.\n"); | |
1133 | return -EBUSY; | |
1134 | } | |
1135 | ||
d9f36a00 TH |
1136 | pci_save_state(pdev); |
1137 | pci_disable_device(pdev); | |
1138 | pci_set_power_state(pdev, PCI_D3hot); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
7fbd721a | 1142 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
1143 | { |
1144 | pci_set_power_state(pdev, PCI_D0); | |
1145 | pci_restore_state(pdev); | |
1146 | return pci_enable_device(pdev); | |
1147 | } | |
1148 | ||
7fbd721a TH |
1149 | static int vmw_pm_suspend(struct device *kdev) |
1150 | { | |
1151 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1152 | struct pm_message dummy; | |
1153 | ||
1154 | dummy.event = 0; | |
1155 | ||
1156 | return vmw_pci_suspend(pdev, dummy); | |
1157 | } | |
1158 | ||
1159 | static int vmw_pm_resume(struct device *kdev) | |
1160 | { | |
1161 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1162 | ||
1163 | return vmw_pci_resume(pdev); | |
1164 | } | |
1165 | ||
1166 | static int vmw_pm_prepare(struct device *kdev) | |
1167 | { | |
1168 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1169 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1170 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1171 | ||
1172 | /** | |
1173 | * Release 3d reference held by fbdev and potentially | |
1174 | * stop fifo. | |
1175 | */ | |
1176 | dev_priv->suspended = true; | |
1177 | if (dev_priv->enable_fb) | |
05730b32 | 1178 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
1179 | |
1180 | if (dev_priv->num_3d_resources != 0) { | |
1181 | ||
1182 | DRM_INFO("Can't suspend or hibernate " | |
1183 | "while 3D resources are active.\n"); | |
1184 | ||
1185 | if (dev_priv->enable_fb) | |
05730b32 | 1186 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
1187 | dev_priv->suspended = false; |
1188 | return -EBUSY; | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static void vmw_pm_complete(struct device *kdev) | |
1195 | { | |
1196 | struct pci_dev *pdev = to_pci_dev(kdev); | |
1197 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1198 | struct vmw_private *dev_priv = vmw_priv(dev); | |
1199 | ||
95e8f6a2 TH |
1200 | mutex_lock(&dev_priv->hw_mutex); |
1201 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
1202 | (void) vmw_read(dev_priv, SVGA_REG_ID); | |
1203 | mutex_unlock(&dev_priv->hw_mutex); | |
1204 | ||
7fbd721a TH |
1205 | /** |
1206 | * Reclaim 3d reference held by fbdev and potentially | |
1207 | * start fifo. | |
1208 | */ | |
1209 | if (dev_priv->enable_fb) | |
05730b32 | 1210 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
1211 | |
1212 | dev_priv->suspended = false; | |
1213 | } | |
1214 | ||
1215 | static const struct dev_pm_ops vmw_pm_ops = { | |
1216 | .prepare = vmw_pm_prepare, | |
1217 | .complete = vmw_pm_complete, | |
1218 | .suspend = vmw_pm_suspend, | |
1219 | .resume = vmw_pm_resume, | |
1220 | }; | |
1221 | ||
e08e96de AV |
1222 | static const struct file_operations vmwgfx_driver_fops = { |
1223 | .owner = THIS_MODULE, | |
1224 | .open = drm_open, | |
1225 | .release = drm_release, | |
1226 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
1227 | .mmap = vmw_mmap, | |
1228 | .poll = vmw_fops_poll, | |
1229 | .read = vmw_fops_read, | |
e08e96de AV |
1230 | #if defined(CONFIG_COMPAT) |
1231 | .compat_ioctl = drm_compat_ioctl, | |
1232 | #endif | |
1233 | .llseek = noop_llseek, | |
1234 | }; | |
1235 | ||
fb1d9738 JB |
1236 | static struct drm_driver driver = { |
1237 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
69977ff5 | 1238 | DRIVER_MODESET | DRIVER_PRIME, |
fb1d9738 JB |
1239 | .load = vmw_driver_load, |
1240 | .unload = vmw_driver_unload, | |
fb1d9738 JB |
1241 | .lastclose = vmw_lastclose, |
1242 | .irq_preinstall = vmw_irq_preinstall, | |
1243 | .irq_postinstall = vmw_irq_postinstall, | |
1244 | .irq_uninstall = vmw_irq_uninstall, | |
1245 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 1246 | .get_vblank_counter = vmw_get_vblank_counter, |
1c482ab3 JB |
1247 | .enable_vblank = vmw_enable_vblank, |
1248 | .disable_vblank = vmw_disable_vblank, | |
fb1d9738 JB |
1249 | .ioctls = vmw_ioctls, |
1250 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
fb1d9738 JB |
1251 | .master_create = vmw_master_create, |
1252 | .master_destroy = vmw_master_destroy, | |
1253 | .master_set = vmw_master_set, | |
1254 | .master_drop = vmw_master_drop, | |
1255 | .open = vmw_driver_open, | |
6b82ef50 | 1256 | .preclose = vmw_preclose, |
fb1d9738 | 1257 | .postclose = vmw_postclose, |
5e1782d2 DA |
1258 | |
1259 | .dumb_create = vmw_dumb_create, | |
1260 | .dumb_map_offset = vmw_dumb_map_offset, | |
1261 | .dumb_destroy = vmw_dumb_destroy, | |
1262 | ||
69977ff5 TH |
1263 | .prime_fd_to_handle = vmw_prime_fd_to_handle, |
1264 | .prime_handle_to_fd = vmw_prime_handle_to_fd, | |
1265 | ||
e08e96de | 1266 | .fops = &vmwgfx_driver_fops, |
fb1d9738 JB |
1267 | .name = VMWGFX_DRIVER_NAME, |
1268 | .desc = VMWGFX_DRIVER_DESC, | |
1269 | .date = VMWGFX_DRIVER_DATE, | |
1270 | .major = VMWGFX_DRIVER_MAJOR, | |
1271 | .minor = VMWGFX_DRIVER_MINOR, | |
1272 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
1273 | }; | |
1274 | ||
8410ea3b DA |
1275 | static struct pci_driver vmw_pci_driver = { |
1276 | .name = VMWGFX_DRIVER_NAME, | |
1277 | .id_table = vmw_pci_id_list, | |
1278 | .probe = vmw_probe, | |
1279 | .remove = vmw_remove, | |
1280 | .driver = { | |
1281 | .pm = &vmw_pm_ops | |
1282 | } | |
1283 | }; | |
1284 | ||
fb1d9738 JB |
1285 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1286 | { | |
dcdb1674 | 1287 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
1288 | } |
1289 | ||
1290 | static int __init vmwgfx_init(void) | |
1291 | { | |
1292 | int ret; | |
8410ea3b | 1293 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1294 | if (ret) |
1295 | DRM_ERROR("Failed initializing DRM.\n"); | |
1296 | return ret; | |
1297 | } | |
1298 | ||
1299 | static void __exit vmwgfx_exit(void) | |
1300 | { | |
8410ea3b | 1301 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
1302 | } |
1303 | ||
1304 | module_init(vmwgfx_init); | |
1305 | module_exit(vmwgfx_exit); | |
1306 | ||
1307 | MODULE_AUTHOR("VMware Inc. and others"); | |
1308 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
1309 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
1310 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
1311 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
1312 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
1313 | "0"); |