]>
Commit | Line | Data |
---|---|---|
fb1d9738 JB |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "vmwgfx_drv.h" | |
30 | #include "ttm/ttm_placement.h" | |
31 | #include "ttm/ttm_bo_driver.h" | |
32 | #include "ttm/ttm_object.h" | |
33 | #include "ttm/ttm_module.h" | |
34 | ||
35 | #define VMWGFX_DRIVER_NAME "vmwgfx" | |
36 | #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" | |
37 | #define VMWGFX_CHIP_SVGAII 0 | |
38 | #define VMW_FB_RESERVATION 0 | |
39 | ||
40 | /** | |
41 | * Fully encoded drm commands. Might move to vmw_drm.h | |
42 | */ | |
43 | ||
44 | #define DRM_IOCTL_VMW_GET_PARAM \ | |
45 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ | |
46 | struct drm_vmw_getparam_arg) | |
47 | #define DRM_IOCTL_VMW_ALLOC_DMABUF \ | |
48 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ | |
49 | union drm_vmw_alloc_dmabuf_arg) | |
50 | #define DRM_IOCTL_VMW_UNREF_DMABUF \ | |
51 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ | |
52 | struct drm_vmw_unref_dmabuf_arg) | |
53 | #define DRM_IOCTL_VMW_CURSOR_BYPASS \ | |
54 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ | |
55 | struct drm_vmw_cursor_bypass_arg) | |
56 | ||
57 | #define DRM_IOCTL_VMW_CONTROL_STREAM \ | |
58 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ | |
59 | struct drm_vmw_control_stream_arg) | |
60 | #define DRM_IOCTL_VMW_CLAIM_STREAM \ | |
61 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ | |
62 | struct drm_vmw_stream_arg) | |
63 | #define DRM_IOCTL_VMW_UNREF_STREAM \ | |
64 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ | |
65 | struct drm_vmw_stream_arg) | |
66 | ||
67 | #define DRM_IOCTL_VMW_CREATE_CONTEXT \ | |
68 | DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ | |
69 | struct drm_vmw_context_arg) | |
70 | #define DRM_IOCTL_VMW_UNREF_CONTEXT \ | |
71 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ | |
72 | struct drm_vmw_context_arg) | |
73 | #define DRM_IOCTL_VMW_CREATE_SURFACE \ | |
74 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ | |
75 | union drm_vmw_surface_create_arg) | |
76 | #define DRM_IOCTL_VMW_UNREF_SURFACE \ | |
77 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ | |
78 | struct drm_vmw_surface_arg) | |
79 | #define DRM_IOCTL_VMW_REF_SURFACE \ | |
80 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ | |
81 | union drm_vmw_surface_reference_arg) | |
82 | #define DRM_IOCTL_VMW_EXECBUF \ | |
83 | DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ | |
84 | struct drm_vmw_execbuf_arg) | |
fb1d9738 JB |
85 | #define DRM_IOCTL_VMW_FENCE_WAIT \ |
86 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ | |
87 | struct drm_vmw_fence_wait_arg) | |
fb1d9738 JB |
88 | |
89 | /** | |
90 | * The core DRM version of this macro doesn't account for | |
91 | * DRM_COMMAND_BASE. | |
92 | */ | |
93 | ||
94 | #define VMW_IOCTL_DEF(ioctl, func, flags) \ | |
1b2f1489 | 95 | [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} |
fb1d9738 JB |
96 | |
97 | /** | |
98 | * Ioctl definitions. | |
99 | */ | |
100 | ||
101 | static struct drm_ioctl_desc vmw_ioctls[] = { | |
1b2f1489 | 102 | VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, |
e1f78003 | 103 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 104 | VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, |
e1f78003 | 105 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 106 | VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, |
e1f78003 | 107 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 108 | VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, |
e1f78003 TH |
109 | vmw_kms_cursor_bypass_ioctl, |
110 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), | |
fb1d9738 | 111 | |
1b2f1489 | 112 | VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, |
e1f78003 | 113 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 114 | VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, |
e1f78003 | 115 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
1b2f1489 | 116 | VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, |
e1f78003 | 117 | DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), |
fb1d9738 | 118 | |
1b2f1489 | 119 | VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, |
e1f78003 | 120 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 121 | VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, |
e1f78003 | 122 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 123 | VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, |
e1f78003 | 124 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 125 | VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, |
e1f78003 | 126 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 127 | VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, |
e1f78003 | 128 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 129 | VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, |
e1f78003 | 130 | DRM_AUTH | DRM_UNLOCKED), |
1b2f1489 | 131 | VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl, |
d8bd19d2 | 132 | DRM_AUTH | DRM_UNLOCKED), |
fb1d9738 JB |
133 | }; |
134 | ||
135 | static struct pci_device_id vmw_pci_id_list[] = { | |
136 | {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, | |
137 | {0, 0, 0} | |
138 | }; | |
139 | ||
30c78bb8 | 140 | static int enable_fbdev; |
fb1d9738 JB |
141 | |
142 | static int vmw_probe(struct pci_dev *, const struct pci_device_id *); | |
143 | static void vmw_master_init(struct vmw_master *); | |
d9f36a00 TH |
144 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
145 | void *ptr); | |
fb1d9738 | 146 | |
30c78bb8 TH |
147 | MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); |
148 | module_param_named(enable_fbdev, enable_fbdev, int, 0600); | |
149 | ||
fb1d9738 JB |
150 | static void vmw_print_capabilities(uint32_t capabilities) |
151 | { | |
152 | DRM_INFO("Capabilities:\n"); | |
153 | if (capabilities & SVGA_CAP_RECT_COPY) | |
154 | DRM_INFO(" Rect copy.\n"); | |
155 | if (capabilities & SVGA_CAP_CURSOR) | |
156 | DRM_INFO(" Cursor.\n"); | |
157 | if (capabilities & SVGA_CAP_CURSOR_BYPASS) | |
158 | DRM_INFO(" Cursor bypass.\n"); | |
159 | if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) | |
160 | DRM_INFO(" Cursor bypass 2.\n"); | |
161 | if (capabilities & SVGA_CAP_8BIT_EMULATION) | |
162 | DRM_INFO(" 8bit emulation.\n"); | |
163 | if (capabilities & SVGA_CAP_ALPHA_CURSOR) | |
164 | DRM_INFO(" Alpha cursor.\n"); | |
165 | if (capabilities & SVGA_CAP_3D) | |
166 | DRM_INFO(" 3D.\n"); | |
167 | if (capabilities & SVGA_CAP_EXTENDED_FIFO) | |
168 | DRM_INFO(" Extended Fifo.\n"); | |
169 | if (capabilities & SVGA_CAP_MULTIMON) | |
170 | DRM_INFO(" Multimon.\n"); | |
171 | if (capabilities & SVGA_CAP_PITCHLOCK) | |
172 | DRM_INFO(" Pitchlock.\n"); | |
173 | if (capabilities & SVGA_CAP_IRQMASK) | |
174 | DRM_INFO(" Irq mask.\n"); | |
175 | if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) | |
176 | DRM_INFO(" Display Topology.\n"); | |
177 | if (capabilities & SVGA_CAP_GMR) | |
178 | DRM_INFO(" GMR.\n"); | |
179 | if (capabilities & SVGA_CAP_TRACES) | |
180 | DRM_INFO(" Traces.\n"); | |
dcca2862 TH |
181 | if (capabilities & SVGA_CAP_GMR2) |
182 | DRM_INFO(" GMR2.\n"); | |
183 | if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) | |
184 | DRM_INFO(" Screen Object 2.\n"); | |
fb1d9738 JB |
185 | } |
186 | ||
187 | static int vmw_request_device(struct vmw_private *dev_priv) | |
188 | { | |
189 | int ret; | |
190 | ||
fb1d9738 JB |
191 | ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); |
192 | if (unlikely(ret != 0)) { | |
193 | DRM_ERROR("Unable to initialize FIFO.\n"); | |
194 | return ret; | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static void vmw_release_device(struct vmw_private *dev_priv) | |
201 | { | |
202 | vmw_fifo_release(dev_priv, &dev_priv->fifo); | |
30c78bb8 TH |
203 | } |
204 | ||
05730b32 TH |
205 | /** |
206 | * Increase the 3d resource refcount. | |
207 | * If the count was prevously zero, initialize the fifo, switching to svga | |
208 | * mode. Note that the master holds a ref as well, and may request an | |
209 | * explicit switch to svga mode if fb is not running, using @unhide_svga. | |
210 | */ | |
211 | int vmw_3d_resource_inc(struct vmw_private *dev_priv, | |
212 | bool unhide_svga) | |
30c78bb8 TH |
213 | { |
214 | int ret = 0; | |
215 | ||
216 | mutex_lock(&dev_priv->release_mutex); | |
217 | if (unlikely(dev_priv->num_3d_resources++ == 0)) { | |
218 | ret = vmw_request_device(dev_priv); | |
219 | if (unlikely(ret != 0)) | |
220 | --dev_priv->num_3d_resources; | |
05730b32 TH |
221 | } else if (unhide_svga) { |
222 | mutex_lock(&dev_priv->hw_mutex); | |
223 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
224 | vmw_read(dev_priv, SVGA_REG_ENABLE) & | |
225 | ~SVGA_REG_ENABLE_HIDE); | |
226 | mutex_unlock(&dev_priv->hw_mutex); | |
30c78bb8 | 227 | } |
05730b32 | 228 | |
30c78bb8 TH |
229 | mutex_unlock(&dev_priv->release_mutex); |
230 | return ret; | |
fb1d9738 JB |
231 | } |
232 | ||
05730b32 TH |
233 | /** |
234 | * Decrease the 3d resource refcount. | |
235 | * If the count reaches zero, disable the fifo, switching to vga mode. | |
236 | * Note that the master holds a refcount as well, and may request an | |
237 | * explicit switch to vga mode when it releases its refcount to account | |
238 | * for the situation of an X server vt switch to VGA with 3d resources | |
239 | * active. | |
240 | */ | |
241 | void vmw_3d_resource_dec(struct vmw_private *dev_priv, | |
242 | bool hide_svga) | |
30c78bb8 TH |
243 | { |
244 | int32_t n3d; | |
245 | ||
246 | mutex_lock(&dev_priv->release_mutex); | |
247 | if (unlikely(--dev_priv->num_3d_resources == 0)) | |
248 | vmw_release_device(dev_priv); | |
05730b32 TH |
249 | else if (hide_svga) { |
250 | mutex_lock(&dev_priv->hw_mutex); | |
251 | vmw_write(dev_priv, SVGA_REG_ENABLE, | |
252 | vmw_read(dev_priv, SVGA_REG_ENABLE) | | |
253 | SVGA_REG_ENABLE_HIDE); | |
254 | mutex_unlock(&dev_priv->hw_mutex); | |
255 | } | |
256 | ||
30c78bb8 TH |
257 | n3d = (int32_t) dev_priv->num_3d_resources; |
258 | mutex_unlock(&dev_priv->release_mutex); | |
259 | ||
260 | BUG_ON(n3d < 0); | |
261 | } | |
262 | ||
fb1d9738 JB |
263 | static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) |
264 | { | |
265 | struct vmw_private *dev_priv; | |
266 | int ret; | |
c188660f | 267 | uint32_t svga_id; |
fb1d9738 JB |
268 | |
269 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
270 | if (unlikely(dev_priv == NULL)) { | |
271 | DRM_ERROR("Failed allocating a device private struct.\n"); | |
272 | return -ENOMEM; | |
273 | } | |
274 | memset(dev_priv, 0, sizeof(*dev_priv)); | |
275 | ||
276 | dev_priv->dev = dev; | |
277 | dev_priv->vmw_chipset = chipset; | |
7704befb | 278 | dev_priv->last_read_sequence = (uint32_t) -100; |
fb1d9738 JB |
279 | mutex_init(&dev_priv->hw_mutex); |
280 | mutex_init(&dev_priv->cmdbuf_mutex); | |
30c78bb8 | 281 | mutex_init(&dev_priv->release_mutex); |
fb1d9738 JB |
282 | rwlock_init(&dev_priv->resource_lock); |
283 | idr_init(&dev_priv->context_idr); | |
284 | idr_init(&dev_priv->surface_idr); | |
285 | idr_init(&dev_priv->stream_idr); | |
fb1d9738 JB |
286 | mutex_init(&dev_priv->init_mutex); |
287 | init_waitqueue_head(&dev_priv->fence_queue); | |
288 | init_waitqueue_head(&dev_priv->fifo_queue); | |
289 | atomic_set(&dev_priv->fence_queue_waiters, 0); | |
290 | atomic_set(&dev_priv->fifo_queue_waiters, 0); | |
fb1d9738 JB |
291 | |
292 | dev_priv->io_start = pci_resource_start(dev->pdev, 0); | |
293 | dev_priv->vram_start = pci_resource_start(dev->pdev, 1); | |
294 | dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); | |
295 | ||
30c78bb8 TH |
296 | dev_priv->enable_fb = enable_fbdev; |
297 | ||
fb1d9738 | 298 | mutex_lock(&dev_priv->hw_mutex); |
c188660f PH |
299 | |
300 | vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); | |
301 | svga_id = vmw_read(dev_priv, SVGA_REG_ID); | |
302 | if (svga_id != SVGA_ID_2) { | |
303 | ret = -ENOSYS; | |
304 | DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id); | |
305 | mutex_unlock(&dev_priv->hw_mutex); | |
306 | goto out_err0; | |
307 | } | |
308 | ||
fb1d9738 JB |
309 | dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); |
310 | ||
311 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
312 | dev_priv->max_gmr_descriptors = | |
313 | vmw_read(dev_priv, | |
314 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); | |
315 | dev_priv->max_gmr_ids = | |
316 | vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); | |
317 | } | |
fb17f189 TH |
318 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
319 | dev_priv->max_gmr_pages = | |
320 | vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); | |
321 | dev_priv->memory_size = | |
322 | vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); | |
323 | } | |
fb1d9738 JB |
324 | |
325 | dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); | |
326 | dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); | |
327 | dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); | |
328 | dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); | |
329 | ||
330 | mutex_unlock(&dev_priv->hw_mutex); | |
331 | ||
332 | vmw_print_capabilities(dev_priv->capabilities); | |
333 | ||
334 | if (dev_priv->capabilities & SVGA_CAP_GMR) { | |
335 | DRM_INFO("Max GMR ids is %u\n", | |
336 | (unsigned)dev_priv->max_gmr_ids); | |
337 | DRM_INFO("Max GMR descriptors is %u\n", | |
338 | (unsigned)dev_priv->max_gmr_descriptors); | |
339 | } | |
fb17f189 TH |
340 | if (dev_priv->capabilities & SVGA_CAP_GMR2) { |
341 | DRM_INFO("Max number of GMR pages is %u\n", | |
342 | (unsigned)dev_priv->max_gmr_pages); | |
343 | DRM_INFO("Max dedicated hypervisor graphics memory is %u\n", | |
344 | (unsigned)dev_priv->memory_size); | |
345 | } | |
fb1d9738 JB |
346 | DRM_INFO("VRAM at 0x%08x size is %u kiB\n", |
347 | dev_priv->vram_start, dev_priv->vram_size / 1024); | |
348 | DRM_INFO("MMIO at 0x%08x size is %u kiB\n", | |
349 | dev_priv->mmio_start, dev_priv->mmio_size / 1024); | |
350 | ||
351 | ret = vmw_ttm_global_init(dev_priv); | |
352 | if (unlikely(ret != 0)) | |
353 | goto out_err0; | |
354 | ||
355 | ||
356 | vmw_master_init(&dev_priv->fbdev_master); | |
357 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
358 | dev_priv->active_master = &dev_priv->fbdev_master; | |
359 | ||
a2c06ee2 | 360 | |
fb1d9738 JB |
361 | ret = ttm_bo_device_init(&dev_priv->bdev, |
362 | dev_priv->bo_global_ref.ref.object, | |
363 | &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, | |
364 | false); | |
365 | if (unlikely(ret != 0)) { | |
366 | DRM_ERROR("Failed initializing TTM buffer object driver.\n"); | |
367 | goto out_err1; | |
368 | } | |
369 | ||
370 | ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, | |
371 | (dev_priv->vram_size >> PAGE_SHIFT)); | |
372 | if (unlikely(ret != 0)) { | |
373 | DRM_ERROR("Failed initializing memory manager for VRAM.\n"); | |
374 | goto out_err2; | |
375 | } | |
376 | ||
135cba0d TH |
377 | dev_priv->has_gmr = true; |
378 | if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, | |
379 | dev_priv->max_gmr_ids) != 0) { | |
380 | DRM_INFO("No GMR memory available. " | |
381 | "Graphics memory resources are very limited.\n"); | |
382 | dev_priv->has_gmr = false; | |
383 | } | |
384 | ||
fb1d9738 JB |
385 | dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start, |
386 | dev_priv->mmio_size, DRM_MTRR_WC); | |
387 | ||
388 | dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, | |
389 | dev_priv->mmio_size); | |
390 | ||
391 | if (unlikely(dev_priv->mmio_virt == NULL)) { | |
392 | ret = -ENOMEM; | |
393 | DRM_ERROR("Failed mapping MMIO.\n"); | |
394 | goto out_err3; | |
395 | } | |
396 | ||
d7e1958d JB |
397 | /* Need mmio memory to check for fifo pitchlock cap. */ |
398 | if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && | |
399 | !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && | |
400 | !vmw_fifo_have_pitchlock(dev_priv)) { | |
401 | ret = -ENOSYS; | |
402 | DRM_ERROR("Hardware has no pitchlock\n"); | |
403 | goto out_err4; | |
404 | } | |
405 | ||
fb1d9738 JB |
406 | dev_priv->tdev = ttm_object_device_init |
407 | (dev_priv->mem_global_ref.object, 12); | |
408 | ||
409 | if (unlikely(dev_priv->tdev == NULL)) { | |
410 | DRM_ERROR("Unable to initialize TTM object management.\n"); | |
411 | ret = -ENOMEM; | |
412 | goto out_err4; | |
413 | } | |
414 | ||
415 | dev->dev_private = dev_priv; | |
416 | ||
fb1d9738 JB |
417 | ret = pci_request_regions(dev->pdev, "vmwgfx probe"); |
418 | dev_priv->stealth = (ret != 0); | |
419 | if (dev_priv->stealth) { | |
420 | /** | |
421 | * Request at least the mmio PCI resource. | |
422 | */ | |
423 | ||
424 | DRM_INFO("It appears like vesafb is loaded. " | |
f2d12b8e | 425 | "Ignore above error if any.\n"); |
fb1d9738 JB |
426 | ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); |
427 | if (unlikely(ret != 0)) { | |
428 | DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); | |
429 | goto out_no_device; | |
430 | } | |
fb1d9738 | 431 | } |
7a1c2f6c TH |
432 | ret = vmw_kms_init(dev_priv); |
433 | if (unlikely(ret != 0)) | |
434 | goto out_no_kms; | |
f2d12b8e | 435 | vmw_overlay_init(dev_priv); |
30c78bb8 | 436 | if (dev_priv->enable_fb) { |
05730b32 | 437 | ret = vmw_3d_resource_inc(dev_priv, false); |
30c78bb8 TH |
438 | if (unlikely(ret != 0)) |
439 | goto out_no_fifo; | |
440 | vmw_kms_save_vga(dev_priv); | |
441 | vmw_fb_init(dev_priv); | |
442 | DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? | |
443 | "Detected device 3D availability.\n" : | |
444 | "Detected no device 3D availability.\n"); | |
445 | } else { | |
446 | DRM_INFO("Delayed 3D detection since we're not " | |
447 | "running the device in SVGA mode yet.\n"); | |
448 | } | |
fb1d9738 | 449 | |
7a1c2f6c TH |
450 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { |
451 | ret = drm_irq_install(dev); | |
452 | if (unlikely(ret != 0)) { | |
453 | DRM_ERROR("Failed installing irq: %d\n", ret); | |
454 | goto out_no_irq; | |
455 | } | |
456 | } | |
457 | ||
d9f36a00 TH |
458 | dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; |
459 | register_pm_notifier(&dev_priv->pm_nb); | |
460 | ||
fb1d9738 JB |
461 | return 0; |
462 | ||
7a1c2f6c TH |
463 | out_no_irq: |
464 | if (dev_priv->enable_fb) { | |
465 | vmw_fb_close(dev_priv); | |
466 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 467 | vmw_3d_resource_dec(dev_priv, false); |
7a1c2f6c | 468 | } |
30c78bb8 TH |
469 | out_no_fifo: |
470 | vmw_overlay_close(dev_priv); | |
471 | vmw_kms_close(dev_priv); | |
7a1c2f6c | 472 | out_no_kms: |
30c78bb8 TH |
473 | if (dev_priv->stealth) |
474 | pci_release_region(dev->pdev, 2); | |
475 | else | |
476 | pci_release_regions(dev->pdev); | |
fb1d9738 | 477 | out_no_device: |
fb1d9738 JB |
478 | ttm_object_device_release(&dev_priv->tdev); |
479 | out_err4: | |
480 | iounmap(dev_priv->mmio_virt); | |
481 | out_err3: | |
482 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
483 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
484 | if (dev_priv->has_gmr) |
485 | (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
486 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
487 | out_err2: | |
488 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
489 | out_err1: | |
490 | vmw_ttm_global_release(dev_priv); | |
491 | out_err0: | |
fb1d9738 JB |
492 | idr_destroy(&dev_priv->surface_idr); |
493 | idr_destroy(&dev_priv->context_idr); | |
494 | idr_destroy(&dev_priv->stream_idr); | |
495 | kfree(dev_priv); | |
496 | return ret; | |
497 | } | |
498 | ||
499 | static int vmw_driver_unload(struct drm_device *dev) | |
500 | { | |
501 | struct vmw_private *dev_priv = vmw_priv(dev); | |
502 | ||
d9f36a00 TH |
503 | unregister_pm_notifier(&dev_priv->pm_nb); |
504 | ||
be38ab6e TH |
505 | if (dev_priv->ctx.cmd_bounce) |
506 | vfree(dev_priv->ctx.cmd_bounce); | |
7a1c2f6c TH |
507 | if (dev_priv->capabilities & SVGA_CAP_IRQMASK) |
508 | drm_irq_uninstall(dev_priv->dev); | |
30c78bb8 TH |
509 | if (dev_priv->enable_fb) { |
510 | vmw_fb_close(dev_priv); | |
511 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 512 | vmw_3d_resource_dec(dev_priv, false); |
30c78bb8 | 513 | } |
f2d12b8e TH |
514 | vmw_kms_close(dev_priv); |
515 | vmw_overlay_close(dev_priv); | |
f2d12b8e | 516 | if (dev_priv->stealth) |
fb1d9738 | 517 | pci_release_region(dev->pdev, 2); |
f2d12b8e TH |
518 | else |
519 | pci_release_regions(dev->pdev); | |
520 | ||
fb1d9738 JB |
521 | ttm_object_device_release(&dev_priv->tdev); |
522 | iounmap(dev_priv->mmio_virt); | |
523 | drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, | |
524 | dev_priv->mmio_size, DRM_MTRR_WC); | |
135cba0d TH |
525 | if (dev_priv->has_gmr) |
526 | (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); | |
fb1d9738 JB |
527 | (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); |
528 | (void)ttm_bo_device_release(&dev_priv->bdev); | |
529 | vmw_ttm_global_release(dev_priv); | |
fb1d9738 JB |
530 | idr_destroy(&dev_priv->surface_idr); |
531 | idr_destroy(&dev_priv->context_idr); | |
532 | idr_destroy(&dev_priv->stream_idr); | |
533 | ||
534 | kfree(dev_priv); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | static void vmw_postclose(struct drm_device *dev, | |
540 | struct drm_file *file_priv) | |
541 | { | |
542 | struct vmw_fpriv *vmw_fp; | |
543 | ||
544 | vmw_fp = vmw_fpriv(file_priv); | |
545 | ttm_object_file_release(&vmw_fp->tfile); | |
546 | if (vmw_fp->locked_master) | |
547 | drm_master_put(&vmw_fp->locked_master); | |
548 | kfree(vmw_fp); | |
549 | } | |
550 | ||
551 | static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) | |
552 | { | |
553 | struct vmw_private *dev_priv = vmw_priv(dev); | |
554 | struct vmw_fpriv *vmw_fp; | |
555 | int ret = -ENOMEM; | |
556 | ||
557 | vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); | |
558 | if (unlikely(vmw_fp == NULL)) | |
559 | return ret; | |
560 | ||
561 | vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); | |
562 | if (unlikely(vmw_fp->tfile == NULL)) | |
563 | goto out_no_tfile; | |
564 | ||
565 | file_priv->driver_priv = vmw_fp; | |
566 | ||
567 | if (unlikely(dev_priv->bdev.dev_mapping == NULL)) | |
568 | dev_priv->bdev.dev_mapping = | |
569 | file_priv->filp->f_path.dentry->d_inode->i_mapping; | |
570 | ||
571 | return 0; | |
572 | ||
573 | out_no_tfile: | |
574 | kfree(vmw_fp); | |
575 | return ret; | |
576 | } | |
577 | ||
578 | static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, | |
579 | unsigned long arg) | |
580 | { | |
581 | struct drm_file *file_priv = filp->private_data; | |
582 | struct drm_device *dev = file_priv->minor->dev; | |
583 | unsigned int nr = DRM_IOCTL_NR(cmd); | |
fb1d9738 JB |
584 | |
585 | /* | |
e1f78003 | 586 | * Do extra checking on driver private ioctls. |
fb1d9738 JB |
587 | */ |
588 | ||
589 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) | |
590 | && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { | |
591 | struct drm_ioctl_desc *ioctl = | |
592 | &vmw_ioctls[nr - DRM_COMMAND_BASE]; | |
593 | ||
2854eeda | 594 | if (unlikely(ioctl->cmd_drv != cmd)) { |
fb1d9738 JB |
595 | DRM_ERROR("Invalid command format, ioctl %d\n", |
596 | nr - DRM_COMMAND_BASE); | |
597 | return -EINVAL; | |
598 | } | |
fb1d9738 JB |
599 | } |
600 | ||
e1f78003 | 601 | return drm_ioctl(filp, cmd, arg); |
fb1d9738 JB |
602 | } |
603 | ||
604 | static int vmw_firstopen(struct drm_device *dev) | |
605 | { | |
606 | struct vmw_private *dev_priv = vmw_priv(dev); | |
607 | dev_priv->is_opened = true; | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | static void vmw_lastclose(struct drm_device *dev) | |
613 | { | |
614 | struct vmw_private *dev_priv = vmw_priv(dev); | |
615 | struct drm_crtc *crtc; | |
616 | struct drm_mode_set set; | |
617 | int ret; | |
618 | ||
619 | /** | |
620 | * Do nothing on the lastclose call from drm_unload. | |
621 | */ | |
622 | ||
623 | if (!dev_priv->is_opened) | |
624 | return; | |
625 | ||
626 | dev_priv->is_opened = false; | |
627 | set.x = 0; | |
628 | set.y = 0; | |
629 | set.fb = NULL; | |
630 | set.mode = NULL; | |
631 | set.connectors = NULL; | |
632 | set.num_connectors = 0; | |
633 | ||
634 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
635 | set.crtc = crtc; | |
636 | ret = crtc->funcs->set_config(&set); | |
637 | WARN_ON(ret != 0); | |
638 | } | |
639 | ||
640 | } | |
641 | ||
642 | static void vmw_master_init(struct vmw_master *vmaster) | |
643 | { | |
644 | ttm_lock_init(&vmaster->lock); | |
3a939a5e TH |
645 | INIT_LIST_HEAD(&vmaster->fb_surf); |
646 | mutex_init(&vmaster->fb_surf_mutex); | |
fb1d9738 JB |
647 | } |
648 | ||
649 | static int vmw_master_create(struct drm_device *dev, | |
650 | struct drm_master *master) | |
651 | { | |
652 | struct vmw_master *vmaster; | |
653 | ||
fb1d9738 JB |
654 | vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); |
655 | if (unlikely(vmaster == NULL)) | |
656 | return -ENOMEM; | |
657 | ||
3a939a5e | 658 | vmw_master_init(vmaster); |
fb1d9738 JB |
659 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); |
660 | master->driver_priv = vmaster; | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static void vmw_master_destroy(struct drm_device *dev, | |
666 | struct drm_master *master) | |
667 | { | |
668 | struct vmw_master *vmaster = vmw_master(master); | |
669 | ||
fb1d9738 JB |
670 | master->driver_priv = NULL; |
671 | kfree(vmaster); | |
672 | } | |
673 | ||
674 | ||
675 | static int vmw_master_set(struct drm_device *dev, | |
676 | struct drm_file *file_priv, | |
677 | bool from_open) | |
678 | { | |
679 | struct vmw_private *dev_priv = vmw_priv(dev); | |
680 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
681 | struct vmw_master *active = dev_priv->active_master; | |
682 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
683 | int ret = 0; | |
684 | ||
30c78bb8 | 685 | if (!dev_priv->enable_fb) { |
05730b32 | 686 | ret = vmw_3d_resource_inc(dev_priv, true); |
30c78bb8 TH |
687 | if (unlikely(ret != 0)) |
688 | return ret; | |
689 | vmw_kms_save_vga(dev_priv); | |
690 | mutex_lock(&dev_priv->hw_mutex); | |
691 | vmw_write(dev_priv, SVGA_REG_TRACES, 0); | |
692 | mutex_unlock(&dev_priv->hw_mutex); | |
693 | } | |
694 | ||
fb1d9738 JB |
695 | if (active) { |
696 | BUG_ON(active != &dev_priv->fbdev_master); | |
697 | ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); | |
698 | if (unlikely(ret != 0)) | |
699 | goto out_no_active_lock; | |
700 | ||
701 | ttm_lock_set_kill(&active->lock, true, SIGTERM); | |
702 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
703 | if (unlikely(ret != 0)) { | |
704 | DRM_ERROR("Unable to clean VRAM on " | |
705 | "master drop.\n"); | |
706 | } | |
707 | ||
708 | dev_priv->active_master = NULL; | |
709 | } | |
710 | ||
711 | ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); | |
712 | if (!from_open) { | |
713 | ttm_vt_unlock(&vmaster->lock); | |
714 | BUG_ON(vmw_fp->locked_master != file_priv->master); | |
715 | drm_master_put(&vmw_fp->locked_master); | |
716 | } | |
717 | ||
718 | dev_priv->active_master = vmaster; | |
719 | ||
720 | return 0; | |
721 | ||
722 | out_no_active_lock: | |
30c78bb8 TH |
723 | if (!dev_priv->enable_fb) { |
724 | mutex_lock(&dev_priv->hw_mutex); | |
725 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
726 | mutex_unlock(&dev_priv->hw_mutex); | |
727 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 728 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 | 729 | } |
fb1d9738 JB |
730 | return ret; |
731 | } | |
732 | ||
733 | static void vmw_master_drop(struct drm_device *dev, | |
734 | struct drm_file *file_priv, | |
735 | bool from_release) | |
736 | { | |
737 | struct vmw_private *dev_priv = vmw_priv(dev); | |
738 | struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); | |
739 | struct vmw_master *vmaster = vmw_master(file_priv->master); | |
740 | int ret; | |
741 | ||
fb1d9738 JB |
742 | /** |
743 | * Make sure the master doesn't disappear while we have | |
744 | * it locked. | |
745 | */ | |
746 | ||
747 | vmw_fp->locked_master = drm_master_get(file_priv->master); | |
748 | ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); | |
3a939a5e | 749 | vmw_kms_idle_workqueues(vmaster); |
fb1d9738 JB |
750 | |
751 | if (unlikely((ret != 0))) { | |
752 | DRM_ERROR("Unable to lock TTM at VT switch.\n"); | |
753 | drm_master_put(&vmw_fp->locked_master); | |
754 | } | |
755 | ||
756 | ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); | |
757 | ||
30c78bb8 TH |
758 | if (!dev_priv->enable_fb) { |
759 | ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); | |
760 | if (unlikely(ret != 0)) | |
761 | DRM_ERROR("Unable to clean VRAM on master drop.\n"); | |
762 | mutex_lock(&dev_priv->hw_mutex); | |
763 | vmw_write(dev_priv, SVGA_REG_TRACES, 1); | |
764 | mutex_unlock(&dev_priv->hw_mutex); | |
765 | vmw_kms_restore_vga(dev_priv); | |
05730b32 | 766 | vmw_3d_resource_dec(dev_priv, true); |
30c78bb8 TH |
767 | } |
768 | ||
fb1d9738 JB |
769 | dev_priv->active_master = &dev_priv->fbdev_master; |
770 | ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); | |
771 | ttm_vt_unlock(&dev_priv->fbdev_master.lock); | |
772 | ||
30c78bb8 TH |
773 | if (dev_priv->enable_fb) |
774 | vmw_fb_on(dev_priv); | |
fb1d9738 JB |
775 | } |
776 | ||
777 | ||
778 | static void vmw_remove(struct pci_dev *pdev) | |
779 | { | |
780 | struct drm_device *dev = pci_get_drvdata(pdev); | |
781 | ||
782 | drm_put_dev(dev); | |
783 | } | |
784 | ||
d9f36a00 TH |
785 | static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, |
786 | void *ptr) | |
787 | { | |
788 | struct vmw_private *dev_priv = | |
789 | container_of(nb, struct vmw_private, pm_nb); | |
790 | struct vmw_master *vmaster = dev_priv->active_master; | |
791 | ||
792 | switch (val) { | |
793 | case PM_HIBERNATION_PREPARE: | |
794 | case PM_SUSPEND_PREPARE: | |
795 | ttm_suspend_lock(&vmaster->lock); | |
796 | ||
797 | /** | |
798 | * This empties VRAM and unbinds all GMR bindings. | |
799 | * Buffer contents is moved to swappable memory. | |
800 | */ | |
801 | ttm_bo_swapout_all(&dev_priv->bdev); | |
094e0fa8 | 802 | |
d9f36a00 TH |
803 | break; |
804 | case PM_POST_HIBERNATION: | |
805 | case PM_POST_SUSPEND: | |
094e0fa8 | 806 | case PM_POST_RESTORE: |
d9f36a00 | 807 | ttm_suspend_unlock(&vmaster->lock); |
094e0fa8 | 808 | |
d9f36a00 TH |
809 | break; |
810 | case PM_RESTORE_PREPARE: | |
811 | break; | |
d9f36a00 TH |
812 | default: |
813 | break; | |
814 | } | |
815 | return 0; | |
816 | } | |
817 | ||
818 | /** | |
819 | * These might not be needed with the virtual SVGA device. | |
820 | */ | |
821 | ||
7fbd721a | 822 | static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
d9f36a00 | 823 | { |
094e0fa8 TH |
824 | struct drm_device *dev = pci_get_drvdata(pdev); |
825 | struct vmw_private *dev_priv = vmw_priv(dev); | |
826 | ||
827 | if (dev_priv->num_3d_resources != 0) { | |
828 | DRM_INFO("Can't suspend or hibernate " | |
829 | "while 3D resources are active.\n"); | |
830 | return -EBUSY; | |
831 | } | |
832 | ||
d9f36a00 TH |
833 | pci_save_state(pdev); |
834 | pci_disable_device(pdev); | |
835 | pci_set_power_state(pdev, PCI_D3hot); | |
836 | return 0; | |
837 | } | |
838 | ||
7fbd721a | 839 | static int vmw_pci_resume(struct pci_dev *pdev) |
d9f36a00 TH |
840 | { |
841 | pci_set_power_state(pdev, PCI_D0); | |
842 | pci_restore_state(pdev); | |
843 | return pci_enable_device(pdev); | |
844 | } | |
845 | ||
7fbd721a TH |
846 | static int vmw_pm_suspend(struct device *kdev) |
847 | { | |
848 | struct pci_dev *pdev = to_pci_dev(kdev); | |
849 | struct pm_message dummy; | |
850 | ||
851 | dummy.event = 0; | |
852 | ||
853 | return vmw_pci_suspend(pdev, dummy); | |
854 | } | |
855 | ||
856 | static int vmw_pm_resume(struct device *kdev) | |
857 | { | |
858 | struct pci_dev *pdev = to_pci_dev(kdev); | |
859 | ||
860 | return vmw_pci_resume(pdev); | |
861 | } | |
862 | ||
863 | static int vmw_pm_prepare(struct device *kdev) | |
864 | { | |
865 | struct pci_dev *pdev = to_pci_dev(kdev); | |
866 | struct drm_device *dev = pci_get_drvdata(pdev); | |
867 | struct vmw_private *dev_priv = vmw_priv(dev); | |
868 | ||
869 | /** | |
870 | * Release 3d reference held by fbdev and potentially | |
871 | * stop fifo. | |
872 | */ | |
873 | dev_priv->suspended = true; | |
874 | if (dev_priv->enable_fb) | |
05730b32 | 875 | vmw_3d_resource_dec(dev_priv, true); |
7fbd721a TH |
876 | |
877 | if (dev_priv->num_3d_resources != 0) { | |
878 | ||
879 | DRM_INFO("Can't suspend or hibernate " | |
880 | "while 3D resources are active.\n"); | |
881 | ||
882 | if (dev_priv->enable_fb) | |
05730b32 | 883 | vmw_3d_resource_inc(dev_priv, true); |
7fbd721a TH |
884 | dev_priv->suspended = false; |
885 | return -EBUSY; | |
886 | } | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | static void vmw_pm_complete(struct device *kdev) | |
892 | { | |
893 | struct pci_dev *pdev = to_pci_dev(kdev); | |
894 | struct drm_device *dev = pci_get_drvdata(pdev); | |
895 | struct vmw_private *dev_priv = vmw_priv(dev); | |
896 | ||
897 | /** | |
898 | * Reclaim 3d reference held by fbdev and potentially | |
899 | * start fifo. | |
900 | */ | |
901 | if (dev_priv->enable_fb) | |
05730b32 | 902 | vmw_3d_resource_inc(dev_priv, false); |
7fbd721a TH |
903 | |
904 | dev_priv->suspended = false; | |
905 | } | |
906 | ||
907 | static const struct dev_pm_ops vmw_pm_ops = { | |
908 | .prepare = vmw_pm_prepare, | |
909 | .complete = vmw_pm_complete, | |
910 | .suspend = vmw_pm_suspend, | |
911 | .resume = vmw_pm_resume, | |
912 | }; | |
913 | ||
fb1d9738 JB |
914 | static struct drm_driver driver = { |
915 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | | |
916 | DRIVER_MODESET, | |
917 | .load = vmw_driver_load, | |
918 | .unload = vmw_driver_unload, | |
919 | .firstopen = vmw_firstopen, | |
920 | .lastclose = vmw_lastclose, | |
921 | .irq_preinstall = vmw_irq_preinstall, | |
922 | .irq_postinstall = vmw_irq_postinstall, | |
923 | .irq_uninstall = vmw_irq_uninstall, | |
924 | .irq_handler = vmw_irq_handler, | |
7a1c2f6c | 925 | .get_vblank_counter = vmw_get_vblank_counter, |
fb1d9738 | 926 | .reclaim_buffers_locked = NULL, |
fb1d9738 JB |
927 | .ioctls = vmw_ioctls, |
928 | .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), | |
929 | .dma_quiescent = NULL, /*vmw_dma_quiescent, */ | |
930 | .master_create = vmw_master_create, | |
931 | .master_destroy = vmw_master_destroy, | |
932 | .master_set = vmw_master_set, | |
933 | .master_drop = vmw_master_drop, | |
934 | .open = vmw_driver_open, | |
935 | .postclose = vmw_postclose, | |
936 | .fops = { | |
937 | .owner = THIS_MODULE, | |
938 | .open = drm_open, | |
939 | .release = drm_release, | |
940 | .unlocked_ioctl = vmw_unlocked_ioctl, | |
941 | .mmap = vmw_mmap, | |
942 | .poll = drm_poll, | |
943 | .fasync = drm_fasync, | |
944 | #if defined(CONFIG_COMPAT) | |
945 | .compat_ioctl = drm_compat_ioctl, | |
946 | #endif | |
dc880abe | 947 | .llseek = noop_llseek, |
7fbd721a | 948 | }, |
fb1d9738 JB |
949 | .name = VMWGFX_DRIVER_NAME, |
950 | .desc = VMWGFX_DRIVER_DESC, | |
951 | .date = VMWGFX_DRIVER_DATE, | |
952 | .major = VMWGFX_DRIVER_MAJOR, | |
953 | .minor = VMWGFX_DRIVER_MINOR, | |
954 | .patchlevel = VMWGFX_DRIVER_PATCHLEVEL | |
955 | }; | |
956 | ||
8410ea3b DA |
957 | static struct pci_driver vmw_pci_driver = { |
958 | .name = VMWGFX_DRIVER_NAME, | |
959 | .id_table = vmw_pci_id_list, | |
960 | .probe = vmw_probe, | |
961 | .remove = vmw_remove, | |
962 | .driver = { | |
963 | .pm = &vmw_pm_ops | |
964 | } | |
965 | }; | |
966 | ||
fb1d9738 JB |
967 | static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
968 | { | |
dcdb1674 | 969 | return drm_get_pci_dev(pdev, ent, &driver); |
fb1d9738 JB |
970 | } |
971 | ||
972 | static int __init vmwgfx_init(void) | |
973 | { | |
974 | int ret; | |
8410ea3b | 975 | ret = drm_pci_init(&driver, &vmw_pci_driver); |
fb1d9738 JB |
976 | if (ret) |
977 | DRM_ERROR("Failed initializing DRM.\n"); | |
978 | return ret; | |
979 | } | |
980 | ||
981 | static void __exit vmwgfx_exit(void) | |
982 | { | |
8410ea3b | 983 | drm_pci_exit(&driver, &vmw_pci_driver); |
fb1d9738 JB |
984 | } |
985 | ||
986 | module_init(vmwgfx_init); | |
987 | module_exit(vmwgfx_exit); | |
988 | ||
989 | MODULE_AUTHOR("VMware Inc. and others"); | |
990 | MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); | |
991 | MODULE_LICENSE("GPL and additional rights"); | |
73558ead TH |
992 | MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." |
993 | __stringify(VMWGFX_DRIVER_MINOR) "." | |
994 | __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." | |
995 | "0"); |