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vmwgfx: Only allow 64x64 cursors
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
baa91d64
JB		 108 /* A lot of the code assumes this */
109 if (handle && (width != 64 || height != 64))
110 return -EINVAL;
111
fb1d9738 112 if (handle) {
7a73ba74
TH		 113 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
114 handle, &surface);
fb1d9738
JB		 115 if (!ret) {
116 if (!surface->snooper.image) {
117 DRM_ERROR("surface not suitable for cursor\n");
e5c8dbb8 118 vmw_surface_unreference(&surface);
fb1d9738
JB		 119 return -EINVAL;
120 }
121 } else {
122 ret = vmw_user_dmabuf_lookup(tfile,
123 handle, &dmabuf);
124 if (ret) {
125 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
126 return -EINVAL;
127 }
128 }
129 }
130
131 /* takedown old cursor */
132 if (du->cursor_surface) {
133 du->cursor_surface->snooper.crtc = NULL;
134 vmw_surface_unreference(&du->cursor_surface);
135 }
136 if (du->cursor_dmabuf)
137 vmw_dmabuf_unreference(&du->cursor_dmabuf);
138
139 /* setup new image */
140 if (surface) {
141 /* vmw_user_surface_lookup takes one reference */
142 du->cursor_surface = surface;
143
144 du->cursor_surface->snooper.crtc = crtc;
145 du->cursor_age = du->cursor_surface->snooper.age;
146 vmw_cursor_update_image(dev_priv, surface->snooper.image,
147 64, 64, du->hotspot_x, du->hotspot_y);
148 } else if (dmabuf) {
149 struct ttm_bo_kmap_obj map;
150 unsigned long kmap_offset;
151 unsigned long kmap_num;
152 void *virtual;
153 bool dummy;
154
155 /* vmw_user_surface_lookup takes one reference */
156 du->cursor_dmabuf = dmabuf;
157
158 kmap_offset = 0;
159 kmap_num = (64*64*4) >> PAGE_SHIFT;
160
161 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
162 if (unlikely(ret != 0)) {
163 DRM_ERROR("reserve failed\n");
164 return -EINVAL;
165 }
166
167 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
168 if (unlikely(ret != 0))
169 goto err_unreserve;
170
171 virtual = ttm_kmap_obj_virtual(&map, &dummy);
172 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
173 du->hotspot_x, du->hotspot_y);
174
175 ttm_bo_kunmap(&map);
176err_unreserve:
177 ttm_bo_unreserve(&dmabuf->base);
178
179 } else {
180 vmw_cursor_update_position(dev_priv, false, 0, 0);
181 return 0;
182 }
183
da7653d6
TH		 184 vmw_cursor_update_position(dev_priv, true,
185 du->cursor_x + du->hotspot_x,
186 du->cursor_y + du->hotspot_y);
fb1d9738
JB		 187
188 return 0;
189}
190
191int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
192{
193 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
194 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
195 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
196
197 du->cursor_x = x + crtc->x;
198 du->cursor_y = y + crtc->y;
199
200 vmw_cursor_update_position(dev_priv, shown,
da7653d6
TH		 201 du->cursor_x + du->hotspot_x,
202 du->cursor_y + du->hotspot_y);
fb1d9738
JB		 203
204 return 0;
205}
206
207void vmw_kms_cursor_snoop(struct vmw_surface *srf,
208 struct ttm_object_file *tfile,
209 struct ttm_buffer_object *bo,
210 SVGA3dCmdHeader *header)
211{
212 struct ttm_bo_kmap_obj map;
213 unsigned long kmap_offset;
214 unsigned long kmap_num;
215 SVGA3dCopyBox *box;
216 unsigned box_count;
217 void *virtual;
218 bool dummy;
219 struct vmw_dma_cmd {
220 SVGA3dCmdHeader header;
221 SVGA3dCmdSurfaceDMA dma;
222 } *cmd;
2ac86371 223 int i, ret;
fb1d9738
JB		 224
225 cmd = container_of(header, struct vmw_dma_cmd, header);
226
227 /* No snooper installed */
228 if (!srf->snooper.image)
229 return;
230
231 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
232 DRM_ERROR("face and mipmap for cursors should never != 0\n");
233 return;
234 }
235
236 if (cmd->header.size < 64) {
237 DRM_ERROR("at least one full copy box must be given\n");
238 return;
239 }
240
241 box = (SVGA3dCopyBox *)&cmd[1];
242 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
243 sizeof(SVGA3dCopyBox);
244
2ac86371 245 if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
fb1d9738
JB		 246 box->x != 0 || box->y != 0 || box->z != 0 ||
247 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
2ac86371 248 box->d != 1 || box_count != 1) {
fb1d9738 249 /* TODO handle none page aligned offsets */
2ac86371
JB		 250 /* TODO handle more dst & src != 0 */
251 /* TODO handle more then one copy */
252 DRM_ERROR("Cant snoop dma request for cursor!\n");
253 DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
254 box->srcx, box->srcy, box->srcz,
255 box->x, box->y, box->z,
256 box->w, box->h, box->d, box_count,
257 cmd->dma.guest.ptr.offset);
fb1d9738
JB		 258 return;
259 }
260
261 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
262 kmap_num = (64*64*4) >> PAGE_SHIFT;
263
264 ret = ttm_bo_reserve(bo, true, false, false, 0);
265 if (unlikely(ret != 0)) {
266 DRM_ERROR("reserve failed\n");
267 return;
268 }
269
270 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
271 if (unlikely(ret != 0))
272 goto err_unreserve;
273
274 virtual = ttm_kmap_obj_virtual(&map, &dummy);
275
2ac86371
JB		 276 if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
277 memcpy(srf->snooper.image, virtual, 64*64*4);
278 } else {
279 /* Image is unsigned pointer. */
280 for (i = 0; i < box->h; i++)
281 memcpy(srf->snooper.image + i * 64,
282 virtual + i * cmd->dma.guest.pitch,
283 box->w * 4);
284 }
285
fb1d9738
JB		 286 srf->snooper.age++;
287
288 /* we can't call this function from this function since execbuf has
289 * reserved fifo space.
290 *
291 * if (srf->snooper.crtc)
292 * vmw_ldu_crtc_cursor_update_image(dev_priv,
293 * srf->snooper.image, 64, 64,
294 * du->hotspot_x, du->hotspot_y);
295 */
296
297 ttm_bo_kunmap(&map);
298err_unreserve:
299 ttm_bo_unreserve(bo);
300}
301
302void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
303{
304 struct drm_device *dev = dev_priv->dev;
305 struct vmw_display_unit *du;
306 struct drm_crtc *crtc;
307
308 mutex_lock(&dev->mode_config.mutex);
309
310 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
311 du = vmw_crtc_to_du(crtc);
312 if (!du->cursor_surface ||
313 du->cursor_age == du->cursor_surface->snooper.age)
314 continue;
315
316 du->cursor_age = du->cursor_surface->snooper.age;
317 vmw_cursor_update_image(dev_priv,
318 du->cursor_surface->snooper.image,
319 64, 64, du->hotspot_x, du->hotspot_y);
320 }
321
322 mutex_unlock(&dev->mode_config.mutex);
323}
324
325/*
326 * Generic framebuffer code
327 */
328
329int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
330 struct drm_file *file_priv,
331 unsigned int *handle)
332{
333 if (handle)
334 handle = 0;
335
336 return 0;
337}
338
339/*
340 * Surface framebuffer code
341 */
342
343#define vmw_framebuffer_to_vfbs(x) \
344 container_of(x, struct vmw_framebuffer_surface, base.base)
345
346struct vmw_framebuffer_surface {
347 struct vmw_framebuffer base;
348 struct vmw_surface *surface;
22ee861c 349 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 350 struct list_head head;
351 struct drm_master *master;
fb1d9738
JB		 352};
353
354void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
355{
3a939a5e 356 struct vmw_framebuffer_surface *vfbs =
fb1d9738 357 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 358 struct vmw_master *vmaster = vmw_master(vfbs->master);
359
360
361 mutex_lock(&vmaster->fb_surf_mutex);
362 list_del(&vfbs->head);
363 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 364
3a939a5e 365 drm_master_put(&vfbs->master);
fb1d9738 366 drm_framebuffer_cleanup(framebuffer);
3a939a5e 367 vmw_surface_unreference(&vfbs->surface);
90ff18bc 368 ttm_base_object_unref(&vfbs->base.user_obj);
fb1d9738 369
3a939a5e 370 kfree(vfbs);
fb1d9738
JB		 371}
372
56d1c78d 373static int do_surface_dirty_sou(struct vmw_private *dev_priv,
90ff18bc 374 struct drm_file *file_priv,
56d1c78d 375 struct vmw_framebuffer *framebuffer,
56d1c78d
JB		 376 unsigned flags, unsigned color,
377 struct drm_clip_rect *clips,
378 unsigned num_clips, int inc)
379{
c6ca8391
JB		 380 struct drm_clip_rect *clips_ptr;
381 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
382 struct drm_crtc *crtc;
56d1c78d 383 size_t fifo_size;
c6ca8391
JB		 384 int i, num_units;
385 int ret = 0; /* silence warning */
386 int left, right, top, bottom;
56d1c78d
JB		 387
388 struct {
389 SVGA3dCmdHeader header;
390 SVGA3dCmdBlitSurfaceToScreen body;
391 } *cmd;
c6ca8391 392 SVGASignedRect *blits;
56d1c78d
JB		 393
394
c6ca8391
JB		 395 num_units = 0;
396 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
397 head) {
398 if (crtc->fb != &framebuffer->base)
399 continue;
400 units[num_units++] = vmw_crtc_to_du(crtc);
401 }
402
c6ca8391
JB		 403 BUG_ON(!clips || !num_clips);
404
405 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
90ff18bc 406 cmd = kzalloc(fifo_size, GFP_KERNEL);
56d1c78d 407 if (unlikely(cmd == NULL)) {
90ff18bc 408 DRM_ERROR("Temporary fifo memory alloc failed.\n");
56d1c78d
JB		 409 return -ENOMEM;
410 }
411
c6ca8391
JB		 412 left = clips->x1;
413 right = clips->x2;
414 top = clips->y1;
415 bottom = clips->y2;
416
f0c8a652
JB		 417 /* skip the first clip rect */
418 for (i = 1, clips_ptr = clips + inc;
419 i < num_clips; i++, clips_ptr += inc) {
c6ca8391
JB		 420 left = min_t(int, left, (int)clips_ptr->x1);
421 right = max_t(int, right, (int)clips_ptr->x2);
422 top = min_t(int, top, (int)clips_ptr->y1);
423 bottom = max_t(int, bottom, (int)clips_ptr->y2);
56d1c78d
JB		 424 }
425
c6ca8391
JB		 426 /* only need to do this once */
427 memset(cmd, 0, fifo_size);
428 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
429 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
430
56d1c78d
JB		 431 cmd->body.srcRect.left = left;
432 cmd->body.srcRect.right = right;
433 cmd->body.srcRect.top = top;
434 cmd->body.srcRect.bottom = bottom;
435
c6ca8391
JB		 436 clips_ptr = clips;
437 blits = (SVGASignedRect *)&cmd[1];
438 for (i = 0; i < num_clips; i++, clips_ptr += inc) {
439 blits[i].left = clips_ptr->x1 - left;
440 blits[i].right = clips_ptr->x2 - left;
441 blits[i].top = clips_ptr->y1 - top;
442 blits[i].bottom = clips_ptr->y2 - top;
443 }
444
445 /* do per unit writing, reuse fifo for each */
446 for (i = 0; i < num_units; i++) {
447 struct vmw_display_unit *unit = units[i];
448 int clip_x1 = left - unit->crtc.x;
449 int clip_y1 = top - unit->crtc.y;
450 int clip_x2 = right - unit->crtc.x;
451 int clip_y2 = bottom - unit->crtc.y;
452
453 /* skip any crtcs that misses the clip region */
454 if (clip_x1 >= unit->crtc.mode.hdisplay ||
455 clip_y1 >= unit->crtc.mode.vdisplay ||
456 clip_x2 <= 0 || clip_y2 <= 0)
457 continue;
458
459 /* need to reset sid as it is changed by execbuf */
460 cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
461
462 cmd->body.destScreenId = unit->unit;
463
464 /*
465 * The blit command is a lot more resilient then the
466 * readback command when it comes to clip rects. So its
467 * okay to go out of bounds.
468 */
469
470 cmd->body.destRect.left = clip_x1;
471 cmd->body.destRect.right = clip_x2;
472 cmd->body.destRect.top = clip_y1;
473 cmd->body.destRect.bottom = clip_y2;
474
475
476 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
477 fifo_size, 0, NULL);
478
479 if (unlikely(ret != 0))
480 break;
481 }
56d1c78d 482
90ff18bc 483 kfree(cmd);
56d1c78d 484
90ff18bc 485 return ret;
5deb65cf 486}
fb1d9738
JB		 487
488int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 489 struct drm_file *file_priv,
fb1d9738
JB		 490 unsigned flags, unsigned color,
491 struct drm_clip_rect *clips,
492 unsigned num_clips)
493{
494 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 495 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 496 struct vmw_framebuffer_surface *vfbs =
497 vmw_framebuffer_to_vfbs(framebuffer);
fb1d9738 498 struct drm_clip_rect norect;
5deb65cf 499 int ret, inc = 1;
fb1d9738 500
3a939a5e
TH		 501 if (unlikely(vfbs->master != file_priv->master))
502 return -EINVAL;
503
01e81419
JB		 504 /* Require ScreenObject support for 3D */
505 if (!dev_priv->sou_priv)
506 return -EINVAL;
507
3a939a5e
TH		 508 ret = ttm_read_lock(&vmaster->lock, true);
509 if (unlikely(ret != 0))
510 return ret;
511
fb1d9738
JB		 512 if (!num_clips) {
513 num_clips = 1;
514 clips = &norect;
515 norect.x1 = norect.y1 = 0;
516 norect.x2 = framebuffer->width;
517 norect.y2 = framebuffer->height;
518 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
519 num_clips /= 2;
520 inc = 2; /* skip source rects */
521 }
522
c5c42360 523 ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
01e81419
JB		 524 flags, color,
525 clips, num_clips, inc);
fb1d9738 526
3a939a5e 527 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 528 return 0;
529}
530
531static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
532 .destroy = vmw_framebuffer_surface_destroy,
533 .dirty = vmw_framebuffer_surface_dirty,
534 .create_handle = vmw_framebuffer_create_handle,
535};
536
d3216a0c 537static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 538 struct drm_file *file_priv,
d3216a0c
TH		 539 struct vmw_surface *surface,
540 struct vmw_framebuffer **out,
541 const struct drm_mode_fb_cmd
542 *mode_cmd)
fb1d9738
JB		 543
544{
545 struct drm_device *dev = dev_priv->dev;
546 struct vmw_framebuffer_surface *vfbs;
d3216a0c 547 enum SVGA3dSurfaceFormat format;
3a939a5e 548 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 549 int ret;
550
01e81419
JB		 551 /* 3D is only supported on HWv8 hosts which supports screen objects */
552 if (!dev_priv->sou_priv)
553 return -ENOSYS;
554
d3216a0c
TH		 555 /*
556 * Sanity checks.
557 */
558
559 if (unlikely(surface->mip_levels[0] != 1 ||
560 surface->num_sizes != 1 ||
561 surface->sizes[0].width < mode_cmd->width ||
562 surface->sizes[0].height < mode_cmd->height ||
563 surface->sizes[0].depth != 1)) {
564 DRM_ERROR("Incompatible surface dimensions "
565 "for requested mode.\n");
566 return -EINVAL;
567 }
568
569 switch (mode_cmd->depth) {
570 case 32:
571 format = SVGA3D_A8R8G8B8;
572 break;
573 case 24:
574 format = SVGA3D_X8R8G8B8;
575 break;
576 case 16:
577 format = SVGA3D_R5G6B5;
578 break;
579 case 15:
580 format = SVGA3D_A1R5G5B5;
581 break;
f01b7ba0
MD		 582 case 8:
583 format = SVGA3D_LUMINANCE8;
584 break;
d3216a0c
TH		 585 default:
586 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
587 return -EINVAL;
588 }
589
590 if (unlikely(format != surface->format)) {
591 DRM_ERROR("Invalid surface format for requested mode.\n");
592 return -EINVAL;
593 }
594
fb1d9738
JB		 595 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
596 if (!vfbs) {
597 ret = -ENOMEM;
598 goto out_err1;
599 }
600
601 ret = drm_framebuffer_init(dev, &vfbs->base.base,
602 &vmw_framebuffer_surface_funcs);
603 if (ret)
604 goto out_err2;
605
606 if (!vmw_surface_reference(surface)) {
607 DRM_ERROR("failed to reference surface %p\n", surface);
608 goto out_err3;
609 }
610
611 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 612 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
613 vfbs->base.base.pitch = mode_cmd->pitch;
614 vfbs->base.base.depth = mode_cmd->depth;
615 vfbs->base.base.width = mode_cmd->width;
616 vfbs->base.base.height = mode_cmd->height;
fb1d9738 617 vfbs->surface = surface;
90ff18bc 618 vfbs->base.user_handle = mode_cmd->handle;
3a939a5e 619 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 620
621 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 622 list_add_tail(&vfbs->head, &vmaster->fb_surf);
623 mutex_unlock(&vmaster->fb_surf_mutex);
624
fb1d9738
JB		 625 *out = &vfbs->base;
626
627 return 0;
628
629out_err3:
630 drm_framebuffer_cleanup(&vfbs->base.base);
631out_err2:
632 kfree(vfbs);
633out_err1:
634 return ret;
635}
636
637/*
638 * Dmabuf framebuffer code
639 */
640
641#define vmw_framebuffer_to_vfbd(x) \
642 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
643
644struct vmw_framebuffer_dmabuf {
645 struct vmw_framebuffer base;
646 struct vmw_dma_buffer *buffer;
647};
648
649void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
650{
651 struct vmw_framebuffer_dmabuf *vfbd =
652 vmw_framebuffer_to_vfbd(framebuffer);
653
654 drm_framebuffer_cleanup(framebuffer);
655 vmw_dmabuf_unreference(&vfbd->buffer);
90ff18bc 656 ttm_base_object_unref(&vfbd->base.user_obj);
fb1d9738
JB		 657
658 kfree(vfbd);
659}
660
5deb65cf
JB		 661static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
662 struct vmw_framebuffer *framebuffer,
5deb65cf
JB		 663 unsigned flags, unsigned color,
664 struct drm_clip_rect *clips,
665 unsigned num_clips, int increment)
666{
667 size_t fifo_size;
668 int i;
669
670 struct {
671 uint32_t header;
672 SVGAFifoCmdUpdate body;
673 } *cmd;
674
675 fifo_size = sizeof(*cmd) * num_clips;
676 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
677 if (unlikely(cmd == NULL)) {
678 DRM_ERROR("Fifo reserve failed.\n");
679 return -ENOMEM;
680 }
681
682 memset(cmd, 0, fifo_size);
683 for (i = 0; i < num_clips; i++, clips += increment) {
684 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
685 cmd[i].body.x = cpu_to_le32(clips->x1);
686 cmd[i].body.y = cpu_to_le32(clips->y1);
687 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
688 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
689 }
690
691 vmw_fifo_commit(dev_priv, fifo_size);
692 return 0;
693}
694
c6ca8391
JB		 695static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
696 struct vmw_private *dev_priv,
697 struct vmw_framebuffer *framebuffer)
56d1c78d 698{
64fc9944 699 int depth = framebuffer->base.depth;
56d1c78d 700 size_t fifo_size;
c6ca8391 701 int ret;
56d1c78d
JB		 702
703 struct {
704 uint32_t header;
705 SVGAFifoCmdDefineGMRFB body;
706 } *cmd;
56d1c78d 707
64fc9944
JB		 708 /* Emulate RGBA support, contrary to svga_reg.h this is not
709 * supported by hosts. This is only a problem if we are reading
710 * this value later and expecting what we uploaded back.
711 */
712 if (depth == 32)
713 depth = 24;
714
c6ca8391 715 fifo_size = sizeof(*cmd);
56d1c78d
JB		 716 cmd = kmalloc(fifo_size, GFP_KERNEL);
717 if (unlikely(cmd == NULL)) {
718 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
719 return -ENOMEM;
720 }
721
722 memset(cmd, 0, fifo_size);
723 cmd->header = SVGA_CMD_DEFINE_GMRFB;
724 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
64fc9944 725 cmd->body.format.colorDepth = depth;
56d1c78d
JB		 726 cmd->body.format.reserved = 0;
727 cmd->body.bytesPerLine = framebuffer->base.pitch;
90ff18bc 728 cmd->body.ptr.gmrId = framebuffer->user_handle;
56d1c78d
JB		 729 cmd->body.ptr.offset = 0;
730
56d1c78d
JB		 731 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
732 fifo_size, 0, NULL);
733
734 kfree(cmd);
735
736 return ret;
737}
738
c6ca8391
JB		 739static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
740 struct vmw_private *dev_priv,
741 struct vmw_framebuffer *framebuffer,
c6ca8391
JB		 742 unsigned flags, unsigned color,
743 struct drm_clip_rect *clips,
744 unsigned num_clips, int increment)
745{
746 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
747 struct drm_clip_rect *clips_ptr;
748 int i, k, num_units, ret;
749 struct drm_crtc *crtc;
750 size_t fifo_size;
751
752 struct {
753 uint32_t header;
754 SVGAFifoCmdBlitGMRFBToScreen body;
755 } *blits;
756
757 ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
758 if (unlikely(ret != 0))
759 return ret; /* define_gmrfb prints warnings */
760
761 fifo_size = sizeof(*blits) * num_clips;
762 blits = kmalloc(fifo_size, GFP_KERNEL);
763 if (unlikely(blits == NULL)) {
764 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
765 return -ENOMEM;
766 }
767
768 num_units = 0;
769 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
770 if (crtc->fb != &framebuffer->base)
771 continue;
772 units[num_units++] = vmw_crtc_to_du(crtc);
773 }
774
775 for (k = 0; k < num_units; k++) {
776 struct vmw_display_unit *unit = units[k];
777 int hit_num = 0;
778
779 clips_ptr = clips;
780 for (i = 0; i < num_clips; i++, clips_ptr += increment) {
781 int clip_x1 = clips_ptr->x1 - unit->crtc.x;
782 int clip_y1 = clips_ptr->y1 - unit->crtc.y;
783 int clip_x2 = clips_ptr->x2 - unit->crtc.x;
784 int clip_y2 = clips_ptr->y2 - unit->crtc.y;
785
786 /* skip any crtcs that misses the clip region */
787 if (clip_x1 >= unit->crtc.mode.hdisplay ||
788 clip_y1 >= unit->crtc.mode.vdisplay ||
789 clip_x2 <= 0 || clip_y2 <= 0)
790 continue;
791
792 blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
793 blits[hit_num].body.destScreenId = unit->unit;
794 blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
795 blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
796 blits[hit_num].body.destRect.left = clip_x1;
797 blits[hit_num].body.destRect.top = clip_y1;
798 blits[hit_num].body.destRect.right = clip_x2;
799 blits[hit_num].body.destRect.bottom = clip_y2;
800 hit_num++;
801 }
802
803 /* no clips hit the crtc */
804 if (hit_num == 0)
805 continue;
806
807 fifo_size = sizeof(*blits) * hit_num;
808 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
809 fifo_size, 0, NULL);
810
811 if (unlikely(ret != 0))
812 break;
813 }
814
815 kfree(blits);
816
817 return ret;
818}
819
fb1d9738 820int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 821 struct drm_file *file_priv,
fb1d9738
JB		 822 unsigned flags, unsigned color,
823 struct drm_clip_rect *clips,
824 unsigned num_clips)
825{
826 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 827 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 828 struct vmw_framebuffer_dmabuf *vfbd =
829 vmw_framebuffer_to_vfbd(framebuffer);
fb1d9738 830 struct drm_clip_rect norect;
5deb65cf 831 int ret, increment = 1;
fb1d9738 832
3a939a5e
TH		 833 ret = ttm_read_lock(&vmaster->lock, true);
834 if (unlikely(ret != 0))
835 return ret;
836
df1c93ba 837 if (!num_clips) {
fb1d9738
JB		 838 num_clips = 1;
839 clips = &norect;
840 norect.x1 = norect.y1 = 0;
841 norect.x2 = framebuffer->width;
842 norect.y2 = framebuffer->height;
843 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
844 num_clips /= 2;
845 increment = 2;
846 }
847
56d1c78d 848 if (dev_priv->ldu_priv) {
c5c42360 849 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
56d1c78d
JB		 850 flags, color,
851 clips, num_clips, increment);
852 } else {
853 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
c5c42360 854 flags, color,
56d1c78d
JB		 855 clips, num_clips, increment);
856 }
fb1d9738 857
3a939a5e 858 ttm_read_unlock(&vmaster->lock);
5deb65cf 859 return ret;
fb1d9738
JB		 860}
861
862static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
863 .destroy = vmw_framebuffer_dmabuf_destroy,
864 .dirty = vmw_framebuffer_dmabuf_dirty,
865 .create_handle = vmw_framebuffer_create_handle,
866};
867
497a3ff9
JB		 868/**
869 * Pin the dmabuffer to the start of vram.
870 */
fb1d9738
JB		 871static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
872{
873 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
874 struct vmw_framebuffer_dmabuf *vfbd =
875 vmw_framebuffer_to_vfbd(&vfb->base);
876 int ret;
877
56d1c78d
JB		 878 /* This code should not be used with screen objects */
879 BUG_ON(dev_priv->sou_priv);
d7e1958d 880
fb1d9738
JB		 881 vmw_overlay_pause_all(dev_priv);
882
d991ef03 883 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 884
fb1d9738
JB		 885 vmw_overlay_resume_all(dev_priv);
886
316ab13a
JB		 887 WARN_ON(ret != 0);
888
fb1d9738
JB		 889 return 0;
890}
891
892static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
893{
894 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
895 struct vmw_framebuffer_dmabuf *vfbd =
896 vmw_framebuffer_to_vfbd(&vfb->base);
897
898 if (!vfbd->buffer) {
899 WARN_ON(!vfbd->buffer);
900 return 0;
901 }
902
d991ef03 903 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 904}
905
d3216a0c
TH		 906static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
907 struct vmw_dma_buffer *dmabuf,
908 struct vmw_framebuffer **out,
909 const struct drm_mode_fb_cmd
910 *mode_cmd)
fb1d9738
JB		 911
912{
913 struct drm_device *dev = dev_priv->dev;
914 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 915 unsigned int requested_size;
fb1d9738
JB		 916 int ret;
917
d3216a0c
TH		 918 requested_size = mode_cmd->height * mode_cmd->pitch;
919 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
920 DRM_ERROR("Screen buffer object size is too small "
921 "for requested mode.\n");
922 return -EINVAL;
923 }
924
c337ada7
JB		 925 /* Limited framebuffer color depth support for screen objects */
926 if (dev_priv->sou_priv) {
927 switch (mode_cmd->depth) {
928 case 32:
929 case 24:
930 /* Only support 32 bpp for 32 and 24 depth fbs */
931 if (mode_cmd->bpp == 32)
932 break;
933
934 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
935 mode_cmd->depth, mode_cmd->bpp);
936 return -EINVAL;
937 case 16:
938 case 15:
939 /* Only support 16 bpp for 16 and 15 depth fbs */
940 if (mode_cmd->bpp == 16)
941 break;
942
943 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
944 mode_cmd->depth, mode_cmd->bpp);
945 return -EINVAL;
946 default:
947 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
948 return -EINVAL;
949 }
950 }
951
fb1d9738
JB		 952 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
953 if (!vfbd) {
954 ret = -ENOMEM;
955 goto out_err1;
956 }
957
958 ret = drm_framebuffer_init(dev, &vfbd->base.base,
959 &vmw_framebuffer_dmabuf_funcs);
960 if (ret)
961 goto out_err2;
962
963 if (!vmw_dmabuf_reference(dmabuf)) {
964 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
965 goto out_err3;
966 }
967
d3216a0c
TH		 968 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
969 vfbd->base.base.pitch = mode_cmd->pitch;
970 vfbd->base.base.depth = mode_cmd->depth;
971 vfbd->base.base.width = mode_cmd->width;
972 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 973 if (!dev_priv->sou_priv) {
974 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
975 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
976 }
2fcd5a73 977 vfbd->base.dmabuf = true;
fb1d9738 978 vfbd->buffer = dmabuf;
90ff18bc 979 vfbd->base.user_handle = mode_cmd->handle;
fb1d9738
JB		 980 *out = &vfbd->base;
981
982 return 0;
983
984out_err3:
985 drm_framebuffer_cleanup(&vfbd->base.base);
986out_err2:
987 kfree(vfbd);
988out_err1:
989 return ret;
990}
991
992/*
993 * Generic Kernel modesetting functions
994 */
995
996static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
997 struct drm_file *file_priv,
998 struct drm_mode_fb_cmd *mode_cmd)
999{
1000 struct vmw_private *dev_priv = vmw_priv(dev);
1001 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
1002 struct vmw_framebuffer *vfb = NULL;
1003 struct vmw_surface *surface = NULL;
1004 struct vmw_dma_buffer *bo = NULL;
90ff18bc 1005 struct ttm_base_object *user_obj;
e133e737 1006 u64 required_size;
fb1d9738
JB		 1007 int ret;
1008
d3216a0c
TH		 1009 /**
1010 * This code should be conditioned on Screen Objects not being used.
1011 * If screen objects are used, we can allocate a GMR to hold the
1012 * requested framebuffer.
1013 */
1014
1015 required_size = mode_cmd->pitch * mode_cmd->height;
e133e737 1016 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c 1017 DRM_ERROR("VRAM size is too small for requested mode.\n");
d9826409 1018 return ERR_PTR(-ENOMEM);
d3216a0c
TH		 1019 }
1020
90ff18bc
TH		 1021 /*
1022 * Take a reference on the user object of the resource
1023 * backing the kms fb. This ensures that user-space handle
1024 * lookups on that resource will always work as long as
1025 * it's registered with a kms framebuffer. This is important,
1026 * since vmw_execbuf_process identifies resources in the
1027 * command stream using user-space handles.
1028 */
1029
1030 user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
1031 if (unlikely(user_obj == NULL)) {
1032 DRM_ERROR("Could not locate requested kms frame buffer.\n");
1033 return ERR_PTR(-ENOENT);
1034 }
1035
d3216a0c
TH		 1036 /**
1037 * End conditioned code.
1038 */
1039
7a73ba74
TH		 1040 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
1041 mode_cmd->handle, &surface);
fb1d9738
JB		 1042 if (ret)
1043 goto try_dmabuf;
1044
5ffdb658
JB		 1045 if (!surface->scanout)
1046 goto err_not_scanout;
1047
3a939a5e
TH		 1048 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
1049 &vfb, mode_cmd);
fb1d9738
JB		 1050
1051 /* vmw_user_surface_lookup takes one ref so does new_fb */
1052 vmw_surface_unreference(&surface);
1053
1054 if (ret) {
1055 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1056 ttm_base_object_unref(&user_obj);
cce13ff7 1057 return ERR_PTR(ret);
90ff18bc
TH		 1058 } else
1059 vfb->user_obj = user_obj;
fb1d9738
JB		 1060 return &vfb->base;
1061
1062try_dmabuf:
1063 DRM_INFO("%s: trying buffer\n", __func__);
1064
1065 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
1066 if (ret) {
1067 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 1068 return ERR_PTR(-ENOENT);
fb1d9738
JB		 1069 }
1070
1071 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
d3216a0c 1072 mode_cmd);
fb1d9738
JB		 1073
1074 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
1075 vmw_dmabuf_unreference(&bo);
1076
1077 if (ret) {
1078 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1079 ttm_base_object_unref(&user_obj);
cce13ff7 1080 return ERR_PTR(ret);
90ff18bc
TH		 1081 } else
1082 vfb->user_obj = user_obj;
fb1d9738
JB		 1083
1084 return &vfb->base;
5ffdb658
JB		 1085
1086err_not_scanout:
1087 DRM_ERROR("surface not marked as scanout\n");
1088 /* vmw_user_surface_lookup takes one ref */
1089 vmw_surface_unreference(&surface);
90ff18bc 1090 ttm_base_object_unref(&user_obj);
5ffdb658 1091
cce13ff7 1092 return ERR_PTR(-EINVAL);
fb1d9738
JB		 1093}
1094
fb1d9738
JB		 1095static struct drm_mode_config_funcs vmw_kms_funcs = {
1096 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 1097};
1098
2fcd5a73
JB		 1099int vmw_kms_present(struct vmw_private *dev_priv,
1100 struct drm_file *file_priv,
1101 struct vmw_framebuffer *vfb,
1102 struct vmw_surface *surface,
1103 uint32_t sid,
1104 int32_t destX, int32_t destY,
1105 struct drm_vmw_rect *clips,
1106 uint32_t num_clips)
1107{
c6ca8391
JB		 1108 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1109 struct drm_crtc *crtc;
2fcd5a73 1110 size_t fifo_size;
c6ca8391
JB		 1111 int i, k, num_units;
1112 int ret = 0; /* silence warning */
2fcd5a73
JB		 1113
1114 struct {
1115 SVGA3dCmdHeader header;
1116 SVGA3dCmdBlitSurfaceToScreen body;
1117 } *cmd;
1118 SVGASignedRect *blits;
1119
c6ca8391
JB		 1120 num_units = 0;
1121 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1122 if (crtc->fb != &vfb->base)
1123 continue;
1124 units[num_units++] = vmw_crtc_to_du(crtc);
1125 }
1126
2fcd5a73
JB		 1127 BUG_ON(surface == NULL);
1128 BUG_ON(!clips || !num_clips);
1129
1130 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
1131 cmd = kmalloc(fifo_size, GFP_KERNEL);
1132 if (unlikely(cmd == NULL)) {
1133 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1134 return -ENOMEM;
1135 }
1136
c6ca8391 1137 /* only need to do this once */
2fcd5a73 1138 memset(cmd, 0, fifo_size);
2fcd5a73
JB		 1139 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
1140 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
1141
2fcd5a73
JB		 1142 cmd->body.srcRect.left = 0;
1143 cmd->body.srcRect.right = surface->sizes[0].width;
1144 cmd->body.srcRect.top = 0;
1145 cmd->body.srcRect.bottom = surface->sizes[0].height;
1146
2fcd5a73
JB		 1147 blits = (SVGASignedRect *)&cmd[1];
1148 for (i = 0; i < num_clips; i++) {
1149 blits[i].left = clips[i].x;
1150 blits[i].right = clips[i].x + clips[i].w;
1151 blits[i].top = clips[i].y;
1152 blits[i].bottom = clips[i].y + clips[i].h;
1153 }
1154
c6ca8391
JB		 1155 for (k = 0; k < num_units; k++) {
1156 struct vmw_display_unit *unit = units[k];
1157 int clip_x1 = destX - unit->crtc.x;
1158 int clip_y1 = destY - unit->crtc.y;
1159 int clip_x2 = clip_x1 + surface->sizes[0].width;
1160 int clip_y2 = clip_y1 + surface->sizes[0].height;
1161
1162 /* skip any crtcs that misses the clip region */
1163 if (clip_x1 >= unit->crtc.mode.hdisplay ||
1164 clip_y1 >= unit->crtc.mode.vdisplay ||
1165 clip_x2 <= 0 || clip_y2 <= 0)
1166 continue;
1167
1168 /* need to reset sid as it is changed by execbuf */
1169 cmd->body.srcImage.sid = sid;
1170
1171 cmd->body.destScreenId = unit->unit;
1172
1173 /*
1174 * The blit command is a lot more resilient then the
1175 * readback command when it comes to clip rects. So its
1176 * okay to go out of bounds.
1177 */
1178
1179 cmd->body.destRect.left = clip_x1;
1180 cmd->body.destRect.right = clip_x2;
1181 cmd->body.destRect.top = clip_y1;
1182 cmd->body.destRect.bottom = clip_y2;
1183
1184 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
1185 fifo_size, 0, NULL);
1186
1187 if (unlikely(ret != 0))
1188 break;
1189 }
2fcd5a73
JB		 1190
1191 kfree(cmd);
1192
1193 return ret;
1194}
1195
1196int vmw_kms_readback(struct vmw_private *dev_priv,
1197 struct drm_file *file_priv,
1198 struct vmw_framebuffer *vfb,
1199 struct drm_vmw_fence_rep __user *user_fence_rep,
1200 struct drm_vmw_rect *clips,
1201 uint32_t num_clips)
1202{
1203 struct vmw_framebuffer_dmabuf *vfbd =
1204 vmw_framebuffer_to_vfbd(&vfb->base);
1205 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
1206 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1207 struct drm_crtc *crtc;
1208 size_t fifo_size;
1209 int i, k, ret, num_units, blits_pos;
1210
1211 struct {
1212 uint32_t header;
1213 SVGAFifoCmdDefineGMRFB body;
1214 } *cmd;
1215 struct {
1216 uint32_t header;
1217 SVGAFifoCmdBlitScreenToGMRFB body;
1218 } *blits;
1219
1220 num_units = 0;
1221 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1222 if (crtc->fb != &vfb->base)
1223 continue;
1224 units[num_units++] = vmw_crtc_to_du(crtc);
1225 }
1226
1227 BUG_ON(dmabuf == NULL);
1228 BUG_ON(!clips || !num_clips);
1229
1230 /* take a safe guess at fifo size */
1231 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
1232 cmd = kmalloc(fifo_size, GFP_KERNEL);
1233 if (unlikely(cmd == NULL)) {
1234 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1235 return -ENOMEM;
1236 }
1237
1238 memset(cmd, 0, fifo_size);
1239 cmd->header = SVGA_CMD_DEFINE_GMRFB;
1240 cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
1241 cmd->body.format.colorDepth = vfb->base.depth;
1242 cmd->body.format.reserved = 0;
1243 cmd->body.bytesPerLine = vfb->base.pitch;
90ff18bc 1244 cmd->body.ptr.gmrId = vfb->user_handle;
2fcd5a73
JB		 1245 cmd->body.ptr.offset = 0;
1246
1247 blits = (void *)&cmd[1];
1248 blits_pos = 0;
1249 for (i = 0; i < num_units; i++) {
1250 struct drm_vmw_rect *c = clips;
1251 for (k = 0; k < num_clips; k++, c++) {
1252 /* transform clip coords to crtc origin based coords */
1253 int clip_x1 = c->x - units[i]->crtc.x;
1254 int clip_x2 = c->x - units[i]->crtc.x + c->w;
1255 int clip_y1 = c->y - units[i]->crtc.y;
1256 int clip_y2 = c->y - units[i]->crtc.y + c->h;
1257 int dest_x = c->x;
1258 int dest_y = c->y;
1259
1260 /* compensate for clipping, we negate
1261 * a negative number and add that.
1262 */
1263 if (clip_x1 < 0)
1264 dest_x += -clip_x1;
1265 if (clip_y1 < 0)
1266 dest_y += -clip_y1;
1267
1268 /* clip */
1269 clip_x1 = max(clip_x1, 0);
1270 clip_y1 = max(clip_y1, 0);
1271 clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
1272 clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
1273
1274 /* and cull any rects that misses the crtc */
1275 if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
1276 clip_y1 >= units[i]->crtc.mode.vdisplay ||
1277 clip_x2 <= 0 || clip_y2 <= 0)
1278 continue;
1279
1280 blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1281 blits[blits_pos].body.srcScreenId = units[i]->unit;
1282 blits[blits_pos].body.destOrigin.x = dest_x;
1283 blits[blits_pos].body.destOrigin.y = dest_y;
1284
1285 blits[blits_pos].body.srcRect.left = clip_x1;
1286 blits[blits_pos].body.srcRect.top = clip_y1;
1287 blits[blits_pos].body.srcRect.right = clip_x2;
1288 blits[blits_pos].body.srcRect.bottom = clip_y2;
1289 blits_pos++;
1290 }
1291 }
1292 /* reset size here and use calculated exact size from loops */
1293 fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
1294
1295 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
1296 0, user_fence_rep);
1297
1298 kfree(cmd);
1299
1300 return ret;
1301}
1302
fb1d9738
JB		 1303int vmw_kms_init(struct vmw_private *dev_priv)
1304{
1305 struct drm_device *dev = dev_priv->dev;
1306 int ret;
1307
1308 drm_mode_config_init(dev);
1309 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 1310 dev->mode_config.min_width = 1;
1311 dev->mode_config.min_height = 1;
7e71f8a5
JB		 1312 /* assumed largest fb size */
1313 dev->mode_config.max_width = 8192;
1314 dev->mode_config.max_height = 8192;
fb1d9738 1315
56d1c78d
JB		 1316 ret = vmw_kms_init_screen_object_display(dev_priv);
1317 if (ret) /* Fallback */
1318 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 1319
1320 return 0;
1321}
1322
1323int vmw_kms_close(struct vmw_private *dev_priv)
1324{
1325 /*
1326 * Docs says we should take the lock before calling this function
1327 * but since it destroys encoders and our destructor calls
1328 * drm_encoder_cleanup which takes the lock we deadlock.
1329 */
1330 drm_mode_config_cleanup(dev_priv->dev);
c0d18316
JB		 1331 if (dev_priv->sou_priv)
1332 vmw_kms_close_screen_object_display(dev_priv);
1333 else
1334 vmw_kms_close_legacy_display_system(dev_priv);
fb1d9738
JB		 1335 return 0;
1336}
1337
1338int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *file_priv)
1340{
1341 struct drm_vmw_cursor_bypass_arg *arg = data;
1342 struct vmw_display_unit *du;
1343 struct drm_mode_object *obj;
1344 struct drm_crtc *crtc;
1345 int ret = 0;
1346
1347
1348 mutex_lock(&dev->mode_config.mutex);
1349 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
1350
1351 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1352 du = vmw_crtc_to_du(crtc);
1353 du->hotspot_x = arg->xhot;
1354 du->hotspot_y = arg->yhot;
1355 }
1356
1357 mutex_unlock(&dev->mode_config.mutex);
1358 return 0;
1359 }
1360
1361 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
1362 if (!obj) {
1363 ret = -EINVAL;
1364 goto out;
1365 }
1366
1367 crtc = obj_to_crtc(obj);
1368 du = vmw_crtc_to_du(crtc);
1369
1370 du->hotspot_x = arg->xhot;
1371 du->hotspot_y = arg->yhot;
1372
1373out:
1374 mutex_unlock(&dev->mode_config.mutex);
1375
1376 return ret;
1377}
1378
0bef23f9 1379int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 1380 unsigned width, unsigned height, unsigned pitch,
6558429b 1381 unsigned bpp, unsigned depth)
fb1d9738 1382{
d7e1958d
JB		 1383 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1384 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1385 else if (vmw_fifo_have_pitchlock(vmw_priv))
1386 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
1387 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1388 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 1389 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 1390
1391 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1392 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
1393 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
1394 return -EINVAL;
1395 }
1396
1397 return 0;
d7e1958d 1398}
fb1d9738 1399
d7e1958d
JB		 1400int vmw_kms_save_vga(struct vmw_private *vmw_priv)
1401{
7c4f7780
TH		 1402 struct vmw_vga_topology_state *save;
1403 uint32_t i;
1404
fb1d9738
JB		 1405 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1406 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1407 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1408 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1409 vmw_priv->vga_pitchlock =
7c4f7780 1410 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1411 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1412 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1413 SVGA_FIFO_PITCHLOCK);
1414
1415 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1416 return 0;
fb1d9738 1417
7c4f7780
TH		 1418 vmw_priv->num_displays = vmw_read(vmw_priv,
1419 SVGA_REG_NUM_GUEST_DISPLAYS);
1420
029e50bf
TH		 1421 if (vmw_priv->num_displays == 0)
1422 vmw_priv->num_displays = 1;
1423
7c4f7780
TH		 1424 for (i = 0; i < vmw_priv->num_displays; ++i) {
1425 save = &vmw_priv->vga_save[i];
1426 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1427 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1428 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1429 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1430 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1431 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1432 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1433 if (i == 0 && vmw_priv->num_displays == 1 &&
1434 save->width == 0 && save->height == 0) {
1435
1436 /*
1437 * It should be fairly safe to assume that these
1438 * values are uninitialized.
1439 */
1440
1441 save->width = vmw_priv->vga_width - save->pos_x;
1442 save->height = vmw_priv->vga_height - save->pos_y;
1443 }
7c4f7780 1444 }
30c78bb8 1445
fb1d9738
JB		 1446 return 0;
1447}
1448
1449int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1450{
7c4f7780
TH		 1451 struct vmw_vga_topology_state *save;
1452 uint32_t i;
1453
fb1d9738
JB		 1454 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1455 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1456 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1457 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1458 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1459 vmw_priv->vga_pitchlock);
1460 else if (vmw_fifo_have_pitchlock(vmw_priv))
1461 iowrite32(vmw_priv->vga_pitchlock,
1462 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1463
7c4f7780
TH		 1464 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1465 return 0;
1466
1467 for (i = 0; i < vmw_priv->num_displays; ++i) {
1468 save = &vmw_priv->vga_save[i];
1469 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1470 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1471 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1472 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1473 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1474 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1475 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1476 }
1477
fb1d9738
JB		 1478 return 0;
1479}
d8bd19d2 1480
e133e737
TH		 1481bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1482 uint32_t pitch,
1483 uint32_t height)
1484{
1485 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1486}
1487
1c482ab3
JB		 1488
1489/**
1490 * Function called by DRM code called with vbl_lock held.
1491 */
7a1c2f6c
TH		 1492u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1493{
1494 return 0;
1495}
626ab771 1496
1c482ab3
JB		 1497/**
1498 * Function called by DRM code called with vbl_lock held.
1499 */
1500int vmw_enable_vblank(struct drm_device *dev, int crtc)
1501{
1502 return -ENOSYS;
1503}
1504
1505/**
1506 * Function called by DRM code called with vbl_lock held.
1507 */
1508void vmw_disable_vblank(struct drm_device *dev, int crtc)
1509{
1510}
1511
626ab771
JB		 1512
1513/*
1514 * Small shared kms functions.
1515 */
1516
1517int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1518 struct drm_vmw_rect *rects)
1519{
1520 struct drm_device *dev = dev_priv->dev;
1521 struct vmw_display_unit *du;
1522 struct drm_connector *con;
626ab771
JB		 1523
1524 mutex_lock(&dev->mode_config.mutex);
1525
1526#if 0
6ea77d13
TH		 1527 {
1528 unsigned int i;
1529
1530 DRM_INFO("%s: new layout ", __func__);
1531 for (i = 0; i < num; i++)
1532 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1533 rects[i].w, rects[i].h);
1534 DRM_INFO("\n");
1535 }
626ab771
JB		 1536#endif
1537
1538 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1539 du = vmw_connector_to_du(con);
1540 if (num > du->unit) {
1541 du->pref_width = rects[du->unit].w;
1542 du->pref_height = rects[du->unit].h;
1543 du->pref_active = true;
cd2b89e7
TH		 1544 du->gui_x = rects[du->unit].x;
1545 du->gui_y = rects[du->unit].y;
626ab771
JB		 1546 } else {
1547 du->pref_width = 800;
1548 du->pref_height = 600;
1549 du->pref_active = false;
1550 }
1551 con->status = vmw_du_connector_detect(con, true);
1552 }
1553
1554 mutex_unlock(&dev->mode_config.mutex);
1555
1556 return 0;
1557}
1558
1559void vmw_du_crtc_save(struct drm_crtc *crtc)
1560{
1561}
1562
1563void vmw_du_crtc_restore(struct drm_crtc *crtc)
1564{
1565}
1566
1567void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1568 u16 *r, u16 *g, u16 *b,
1569 uint32_t start, uint32_t size)
1570{
1571 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1572 int i;
1573
1574 for (i = 0; i < size; i++) {
1575 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1576 r[i], g[i], b[i]);
1577 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1578 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1579 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1580 }
1581}
1582
1583void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1584{
1585}
1586
1587void vmw_du_connector_save(struct drm_connector *connector)
1588{
1589}
1590
1591void vmw_du_connector_restore(struct drm_connector *connector)
1592{
1593}
1594
1595enum drm_connector_status
1596vmw_du_connector_detect(struct drm_connector *connector, bool force)
1597{
1598 uint32_t num_displays;
1599 struct drm_device *dev = connector->dev;
1600 struct vmw_private *dev_priv = vmw_priv(dev);
cd2b89e7 1601 struct vmw_display_unit *du = vmw_connector_to_du(connector);
626ab771
JB		 1602
1603 mutex_lock(&dev_priv->hw_mutex);
1604 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1605 mutex_unlock(&dev_priv->hw_mutex);
1606
cd2b89e7
TH		 1607 return ((vmw_connector_to_du(connector)->unit < num_displays &&
1608 du->pref_active) ?
626ab771
JB		 1609 connector_status_connected : connector_status_disconnected);
1610}
1611
1612static struct drm_display_mode vmw_kms_connector_builtin[] = {
1613 /* 640x480@60Hz */
1614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1615 752, 800, 0, 480, 489, 492, 525, 0,
1616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1617 /* 800x600@60Hz */
1618 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1619 968, 1056, 0, 600, 601, 605, 628, 0,
1620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1621 /* 1024x768@60Hz */
1622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1623 1184, 1344, 0, 768, 771, 777, 806, 0,
1624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1625 /* 1152x864@75Hz */
1626 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1627 1344, 1600, 0, 864, 865, 868, 900, 0,
1628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1629 /* 1280x768@60Hz */
1630 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1631 1472, 1664, 0, 768, 771, 778, 798, 0,
1632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1633 /* 1280x800@60Hz */
1634 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1635 1480, 1680, 0, 800, 803, 809, 831, 0,
1636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1637 /* 1280x960@60Hz */
1638 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1639 1488, 1800, 0, 960, 961, 964, 1000, 0,
1640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1641 /* 1280x1024@60Hz */
1642 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1643 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1645 /* 1360x768@60Hz */
1646 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1647 1536, 1792, 0, 768, 771, 777, 795, 0,
1648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1649 /* 1440x1050@60Hz */
1650 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1651 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1653 /* 1440x900@60Hz */
1654 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1655 1672, 1904, 0, 900, 903, 909, 934, 0,
1656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1657 /* 1600x1200@60Hz */
1658 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1659 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1661 /* 1680x1050@60Hz */
1662 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1663 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1665 /* 1792x1344@60Hz */
1666 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1667 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1669 /* 1853x1392@60Hz */
1670 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1671 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1673 /* 1920x1200@60Hz */
1674 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1675 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1676 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1677 /* 1920x1440@60Hz */
1678 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1679 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1681 /* 2560x1600@60Hz */
1682 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1683 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1685 /* Terminate */
1686 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1687};
1688
1543b4dd
TH		 1689/**
1690 * vmw_guess_mode_timing - Provide fake timings for a
1691 * 60Hz vrefresh mode.
1692 *
1693 * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
1694 * members filled in.
1695 */
1696static void vmw_guess_mode_timing(struct drm_display_mode *mode)
1697{
1698 mode->hsync_start = mode->hdisplay + 50;
1699 mode->hsync_end = mode->hsync_start + 50;
1700 mode->htotal = mode->hsync_end + 50;
1701
1702 mode->vsync_start = mode->vdisplay + 50;
1703 mode->vsync_end = mode->vsync_start + 50;
1704 mode->vtotal = mode->vsync_end + 50;
1705
1706 mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
1707 mode->vrefresh = drm_mode_vrefresh(mode);
1708}
1709
1710
626ab771
JB		 1711int vmw_du_connector_fill_modes(struct drm_connector *connector,
1712 uint32_t max_width, uint32_t max_height)
1713{
1714 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1715 struct drm_device *dev = connector->dev;
1716 struct vmw_private *dev_priv = vmw_priv(dev);
1717 struct drm_display_mode *mode = NULL;
1718 struct drm_display_mode *bmode;
1719 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1720 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1723 };
1724 int i;
1725
1726 /* Add preferred mode */
1727 {
1728 mode = drm_mode_duplicate(dev, &prefmode);
1729 if (!mode)
1730 return 0;
1731 mode->hdisplay = du->pref_width;
1732 mode->vdisplay = du->pref_height;
1543b4dd 1733 vmw_guess_mode_timing(mode);
55bde5b2 1734
626ab771
JB		 1735 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1736 mode->vdisplay)) {
1737 drm_mode_probed_add(connector, mode);
55bde5b2
JB		 1738 } else {
1739 drm_mode_destroy(dev, mode);
1740 mode = NULL;
1741 }
626ab771 1742
55bde5b2
JB		 1743 if (du->pref_mode) {
1744 list_del_init(&du->pref_mode->head);
1745 drm_mode_destroy(dev, du->pref_mode);
626ab771 1746 }
55bde5b2
JB		 1747
1748 /* mode might be null here, this is intended */
1749 du->pref_mode = mode;
626ab771
JB		 1750 }
1751
1752 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1753 bmode = &vmw_kms_connector_builtin[i];
1754 if (bmode->hdisplay > max_width ||
1755 bmode->vdisplay > max_height)
1756 continue;
1757
1758 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1759 bmode->vdisplay))
1760 continue;
1761
1762 mode = drm_mode_duplicate(dev, bmode);
1763 if (!mode)
1764 return 0;
1765 mode->vrefresh = drm_mode_vrefresh(mode);
1766
1767 drm_mode_probed_add(connector, mode);
1768 }
1769
d41025c0
JB		 1770 /* Move the prefered mode first, help apps pick the right mode. */
1771 if (du->pref_mode)
1772 list_move(&du->pref_mode->head, &connector->probed_modes);
1773
626ab771
JB		 1774 drm_mode_connector_list_update(connector);
1775
1776 return 1;
1777}
1778
1779int vmw_du_connector_set_property(struct drm_connector *connector,
1780 struct drm_property *property,
1781 uint64_t val)
1782{
1783 return 0;
1784}
cd2b89e7
TH		 1785
1786
1787int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
1788 struct drm_file *file_priv)
1789{
1790 struct vmw_private *dev_priv = vmw_priv(dev);
1791 struct drm_vmw_update_layout_arg *arg =
1792 (struct drm_vmw_update_layout_arg *)data;
1793 struct vmw_master *vmaster = vmw_master(file_priv->master);
1794 void __user *user_rects;
1795 struct drm_vmw_rect *rects;
1796 unsigned rects_size;
1797 int ret;
1798 int i;
1799 struct drm_mode_config *mode_config = &dev->mode_config;
1800
1801 ret = ttm_read_lock(&vmaster->lock, true);
1802 if (unlikely(ret != 0))
1803 return ret;
1804
1805 if (!arg->num_outputs) {
1806 struct drm_vmw_rect def_rect = {0, 0, 800, 600};
1807 vmw_du_update_layout(dev_priv, 1, &def_rect);
1808 goto out_unlock;
1809 }
1810
1811 rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
1812 rects = kzalloc(rects_size, GFP_KERNEL);
1813 if (unlikely(!rects)) {
1814 ret = -ENOMEM;
1815 goto out_unlock;
1816 }
1817
1818 user_rects = (void __user *)(unsigned long)arg->rects;
1819 ret = copy_from_user(rects, user_rects, rects_size);
1820 if (unlikely(ret != 0)) {
1821 DRM_ERROR("Failed to get rects.\n");
1822 ret = -EFAULT;
1823 goto out_free;
1824 }
1825
1826 for (i = 0; i < arg->num_outputs; ++i) {
1827 if (rects->x < 0 ||
1828 rects->y < 0 ||
1829 rects->x + rects->w > mode_config->max_width ||
1830 rects->y + rects->h > mode_config->max_height) {
1831 DRM_ERROR("Invalid GUI layout.\n");
1832 ret = -EINVAL;
1833 goto out_free;
1834 }
1835 }
1836
1837 vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
1838
1839out_free:
1840 kfree(rects);
1841out_unlock:
1842 ttm_read_unlock(&vmaster->lock);
1843 return ret;
1844}
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