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vmwgfx: Bump driver minor to advertise support for new ioctls.
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
108 if (handle) {
7a73ba74
TH		 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface);
fb1d9738
JB		 111 if (!ret) {
112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n");
114 return -EINVAL;
115 }
116 } else {
117 ret = vmw_user_dmabuf_lookup(tfile,
118 handle, &dmabuf);
119 if (ret) {
120 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
121 return -EINVAL;
122 }
123 }
124 }
125
126 /* takedown old cursor */
127 if (du->cursor_surface) {
128 du->cursor_surface->snooper.crtc = NULL;
129 vmw_surface_unreference(&du->cursor_surface);
130 }
131 if (du->cursor_dmabuf)
132 vmw_dmabuf_unreference(&du->cursor_dmabuf);
133
134 /* setup new image */
135 if (surface) {
136 /* vmw_user_surface_lookup takes one reference */
137 du->cursor_surface = surface;
138
139 du->cursor_surface->snooper.crtc = crtc;
140 du->cursor_age = du->cursor_surface->snooper.age;
141 vmw_cursor_update_image(dev_priv, surface->snooper.image,
142 64, 64, du->hotspot_x, du->hotspot_y);
143 } else if (dmabuf) {
144 struct ttm_bo_kmap_obj map;
145 unsigned long kmap_offset;
146 unsigned long kmap_num;
147 void *virtual;
148 bool dummy;
149
150 /* vmw_user_surface_lookup takes one reference */
151 du->cursor_dmabuf = dmabuf;
152
153 kmap_offset = 0;
154 kmap_num = (64*64*4) >> PAGE_SHIFT;
155
156 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
157 if (unlikely(ret != 0)) {
158 DRM_ERROR("reserve failed\n");
159 return -EINVAL;
160 }
161
162 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
163 if (unlikely(ret != 0))
164 goto err_unreserve;
165
166 virtual = ttm_kmap_obj_virtual(&map, &dummy);
167 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
168 du->hotspot_x, du->hotspot_y);
169
170 ttm_bo_kunmap(&map);
171err_unreserve:
172 ttm_bo_unreserve(&dmabuf->base);
173
174 } else {
175 vmw_cursor_update_position(dev_priv, false, 0, 0);
176 return 0;
177 }
178
179 vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
180
181 return 0;
182}
183
184int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
185{
186 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
187 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
188 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
189
190 du->cursor_x = x + crtc->x;
191 du->cursor_y = y + crtc->y;
192
193 vmw_cursor_update_position(dev_priv, shown,
194 du->cursor_x, du->cursor_y);
195
196 return 0;
197}
198
199void vmw_kms_cursor_snoop(struct vmw_surface *srf,
200 struct ttm_object_file *tfile,
201 struct ttm_buffer_object *bo,
202 SVGA3dCmdHeader *header)
203{
204 struct ttm_bo_kmap_obj map;
205 unsigned long kmap_offset;
206 unsigned long kmap_num;
207 SVGA3dCopyBox *box;
208 unsigned box_count;
209 void *virtual;
210 bool dummy;
211 struct vmw_dma_cmd {
212 SVGA3dCmdHeader header;
213 SVGA3dCmdSurfaceDMA dma;
214 } *cmd;
215 int ret;
216
217 cmd = container_of(header, struct vmw_dma_cmd, header);
218
219 /* No snooper installed */
220 if (!srf->snooper.image)
221 return;
222
223 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
224 DRM_ERROR("face and mipmap for cursors should never != 0\n");
225 return;
226 }
227
228 if (cmd->header.size < 64) {
229 DRM_ERROR("at least one full copy box must be given\n");
230 return;
231 }
232
233 box = (SVGA3dCopyBox *)&cmd[1];
234 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
235 sizeof(SVGA3dCopyBox);
236
237 if (cmd->dma.guest.pitch != (64 * 4) ||
238 cmd->dma.guest.ptr.offset % PAGE_SIZE ||
239 box->x != 0 || box->y != 0 || box->z != 0 ||
240 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
241 box->w != 64 || box->h != 64 || box->d != 1 ||
242 box_count != 1) {
243 /* TODO handle none page aligned offsets */
244 /* TODO handle partial uploads and pitch != 256 */
245 /* TODO handle more then one copy (size != 64) */
25985edc 246 DRM_ERROR("lazy programmer, can't handle weird stuff\n");
fb1d9738
JB		 247 return;
248 }
249
250 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
251 kmap_num = (64*64*4) >> PAGE_SHIFT;
252
253 ret = ttm_bo_reserve(bo, true, false, false, 0);
254 if (unlikely(ret != 0)) {
255 DRM_ERROR("reserve failed\n");
256 return;
257 }
258
259 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
260 if (unlikely(ret != 0))
261 goto err_unreserve;
262
263 virtual = ttm_kmap_obj_virtual(&map, &dummy);
264
265 memcpy(srf->snooper.image, virtual, 64*64*4);
266 srf->snooper.age++;
267
268 /* we can't call this function from this function since execbuf has
269 * reserved fifo space.
270 *
271 * if (srf->snooper.crtc)
272 * vmw_ldu_crtc_cursor_update_image(dev_priv,
273 * srf->snooper.image, 64, 64,
274 * du->hotspot_x, du->hotspot_y);
275 */
276
277 ttm_bo_kunmap(&map);
278err_unreserve:
279 ttm_bo_unreserve(bo);
280}
281
282void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
283{
284 struct drm_device *dev = dev_priv->dev;
285 struct vmw_display_unit *du;
286 struct drm_crtc *crtc;
287
288 mutex_lock(&dev->mode_config.mutex);
289
290 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
291 du = vmw_crtc_to_du(crtc);
292 if (!du->cursor_surface ||
293 du->cursor_age == du->cursor_surface->snooper.age)
294 continue;
295
296 du->cursor_age = du->cursor_surface->snooper.age;
297 vmw_cursor_update_image(dev_priv,
298 du->cursor_surface->snooper.image,
299 64, 64, du->hotspot_x, du->hotspot_y);
300 }
301
302 mutex_unlock(&dev->mode_config.mutex);
303}
304
305/*
306 * Generic framebuffer code
307 */
308
309int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
310 struct drm_file *file_priv,
311 unsigned int *handle)
312{
313 if (handle)
314 handle = 0;
315
316 return 0;
317}
318
319/*
320 * Surface framebuffer code
321 */
322
323#define vmw_framebuffer_to_vfbs(x) \
324 container_of(x, struct vmw_framebuffer_surface, base.base)
325
326struct vmw_framebuffer_surface {
327 struct vmw_framebuffer base;
328 struct vmw_surface *surface;
22ee861c 329 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 330 struct list_head head;
331 struct drm_master *master;
fb1d9738
JB		 332};
333
334void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
335{
3a939a5e 336 struct vmw_framebuffer_surface *vfbs =
fb1d9738 337 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 338 struct vmw_master *vmaster = vmw_master(vfbs->master);
339
340
341 mutex_lock(&vmaster->fb_surf_mutex);
342 list_del(&vfbs->head);
343 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 344
3a939a5e 345 drm_master_put(&vfbs->master);
fb1d9738 346 drm_framebuffer_cleanup(framebuffer);
3a939a5e 347 vmw_surface_unreference(&vfbs->surface);
90ff18bc 348 ttm_base_object_unref(&vfbs->base.user_obj);
fb1d9738 349
3a939a5e 350 kfree(vfbs);
fb1d9738
JB		 351}
352
56d1c78d 353static int do_surface_dirty_sou(struct vmw_private *dev_priv,
90ff18bc 354 struct drm_file *file_priv,
56d1c78d
JB		 355 struct vmw_framebuffer *framebuffer,
356 struct vmw_surface *surf,
357 unsigned flags, unsigned color,
358 struct drm_clip_rect *clips,
359 unsigned num_clips, int inc)
360{
361 int left = clips->x2, right = clips->x1;
362 int top = clips->y2, bottom = clips->y1;
363 size_t fifo_size;
90ff18bc 364 int i, ret;
56d1c78d
JB		 365
366 struct {
367 SVGA3dCmdHeader header;
368 SVGA3dCmdBlitSurfaceToScreen body;
369 } *cmd;
370
371
372 fifo_size = sizeof(*cmd);
90ff18bc 373 cmd = kzalloc(fifo_size, GFP_KERNEL);
56d1c78d 374 if (unlikely(cmd == NULL)) {
90ff18bc 375 DRM_ERROR("Temporary fifo memory alloc failed.\n");
56d1c78d
JB		 376 return -ENOMEM;
377 }
378
56d1c78d
JB		 379 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
380 cmd->header.size = cpu_to_le32(sizeof(cmd->body));
381
90ff18bc 382 cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
56d1c78d
JB		 383 cmd->body.destScreenId = SVGA_ID_INVALID; /* virtual coords */
384
385 for (i = 0; i < num_clips; i++, clips += inc) {
386 left = min_t(int, left, (int)clips->x1);
387 right = max_t(int, right, (int)clips->x2);
388 top = min_t(int, top, (int)clips->y1);
389 bottom = max_t(int, bottom, (int)clips->y2);
390 }
391
392 cmd->body.srcRect.left = left;
393 cmd->body.srcRect.right = right;
394 cmd->body.srcRect.top = top;
395 cmd->body.srcRect.bottom = bottom;
396
397 cmd->body.destRect.left = left;
398 cmd->body.destRect.right = right;
399 cmd->body.destRect.top = top;
400 cmd->body.destRect.bottom = bottom;
401
90ff18bc
TH		 402 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
403 0, NULL);
404 kfree(cmd);
56d1c78d 405
90ff18bc 406 return ret;
5deb65cf 407}
fb1d9738
JB		 408
409int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 410 struct drm_file *file_priv,
fb1d9738
JB		 411 unsigned flags, unsigned color,
412 struct drm_clip_rect *clips,
413 unsigned num_clips)
414{
415 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 416 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 417 struct vmw_framebuffer_surface *vfbs =
418 vmw_framebuffer_to_vfbs(framebuffer);
419 struct vmw_surface *surf = vfbs->surface;
420 struct drm_clip_rect norect;
5deb65cf 421 int ret, inc = 1;
fb1d9738 422
3a939a5e
TH		 423 if (unlikely(vfbs->master != file_priv->master))
424 return -EINVAL;
425
01e81419
JB		 426 /* Require ScreenObject support for 3D */
427 if (!dev_priv->sou_priv)
428 return -EINVAL;
429
3a939a5e
TH		 430 ret = ttm_read_lock(&vmaster->lock, true);
431 if (unlikely(ret != 0))
432 return ret;
433
fb1d9738
JB		 434 if (!num_clips) {
435 num_clips = 1;
436 clips = &norect;
437 norect.x1 = norect.y1 = 0;
438 norect.x2 = framebuffer->width;
439 norect.y2 = framebuffer->height;
440 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
441 num_clips /= 2;
442 inc = 2; /* skip source rects */
443 }
444
90ff18bc 445 ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base, surf,
01e81419
JB		 446 flags, color,
447 clips, num_clips, inc);
fb1d9738 448
3a939a5e 449 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 450 return 0;
451}
452
453static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
454 .destroy = vmw_framebuffer_surface_destroy,
455 .dirty = vmw_framebuffer_surface_dirty,
456 .create_handle = vmw_framebuffer_create_handle,
457};
458
d3216a0c 459static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 460 struct drm_file *file_priv,
d3216a0c
TH		 461 struct vmw_surface *surface,
462 struct vmw_framebuffer **out,
463 const struct drm_mode_fb_cmd
464 *mode_cmd)
fb1d9738
JB		 465
466{
467 struct drm_device *dev = dev_priv->dev;
468 struct vmw_framebuffer_surface *vfbs;
d3216a0c 469 enum SVGA3dSurfaceFormat format;
3a939a5e 470 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 471 int ret;
472
01e81419
JB		 473 /* 3D is only supported on HWv8 hosts which supports screen objects */
474 if (!dev_priv->sou_priv)
475 return -ENOSYS;
476
d3216a0c
TH		 477 /*
478 * Sanity checks.
479 */
480
481 if (unlikely(surface->mip_levels[0] != 1 ||
482 surface->num_sizes != 1 ||
483 surface->sizes[0].width < mode_cmd->width ||
484 surface->sizes[0].height < mode_cmd->height ||
485 surface->sizes[0].depth != 1)) {
486 DRM_ERROR("Incompatible surface dimensions "
487 "for requested mode.\n");
488 return -EINVAL;
489 }
490
491 switch (mode_cmd->depth) {
492 case 32:
493 format = SVGA3D_A8R8G8B8;
494 break;
495 case 24:
496 format = SVGA3D_X8R8G8B8;
497 break;
498 case 16:
499 format = SVGA3D_R5G6B5;
500 break;
501 case 15:
502 format = SVGA3D_A1R5G5B5;
503 break;
f01b7ba0
MD		 504 case 8:
505 format = SVGA3D_LUMINANCE8;
506 break;
d3216a0c
TH		 507 default:
508 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
509 return -EINVAL;
510 }
511
512 if (unlikely(format != surface->format)) {
513 DRM_ERROR("Invalid surface format for requested mode.\n");
514 return -EINVAL;
515 }
516
fb1d9738
JB		 517 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
518 if (!vfbs) {
519 ret = -ENOMEM;
520 goto out_err1;
521 }
522
523 ret = drm_framebuffer_init(dev, &vfbs->base.base,
524 &vmw_framebuffer_surface_funcs);
525 if (ret)
526 goto out_err2;
527
528 if (!vmw_surface_reference(surface)) {
529 DRM_ERROR("failed to reference surface %p\n", surface);
530 goto out_err3;
531 }
532
533 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 534 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
535 vfbs->base.base.pitch = mode_cmd->pitch;
536 vfbs->base.base.depth = mode_cmd->depth;
537 vfbs->base.base.width = mode_cmd->width;
538 vfbs->base.base.height = mode_cmd->height;
fb1d9738 539 vfbs->surface = surface;
90ff18bc 540 vfbs->base.user_handle = mode_cmd->handle;
3a939a5e 541 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 542
543 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 544 list_add_tail(&vfbs->head, &vmaster->fb_surf);
545 mutex_unlock(&vmaster->fb_surf_mutex);
546
fb1d9738
JB		 547 *out = &vfbs->base;
548
549 return 0;
550
551out_err3:
552 drm_framebuffer_cleanup(&vfbs->base.base);
553out_err2:
554 kfree(vfbs);
555out_err1:
556 return ret;
557}
558
559/*
560 * Dmabuf framebuffer code
561 */
562
563#define vmw_framebuffer_to_vfbd(x) \
564 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
565
566struct vmw_framebuffer_dmabuf {
567 struct vmw_framebuffer base;
568 struct vmw_dma_buffer *buffer;
569};
570
571void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
572{
573 struct vmw_framebuffer_dmabuf *vfbd =
574 vmw_framebuffer_to_vfbd(framebuffer);
575
576 drm_framebuffer_cleanup(framebuffer);
577 vmw_dmabuf_unreference(&vfbd->buffer);
90ff18bc 578 ttm_base_object_unref(&vfbd->base.user_obj);
fb1d9738
JB		 579
580 kfree(vfbd);
581}
582
5deb65cf
JB		 583static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
584 struct vmw_framebuffer *framebuffer,
585 struct vmw_dma_buffer *buffer,
586 unsigned flags, unsigned color,
587 struct drm_clip_rect *clips,
588 unsigned num_clips, int increment)
589{
590 size_t fifo_size;
591 int i;
592
593 struct {
594 uint32_t header;
595 SVGAFifoCmdUpdate body;
596 } *cmd;
597
598 fifo_size = sizeof(*cmd) * num_clips;
599 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
600 if (unlikely(cmd == NULL)) {
601 DRM_ERROR("Fifo reserve failed.\n");
602 return -ENOMEM;
603 }
604
605 memset(cmd, 0, fifo_size);
606 for (i = 0; i < num_clips; i++, clips += increment) {
607 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
608 cmd[i].body.x = cpu_to_le32(clips->x1);
609 cmd[i].body.y = cpu_to_le32(clips->y1);
610 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
611 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
612 }
613
614 vmw_fifo_commit(dev_priv, fifo_size);
615 return 0;
616}
617
56d1c78d
JB		 618static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
619 struct vmw_private *dev_priv,
620 struct vmw_framebuffer *framebuffer,
621 struct vmw_dma_buffer *buffer,
622 unsigned flags, unsigned color,
623 struct drm_clip_rect *clips,
624 unsigned num_clips, int increment)
625{
56d1c78d
JB		 626 size_t fifo_size;
627 int i, ret;
628
629 struct {
630 uint32_t header;
631 SVGAFifoCmdDefineGMRFB body;
632 } *cmd;
633 struct {
634 uint32_t header;
635 SVGAFifoCmdBlitGMRFBToScreen body;
636 } *blits;
637
638 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips;
639 cmd = kmalloc(fifo_size, GFP_KERNEL);
640 if (unlikely(cmd == NULL)) {
641 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
642 return -ENOMEM;
643 }
644
645 memset(cmd, 0, fifo_size);
646 cmd->header = SVGA_CMD_DEFINE_GMRFB;
647 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
648 cmd->body.format.colorDepth = framebuffer->base.depth;
649 cmd->body.format.reserved = 0;
650 cmd->body.bytesPerLine = framebuffer->base.pitch;
90ff18bc 651 cmd->body.ptr.gmrId = framebuffer->user_handle;
56d1c78d
JB		 652 cmd->body.ptr.offset = 0;
653
654 blits = (void *)&cmd[1];
655 for (i = 0; i < num_clips; i++, clips += increment) {
656 blits[i].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
657 blits[i].body.srcOrigin.x = clips->x1;
658 blits[i].body.srcOrigin.y = clips->y1;
659 blits[i].body.destRect.left = clips->x1;
660 blits[i].body.destRect.top = clips->y1;
661 blits[i].body.destRect.right = clips->x2;
662 blits[i].body.destRect.bottom = clips->y2;
663 }
664
665 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
666 fifo_size, 0, NULL);
667
668 kfree(cmd);
669
670 return ret;
671}
672
fb1d9738 673int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 674 struct drm_file *file_priv,
fb1d9738
JB		 675 unsigned flags, unsigned color,
676 struct drm_clip_rect *clips,
677 unsigned num_clips)
678{
679 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 680 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 681 struct vmw_framebuffer_dmabuf *vfbd =
682 vmw_framebuffer_to_vfbd(framebuffer);
683 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
fb1d9738 684 struct drm_clip_rect norect;
5deb65cf 685 int ret, increment = 1;
fb1d9738 686
3a939a5e
TH		 687 ret = ttm_read_lock(&vmaster->lock, true);
688 if (unlikely(ret != 0))
689 return ret;
690
df1c93ba 691 if (!num_clips) {
fb1d9738
JB		 692 num_clips = 1;
693 clips = &norect;
694 norect.x1 = norect.y1 = 0;
695 norect.x2 = framebuffer->width;
696 norect.y2 = framebuffer->height;
697 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
698 num_clips /= 2;
699 increment = 2;
700 }
701
56d1c78d
JB		 702 if (dev_priv->ldu_priv) {
703 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base, dmabuf,
704 flags, color,
705 clips, num_clips, increment);
706 } else {
707 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
708 dmabuf, flags, color,
709 clips, num_clips, increment);
710 }
fb1d9738 711
3a939a5e 712 ttm_read_unlock(&vmaster->lock);
5deb65cf 713 return ret;
fb1d9738
JB		 714}
715
716static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
717 .destroy = vmw_framebuffer_dmabuf_destroy,
718 .dirty = vmw_framebuffer_dmabuf_dirty,
719 .create_handle = vmw_framebuffer_create_handle,
720};
721
497a3ff9
JB		 722/**
723 * Pin the dmabuffer to the start of vram.
724 */
fb1d9738
JB		 725static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
726{
727 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
728 struct vmw_framebuffer_dmabuf *vfbd =
729 vmw_framebuffer_to_vfbd(&vfb->base);
730 int ret;
731
56d1c78d
JB		 732 /* This code should not be used with screen objects */
733 BUG_ON(dev_priv->sou_priv);
d7e1958d 734
fb1d9738
JB		 735 vmw_overlay_pause_all(dev_priv);
736
d991ef03 737 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 738
fb1d9738
JB		 739 vmw_overlay_resume_all(dev_priv);
740
316ab13a
JB		 741 WARN_ON(ret != 0);
742
fb1d9738
JB		 743 return 0;
744}
745
746static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
747{
748 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
749 struct vmw_framebuffer_dmabuf *vfbd =
750 vmw_framebuffer_to_vfbd(&vfb->base);
751
752 if (!vfbd->buffer) {
753 WARN_ON(!vfbd->buffer);
754 return 0;
755 }
756
d991ef03 757 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 758}
759
d3216a0c
TH		 760static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
761 struct vmw_dma_buffer *dmabuf,
762 struct vmw_framebuffer **out,
763 const struct drm_mode_fb_cmd
764 *mode_cmd)
fb1d9738
JB		 765
766{
767 struct drm_device *dev = dev_priv->dev;
768 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 769 unsigned int requested_size;
fb1d9738
JB		 770 int ret;
771
d3216a0c
TH		 772 requested_size = mode_cmd->height * mode_cmd->pitch;
773 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
774 DRM_ERROR("Screen buffer object size is too small "
775 "for requested mode.\n");
776 return -EINVAL;
777 }
778
c337ada7
JB		 779 /* Limited framebuffer color depth support for screen objects */
780 if (dev_priv->sou_priv) {
781 switch (mode_cmd->depth) {
782 case 32:
783 case 24:
784 /* Only support 32 bpp for 32 and 24 depth fbs */
785 if (mode_cmd->bpp == 32)
786 break;
787
788 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
789 mode_cmd->depth, mode_cmd->bpp);
790 return -EINVAL;
791 case 16:
792 case 15:
793 /* Only support 16 bpp for 16 and 15 depth fbs */
794 if (mode_cmd->bpp == 16)
795 break;
796
797 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
798 mode_cmd->depth, mode_cmd->bpp);
799 return -EINVAL;
800 default:
801 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
802 return -EINVAL;
803 }
804 }
805
fb1d9738
JB		 806 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
807 if (!vfbd) {
808 ret = -ENOMEM;
809 goto out_err1;
810 }
811
812 ret = drm_framebuffer_init(dev, &vfbd->base.base,
813 &vmw_framebuffer_dmabuf_funcs);
814 if (ret)
815 goto out_err2;
816
817 if (!vmw_dmabuf_reference(dmabuf)) {
818 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
819 goto out_err3;
820 }
821
d3216a0c
TH		 822 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
823 vfbd->base.base.pitch = mode_cmd->pitch;
824 vfbd->base.base.depth = mode_cmd->depth;
825 vfbd->base.base.width = mode_cmd->width;
826 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 827 if (!dev_priv->sou_priv) {
828 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
829 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
830 }
2fcd5a73 831 vfbd->base.dmabuf = true;
fb1d9738 832 vfbd->buffer = dmabuf;
90ff18bc 833 vfbd->base.user_handle = mode_cmd->handle;
fb1d9738
JB		 834 *out = &vfbd->base;
835
836 return 0;
837
838out_err3:
839 drm_framebuffer_cleanup(&vfbd->base.base);
840out_err2:
841 kfree(vfbd);
842out_err1:
843 return ret;
844}
845
846/*
847 * Generic Kernel modesetting functions
848 */
849
850static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
851 struct drm_file *file_priv,
852 struct drm_mode_fb_cmd *mode_cmd)
853{
854 struct vmw_private *dev_priv = vmw_priv(dev);
855 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
856 struct vmw_framebuffer *vfb = NULL;
857 struct vmw_surface *surface = NULL;
858 struct vmw_dma_buffer *bo = NULL;
90ff18bc 859 struct ttm_base_object *user_obj;
e133e737 860 u64 required_size;
fb1d9738
JB		 861 int ret;
862
d3216a0c
TH		 863 /**
864 * This code should be conditioned on Screen Objects not being used.
865 * If screen objects are used, we can allocate a GMR to hold the
866 * requested framebuffer.
867 */
868
869 required_size = mode_cmd->pitch * mode_cmd->height;
e133e737 870 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c
TH		 871 DRM_ERROR("VRAM size is too small for requested mode.\n");
872 return NULL;
873 }
874
90ff18bc
TH		 875 /*
876 * Take a reference on the user object of the resource
877 * backing the kms fb. This ensures that user-space handle
878 * lookups on that resource will always work as long as
879 * it's registered with a kms framebuffer. This is important,
880 * since vmw_execbuf_process identifies resources in the
881 * command stream using user-space handles.
882 */
883
884 user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
885 if (unlikely(user_obj == NULL)) {
886 DRM_ERROR("Could not locate requested kms frame buffer.\n");
887 return ERR_PTR(-ENOENT);
888 }
889
d3216a0c
TH		 890 /**
891 * End conditioned code.
892 */
893
7a73ba74
TH		 894 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
895 mode_cmd->handle, &surface);
fb1d9738
JB		 896 if (ret)
897 goto try_dmabuf;
898
5ffdb658
JB		 899 if (!surface->scanout)
900 goto err_not_scanout;
901
3a939a5e
TH		 902 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
903 &vfb, mode_cmd);
fb1d9738
JB		 904
905 /* vmw_user_surface_lookup takes one ref so does new_fb */
906 vmw_surface_unreference(&surface);
907
908 if (ret) {
909 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 910 ttm_base_object_unref(&user_obj);
cce13ff7 911 return ERR_PTR(ret);
90ff18bc
TH		 912 } else
913 vfb->user_obj = user_obj;
fb1d9738
JB		 914 return &vfb->base;
915
916try_dmabuf:
917 DRM_INFO("%s: trying buffer\n", __func__);
918
919 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
920 if (ret) {
921 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 922 return ERR_PTR(-ENOENT);
fb1d9738
JB		 923 }
924
925 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
d3216a0c 926 mode_cmd);
fb1d9738
JB		 927
928 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
929 vmw_dmabuf_unreference(&bo);
930
931 if (ret) {
932 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 933 ttm_base_object_unref(&user_obj);
cce13ff7 934 return ERR_PTR(ret);
90ff18bc
TH		 935 } else
936 vfb->user_obj = user_obj;
fb1d9738
JB		 937
938 return &vfb->base;
5ffdb658
JB		 939
940err_not_scanout:
941 DRM_ERROR("surface not marked as scanout\n");
942 /* vmw_user_surface_lookup takes one ref */
943 vmw_surface_unreference(&surface);
90ff18bc 944 ttm_base_object_unref(&user_obj);
5ffdb658 945
cce13ff7 946 return ERR_PTR(-EINVAL);
fb1d9738
JB		 947}
948
fb1d9738
JB		 949static struct drm_mode_config_funcs vmw_kms_funcs = {
950 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 951};
952
2fcd5a73
JB		 953int vmw_kms_present(struct vmw_private *dev_priv,
954 struct drm_file *file_priv,
955 struct vmw_framebuffer *vfb,
956 struct vmw_surface *surface,
957 uint32_t sid,
958 int32_t destX, int32_t destY,
959 struct drm_vmw_rect *clips,
960 uint32_t num_clips)
961{
962 size_t fifo_size;
963 int i, ret;
964
965 struct {
966 SVGA3dCmdHeader header;
967 SVGA3dCmdBlitSurfaceToScreen body;
968 } *cmd;
969 SVGASignedRect *blits;
970
971 BUG_ON(surface == NULL);
972 BUG_ON(!clips || !num_clips);
973
974 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
975 cmd = kmalloc(fifo_size, GFP_KERNEL);
976 if (unlikely(cmd == NULL)) {
977 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
978 return -ENOMEM;
979 }
980
981 memset(cmd, 0, fifo_size);
982
983 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
984 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
985
986 cmd->body.srcImage.sid = sid;
987 cmd->body.destScreenId = SVGA_ID_INVALID; /* virtual coords */
988
989 cmd->body.srcRect.left = 0;
990 cmd->body.srcRect.right = surface->sizes[0].width;
991 cmd->body.srcRect.top = 0;
992 cmd->body.srcRect.bottom = surface->sizes[0].height;
993
994 cmd->body.destRect.left = destX;
995 cmd->body.destRect.right = destX + surface->sizes[0].width;
996 cmd->body.destRect.top = destY;
997 cmd->body.destRect.bottom = destY + surface->sizes[0].height;
998
999 blits = (SVGASignedRect *)&cmd[1];
1000 for (i = 0; i < num_clips; i++) {
1001 blits[i].left = clips[i].x;
1002 blits[i].right = clips[i].x + clips[i].w;
1003 blits[i].top = clips[i].y;
1004 blits[i].bottom = clips[i].y + clips[i].h;
1005 }
1006
1007 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
1008 fifo_size, 0, NULL);
1009
1010 kfree(cmd);
1011
1012 return ret;
1013}
1014
1015int vmw_kms_readback(struct vmw_private *dev_priv,
1016 struct drm_file *file_priv,
1017 struct vmw_framebuffer *vfb,
1018 struct drm_vmw_fence_rep __user *user_fence_rep,
1019 struct drm_vmw_rect *clips,
1020 uint32_t num_clips)
1021{
1022 struct vmw_framebuffer_dmabuf *vfbd =
1023 vmw_framebuffer_to_vfbd(&vfb->base);
1024 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
1025 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1026 struct drm_crtc *crtc;
1027 size_t fifo_size;
1028 int i, k, ret, num_units, blits_pos;
1029
1030 struct {
1031 uint32_t header;
1032 SVGAFifoCmdDefineGMRFB body;
1033 } *cmd;
1034 struct {
1035 uint32_t header;
1036 SVGAFifoCmdBlitScreenToGMRFB body;
1037 } *blits;
1038
1039 num_units = 0;
1040 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1041 if (crtc->fb != &vfb->base)
1042 continue;
1043 units[num_units++] = vmw_crtc_to_du(crtc);
1044 }
1045
1046 BUG_ON(dmabuf == NULL);
1047 BUG_ON(!clips || !num_clips);
1048
1049 /* take a safe guess at fifo size */
1050 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
1051 cmd = kmalloc(fifo_size, GFP_KERNEL);
1052 if (unlikely(cmd == NULL)) {
1053 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1054 return -ENOMEM;
1055 }
1056
1057 memset(cmd, 0, fifo_size);
1058 cmd->header = SVGA_CMD_DEFINE_GMRFB;
1059 cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
1060 cmd->body.format.colorDepth = vfb->base.depth;
1061 cmd->body.format.reserved = 0;
1062 cmd->body.bytesPerLine = vfb->base.pitch;
90ff18bc 1063 cmd->body.ptr.gmrId = vfb->user_handle;
2fcd5a73
JB		 1064 cmd->body.ptr.offset = 0;
1065
1066 blits = (void *)&cmd[1];
1067 blits_pos = 0;
1068 for (i = 0; i < num_units; i++) {
1069 struct drm_vmw_rect *c = clips;
1070 for (k = 0; k < num_clips; k++, c++) {
1071 /* transform clip coords to crtc origin based coords */
1072 int clip_x1 = c->x - units[i]->crtc.x;
1073 int clip_x2 = c->x - units[i]->crtc.x + c->w;
1074 int clip_y1 = c->y - units[i]->crtc.y;
1075 int clip_y2 = c->y - units[i]->crtc.y + c->h;
1076 int dest_x = c->x;
1077 int dest_y = c->y;
1078
1079 /* compensate for clipping, we negate
1080 * a negative number and add that.
1081 */
1082 if (clip_x1 < 0)
1083 dest_x += -clip_x1;
1084 if (clip_y1 < 0)
1085 dest_y += -clip_y1;
1086
1087 /* clip */
1088 clip_x1 = max(clip_x1, 0);
1089 clip_y1 = max(clip_y1, 0);
1090 clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
1091 clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
1092
1093 /* and cull any rects that misses the crtc */
1094 if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
1095 clip_y1 >= units[i]->crtc.mode.vdisplay ||
1096 clip_x2 <= 0 || clip_y2 <= 0)
1097 continue;
1098
1099 blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1100 blits[blits_pos].body.srcScreenId = units[i]->unit;
1101 blits[blits_pos].body.destOrigin.x = dest_x;
1102 blits[blits_pos].body.destOrigin.y = dest_y;
1103
1104 blits[blits_pos].body.srcRect.left = clip_x1;
1105 blits[blits_pos].body.srcRect.top = clip_y1;
1106 blits[blits_pos].body.srcRect.right = clip_x2;
1107 blits[blits_pos].body.srcRect.bottom = clip_y2;
1108 blits_pos++;
1109 }
1110 }
1111 /* reset size here and use calculated exact size from loops */
1112 fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
1113
1114 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
1115 0, user_fence_rep);
1116
1117 kfree(cmd);
1118
1119 return ret;
1120}
1121
fb1d9738
JB		 1122int vmw_kms_init(struct vmw_private *dev_priv)
1123{
1124 struct drm_device *dev = dev_priv->dev;
1125 int ret;
1126
1127 drm_mode_config_init(dev);
1128 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 1129 dev->mode_config.min_width = 1;
1130 dev->mode_config.min_height = 1;
7e71f8a5
JB		 1131 /* assumed largest fb size */
1132 dev->mode_config.max_width = 8192;
1133 dev->mode_config.max_height = 8192;
fb1d9738 1134
56d1c78d
JB		 1135 ret = vmw_kms_init_screen_object_display(dev_priv);
1136 if (ret) /* Fallback */
1137 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 1138
1139 return 0;
1140}
1141
1142int vmw_kms_close(struct vmw_private *dev_priv)
1143{
1144 /*
1145 * Docs says we should take the lock before calling this function
1146 * but since it destroys encoders and our destructor calls
1147 * drm_encoder_cleanup which takes the lock we deadlock.
1148 */
1149 drm_mode_config_cleanup(dev_priv->dev);
1150 vmw_kms_close_legacy_display_system(dev_priv);
1151 return 0;
1152}
1153
1154int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
1155 struct drm_file *file_priv)
1156{
1157 struct drm_vmw_cursor_bypass_arg *arg = data;
1158 struct vmw_display_unit *du;
1159 struct drm_mode_object *obj;
1160 struct drm_crtc *crtc;
1161 int ret = 0;
1162
1163
1164 mutex_lock(&dev->mode_config.mutex);
1165 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
1166
1167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1168 du = vmw_crtc_to_du(crtc);
1169 du->hotspot_x = arg->xhot;
1170 du->hotspot_y = arg->yhot;
1171 }
1172
1173 mutex_unlock(&dev->mode_config.mutex);
1174 return 0;
1175 }
1176
1177 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
1178 if (!obj) {
1179 ret = -EINVAL;
1180 goto out;
1181 }
1182
1183 crtc = obj_to_crtc(obj);
1184 du = vmw_crtc_to_du(crtc);
1185
1186 du->hotspot_x = arg->xhot;
1187 du->hotspot_y = arg->yhot;
1188
1189out:
1190 mutex_unlock(&dev->mode_config.mutex);
1191
1192 return ret;
1193}
1194
0bef23f9 1195int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 1196 unsigned width, unsigned height, unsigned pitch,
6558429b 1197 unsigned bpp, unsigned depth)
fb1d9738 1198{
d7e1958d
JB		 1199 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1200 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1201 else if (vmw_fifo_have_pitchlock(vmw_priv))
1202 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
1203 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1204 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 1205 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 1206
1207 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1208 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
1209 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
1210 return -EINVAL;
1211 }
1212
1213 return 0;
d7e1958d 1214}
fb1d9738 1215
d7e1958d
JB		 1216int vmw_kms_save_vga(struct vmw_private *vmw_priv)
1217{
7c4f7780
TH		 1218 struct vmw_vga_topology_state *save;
1219 uint32_t i;
1220
fb1d9738
JB		 1221 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1222 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1223 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1224 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1225 vmw_priv->vga_pitchlock =
7c4f7780 1226 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1227 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1228 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1229 SVGA_FIFO_PITCHLOCK);
1230
1231 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1232 return 0;
fb1d9738 1233
7c4f7780
TH		 1234 vmw_priv->num_displays = vmw_read(vmw_priv,
1235 SVGA_REG_NUM_GUEST_DISPLAYS);
1236
029e50bf
TH		 1237 if (vmw_priv->num_displays == 0)
1238 vmw_priv->num_displays = 1;
1239
7c4f7780
TH		 1240 for (i = 0; i < vmw_priv->num_displays; ++i) {
1241 save = &vmw_priv->vga_save[i];
1242 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1243 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1244 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1245 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1246 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1247 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1248 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1249 if (i == 0 && vmw_priv->num_displays == 1 &&
1250 save->width == 0 && save->height == 0) {
1251
1252 /*
1253 * It should be fairly safe to assume that these
1254 * values are uninitialized.
1255 */
1256
1257 save->width = vmw_priv->vga_width - save->pos_x;
1258 save->height = vmw_priv->vga_height - save->pos_y;
1259 }
7c4f7780 1260 }
30c78bb8 1261
fb1d9738
JB		 1262 return 0;
1263}
1264
1265int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1266{
7c4f7780
TH		 1267 struct vmw_vga_topology_state *save;
1268 uint32_t i;
1269
fb1d9738
JB		 1270 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1271 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1272 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1273 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1274 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1275 vmw_priv->vga_pitchlock);
1276 else if (vmw_fifo_have_pitchlock(vmw_priv))
1277 iowrite32(vmw_priv->vga_pitchlock,
1278 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1279
7c4f7780
TH		 1280 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1281 return 0;
1282
1283 for (i = 0; i < vmw_priv->num_displays; ++i) {
1284 save = &vmw_priv->vga_save[i];
1285 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1286 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1287 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1288 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1289 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1290 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1291 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1292 }
1293
fb1d9738
JB		 1294 return 0;
1295}
d8bd19d2 1296
e133e737
TH		 1297bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1298 uint32_t pitch,
1299 uint32_t height)
1300{
1301 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1302}
1303
7a1c2f6c
TH		 1304u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1305{
1306 return 0;
1307}
626ab771
JB		 1308
1309
1310/*
1311 * Small shared kms functions.
1312 */
1313
1314int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1315 struct drm_vmw_rect *rects)
1316{
1317 struct drm_device *dev = dev_priv->dev;
1318 struct vmw_display_unit *du;
1319 struct drm_connector *con;
1320 int i;
1321
1322 mutex_lock(&dev->mode_config.mutex);
1323
1324#if 0
1325 DRM_INFO("%s: new layout ", __func__);
1326 for (i = 0; i < (int)num; i++)
1327 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1328 rects[i].w, rects[i].h);
1329 DRM_INFO("\n");
1330#else
1331 (void)i;
1332#endif
1333
1334 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1335 du = vmw_connector_to_du(con);
1336 if (num > du->unit) {
1337 du->pref_width = rects[du->unit].w;
1338 du->pref_height = rects[du->unit].h;
1339 du->pref_active = true;
1340 } else {
1341 du->pref_width = 800;
1342 du->pref_height = 600;
1343 du->pref_active = false;
1344 }
1345 con->status = vmw_du_connector_detect(con, true);
1346 }
1347
1348 mutex_unlock(&dev->mode_config.mutex);
1349
1350 return 0;
1351}
1352
1353void vmw_du_crtc_save(struct drm_crtc *crtc)
1354{
1355}
1356
1357void vmw_du_crtc_restore(struct drm_crtc *crtc)
1358{
1359}
1360
1361void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1362 u16 *r, u16 *g, u16 *b,
1363 uint32_t start, uint32_t size)
1364{
1365 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1366 int i;
1367
1368 for (i = 0; i < size; i++) {
1369 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1370 r[i], g[i], b[i]);
1371 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1372 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1373 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1374 }
1375}
1376
1377void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1378{
1379}
1380
1381void vmw_du_connector_save(struct drm_connector *connector)
1382{
1383}
1384
1385void vmw_du_connector_restore(struct drm_connector *connector)
1386{
1387}
1388
1389enum drm_connector_status
1390vmw_du_connector_detect(struct drm_connector *connector, bool force)
1391{
1392 uint32_t num_displays;
1393 struct drm_device *dev = connector->dev;
1394 struct vmw_private *dev_priv = vmw_priv(dev);
1395
1396 mutex_lock(&dev_priv->hw_mutex);
1397 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1398 mutex_unlock(&dev_priv->hw_mutex);
1399
1400 return ((vmw_connector_to_du(connector)->unit < num_displays) ?
1401 connector_status_connected : connector_status_disconnected);
1402}
1403
1404static struct drm_display_mode vmw_kms_connector_builtin[] = {
1405 /* 640x480@60Hz */
1406 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1407 752, 800, 0, 480, 489, 492, 525, 0,
1408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1409 /* 800x600@60Hz */
1410 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1411 968, 1056, 0, 600, 601, 605, 628, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1413 /* 1024x768@60Hz */
1414 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1415 1184, 1344, 0, 768, 771, 777, 806, 0,
1416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1417 /* 1152x864@75Hz */
1418 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1419 1344, 1600, 0, 864, 865, 868, 900, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1421 /* 1280x768@60Hz */
1422 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1423 1472, 1664, 0, 768, 771, 778, 798, 0,
1424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1425 /* 1280x800@60Hz */
1426 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1427 1480, 1680, 0, 800, 803, 809, 831, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1429 /* 1280x960@60Hz */
1430 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1431 1488, 1800, 0, 960, 961, 964, 1000, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1433 /* 1280x1024@60Hz */
1434 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1435 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1437 /* 1360x768@60Hz */
1438 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1439 1536, 1792, 0, 768, 771, 777, 795, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1441 /* 1440x1050@60Hz */
1442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1443 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1445 /* 1440x900@60Hz */
1446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1447 1672, 1904, 0, 900, 903, 909, 934, 0,
1448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1449 /* 1600x1200@60Hz */
1450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1453 /* 1680x1050@60Hz */
1454 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1455 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1457 /* 1792x1344@60Hz */
1458 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1459 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1461 /* 1853x1392@60Hz */
1462 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1463 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1465 /* 1920x1200@60Hz */
1466 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1467 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1469 /* 1920x1440@60Hz */
1470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1471 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1473 /* 2560x1600@60Hz */
1474 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1475 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1477 /* Terminate */
1478 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1479};
1480
1481int vmw_du_connector_fill_modes(struct drm_connector *connector,
1482 uint32_t max_width, uint32_t max_height)
1483{
1484 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1485 struct drm_device *dev = connector->dev;
1486 struct vmw_private *dev_priv = vmw_priv(dev);
1487 struct drm_display_mode *mode = NULL;
1488 struct drm_display_mode *bmode;
1489 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1490 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1493 };
1494 int i;
1495
1496 /* Add preferred mode */
1497 {
1498 mode = drm_mode_duplicate(dev, &prefmode);
1499 if (!mode)
1500 return 0;
1501 mode->hdisplay = du->pref_width;
1502 mode->vdisplay = du->pref_height;
1503 mode->vrefresh = drm_mode_vrefresh(mode);
1504 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1505 mode->vdisplay)) {
1506 drm_mode_probed_add(connector, mode);
1507
1508 if (du->pref_mode) {
1509 list_del_init(&du->pref_mode->head);
1510 drm_mode_destroy(dev, du->pref_mode);
1511 }
1512
1513 du->pref_mode = mode;
1514 }
1515 }
1516
1517 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1518 bmode = &vmw_kms_connector_builtin[i];
1519 if (bmode->hdisplay > max_width ||
1520 bmode->vdisplay > max_height)
1521 continue;
1522
1523 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1524 bmode->vdisplay))
1525 continue;
1526
1527 mode = drm_mode_duplicate(dev, bmode);
1528 if (!mode)
1529 return 0;
1530 mode->vrefresh = drm_mode_vrefresh(mode);
1531
1532 drm_mode_probed_add(connector, mode);
1533 }
1534
1535 drm_mode_connector_list_update(connector);
1536
1537 return 1;
1538}
1539
1540int vmw_du_connector_set_property(struct drm_connector *connector,
1541 struct drm_property *property,
1542 uint64_t val)
1543{
1544 return 0;
1545}
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