[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / zte / zx_vou.h

/*
 * Copyright 2016 Linaro Ltd.
 * Copyright 2016 ZTE Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ZX_VOU_H__
#define __ZX_VOU_H__

#define VOU_CRTC_MASK		0x3

/* VOU output interfaces */
enum vou_inf_id {
	VOU_HDMI	= 0,
	VOU_RGB_LCD	= 1,
	VOU_TV_ENC	= 2,
	VOU_MIPI_DSI	= 3,
	VOU_LVDS	= 4,
	VOU_VGA		= 5,
};

enum vou_inf_hdmi_audio {
	VOU_HDMI_AUD_SPDIF	= BIT(0),
	VOU_HDMI_AUD_I2S	= BIT(1),
	VOU_HDMI_AUD_DSD	= BIT(2),
	VOU_HDMI_AUD_HBR	= BIT(3),
	VOU_HDMI_AUD_PARALLEL	= BIT(4),
};

void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
			    enum vou_inf_hdmi_audio aud);
void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);

enum vou_div_id {
	VOU_DIV_VGA,
	VOU_DIV_PIC,
	VOU_DIV_TVENC,
	VOU_DIV_HDMI_PNX,
	VOU_DIV_HDMI,
	VOU_DIV_INF,
	VOU_DIV_LAYER,
};

enum vou_div_val {
	VOU_DIV_1 = 0,
	VOU_DIV_2 = 1,
	VOU_DIV_4 = 3,
	VOU_DIV_8 = 7,
};

struct vou_div_config {
	enum vou_div_id id;
	enum vou_div_val val;
};

void zx_vou_config_dividers(struct drm_crtc *crtc,
			    struct vou_div_config *configs, int num);

void zx_vou_layer_enable(struct drm_plane *plane);
void zx_vou_layer_disable(struct drm_plane *plane,
			  struct drm_plane_state *old_state);

#endif /* __ZX_VOU_H__ */
Commit	Line	Data
0a886f59 SG	1	/*
	2	* Copyright 2016 Linaro Ltd.
	3	* Copyright 2016 ZTE Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	*/
	10
	11	#ifndef __ZX_VOU_H__
	12	#define __ZX_VOU_H__
	13
	14	#define VOU_CRTC_MASK 0x3
	15
	16	/* VOU output interfaces */
	17	enum vou_inf_id {
	18	VOU_HDMI = 0,
	19	VOU_RGB_LCD = 1,
	20	VOU_TV_ENC = 2,
	21	VOU_MIPI_DSI = 3,
	22	VOU_LVDS = 4,
	23	VOU_VGA = 5,
	24	};
	25
83d71152 SG	26	enum vou_inf_hdmi_audio {
	27	VOU_HDMI_AUD_SPDIF = BIT(0),
	28	VOU_HDMI_AUD_I2S = BIT(1),
	29	VOU_HDMI_AUD_DSD = BIT(2),
	30	VOU_HDMI_AUD_HBR = BIT(3),
	31	VOU_HDMI_AUD_PARALLEL = BIT(4),
	32	};
	33
83d71152 SG	34	void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
83d71152 SG	35	enum vou_inf_hdmi_audio aud);
831a8d5e SG	36	void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
831a8d5e SG	37	void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
0a886f59	38
9cc2a685 SG	39	enum vou_div_id {
	40	VOU_DIV_VGA,
	41	VOU_DIV_PIC,
	42	VOU_DIV_TVENC,
	43	VOU_DIV_HDMI_PNX,
	44	VOU_DIV_HDMI,
	45	VOU_DIV_INF,
	46	VOU_DIV_LAYER,
	47	};
	48
	49	enum vou_div_val {
	50	VOU_DIV_1 = 0,
	51	VOU_DIV_2 = 1,
	52	VOU_DIV_4 = 3,
	53	VOU_DIV_8 = 7,
	54	};
	55
	56	struct vou_div_config {
	57	enum vou_div_id id;
	58	enum vou_div_val val;
	59	};
	60
	61	void zx_vou_config_dividers(struct drm_crtc *crtc,
	62	struct vou_div_config *configs, int num);
	63
7254b1f9	64	void zx_vou_layer_enable(struct drm_plane *plane);
6f6887da VS	65	void zx_vou_layer_disable(struct drm_plane *plane,
6f6887da VS	66	struct drm_plane_state *old_state);
7254b1f9	67
0a886f59	68	#endif /* __ZX_VOU_H__ */