[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / zte / zx_vou.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2016 Linaro Ltd.
 * Copyright 2016 ZTE Corporation.
 */

#ifndef __ZX_VOU_H__
#define __ZX_VOU_H__

#define VOU_CRTC_MASK		0x3

/* VOU output interfaces */
enum vou_inf_id {
	VOU_HDMI	= 0,
	VOU_RGB_LCD	= 1,
	VOU_TV_ENC	= 2,
	VOU_MIPI_DSI	= 3,
	VOU_LVDS	= 4,
	VOU_VGA		= 5,
};

enum vou_inf_hdmi_audio {
	VOU_HDMI_AUD_SPDIF	= BIT(0),
	VOU_HDMI_AUD_I2S	= BIT(1),
	VOU_HDMI_AUD_DSD	= BIT(2),
	VOU_HDMI_AUD_HBR	= BIT(3),
	VOU_HDMI_AUD_PARALLEL	= BIT(4),
};

void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
			    enum vou_inf_hdmi_audio aud);
void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);

enum vou_div_id {
	VOU_DIV_VGA,
	VOU_DIV_PIC,
	VOU_DIV_TVENC,
	VOU_DIV_HDMI_PNX,
	VOU_DIV_HDMI,
	VOU_DIV_INF,
	VOU_DIV_LAYER,
};

enum vou_div_val {
	VOU_DIV_1 = 0,
	VOU_DIV_2 = 1,
	VOU_DIV_4 = 3,
	VOU_DIV_8 = 7,
};

struct vou_div_config {
	enum vou_div_id id;
	enum vou_div_val val;
};

void zx_vou_config_dividers(struct drm_crtc *crtc,
			    struct vou_div_config *configs, int num);

void zx_vou_layer_enable(struct drm_plane *plane);
void zx_vou_layer_disable(struct drm_plane *plane,
			  struct drm_plane_state *old_state);

#endif /* __ZX_VOU_H__ */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
0a886f59 SG	2	/*
	3	* Copyright 2016 Linaro Ltd.
	4	* Copyright 2016 ZTE Corporation.
0a886f59 SG	5	*/
	6
	7	#ifndef __ZX_VOU_H__
	8	#define __ZX_VOU_H__
	9
	10	#define VOU_CRTC_MASK 0x3
	11
	12	/* VOU output interfaces */
	13	enum vou_inf_id {
	14	VOU_HDMI = 0,
	15	VOU_RGB_LCD = 1,
	16	VOU_TV_ENC = 2,
	17	VOU_MIPI_DSI = 3,
	18	VOU_LVDS = 4,
	19	VOU_VGA = 5,
	20	};
	21
83d71152 SG	22	enum vou_inf_hdmi_audio {
	23	VOU_HDMI_AUD_SPDIF = BIT(0),
	24	VOU_HDMI_AUD_I2S = BIT(1),
	25	VOU_HDMI_AUD_DSD = BIT(2),
	26	VOU_HDMI_AUD_HBR = BIT(3),
	27	VOU_HDMI_AUD_PARALLEL = BIT(4),
	28	};
	29
83d71152 SG	30	void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
83d71152 SG	31	enum vou_inf_hdmi_audio aud);
831a8d5e SG	32	void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
831a8d5e SG	33	void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
0a886f59	34
9cc2a685 SG	35	enum vou_div_id {
	36	VOU_DIV_VGA,
	37	VOU_DIV_PIC,
	38	VOU_DIV_TVENC,
	39	VOU_DIV_HDMI_PNX,
	40	VOU_DIV_HDMI,
	41	VOU_DIV_INF,
	42	VOU_DIV_LAYER,
	43	};
	44
	45	enum vou_div_val {
	46	VOU_DIV_1 = 0,
	47	VOU_DIV_2 = 1,
	48	VOU_DIV_4 = 3,
	49	VOU_DIV_8 = 7,
	50	};
	51
	52	struct vou_div_config {
	53	enum vou_div_id id;
	54	enum vou_div_val val;
	55	};
	56
	57	void zx_vou_config_dividers(struct drm_crtc *crtc,
	58	struct vou_div_config *configs, int num);
	59
7254b1f9	60	void zx_vou_layer_enable(struct drm_plane *plane);
6f6887da VS	61	void zx_vou_layer_disable(struct drm_plane *plane,
6f6887da VS	62	struct drm_plane_state *old_state);
7254b1f9	63
0a886f59	64	#endif /* __ZX_VOU_H__ */