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75471687 TB |
1 | /* |
2 | * Tegra host1x driver | |
3 | * | |
4 | * Copyright (c) 2010-2013, NVIDIA Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/io.h> | |
097452e6 | 26 | #include <linux/dma-mapping.h> |
75471687 TB |
27 | |
28 | #define CREATE_TRACE_POINTS | |
29 | #include <trace/events/host1x.h> | |
30 | ||
776dc384 | 31 | #include "bus.h" |
75471687 | 32 | #include "dev.h" |
7ede0b0b | 33 | #include "intr.h" |
6579324a | 34 | #include "channel.h" |
6236451d | 35 | #include "debug.h" |
75471687 | 36 | #include "hw/host1x01.h" |
5407f31b | 37 | #include "hw/host1x02.h" |
e6fff4aa | 38 | #include "hw/host1x04.h" |
a134789a | 39 | #include "hw/host1x05.h" |
75471687 TB |
40 | |
41 | void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) | |
42 | { | |
43 | void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; | |
44 | ||
45 | writel(v, sync_regs + r); | |
46 | } | |
47 | ||
48 | u32 host1x_sync_readl(struct host1x *host1x, u32 r) | |
49 | { | |
50 | void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; | |
51 | ||
52 | return readl(sync_regs + r); | |
53 | } | |
54 | ||
6579324a TB |
55 | void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) |
56 | { | |
57 | writel(v, ch->regs + r); | |
58 | } | |
59 | ||
60 | u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) | |
61 | { | |
62 | return readl(ch->regs + r); | |
63 | } | |
64 | ||
75471687 TB |
65 | static const struct host1x_info host1x01_info = { |
66 | .nb_channels = 8, | |
67 | .nb_pts = 32, | |
68 | .nb_mlocks = 16, | |
69 | .nb_bases = 8, | |
70 | .init = host1x01_init, | |
71 | .sync_offset = 0x3000, | |
097452e6 | 72 | .dma_mask = DMA_BIT_MASK(32), |
75471687 TB |
73 | }; |
74 | ||
5407f31b TR |
75 | static const struct host1x_info host1x02_info = { |
76 | .nb_channels = 9, | |
77 | .nb_pts = 32, | |
78 | .nb_mlocks = 16, | |
79 | .nb_bases = 12, | |
80 | .init = host1x02_init, | |
81 | .sync_offset = 0x3000, | |
097452e6 | 82 | .dma_mask = DMA_BIT_MASK(32), |
5407f31b TR |
83 | }; |
84 | ||
e6fff4aa TR |
85 | static const struct host1x_info host1x04_info = { |
86 | .nb_channels = 12, | |
87 | .nb_pts = 192, | |
88 | .nb_mlocks = 16, | |
89 | .nb_bases = 64, | |
90 | .init = host1x04_init, | |
91 | .sync_offset = 0x2100, | |
097452e6 | 92 | .dma_mask = DMA_BIT_MASK(34), |
e6fff4aa TR |
93 | }; |
94 | ||
a134789a TR |
95 | static const struct host1x_info host1x05_info = { |
96 | .nb_channels = 14, | |
97 | .nb_pts = 192, | |
98 | .nb_mlocks = 16, | |
99 | .nb_bases = 64, | |
100 | .init = host1x05_init, | |
101 | .sync_offset = 0x2100, | |
097452e6 | 102 | .dma_mask = DMA_BIT_MASK(34), |
a134789a TR |
103 | }; |
104 | ||
75471687 | 105 | static struct of_device_id host1x_of_match[] = { |
a134789a | 106 | { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, |
e6fff4aa | 107 | { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, |
5407f31b | 108 | { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, |
75471687 TB |
109 | { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, |
110 | { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, | |
111 | { }, | |
112 | }; | |
113 | MODULE_DEVICE_TABLE(of, host1x_of_match); | |
114 | ||
115 | static int host1x_probe(struct platform_device *pdev) | |
116 | { | |
117 | const struct of_device_id *id; | |
118 | struct host1x *host; | |
119 | struct resource *regs; | |
120 | int syncpt_irq; | |
121 | int err; | |
122 | ||
123 | id = of_match_device(host1x_of_match, &pdev->dev); | |
124 | if (!id) | |
125 | return -EINVAL; | |
126 | ||
127 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
128 | if (!regs) { | |
129 | dev_err(&pdev->dev, "failed to get registers\n"); | |
130 | return -ENXIO; | |
131 | } | |
132 | ||
133 | syncpt_irq = platform_get_irq(pdev, 0); | |
134 | if (syncpt_irq < 0) { | |
135 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
136 | return -ENXIO; | |
137 | } | |
138 | ||
139 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); | |
140 | if (!host) | |
141 | return -ENOMEM; | |
142 | ||
776dc384 TR |
143 | mutex_init(&host->devices_lock); |
144 | INIT_LIST_HEAD(&host->devices); | |
145 | INIT_LIST_HEAD(&host->list); | |
75471687 TB |
146 | host->dev = &pdev->dev; |
147 | host->info = id->data; | |
148 | ||
149 | /* set common host1x device data */ | |
150 | platform_set_drvdata(pdev, host); | |
151 | ||
152 | host->regs = devm_ioremap_resource(&pdev->dev, regs); | |
153 | if (IS_ERR(host->regs)) | |
154 | return PTR_ERR(host->regs); | |
155 | ||
097452e6 AC |
156 | dma_set_mask_and_coherent(host->dev, host->info->dma_mask); |
157 | ||
75471687 TB |
158 | if (host->info->init) { |
159 | err = host->info->init(host); | |
160 | if (err) | |
161 | return err; | |
162 | } | |
163 | ||
164 | host->clk = devm_clk_get(&pdev->dev, NULL); | |
165 | if (IS_ERR(host->clk)) { | |
166 | dev_err(&pdev->dev, "failed to get clock\n"); | |
167 | err = PTR_ERR(host->clk); | |
168 | return err; | |
169 | } | |
170 | ||
6579324a TB |
171 | err = host1x_channel_list_init(host); |
172 | if (err) { | |
173 | dev_err(&pdev->dev, "failed to initialize channel list\n"); | |
174 | return err; | |
175 | } | |
176 | ||
75471687 TB |
177 | err = clk_prepare_enable(host->clk); |
178 | if (err < 0) { | |
179 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
180 | return err; | |
181 | } | |
182 | ||
183 | err = host1x_syncpt_init(host); | |
184 | if (err) { | |
185 | dev_err(&pdev->dev, "failed to initialize syncpts\n"); | |
9c78c4c3 | 186 | goto fail_unprepare_disable; |
75471687 TB |
187 | } |
188 | ||
7ede0b0b TB |
189 | err = host1x_intr_init(host, syncpt_irq); |
190 | if (err) { | |
191 | dev_err(&pdev->dev, "failed to initialize interrupts\n"); | |
192 | goto fail_deinit_syncpt; | |
193 | } | |
194 | ||
6236451d TB |
195 | host1x_debug_init(host); |
196 | ||
776dc384 TR |
197 | err = host1x_register(host); |
198 | if (err < 0) | |
199 | goto fail_deinit_intr; | |
692e6d7b | 200 | |
75471687 | 201 | return 0; |
7ede0b0b | 202 | |
776dc384 TR |
203 | fail_deinit_intr: |
204 | host1x_intr_deinit(host); | |
7ede0b0b TB |
205 | fail_deinit_syncpt: |
206 | host1x_syncpt_deinit(host); | |
9c78c4c3 WY |
207 | fail_unprepare_disable: |
208 | clk_disable_unprepare(host->clk); | |
7ede0b0b | 209 | return err; |
75471687 TB |
210 | } |
211 | ||
452e7f0c | 212 | static int host1x_remove(struct platform_device *pdev) |
75471687 TB |
213 | { |
214 | struct host1x *host = platform_get_drvdata(pdev); | |
215 | ||
776dc384 | 216 | host1x_unregister(host); |
7ede0b0b | 217 | host1x_intr_deinit(host); |
75471687 TB |
218 | host1x_syncpt_deinit(host); |
219 | clk_disable_unprepare(host->clk); | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
692e6d7b | 224 | static struct platform_driver tegra_host1x_driver = { |
75471687 | 225 | .driver = { |
75471687 TB |
226 | .name = "tegra-host1x", |
227 | .of_match_table = host1x_of_match, | |
228 | }, | |
452e7f0c TR |
229 | .probe = host1x_probe, |
230 | .remove = host1x_remove, | |
75471687 TB |
231 | }; |
232 | ||
28fae81f TR |
233 | static struct platform_driver * const drivers[] = { |
234 | &tegra_host1x_driver, | |
235 | &tegra_mipi_driver, | |
236 | }; | |
237 | ||
692e6d7b TB |
238 | static int __init tegra_host1x_init(void) |
239 | { | |
240 | int err; | |
241 | ||
f4c5cf88 | 242 | err = bus_register(&host1x_bus_type); |
692e6d7b TB |
243 | if (err < 0) |
244 | return err; | |
245 | ||
28fae81f | 246 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
4de6a2d6 | 247 | if (err < 0) |
28fae81f | 248 | bus_unregister(&host1x_bus_type); |
692e6d7b | 249 | |
4de6a2d6 | 250 | return err; |
692e6d7b TB |
251 | } |
252 | module_init(tegra_host1x_init); | |
253 | ||
254 | static void __exit tegra_host1x_exit(void) | |
255 | { | |
28fae81f | 256 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
f4c5cf88 | 257 | bus_unregister(&host1x_bus_type); |
692e6d7b TB |
258 | } |
259 | module_exit(tegra_host1x_exit); | |
75471687 | 260 | |
692e6d7b | 261 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
75471687 TB |
262 | MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); |
263 | MODULE_DESCRIPTION("Host1x driver for Tegra products"); | |
264 | MODULE_LICENSE("GPL"); |