[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / host1x / dev.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Tegra host1x driver
 *
 * Copyright (c) 2010-2013, NVIDIA Corporation.
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/slab.h>

#define CREATE_TRACE_POINTS
#include <trace/events/host1x.h>
#undef CREATE_TRACE_POINTS

#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
#include <asm/dma-iommu.h>
#endif

#include "bus.h"
#include "channel.h"
#include "debug.h"
#include "dev.h"
#include "intr.h"

#include "hw/host1x01.h"
#include "hw/host1x02.h"
#include "hw/host1x04.h"
#include "hw/host1x05.h"
#include "hw/host1x06.h"
#include "hw/host1x07.h"

void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
{
	writel(v, host1x->hv_regs + r);
}

u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
{
	return readl(host1x->hv_regs + r);
}

void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	writel(v, sync_regs + r);
}

u32 host1x_sync_readl(struct host1x *host1x, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	return readl(sync_regs + r);
}

void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
{
	writel(v, ch->regs + r);
}

u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
{
	return readl(ch->regs + r);
}

static const struct host1x_info host1x01_info = {
	.nb_channels = 8,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 8,
	.init = host1x01_init,
	.sync_offset = 0x3000,
	.dma_mask = DMA_BIT_MASK(32),
};

static const struct host1x_info host1x02_info = {
	.nb_channels = 9,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 12,
	.init = host1x02_init,
	.sync_offset = 0x3000,
	.dma_mask = DMA_BIT_MASK(32),
};

static const struct host1x_info host1x04_info = {
	.nb_channels = 12,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x04_init,
	.sync_offset = 0x2100,
	.dma_mask = DMA_BIT_MASK(34),
};

static const struct host1x_info host1x05_info = {
	.nb_channels = 14,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x05_init,
	.sync_offset = 0x2100,
	.dma_mask = DMA_BIT_MASK(34),
};

static const struct host1x_sid_entry tegra186_sid_table[] = {
	{
		/* VIC */
		.base = 0x1af0,
		.offset = 0x30,
		.limit = 0x34
	},
};

static const struct host1x_info host1x06_info = {
	.nb_channels = 63,
	.nb_pts = 576,
	.nb_mlocks = 24,
	.nb_bases = 16,
	.init = host1x06_init,
	.sync_offset = 0x0,
	.dma_mask = DMA_BIT_MASK(40),
	.has_hypervisor = true,
	.num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
	.sid_table = tegra186_sid_table,
};

static const struct host1x_sid_entry tegra194_sid_table[] = {
	{
		/* VIC */
		.base = 0x1af0,
		.offset = 0x30,
		.limit = 0x34
	},
};

static const struct host1x_info host1x07_info = {
	.nb_channels = 63,
	.nb_pts = 704,
	.nb_mlocks = 32,
	.nb_bases = 0,
	.init = host1x07_init,
	.sync_offset = 0x0,
	.dma_mask = DMA_BIT_MASK(40),
	.has_hypervisor = true,
	.num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
	.sid_table = tegra194_sid_table,
};

static const struct of_device_id host1x_of_match[] = {
	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
	{ },
};
MODULE_DEVICE_TABLE(of, host1x_of_match);

static void host1x_setup_sid_table(struct host1x *host)
{
	const struct host1x_info *info = host->info;
	unsigned int i;

	for (i = 0; i < info->num_sid_entries; i++) {
		const struct host1x_sid_entry *entry = &info->sid_table[i];

		host1x_hypervisor_writel(host, entry->offset, entry->base);
		host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
	}
}

static int host1x_probe(struct platform_device *pdev)
{
	struct host1x *host;
	struct resource *regs, *hv_regs = NULL;
	int syncpt_irq;
	int err;

	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
	if (!host)
		return -ENOMEM;

	host->info = of_device_get_match_data(&pdev->dev);

	if (host->info->has_hypervisor) {
		regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
		if (!regs) {
			dev_err(&pdev->dev, "failed to get vm registers\n");
			return -ENXIO;
		}

		hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						       "hypervisor");
		if (!hv_regs) {
			dev_err(&pdev->dev,
				"failed to get hypervisor registers\n");
			return -ENXIO;
		}
	} else {
		regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!regs) {
			dev_err(&pdev->dev, "failed to get registers\n");
			return -ENXIO;
		}
	}

	syncpt_irq = platform_get_irq(pdev, 0);
	if (syncpt_irq < 0) {
		dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
		return syncpt_irq;
	}

	mutex_init(&host->devices_lock);
	INIT_LIST_HEAD(&host->devices);
	INIT_LIST_HEAD(&host->list);
	host->dev = &pdev->dev;

	/* set common host1x device data */
	platform_set_drvdata(pdev, host);

	host->regs = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(host->regs))
		return PTR_ERR(host->regs);

	if (host->info->has_hypervisor) {
		host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
		if (IS_ERR(host->hv_regs))
			return PTR_ERR(host->hv_regs);
	}

	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);

	if (host->info->init) {
		err = host->info->init(host);
		if (err)
			return err;
	}

	host->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(host->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		err = PTR_ERR(host->clk);
		return err;
	}

	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
	if (IS_ERR(host->rst)) {
		err = PTR_ERR(host->rst);
		dev_err(&pdev->dev, "failed to get reset: %d\n", err);
		return err;
	}
#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
	if (host->dev->archdata.mapping) {
		struct dma_iommu_mapping *mapping =
				to_dma_iommu_mapping(host->dev);
		arm_iommu_detach_device(host->dev);
		arm_iommu_release_mapping(mapping);
	}
#endif
	if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
		goto skip_iommu;

	host->group = iommu_group_get(&pdev->dev);
	if (host->group) {
		struct iommu_domain_geometry *geometry;
		u64 mask = dma_get_mask(host->dev);
		dma_addr_t start, end;
		unsigned long order;

		err = iova_cache_get();
		if (err < 0)
			goto put_group;

		host->domain = iommu_domain_alloc(&platform_bus_type);
		if (!host->domain) {
			err = -ENOMEM;
			goto put_cache;
		}

		err = iommu_attach_group(host->domain, host->group);
		if (err) {
			if (err == -ENODEV) {
				iommu_domain_free(host->domain);
				host->domain = NULL;
				iova_cache_put();
				iommu_group_put(host->group);
				host->group = NULL;
				goto skip_iommu;
			}

			goto fail_free_domain;
		}

		geometry = &host->domain->geometry;
		start = geometry->aperture_start & mask;
		end = geometry->aperture_end & mask;

		order = __ffs(host->domain->pgsize_bitmap);
		init_iova_domain(&host->iova, 1UL << order, start >> order);
		host->iova_end = end;
	}

skip_iommu:
	err = host1x_channel_list_init(&host->channel_list,
				       host->info->nb_channels);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize channel list\n");
		goto fail_detach_device;
	}

	err = clk_prepare_enable(host->clk);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto fail_free_channels;
	}

	err = reset_control_deassert(host->rst);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
		goto fail_unprepare_disable;
	}

	err = host1x_syncpt_init(host);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize syncpts\n");
		goto fail_reset_assert;
	}

	err = host1x_intr_init(host, syncpt_irq);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize interrupts\n");
		goto fail_deinit_syncpt;
	}

	host1x_debug_init(host);

	if (host->info->has_hypervisor)
		host1x_setup_sid_table(host);

	err = host1x_register(host);
	if (err < 0)
		goto fail_deinit_intr;

	return 0;

fail_deinit_intr:
	host1x_intr_deinit(host);
fail_deinit_syncpt:
	host1x_syncpt_deinit(host);
fail_reset_assert:
	reset_control_assert(host->rst);
fail_unprepare_disable:
	clk_disable_unprepare(host->clk);
fail_free_channels:
	host1x_channel_list_free(&host->channel_list);
fail_detach_device:
	if (host->group && host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_group(host->domain, host->group);
	}
fail_free_domain:
	if (host->domain)
		iommu_domain_free(host->domain);
put_cache:
	if (host->group)
		iova_cache_put();
put_group:
	iommu_group_put(host->group);

	return err;
}

static int host1x_remove(struct platform_device *pdev)
{
	struct host1x *host = platform_get_drvdata(pdev);

	host1x_unregister(host);
	host1x_intr_deinit(host);
	host1x_syncpt_deinit(host);
	reset_control_assert(host->rst);
	clk_disable_unprepare(host->clk);

	if (host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_group(host->domain, host->group);
		iommu_domain_free(host->domain);
		iova_cache_put();
		iommu_group_put(host->group);
	}

	return 0;
}

static struct platform_driver tegra_host1x_driver = {
	.driver = {
		.name = "tegra-host1x",
		.of_match_table = host1x_of_match,
	},
	.probe = host1x_probe,
	.remove = host1x_remove,
};

static struct platform_driver * const drivers[] = {
	&tegra_host1x_driver,
	&tegra_mipi_driver,
};

static int __init tegra_host1x_init(void)
{
	int err;

	err = bus_register(&host1x_bus_type);
	if (err < 0)
		return err;

	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
	if (err < 0)
		bus_unregister(&host1x_bus_type);

	return err;
}
module_init(tegra_host1x_init);

static void __exit tegra_host1x_exit(void)
{
	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
	bus_unregister(&host1x_bus_type);
}
module_exit(tegra_host1x_exit);

MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
MODULE_DESCRIPTION("Host1x driver for Tegra products");
MODULE_LICENSE("GPL");
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
75471687 TB	2	/*
	3	* Tegra host1x driver
	4	*
	5	* Copyright (c) 2010-2013, NVIDIA Corporation.
75471687 TB	6	*/
75471687 TB	7
75471687	8	#include <linux/clk.h>
097452e6	9	#include <linux/dma-mapping.h>
7e7d432c TR	10	#include <linux/io.h>
	11	#include <linux/list.h>
	12	#include <linux/module.h>
	13	#include <linux/of_device.h>
	14	#include <linux/of.h>
	15	#include <linux/slab.h>
75471687 TB	16
	17	#define CREATE_TRACE_POINTS
	18	#include <trace/events/host1x.h>
404bfb78	19	#undef CREATE_TRACE_POINTS
75471687	20
e31c8ea5 DO	21	#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
	22	#include <asm/dma-iommu.h>
	23	#endif
	24
776dc384	25	#include "bus.h"
6579324a	26	#include "channel.h"
6236451d	27	#include "debug.h"
7e7d432c TR	28	#include "dev.h"
	29	#include "intr.h"
	30
75471687	31	#include "hw/host1x01.h"
5407f31b	32	#include "hw/host1x02.h"
e6fff4aa	33	#include "hw/host1x04.h"
a134789a	34	#include "hw/host1x05.h"
f1b53c4e	35	#include "hw/host1x06.h"
ac1bdbf2	36	#include "hw/host1x07.h"
f1b53c4e MP	37
	38	void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
	39	{
	40	writel(v, host1x->hv_regs + r);
	41	}
	42
	43	u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
	44	{
	45	return readl(host1x->hv_regs + r);
	46	}
75471687 TB	47
	48	void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
	49	{
	50	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
	51
	52	writel(v, sync_regs + r);
	53	}
	54
	55	u32 host1x_sync_readl(struct host1x *host1x, u32 r)
	56	{
	57	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
	58
	59	return readl(sync_regs + r);
	60	}
	61
6579324a TB	62	void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
	63	{
	64	writel(v, ch->regs + r);
	65	}
	66
	67	u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
	68	{
	69	return readl(ch->regs + r);
	70	}
	71
75471687	72	static const struct host1x_info host1x01_info = {
0b8070d1 TR	73	.nb_channels = 8,
	74	.nb_pts = 32,
	75	.nb_mlocks = 16,
	76	.nb_bases = 8,
	77	.init = host1x01_init,
	78	.sync_offset = 0x3000,
	79	.dma_mask = DMA_BIT_MASK(32),
75471687 TB	80	};
75471687 TB	81
5407f31b TR	82	static const struct host1x_info host1x02_info = {
	83	.nb_channels = 9,
	84	.nb_pts = 32,
	85	.nb_mlocks = 16,
	86	.nb_bases = 12,
	87	.init = host1x02_init,
	88	.sync_offset = 0x3000,
097452e6	89	.dma_mask = DMA_BIT_MASK(32),
5407f31b TR	90	};
5407f31b TR	91
e6fff4aa TR	92	static const struct host1x_info host1x04_info = {
	93	.nb_channels = 12,
	94	.nb_pts = 192,
	95	.nb_mlocks = 16,
	96	.nb_bases = 64,
	97	.init = host1x04_init,
	98	.sync_offset = 0x2100,
097452e6	99	.dma_mask = DMA_BIT_MASK(34),
e6fff4aa TR	100	};
e6fff4aa TR	101
a134789a TR	102	static const struct host1x_info host1x05_info = {
	103	.nb_channels = 14,
	104	.nb_pts = 192,
	105	.nb_mlocks = 16,
	106	.nb_bases = 64,
	107	.init = host1x05_init,
	108	.sync_offset = 0x2100,
097452e6	109	.dma_mask = DMA_BIT_MASK(34),
a134789a TR	110	};
a134789a TR	111
6841482b TR	112	static const struct host1x_sid_entry tegra186_sid_table[] = {
	113	{
	114	/* VIC */
	115	.base = 0x1af0,
	116	.offset = 0x30,
	117	.limit = 0x34
	118	},
	119	};
	120
f1b53c4e MP	121	static const struct host1x_info host1x06_info = {
	122	.nb_channels = 63,
	123	.nb_pts = 576,
	124	.nb_mlocks = 24,
	125	.nb_bases = 16,
	126	.init = host1x06_init,
	127	.sync_offset = 0x0,
8de896eb	128	.dma_mask = DMA_BIT_MASK(40),
f1b53c4e	129	.has_hypervisor = true,
6841482b TR	130	.num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
	131	.sid_table = tegra186_sid_table,
	132	};
	133
	134	static const struct host1x_sid_entry tegra194_sid_table[] = {
	135	{
	136	/* VIC */
	137	.base = 0x1af0,
	138	.offset = 0x30,
	139	.limit = 0x34
	140	},
f1b53c4e MP	141	};
f1b53c4e MP	142
ac1bdbf2 TR	143	static const struct host1x_info host1x07_info = {
	144	.nb_channels = 63,
	145	.nb_pts = 704,
	146	.nb_mlocks = 32,
	147	.nb_bases = 0,
	148	.init = host1x07_init,
	149	.sync_offset = 0x0,
	150	.dma_mask = DMA_BIT_MASK(40),
	151	.has_hypervisor = true,
6841482b TR	152	.num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
6841482b TR	153	.sid_table = tegra194_sid_table,
ac1bdbf2 TR	154	};
ac1bdbf2 TR	155
6df633d0	156	static const struct of_device_id host1x_of_match[] = {
ac1bdbf2	157	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
f1b53c4e	158	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
a134789a	159	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
e6fff4aa	160	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
5407f31b	161	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
75471687 TB	162	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
	163	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
	164	{ },
	165	};
	166	MODULE_DEVICE_TABLE(of, host1x_of_match);
	167
6841482b TR	168	static void host1x_setup_sid_table(struct host1x *host)
	169	{
	170	const struct host1x_info *info = host->info;
	171	unsigned int i;
	172
	173	for (i = 0; i < info->num_sid_entries; i++) {
	174	const struct host1x_sid_entry *entry = &info->sid_table[i];
	175
	176	host1x_hypervisor_writel(host, entry->offset, entry->base);
	177	host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
	178	}
	179	}
	180
75471687 TB	181	static int host1x_probe(struct platform_device *pdev)
75471687 TB	182	{
75471687	183	struct host1x *host;
f1b53c4e	184	struct resource regs, hv_regs = NULL;
75471687 TB	185	int syncpt_irq;
	186	int err;
	187
6a341fdf TR	188	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
	189	if (!host)
	190	return -ENOMEM;
75471687	191
6a341fdf	192	host->info = of_device_get_match_data(&pdev->dev);
75471687	193
f1b53c4e MP	194	if (host->info->has_hypervisor) {
	195	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
	196	if (!regs) {
	197	dev_err(&pdev->dev, "failed to get vm registers\n");
	198	return -ENXIO;
	199	}
	200
	201	hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	202	"hypervisor");
	203	if (!hv_regs) {
	204	dev_err(&pdev->dev,
	205	"failed to get hypervisor registers\n");
	206	return -ENXIO;
	207	}
	208	} else {
	209	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	210	if (!regs) {
	211	dev_err(&pdev->dev, "failed to get registers\n");
	212	return -ENXIO;
	213	}
75471687 TB	214	}
	215
	216	syncpt_irq = platform_get_irq(pdev, 0);
	217	if (syncpt_irq < 0) {
7b2c63de GS	218	dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
7b2c63de GS	219	return syncpt_irq;
75471687 TB	220	}
75471687 TB	221
776dc384 TR	222	mutex_init(&host->devices_lock);
	223	INIT_LIST_HEAD(&host->devices);
	224	INIT_LIST_HEAD(&host->list);
75471687	225	host->dev = &pdev->dev;
75471687 TB	226
	227	/* set common host1x device data */
	228	platform_set_drvdata(pdev, host);
	229
	230	host->regs = devm_ioremap_resource(&pdev->dev, regs);
	231	if (IS_ERR(host->regs))
	232	return PTR_ERR(host->regs);
	233
f1b53c4e MP	234	if (host->info->has_hypervisor) {
	235	host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
	236	if (IS_ERR(host->hv_regs))
	237	return PTR_ERR(host->hv_regs);
	238	}
	239
097452e6 AC	240	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
097452e6 AC	241
75471687 TB	242	if (host->info->init) {
	243	err = host->info->init(host);
	244	if (err)
	245	return err;
	246	}
	247
	248	host->clk = devm_clk_get(&pdev->dev, NULL);
	249	if (IS_ERR(host->clk)) {
	250	dev_err(&pdev->dev, "failed to get clock\n");
	251	err = PTR_ERR(host->clk);
	252	return err;
	253	}
	254
b386c6b7 TR	255	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
b386c6b7 TR	256	if (IS_ERR(host->rst)) {
59e04bc2	257	err = PTR_ERR(host->rst);
b386c6b7 TR	258	dev_err(&pdev->dev, "failed to get reset: %d\n", err);
	259	return err;
	260	}
e31c8ea5 DO	261	#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
	262	if (host->dev->archdata.mapping) {
	263	struct dma_iommu_mapping *mapping =
	264	to_dma_iommu_mapping(host->dev);
	265	arm_iommu_detach_device(host->dev);
	266	arm_iommu_release_mapping(mapping);
	267	}
	268	#endif
4466b1f0 DO	269	if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
	270	goto skip_iommu;
	271
41c3068c TR	272	host->group = iommu_group_get(&pdev->dev);
41c3068c TR	273	if (host->group) {
404bfb78	274	struct iommu_domain_geometry *geometry;
38fabcc9 TR	275	u64 mask = dma_get_mask(host->dev);
38fabcc9 TR	276	dma_addr_t start, end;
404bfb78 MP	277	unsigned long order;
404bfb78 MP	278
f40e1590 TR	279	err = iova_cache_get();
	280	if (err < 0)
	281	goto put_group;
	282
404bfb78	283	host->domain = iommu_domain_alloc(&platform_bus_type);
41c3068c TR	284	if (!host->domain) {
41c3068c TR	285	err = -ENOMEM;
f40e1590	286	goto put_cache;
41c3068c	287	}
404bfb78	288
41c3068c	289	err = iommu_attach_group(host->domain, host->group);
1f876c3f TR	290	if (err) {
	291	if (err == -ENODEV) {
	292	iommu_domain_free(host->domain);
	293	host->domain = NULL;
f40e1590	294	iova_cache_put();
41c3068c TR	295	iommu_group_put(host->group);
41c3068c TR	296	host->group = NULL;
1f876c3f TR	297	goto skip_iommu;
	298	}
	299
404bfb78	300	goto fail_free_domain;
fea20995	301	}
404bfb78 MP	302
404bfb78 MP	303	geometry = &host->domain->geometry;
38fabcc9 TR	304	start = geometry->aperture_start & mask;
38fabcc9 TR	305	end = geometry->aperture_end & mask;
404bfb78 MP	306
404bfb78 MP	307	order = __ffs(host->domain->pgsize_bitmap);
38fabcc9 TR	308	init_iova_domain(&host->iova, 1UL << order, start >> order);
38fabcc9 TR	309	host->iova_end = end;
404bfb78 MP	310	}
404bfb78 MP	311
fea20995	312	skip_iommu:
8474b025 MP	313	err = host1x_channel_list_init(&host->channel_list,
8474b025 MP	314	host->info->nb_channels);
6579324a TB	315	if (err) {
6579324a TB	316	dev_err(&pdev->dev, "failed to initialize channel list\n");
404bfb78	317	goto fail_detach_device;
6579324a TB	318	}
6579324a TB	319
75471687 TB	320	err = clk_prepare_enable(host->clk);
	321	if (err < 0) {
	322	dev_err(&pdev->dev, "failed to enable clock\n");
8474b025	323	goto fail_free_channels;
75471687 TB	324	}
75471687 TB	325
b386c6b7 TR	326	err = reset_control_deassert(host->rst);
	327	if (err < 0) {
	328	dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
	329	goto fail_unprepare_disable;
	330	}
	331
75471687 TB	332	err = host1x_syncpt_init(host);
	333	if (err) {
	334	dev_err(&pdev->dev, "failed to initialize syncpts\n");
b386c6b7	335	goto fail_reset_assert;
75471687 TB	336	}
75471687 TB	337
7ede0b0b TB	338	err = host1x_intr_init(host, syncpt_irq);
	339	if (err) {
	340	dev_err(&pdev->dev, "failed to initialize interrupts\n");
	341	goto fail_deinit_syncpt;
	342	}
	343
6236451d TB	344	host1x_debug_init(host);
6236451d TB	345
6841482b TR	346	if (host->info->has_hypervisor)
	347	host1x_setup_sid_table(host);
	348
776dc384 TR	349	err = host1x_register(host);
	350	if (err < 0)
	351	goto fail_deinit_intr;
692e6d7b	352
75471687	353	return 0;
7ede0b0b	354
776dc384 TR	355	fail_deinit_intr:
776dc384 TR	356	host1x_intr_deinit(host);
7ede0b0b TB	357	fail_deinit_syncpt:
7ede0b0b TB	358	host1x_syncpt_deinit(host);
b386c6b7 TR	359	fail_reset_assert:
b386c6b7 TR	360	reset_control_assert(host->rst);
9c78c4c3 WY	361	fail_unprepare_disable:
9c78c4c3 WY	362	clk_disable_unprepare(host->clk);
8474b025 MP	363	fail_free_channels:
8474b025 MP	364	host1x_channel_list_free(&host->channel_list);
404bfb78	365	fail_detach_device:
41c3068c	366	if (host->group && host->domain) {
404bfb78	367	put_iova_domain(&host->iova);
41c3068c	368	iommu_detach_group(host->domain, host->group);
404bfb78 MP	369	}
	370	fail_free_domain:
	371	if (host->domain)
	372	iommu_domain_free(host->domain);
f40e1590 TR	373	put_cache:
	374	if (host->group)
	375	iova_cache_put();
41c3068c TR	376	put_group:
41c3068c TR	377	iommu_group_put(host->group);
404bfb78	378
7ede0b0b	379	return err;
75471687 TB	380	}
75471687 TB	381
452e7f0c	382	static int host1x_remove(struct platform_device *pdev)
75471687 TB	383	{
	384	struct host1x *host = platform_get_drvdata(pdev);
	385
776dc384	386	host1x_unregister(host);
7ede0b0b	387	host1x_intr_deinit(host);
75471687	388	host1x_syncpt_deinit(host);
b386c6b7	389	reset_control_assert(host->rst);
75471687 TB	390	clk_disable_unprepare(host->clk);
75471687 TB	391
404bfb78 MP	392	if (host->domain) {
404bfb78 MP	393	put_iova_domain(&host->iova);
41c3068c	394	iommu_detach_group(host->domain, host->group);
404bfb78	395	iommu_domain_free(host->domain);
f40e1590	396	iova_cache_put();
41c3068c	397	iommu_group_put(host->group);
404bfb78 MP	398	}
404bfb78 MP	399
75471687 TB	400	return 0;
	401	}
	402
692e6d7b	403	static struct platform_driver tegra_host1x_driver = {
75471687	404	.driver = {
75471687 TB	405	.name = "tegra-host1x",
	406	.of_match_table = host1x_of_match,
	407	},
452e7f0c TR	408	.probe = host1x_probe,
452e7f0c TR	409	.remove = host1x_remove,
75471687 TB	410	};
75471687 TB	411
28fae81f TR	412	static struct platform_driver * const drivers[] = {
	413	&tegra_host1x_driver,
	414	&tegra_mipi_driver,
	415	};
	416
692e6d7b TB	417	static int __init tegra_host1x_init(void)
	418	{
	419	int err;
	420
f4c5cf88	421	err = bus_register(&host1x_bus_type);
692e6d7b TB	422	if (err < 0)
	423	return err;
	424
28fae81f	425	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
4de6a2d6	426	if (err < 0)
28fae81f	427	bus_unregister(&host1x_bus_type);
692e6d7b	428
4de6a2d6	429	return err;
692e6d7b TB	430	}
	431	module_init(tegra_host1x_init);
	432
	433	static void __exit tegra_host1x_exit(void)
	434	{
28fae81f	435	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
f4c5cf88	436	bus_unregister(&host1x_bus_type);
692e6d7b TB	437	}
692e6d7b TB	438	module_exit(tegra_host1x_exit);
75471687	439
692e6d7b	440	MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
75471687 TB	441	MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
	442	MODULE_DESCRIPTION("Host1x driver for Tegra products");
	443	MODULE_LICENSE("GPL");