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Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux into drm...
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / host1x / drm / dc.c
CommitLineData
d8f4a9ed
TR		 1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
61fd290d 15#include <linux/clk/tegra.h>
d8f4a9ed 16
692e6d7b 17#include "host1x_client.h"
de2ba664
AM		 18#include "dc.h"
19#include "drm.h"
20#include "gem.h"
d8f4a9ed 21
f34bc787
TR		 22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
d8f4a9ed
TR		 25};
26
f34bc787
TR		 27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w,
35 unsigned int crtc_h, uint32_t src_x,
36 uint32_t src_y, uint32_t src_w, uint32_t src_h)
37{
38 struct tegra_plane *p = to_tegra_plane(plane);
39 struct tegra_dc *dc = to_tegra_dc(crtc);
40 struct tegra_dc_window window;
41 unsigned int i;
42
43 memset(&window, 0, sizeof(window));
44 window.src.x = src_x >> 16;
45 window.src.y = src_y >> 16;
46 window.src.w = src_w >> 16;
47 window.src.h = src_h >> 16;
48 window.dst.x = crtc_x;
49 window.dst.y = crtc_y;
50 window.dst.w = crtc_w;
51 window.dst.h = crtc_h;
52 window.format = tegra_dc_format(fb->pixel_format);
53 window.bits_per_pixel = fb->bits_per_pixel;
54
55 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
de2ba664 56 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
f34bc787 57
de2ba664 58 window.base[i] = bo->paddr + fb->offsets[i];
f34bc787
TR		 59
60 /*
61 * Tegra doesn't support different strides for U and V planes
62 * so we display a warning if the user tries to display a
63 * framebuffer with such a configuration.
64 */
65 if (i >= 2) {
66 if (fb->pitches[i] != window.stride[1])
67 DRM_ERROR("unsupported UV-plane configuration\n");
68 } else {
69 window.stride[i] = fb->pitches[i];
70 }
71 }
72
73 return tegra_dc_setup_window(dc, p->index, &window);
74}
75
76static int tegra_plane_disable(struct drm_plane *plane)
77{
78 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
79 struct tegra_plane *p = to_tegra_plane(plane);
80 unsigned long value;
81
2678aeba
TR		 82 if (!plane->crtc)
83 return 0;
84
f34bc787
TR		 85 value = WINDOW_A_SELECT << p->index;
86 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
87
88 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
89 value &= ~WIN_ENABLE;
90 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
91
92 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
93 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
94
95 return 0;
96}
97
98static void tegra_plane_destroy(struct drm_plane *plane)
99{
100 tegra_plane_disable(plane);
101 drm_plane_cleanup(plane);
102}
103
104static const struct drm_plane_funcs tegra_plane_funcs = {
105 .update_plane = tegra_plane_update,
106 .disable_plane = tegra_plane_disable,
107 .destroy = tegra_plane_destroy,
108};
109
110static const uint32_t plane_formats[] = {
dbe4d9a7 111 DRM_FORMAT_XBGR8888,
f34bc787 112 DRM_FORMAT_XRGB8888,
dbe4d9a7 113 DRM_FORMAT_RGB565,
f34bc787
TR		 114 DRM_FORMAT_UYVY,
115 DRM_FORMAT_YUV420,
116 DRM_FORMAT_YUV422,
117};
118
119static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
120{
121 unsigned int i;
122 int err = 0;
123
124 for (i = 0; i < 2; i++) {
125 struct tegra_plane *plane;
126
127 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
128 if (!plane)
129 return -ENOMEM;
130
131 plane->index = 1 + i;
132
133 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
134 &tegra_plane_funcs, plane_formats,
135 ARRAY_SIZE(plane_formats), false);
136 if (err < 0)
137 return err;
138 }
139
140 return 0;
141}
142
23fb4740
TR		 143static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
144 struct drm_framebuffer *fb)
145{
ed683aea 146 unsigned int format = tegra_dc_format(fb->pixel_format);
de2ba664 147 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
23fb4740
TR		 148 unsigned long value;
149
150 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
151
152 value = fb->offsets[0] + y * fb->pitches[0] +
153 x * fb->bits_per_pixel / 8;
154
de2ba664 155 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
23fb4740 156 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
ed683aea 157 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
23fb4740
TR		 158
159 value = GENERAL_UPDATE | WIN_A_UPDATE;
160 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
161
162 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
163 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
164
165 return 0;
166}
167
6e5ff998
TR		 168void tegra_dc_enable_vblank(struct tegra_dc *dc)
169{
170 unsigned long value, flags;
171
172 spin_lock_irqsave(&dc->lock, flags);
173
174 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
175 value |= VBLANK_INT;
176 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
177
178 spin_unlock_irqrestore(&dc->lock, flags);
179}
180
181void tegra_dc_disable_vblank(struct tegra_dc *dc)
182{
183 unsigned long value, flags;
184
185 spin_lock_irqsave(&dc->lock, flags);
186
187 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
188 value &= ~VBLANK_INT;
189 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
190
191 spin_unlock_irqrestore(&dc->lock, flags);
192}
193
3c03c46a
TR		 194static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
195{
196 struct drm_device *drm = dc->base.dev;
197 struct drm_crtc *crtc = &dc->base;
3c03c46a 198 unsigned long flags, base;
de2ba664 199 struct tegra_bo *bo;
3c03c46a
TR		 200
201 if (!dc->event)
202 return;
203
de2ba664 204 bo = tegra_fb_get_plane(crtc->fb, 0);
3c03c46a
TR		 205
206 /* check if new start address has been latched */
207 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
208 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
209 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
210
de2ba664 211 if (base == bo->paddr + crtc->fb->offsets[0]) {
3c03c46a
TR		 212 spin_lock_irqsave(&drm->event_lock, flags);
213 drm_send_vblank_event(drm, dc->pipe, dc->event);
214 drm_vblank_put(drm, dc->pipe);
215 dc->event = NULL;
216 spin_unlock_irqrestore(&drm->event_lock, flags);
217 }
218}
219
220void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
221{
222 struct tegra_dc *dc = to_tegra_dc(crtc);
223 struct drm_device *drm = crtc->dev;
224 unsigned long flags;
225
226 spin_lock_irqsave(&drm->event_lock, flags);
227
228 if (dc->event && dc->event->base.file_priv == file) {
229 dc->event->base.destroy(&dc->event->base);
230 drm_vblank_put(drm, dc->pipe);
231 dc->event = NULL;
232 }
233
234 spin_unlock_irqrestore(&drm->event_lock, flags);
235}
236
237static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
238 struct drm_pending_vblank_event *event)
239{
240 struct tegra_dc *dc = to_tegra_dc(crtc);
241 struct drm_device *drm = crtc->dev;
242
243 if (dc->event)
244 return -EBUSY;
245
246 if (event) {
247 event->pipe = dc->pipe;
248 dc->event = event;
249 drm_vblank_get(drm, dc->pipe);
250 }
251
252 tegra_dc_set_base(dc, 0, 0, fb);
253 crtc->fb = fb;
254
255 return 0;
256}
257
d8f4a9ed 258static const struct drm_crtc_funcs tegra_crtc_funcs = {
3c03c46a 259 .page_flip = tegra_dc_page_flip,
d8f4a9ed
TR		 260 .set_config = drm_crtc_helper_set_config,
261 .destroy = drm_crtc_cleanup,
262};
263
f34bc787 264static void tegra_crtc_disable(struct drm_crtc *crtc)
d8f4a9ed 265{
f34bc787
TR		 266 struct drm_device *drm = crtc->dev;
267 struct drm_plane *plane;
268
269 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
270 if (plane->crtc == crtc) {
271 tegra_plane_disable(plane);
272 plane->crtc = NULL;
273
274 if (plane->fb) {
275 drm_framebuffer_unreference(plane->fb);
276 plane->fb = NULL;
277 }
278 }
279 }
d8f4a9ed
TR		 280}
281
282static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
283 const struct drm_display_mode *mode,
284 struct drm_display_mode *adjusted)
285{
286 return true;
287}
288
f34bc787 289static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
d8f4a9ed
TR		 290 unsigned int bpp)
291{
292 fixed20_12 outf = dfixed_init(out);
f34bc787 293 fixed20_12 inf = dfixed_init(in);
d8f4a9ed
TR		 294 u32 dda_inc;
295 int max;
296
297 if (v)
298 max = 15;
299 else {
300 switch (bpp) {
301 case 2:
302 max = 8;
303 break;
304
305 default:
306 WARN_ON_ONCE(1);
307 /* fallthrough */
308 case 4:
309 max = 4;
310 break;
311 }
312 }
313
314 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
315 inf.full -= dfixed_const(1);
316
317 dda_inc = dfixed_div(inf, outf);
318 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
319
320 return dda_inc;
321}
322
f34bc787 323static inline u32 compute_initial_dda(unsigned int in)
d8f4a9ed 324{
f34bc787
TR		 325 fixed20_12 inf = dfixed_init(in);
326 return dfixed_frac(inf);
d8f4a9ed
TR		 327}
328
329static int tegra_dc_set_timings(struct tegra_dc *dc,
330 struct drm_display_mode *mode)
331{
332 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
333 unsigned int h_ref_to_sync = 0;
334 unsigned int v_ref_to_sync = 0;
335 unsigned long value;
336
337 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
338
339 value = (v_ref_to_sync << 16) | h_ref_to_sync;
340 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
341
342 value = ((mode->vsync_end - mode->vsync_start) << 16) |
343 ((mode->hsync_end - mode->hsync_start) << 0);
344 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
345
d8f4a9ed
TR		 346 value = ((mode->vtotal - mode->vsync_end) << 16) |
347 ((mode->htotal - mode->hsync_end) << 0);
40495089
LS		 348 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
349
350 value = ((mode->vsync_start - mode->vdisplay) << 16) |
351 ((mode->hsync_start - mode->hdisplay) << 0);
d8f4a9ed
TR		 352 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
353
354 value = (mode->vdisplay << 16) | mode->hdisplay;
355 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
356
357 return 0;
358}
359
360static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
361 struct drm_display_mode *mode,
362 unsigned long *div)
363{
364 unsigned long pclk = mode->clock * 1000, rate;
365 struct tegra_dc *dc = to_tegra_dc(crtc);
366 struct tegra_output *output = NULL;
367 struct drm_encoder *encoder;
368 long err;
369
370 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
371 if (encoder->crtc == crtc) {
372 output = encoder_to_output(encoder);
373 break;
374 }
375
376 if (!output)
377 return -ENODEV;
378
379 /*
380 * This assumes that the display controller will divide its parent
381 * clock by 2 to generate the pixel clock.
382 */
383 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
384 if (err < 0) {
385 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
386 return err;
387 }
388
389 rate = clk_get_rate(dc->clk);
390 *div = (rate * 2 / pclk) - 2;
391
392 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
393
394 return 0;
395}
396
f34bc787
TR		 397static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
398{
399 switch (format) {
400 case WIN_COLOR_DEPTH_YCbCr422:
401 case WIN_COLOR_DEPTH_YUV422:
402 if (planar)
403 *planar = false;
404
405 return true;
406
407 case WIN_COLOR_DEPTH_YCbCr420P:
408 case WIN_COLOR_DEPTH_YUV420P:
409 case WIN_COLOR_DEPTH_YCbCr422P:
410 case WIN_COLOR_DEPTH_YUV422P:
411 case WIN_COLOR_DEPTH_YCbCr422R:
412 case WIN_COLOR_DEPTH_YUV422R:
413 case WIN_COLOR_DEPTH_YCbCr422RA:
414 case WIN_COLOR_DEPTH_YUV422RA:
415 if (planar)
416 *planar = true;
417
418 return true;
419 }
420
421 return false;
422}
423
424int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
425 const struct tegra_dc_window *window)
426{
427 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
428 unsigned long value;
429 bool yuv, planar;
430
431 /*
432 * For YUV planar modes, the number of bytes per pixel takes into
433 * account only the luma component and therefore is 1.
434 */
435 yuv = tegra_dc_format_is_yuv(window->format, &planar);
436 if (!yuv)
437 bpp = window->bits_per_pixel / 8;
438 else
439 bpp = planar ? 1 : 2;
440
441 value = WINDOW_A_SELECT << index;
442 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
443
444 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
445 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
446
447 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
448 tegra_dc_writel(dc, value, DC_WIN_POSITION);
449
450 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
451 tegra_dc_writel(dc, value, DC_WIN_SIZE);
452
453 h_offset = window->src.x * bpp;
454 v_offset = window->src.y;
455 h_size = window->src.w * bpp;
456 v_size = window->src.h;
457
458 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
459 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
460
461 /*
462 * For DDA computations the number of bytes per pixel for YUV planar
463 * modes needs to take into account all Y, U and V components.
464 */
465 if (yuv && planar)
466 bpp = 2;
467
468 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
469 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
470
471 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
472 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
473
474 h_dda = compute_initial_dda(window->src.x);
475 v_dda = compute_initial_dda(window->src.y);
476
477 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
478 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
479
480 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
481 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
482
483 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
484
485 if (yuv && planar) {
486 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
487 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
488 value = window->stride[1] << 16 | window->stride[0];
489 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
490 } else {
491 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
492 }
493
494 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
495 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
496
497 value = WIN_ENABLE;
498
499 if (yuv) {
500 /* setup default colorspace conversion coefficients */
501 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
502 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
503 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
504 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
505 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
506 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
507 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
508 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
509
510 value |= CSC_ENABLE;
84ff6b27 511 } else if (window->bits_per_pixel < 24) {
f34bc787
TR		 512 value |= COLOR_EXPAND;
513 }
514
515 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
516
517 /*
518 * Disable blending and assume Window A is the bottom-most window,
519 * Window C is the top-most window and Window B is in the middle.
520 */
521 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
522 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
523
524 switch (index) {
525 case 0:
526 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
527 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
528 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
529 break;
530
531 case 1:
532 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
533 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
534 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
535 break;
536
537 case 2:
538 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
539 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
540 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
541 break;
542 }
543
544 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
545 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
546
547 return 0;
548}
549
550unsigned int tegra_dc_format(uint32_t format)
551{
552 switch (format) {
dbe4d9a7
TR		 553 case DRM_FORMAT_XBGR8888:
554 return WIN_COLOR_DEPTH_R8G8B8A8;
555
f34bc787
TR		 556 case DRM_FORMAT_XRGB8888:
557 return WIN_COLOR_DEPTH_B8G8R8A8;
558
559 case DRM_FORMAT_RGB565:
560 return WIN_COLOR_DEPTH_B5G6R5;
561
562 case DRM_FORMAT_UYVY:
563 return WIN_COLOR_DEPTH_YCbCr422;
564
565 case DRM_FORMAT_YUV420:
566 return WIN_COLOR_DEPTH_YCbCr420P;
567
568 case DRM_FORMAT_YUV422:
569 return WIN_COLOR_DEPTH_YCbCr422P;
570
571 default:
572 break;
573 }
574
575 WARN(1, "unsupported pixel format %u, using default\n", format);
576 return WIN_COLOR_DEPTH_B8G8R8A8;
577}
578
d8f4a9ed
TR		 579static int tegra_crtc_mode_set(struct drm_crtc *crtc,
580 struct drm_display_mode *mode,
581 struct drm_display_mode *adjusted,
582 int x, int y, struct drm_framebuffer *old_fb)
583{
de2ba664 584 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
d8f4a9ed 585 struct tegra_dc *dc = to_tegra_dc(crtc);
f34bc787 586 struct tegra_dc_window window;
d8f4a9ed
TR		 587 unsigned long div, value;
588 int err;
589
6e5ff998
TR		 590 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
591
d8f4a9ed
TR		 592 err = tegra_crtc_setup_clk(crtc, mode, &div);
593 if (err) {
594 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
595 return err;
596 }
597
598 /* program display mode */
599 tegra_dc_set_timings(dc, mode);
600
601 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
602 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
603
604 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
605 value &= ~LVS_OUTPUT_POLARITY_LOW;
606 value &= ~LHS_OUTPUT_POLARITY_LOW;
607 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
608
609 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
610 DISP_ORDER_RED_BLUE;
611 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
612
613 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
614
615 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
616 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
617
618 /* setup window parameters */
f34bc787
TR		 619 memset(&window, 0, sizeof(window));
620 window.src.x = 0;
621 window.src.y = 0;
622 window.src.w = mode->hdisplay;
623 window.src.h = mode->vdisplay;
624 window.dst.x = 0;
625 window.dst.y = 0;
626 window.dst.w = mode->hdisplay;
627 window.dst.h = mode->vdisplay;
628 window.format = tegra_dc_format(crtc->fb->pixel_format);
629 window.bits_per_pixel = crtc->fb->bits_per_pixel;
630 window.stride[0] = crtc->fb->pitches[0];
de2ba664 631 window.base[0] = bo->paddr;
f34bc787
TR		 632
633 err = tegra_dc_setup_window(dc, 0, &window);
634 if (err < 0)
635 dev_err(dc->dev, "failed to enable root plane\n");
d8f4a9ed 636
d8f4a9ed
TR		 637 return 0;
638}
d8f4a9ed 639
23fb4740
TR		 640static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
641 struct drm_framebuffer *old_fb)
642{
643 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed 644
23fb4740 645 return tegra_dc_set_base(dc, x, y, crtc->fb);
d8f4a9ed
TR		 646}
647
648static void tegra_crtc_prepare(struct drm_crtc *crtc)
649{
650 struct tegra_dc *dc = to_tegra_dc(crtc);
651 unsigned int syncpt;
652 unsigned long value;
653
654 /* hardware initialization */
655 tegra_periph_reset_deassert(dc->clk);
656 usleep_range(10000, 20000);
657
658 if (dc->pipe)
659 syncpt = SYNCPT_VBLANK1;
660 else
661 syncpt = SYNCPT_VBLANK0;
662
663 /* initialize display controller */
664 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
665 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
666
667 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
668 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
669
670 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
671 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
672 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
673
674 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
675 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
676 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
677
678 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
679 value |= DISP_CTRL_MODE_C_DISPLAY;
680 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
681
682 /* initialize timer */
683 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
684 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
685 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
686
687 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
688 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
689 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
690
d8f4a9ed
TR		 691 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
692 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
6e5ff998
TR		 693
694 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
695 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
d8f4a9ed
TR		 696}
697
698static void tegra_crtc_commit(struct drm_crtc *crtc)
699{
700 struct tegra_dc *dc = to_tegra_dc(crtc);
d8f4a9ed
TR		 701 unsigned long value;
702
3b9e71ea
TR		 703 value = GENERAL_UPDATE | WIN_A_UPDATE;
704 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 705
3b9e71ea 706 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
6e5ff998 707 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
d8f4a9ed 708
6e5ff998 709 drm_vblank_post_modeset(crtc->dev, dc->pipe);
d8f4a9ed
TR		 710}
711
712static void tegra_crtc_load_lut(struct drm_crtc *crtc)
713{
714}
715
716static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
f34bc787 717 .disable = tegra_crtc_disable,
d8f4a9ed
TR		 718 .mode_fixup = tegra_crtc_mode_fixup,
719 .mode_set = tegra_crtc_mode_set,
23fb4740 720 .mode_set_base = tegra_crtc_mode_set_base,
d8f4a9ed
TR		 721 .prepare = tegra_crtc_prepare,
722 .commit = tegra_crtc_commit,
723 .load_lut = tegra_crtc_load_lut,
724};
725
6e5ff998 726static irqreturn_t tegra_dc_irq(int irq, void *data)
d8f4a9ed
TR		 727{
728 struct tegra_dc *dc = data;
729 unsigned long status;
730
731 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
732 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
733
734 if (status & FRAME_END_INT) {
735 /*
736 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
737 */
738 }
739
740 if (status & VBLANK_INT) {
741 /*
742 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
743 */
744 drm_handle_vblank(dc->base.dev, dc->pipe);
3c03c46a 745 tegra_dc_finish_page_flip(dc);
d8f4a9ed
TR		 746 }
747
748 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
749 /*
750 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
751 */
752 }
753
754 return IRQ_HANDLED;
755}
756
757static int tegra_dc_show_regs(struct seq_file *s, void *data)
758{
759 struct drm_info_node *node = s->private;
760 struct tegra_dc *dc = node->info_ent->data;
761
762#define DUMP_REG(name) \
763 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
764 tegra_dc_readl(dc, name))
765
766 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
767 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
768 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
769 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
770 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
771 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
772 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
773 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
774 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
775 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
776 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
777 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
778 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
779 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
780 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
781 DUMP_REG(DC_CMD_SIGNAL_RAISE);
782 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
783 DUMP_REG(DC_CMD_INT_STATUS);
784 DUMP_REG(DC_CMD_INT_MASK);
785 DUMP_REG(DC_CMD_INT_ENABLE);
786 DUMP_REG(DC_CMD_INT_TYPE);
787 DUMP_REG(DC_CMD_INT_POLARITY);
788 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
789 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
790 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
791 DUMP_REG(DC_CMD_STATE_ACCESS);
792 DUMP_REG(DC_CMD_STATE_CONTROL);
793 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
794 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
795 DUMP_REG(DC_COM_CRC_CONTROL);
796 DUMP_REG(DC_COM_CRC_CHECKSUM);
797 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
798 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
799 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
800 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
801 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
802 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
803 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
804 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
805 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
806 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
807 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
808 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
809 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
810 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
811 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
812 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
813 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
814 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
815 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
816 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
817 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
818 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
819 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
820 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
821 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
822 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
823 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
824 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
825 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
826 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
827 DUMP_REG(DC_COM_SPI_CONTROL);
828 DUMP_REG(DC_COM_SPI_START_BYTE);
829 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
830 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
831 DUMP_REG(DC_COM_HSPI_CS_DC);
832 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
833 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
834 DUMP_REG(DC_COM_GPIO_CTRL);
835 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
836 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
837 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
838 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
839 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
840 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
841 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
842 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
843 DUMP_REG(DC_DISP_REF_TO_SYNC);
844 DUMP_REG(DC_DISP_SYNC_WIDTH);
845 DUMP_REG(DC_DISP_BACK_PORCH);
846 DUMP_REG(DC_DISP_ACTIVE);
847 DUMP_REG(DC_DISP_FRONT_PORCH);
848 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
849 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
850 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
851 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
852 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
853 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
854 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
855 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
856 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
857 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
858 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
859 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
860 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
861 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
862 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
863 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
864 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
865 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
866 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
867 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
868 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
869 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
870 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
871 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
872 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
873 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
874 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
875 DUMP_REG(DC_DISP_M0_CONTROL);
876 DUMP_REG(DC_DISP_M1_CONTROL);
877 DUMP_REG(DC_DISP_DI_CONTROL);
878 DUMP_REG(DC_DISP_PP_CONTROL);
879 DUMP_REG(DC_DISP_PP_SELECT_A);
880 DUMP_REG(DC_DISP_PP_SELECT_B);
881 DUMP_REG(DC_DISP_PP_SELECT_C);
882 DUMP_REG(DC_DISP_PP_SELECT_D);
883 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
884 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
885 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
886 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
887 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
888 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
889 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
890 DUMP_REG(DC_DISP_BORDER_COLOR);
891 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
892 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
893 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
894 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
895 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
896 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
897 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
898 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
899 DUMP_REG(DC_DISP_CURSOR_POSITION);
900 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
901 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
902 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
903 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
904 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
905 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
906 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
907 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
908 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
909 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
910 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
911 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
912 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
913 DUMP_REG(DC_DISP_SD_CONTROL);
914 DUMP_REG(DC_DISP_SD_CSC_COEFF);
915 DUMP_REG(DC_DISP_SD_LUT(0));
916 DUMP_REG(DC_DISP_SD_LUT(1));
917 DUMP_REG(DC_DISP_SD_LUT(2));
918 DUMP_REG(DC_DISP_SD_LUT(3));
919 DUMP_REG(DC_DISP_SD_LUT(4));
920 DUMP_REG(DC_DISP_SD_LUT(5));
921 DUMP_REG(DC_DISP_SD_LUT(6));
922 DUMP_REG(DC_DISP_SD_LUT(7));
923 DUMP_REG(DC_DISP_SD_LUT(8));
924 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
925 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
926 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
927 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
928 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
929 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
930 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
931 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
932 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
933 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
934 DUMP_REG(DC_DISP_SD_BL_TF(0));
935 DUMP_REG(DC_DISP_SD_BL_TF(1));
936 DUMP_REG(DC_DISP_SD_BL_TF(2));
937 DUMP_REG(DC_DISP_SD_BL_TF(3));
938 DUMP_REG(DC_DISP_SD_BL_CONTROL);
939 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
940 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
941 DUMP_REG(DC_WIN_WIN_OPTIONS);
942 DUMP_REG(DC_WIN_BYTE_SWAP);
943 DUMP_REG(DC_WIN_BUFFER_CONTROL);
944 DUMP_REG(DC_WIN_COLOR_DEPTH);
945 DUMP_REG(DC_WIN_POSITION);
946 DUMP_REG(DC_WIN_SIZE);
947 DUMP_REG(DC_WIN_PRESCALED_SIZE);
948 DUMP_REG(DC_WIN_H_INITIAL_DDA);
949 DUMP_REG(DC_WIN_V_INITIAL_DDA);
950 DUMP_REG(DC_WIN_DDA_INC);
951 DUMP_REG(DC_WIN_LINE_STRIDE);
952 DUMP_REG(DC_WIN_BUF_STRIDE);
953 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
954 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
955 DUMP_REG(DC_WIN_DV_CONTROL);
956 DUMP_REG(DC_WIN_BLEND_NOKEY);
957 DUMP_REG(DC_WIN_BLEND_1WIN);
958 DUMP_REG(DC_WIN_BLEND_2WIN_X);
959 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
f34bc787 960 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
d8f4a9ed
TR		 961 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
962 DUMP_REG(DC_WINBUF_START_ADDR);
963 DUMP_REG(DC_WINBUF_START_ADDR_NS);
964 DUMP_REG(DC_WINBUF_START_ADDR_U);
965 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
966 DUMP_REG(DC_WINBUF_START_ADDR_V);
967 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
968 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
969 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
970 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
971 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
972 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
973 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
974 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
975 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
976
977#undef DUMP_REG
978
979 return 0;
980}
981
982static struct drm_info_list debugfs_files[] = {
983 { "regs", tegra_dc_show_regs, 0, NULL },
984};
985
986static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
987{
988 unsigned int i;
989 char *name;
990 int err;
991
992 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
993 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
994 kfree(name);
995
996 if (!dc->debugfs)
997 return -ENOMEM;
998
999 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1000 GFP_KERNEL);
1001 if (!dc->debugfs_files) {
1002 err = -ENOMEM;
1003 goto remove;
1004 }
1005
1006 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1007 dc->debugfs_files[i].data = dc;
1008
1009 err = drm_debugfs_create_files(dc->debugfs_files,
1010 ARRAY_SIZE(debugfs_files),
1011 dc->debugfs, minor);
1012 if (err < 0)
1013 goto free;
1014
1015 dc->minor = minor;
1016
1017 return 0;
1018
1019free:
1020 kfree(dc->debugfs_files);
1021 dc->debugfs_files = NULL;
1022remove:
1023 debugfs_remove(dc->debugfs);
1024 dc->debugfs = NULL;
1025
1026 return err;
1027}
1028
1029static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1030{
1031 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1032 dc->minor);
1033 dc->minor = NULL;
1034
1035 kfree(dc->debugfs_files);
1036 dc->debugfs_files = NULL;
1037
1038 debugfs_remove(dc->debugfs);
1039 dc->debugfs = NULL;
1040
1041 return 0;
1042}
1043
1044static int tegra_dc_drm_init(struct host1x_client *client,
1045 struct drm_device *drm)
1046{
1047 struct tegra_dc *dc = host1x_client_to_dc(client);
1048 int err;
1049
1050 dc->pipe = drm->mode_config.num_crtc;
1051
1052 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1053 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1054 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1055
1056 err = tegra_dc_rgb_init(drm, dc);
1057 if (err < 0 && err != -ENODEV) {
1058 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1059 return err;
1060 }
1061
f34bc787
TR		 1062 err = tegra_dc_add_planes(drm, dc);
1063 if (err < 0)
1064 return err;
1065
d8f4a9ed
TR		 1066 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1067 err = tegra_dc_debugfs_init(dc, drm->primary);
1068 if (err < 0)
1069 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1070 }
1071
6e5ff998 1072 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
d8f4a9ed
TR		 1073 dev_name(dc->dev), dc);
1074 if (err < 0) {
1075 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1076 err);
1077 return err;
1078 }
1079
1080 return 0;
1081}
1082
1083static int tegra_dc_drm_exit(struct host1x_client *client)
1084{
1085 struct tegra_dc *dc = host1x_client_to_dc(client);
1086 int err;
1087
1088 devm_free_irq(dc->dev, dc->irq, dc);
1089
1090 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1091 err = tegra_dc_debugfs_exit(dc);
1092 if (err < 0)
1093 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1094 }
1095
1096 err = tegra_dc_rgb_exit(dc);
1097 if (err) {
1098 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1099 return err;
1100 }
1101
1102 return 0;
1103}
1104
1105static const struct host1x_client_ops dc_client_ops = {
1106 .drm_init = tegra_dc_drm_init,
1107 .drm_exit = tegra_dc_drm_exit,
1108};
1109
1110static int tegra_dc_probe(struct platform_device *pdev)
1111{
692e6d7b 1112 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1113 struct resource *regs;
1114 struct tegra_dc *dc;
1115 int err;
1116
1117 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1118 if (!dc)
1119 return -ENOMEM;
1120
6e5ff998 1121 spin_lock_init(&dc->lock);
d8f4a9ed
TR		 1122 INIT_LIST_HEAD(&dc->list);
1123 dc->dev = &pdev->dev;
1124
1125 dc->clk = devm_clk_get(&pdev->dev, NULL);
1126 if (IS_ERR(dc->clk)) {
1127 dev_err(&pdev->dev, "failed to get clock\n");
1128 return PTR_ERR(dc->clk);
1129 }
1130
1131 err = clk_prepare_enable(dc->clk);
1132 if (err < 0)
1133 return err;
1134
1135 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d4ed6025
TR		 1136 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1137 if (IS_ERR(dc->regs))
1138 return PTR_ERR(dc->regs);
d8f4a9ed
TR		 1139
1140 dc->irq = platform_get_irq(pdev, 0);
1141 if (dc->irq < 0) {
1142 dev_err(&pdev->dev, "failed to get IRQ\n");
1143 return -ENXIO;
1144 }
1145
1146 INIT_LIST_HEAD(&dc->client.list);
1147 dc->client.ops = &dc_client_ops;
1148 dc->client.dev = &pdev->dev;
1149
1150 err = tegra_dc_rgb_probe(dc);
1151 if (err < 0 && err != -ENODEV) {
1152 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1153 return err;
1154 }
1155
1156 err = host1x_register_client(host1x, &dc->client);
1157 if (err < 0) {
1158 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1159 err);
1160 return err;
1161 }
1162
1163 platform_set_drvdata(pdev, dc);
1164
1165 return 0;
1166}
1167
1168static int tegra_dc_remove(struct platform_device *pdev)
1169{
692e6d7b 1170 struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
d8f4a9ed
TR		 1171 struct tegra_dc *dc = platform_get_drvdata(pdev);
1172 int err;
1173
1174 err = host1x_unregister_client(host1x, &dc->client);
1175 if (err < 0) {
1176 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1177 err);
1178 return err;
1179 }
1180
1181 clk_disable_unprepare(dc->clk);
1182
1183 return 0;
1184}
1185
1186static struct of_device_id tegra_dc_of_match[] = {
219e8153 1187 { .compatible = "nvidia,tegra30-dc", },
d8f4a9ed
TR		 1188 { .compatible = "nvidia,tegra20-dc", },
1189 { },
1190};
1191
1192struct platform_driver tegra_dc_driver = {
1193 .driver = {
1194 .name = "tegra-dc",
1195 .owner = THIS_MODULE,
1196 .of_match_table = tegra_dc_of_match,
1197 },
1198 .probe = tegra_dc_probe,
1199 .remove = tegra_dc_remove,
1200};
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