[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / host1x / mipi.c

/*
 * Copyright (C) 2013 NVIDIA Corporation
 *
 * Permission to use, copy, modify, distribute, and sell this software and its
 * documentation for any purpose is hereby granted without fee, provided that
 * the above copyright notice appear in all copies and that both that copyright
 * notice and this permission notice appear in supporting documentation, and
 * that the name of the copyright holders not be used in advertising or
 * publicity pertaining to distribution of the software without specific,
 * written prior permission.  The copyright holders make no representations
 * about the suitability of this software for any purpose.  It is provided "as
 * is" without express or implied warranty.
 *
 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 * OF THIS SOFTWARE.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/host1x.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "dev.h"

#define MIPI_CAL_CTRL			0x00
#define MIPI_CAL_CTRL_START		(1 << 0)

#define MIPI_CAL_AUTOCAL_CTRL		0x01

#define MIPI_CAL_STATUS			0x02
#define MIPI_CAL_STATUS_DONE		(1 << 16)
#define MIPI_CAL_STATUS_ACTIVE		(1 <<  0)

#define MIPI_CAL_CONFIG_CSIA		0x05
#define MIPI_CAL_CONFIG_CSIB		0x06
#define MIPI_CAL_CONFIG_CSIC		0x07
#define MIPI_CAL_CONFIG_CSID		0x08
#define MIPI_CAL_CONFIG_CSIE		0x09
#define MIPI_CAL_CONFIG_DSIA		0x0e
#define MIPI_CAL_CONFIG_DSIB		0x0f
#define MIPI_CAL_CONFIG_DSIC		0x10
#define MIPI_CAL_CONFIG_DSID		0x11

#define MIPI_CAL_CONFIG_SELECT		(1 << 21)
#define MIPI_CAL_CONFIG_HSPDOS(x)	(((x) & 0x1f) << 16)
#define MIPI_CAL_CONFIG_HSPUOS(x)	(((x) & 0x1f) <<  8)
#define MIPI_CAL_CONFIG_TERMOS(x)	(((x) & 0x1f) <<  0)

#define MIPI_CAL_BIAS_PAD_CFG0		0x16
#define MIPI_CAL_BIAS_PAD_PDVCLAMP	(1 << 1)
#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF	(1 << 0)

#define MIPI_CAL_BIAS_PAD_CFG1		0x17

#define MIPI_CAL_BIAS_PAD_CFG2		0x18
#define MIPI_CAL_BIAS_PAD_PDVREG	(1 << 1)

static const struct module {
	unsigned long reg;
} modules[] = {
	{ .reg = MIPI_CAL_CONFIG_CSIA },
	{ .reg = MIPI_CAL_CONFIG_CSIB },
	{ .reg = MIPI_CAL_CONFIG_CSIC },
	{ .reg = MIPI_CAL_CONFIG_CSID },
	{ .reg = MIPI_CAL_CONFIG_CSIE },
	{ .reg = MIPI_CAL_CONFIG_DSIA },
	{ .reg = MIPI_CAL_CONFIG_DSIB },
	{ .reg = MIPI_CAL_CONFIG_DSIC },
	{ .reg = MIPI_CAL_CONFIG_DSID },
};

struct tegra_mipi {
	void __iomem *regs;
	struct mutex lock;
	struct clk *clk;
};

struct tegra_mipi_device {
	struct platform_device *pdev;
	struct tegra_mipi *mipi;
	struct device *device;
	unsigned long pads;
};

static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
				   unsigned long offset)
{
	return readl(mipi->regs + (offset << 2));
}

static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
				     unsigned long offset)
{
	writel(value, mipi->regs + (offset << 2));
}

struct tegra_mipi_device *tegra_mipi_request(struct device *device)
{
	struct device_node *np = device->of_node;
	struct tegra_mipi_device *dev;
	struct of_phandle_args args;
	int err;

	err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
					 "#nvidia,mipi-calibrate-cells", 0,
					 &args);
	if (err < 0)
		return ERR_PTR(err);

	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (!dev) {
		of_node_put(args.np);
		err = -ENOMEM;
		goto out;
	}

	dev->pdev = of_find_device_by_node(args.np);
	if (!dev->pdev) {
		of_node_put(args.np);
		err = -ENODEV;
		goto free;
	}

	of_node_put(args.np);

	dev->mipi = platform_get_drvdata(dev->pdev);
	if (!dev->mipi) {
		err = -EPROBE_DEFER;
		goto pdev_put;
	}

	dev->pads = args.args[0];
	dev->device = device;

	return dev;

pdev_put:
	platform_device_put(dev->pdev);
free:
	kfree(dev);
out:
	return ERR_PTR(err);
}
EXPORT_SYMBOL(tegra_mipi_request);

void tegra_mipi_free(struct tegra_mipi_device *device)
{
	platform_device_put(device->pdev);
	kfree(device);
}
EXPORT_SYMBOL(tegra_mipi_free);

static int tegra_mipi_wait(struct tegra_mipi *mipi)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(250);
	u32 value;

	while (time_before(jiffies, timeout)) {
		value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
		if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
		    (value & MIPI_CAL_STATUS_DONE) != 0)
			return 0;

		usleep_range(10, 50);
	}

	return -ETIMEDOUT;
}

int tegra_mipi_calibrate(struct tegra_mipi_device *device)
{
	unsigned int i;
	u32 value;
	int err;

	err = clk_enable(device->mipi->clk);
	if (err < 0)
		return err;

	mutex_lock(&device->mipi->lock);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
	value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
	value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);

	for (i = 0; i < ARRAY_SIZE(modules); i++) {
		if (device->pads & BIT(i))
			value = MIPI_CAL_CONFIG_SELECT |
				MIPI_CAL_CONFIG_HSPDOS(0) |
				MIPI_CAL_CONFIG_HSPUOS(4) |
				MIPI_CAL_CONFIG_TERMOS(5);
		else
			value = 0;

		tegra_mipi_writel(device->mipi, value, modules[i].reg);
	}

	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	value |= MIPI_CAL_CTRL_START;
	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);

	err = tegra_mipi_wait(device->mipi);

	mutex_unlock(&device->mipi->lock);
	clk_disable(device->mipi->clk);

	return err;
}
EXPORT_SYMBOL(tegra_mipi_calibrate);

static int tegra_mipi_probe(struct platform_device *pdev)
{
	struct tegra_mipi *mipi;
	struct resource *res;
	int err;

	mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
	if (!mipi)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mipi->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mipi->regs))
		return PTR_ERR(mipi->regs);

	mutex_init(&mipi->lock);

	mipi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mipi->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(mipi->clk);
	}

	err = clk_prepare(mipi->clk);
	if (err < 0)
		return err;

	platform_set_drvdata(pdev, mipi);

	return 0;
}

static int tegra_mipi_remove(struct platform_device *pdev)
{
	struct tegra_mipi *mipi = platform_get_drvdata(pdev);

	clk_unprepare(mipi->clk);

	return 0;
}

static struct of_device_id tegra_mipi_of_match[] = {
	{ .compatible = "nvidia,tegra114-mipi", },
	{ },
};

struct platform_driver tegra_mipi_driver = {
	.driver = {
		.name = "tegra-mipi",
		.of_match_table = tegra_mipi_of_match,
	},
	.probe = tegra_mipi_probe,
	.remove = tegra_mipi_remove,
};
Commit	Line	Data
4de6a2d6 TR	1	/*
	2	* Copyright (C) 2013 NVIDIA Corporation
	3	*
	4	* Permission to use, copy, modify, distribute, and sell this software and its
	5	* documentation for any purpose is hereby granted without fee, provided that
	6	* the above copyright notice appear in all copies and that both that copyright
	7	* notice and this permission notice appear in supporting documentation, and
	8	* that the name of the copyright holders not be used in advertising or
	9	* publicity pertaining to distribution of the software without specific,
	10	* written prior permission. The copyright holders make no representations
	11	* about the suitability of this software for any purpose. It is provided "as
	12	* is" without express or implied warranty.
	13	*
	14	* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
	15	* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
	16	* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
	17	* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
	18	* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
	19	* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
	20	* OF THIS SOFTWARE.
	21	*/
	22
	23	#include <linux/clk.h>
	24	#include <linux/delay.h>
aef03d3f	25	#include <linux/host1x.h>
4de6a2d6 TR	26	#include <linux/io.h>
	27	#include <linux/of_platform.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/slab.h>
	30
aef03d3f TR	31	#include "dev.h"
aef03d3f TR	32
4de6a2d6 TR	33	#define MIPI_CAL_CTRL 0x00
	34	#define MIPI_CAL_CTRL_START (1 << 0)
	35
	36	#define MIPI_CAL_AUTOCAL_CTRL 0x01
	37
	38	#define MIPI_CAL_STATUS 0x02
	39	#define MIPI_CAL_STATUS_DONE (1 << 16)
	40	#define MIPI_CAL_STATUS_ACTIVE (1 << 0)
	41
	42	#define MIPI_CAL_CONFIG_CSIA 0x05
	43	#define MIPI_CAL_CONFIG_CSIB 0x06
	44	#define MIPI_CAL_CONFIG_CSIC 0x07
	45	#define MIPI_CAL_CONFIG_CSID 0x08
	46	#define MIPI_CAL_CONFIG_CSIE 0x09
	47	#define MIPI_CAL_CONFIG_DSIA 0x0e
	48	#define MIPI_CAL_CONFIG_DSIB 0x0f
	49	#define MIPI_CAL_CONFIG_DSIC 0x10
	50	#define MIPI_CAL_CONFIG_DSID 0x11
	51
	52	#define MIPI_CAL_CONFIG_SELECT (1 << 21)
	53	#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
	54	#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
	55	#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
	56
	57	#define MIPI_CAL_BIAS_PAD_CFG0 0x16
	58	#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
	59	#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
	60
	61	#define MIPI_CAL_BIAS_PAD_CFG1 0x17
	62
	63	#define MIPI_CAL_BIAS_PAD_CFG2 0x18
	64	#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
	65
	66	static const struct module {
	67	unsigned long reg;
	68	} modules[] = {
	69	{ .reg = MIPI_CAL_CONFIG_CSIA },
	70	{ .reg = MIPI_CAL_CONFIG_CSIB },
	71	{ .reg = MIPI_CAL_CONFIG_CSIC },
	72	{ .reg = MIPI_CAL_CONFIG_CSID },
	73	{ .reg = MIPI_CAL_CONFIG_CSIE },
	74	{ .reg = MIPI_CAL_CONFIG_DSIA },
	75	{ .reg = MIPI_CAL_CONFIG_DSIB },
	76	{ .reg = MIPI_CAL_CONFIG_DSIC },
	77	{ .reg = MIPI_CAL_CONFIG_DSID },
	78	};
	79
	80	struct tegra_mipi {
	81	void __iomem *regs;
	82	struct mutex lock;
	83	struct clk *clk;
	84	};
	85
	86	struct tegra_mipi_device {
	87	struct platform_device *pdev;
	88	struct tegra_mipi *mipi;
	89	struct device *device;
	90	unsigned long pads;
	91	};
	92
57b17ae7 TR	93	static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
57b17ae7 TR	94	unsigned long offset)
4de6a2d6	95	{
57b17ae7	96	return readl(mipi->regs + (offset << 2));
4de6a2d6 TR	97	}
4de6a2d6 TR	98
57b17ae7 TR	99	static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
57b17ae7 TR	100	unsigned long offset)
4de6a2d6	101	{
57b17ae7	102	writel(value, mipi->regs + (offset << 2));
4de6a2d6 TR	103	}
	104
	105	struct tegra_mipi_device tegra_mipi_request(struct device device)
	106	{
	107	struct device_node *np = device->of_node;
	108	struct tegra_mipi_device *dev;
	109	struct of_phandle_args args;
	110	int err;
	111
	112	err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
	113	"#nvidia,mipi-calibrate-cells", 0,
	114	&args);
	115	if (err < 0)
	116	return ERR_PTR(err);
	117
	118	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	119	if (!dev) {
	120	of_node_put(args.np);
	121	err = -ENOMEM;
	122	goto out;
	123	}
	124
	125	dev->pdev = of_find_device_by_node(args.np);
	126	if (!dev->pdev) {
	127	of_node_put(args.np);
	128	err = -ENODEV;
	129	goto free;
	130	}
	131
	132	of_node_put(args.np);
	133
	134	dev->mipi = platform_get_drvdata(dev->pdev);
	135	if (!dev->mipi) {
	136	err = -EPROBE_DEFER;
	137	goto pdev_put;
	138	}
	139
	140	dev->pads = args.args[0];
	141	dev->device = device;
	142
	143	return dev;
	144
	145	pdev_put:
	146	platform_device_put(dev->pdev);
	147	free:
	148	kfree(dev);
	149	out:
	150	return ERR_PTR(err);
	151	}
	152	EXPORT_SYMBOL(tegra_mipi_request);
	153
	154	void tegra_mipi_free(struct tegra_mipi_device *device)
	155	{
	156	platform_device_put(device->pdev);
	157	kfree(device);
	158	}
	159	EXPORT_SYMBOL(tegra_mipi_free);
	160
	161	static int tegra_mipi_wait(struct tegra_mipi *mipi)
	162	{
	163	unsigned long timeout = jiffies + msecs_to_jiffies(250);
57b17ae7	164	u32 value;
4de6a2d6 TR	165
	166	while (time_before(jiffies, timeout)) {
	167	value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
	168	if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
	169	(value & MIPI_CAL_STATUS_DONE) != 0)
	170	return 0;
	171
	172	usleep_range(10, 50);
	173	}
	174
	175	return -ETIMEDOUT;
	176	}
	177
	178	int tegra_mipi_calibrate(struct tegra_mipi_device *device)
	179	{
4de6a2d6	180	unsigned int i;
57b17ae7	181	u32 value;
4de6a2d6 TR	182	int err;
	183
	184	err = clk_enable(device->mipi->clk);
	185	if (err < 0)
	186	return err;
	187
	188	mutex_lock(&device->mipi->lock);
	189
	190	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
	191	value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
	192	value \|= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
	193	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
	194
	195	value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
	196	value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
	197	tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
	198
	199	for (i = 0; i < ARRAY_SIZE(modules); i++) {
	200	if (device->pads & BIT(i))
	201	value = MIPI_CAL_CONFIG_SELECT \|
	202	MIPI_CAL_CONFIG_HSPDOS(0) \|
	203	MIPI_CAL_CONFIG_HSPUOS(4) \|
	204	MIPI_CAL_CONFIG_TERMOS(5);
	205	else
	206	value = 0;
	207
	208	tegra_mipi_writel(device->mipi, value, modules[i].reg);
	209	}
	210
26f7a92a SP	211	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
	212	value \|= MIPI_CAL_CTRL_START;
	213	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
4de6a2d6 TR	214
	215	err = tegra_mipi_wait(device->mipi);
	216
	217	mutex_unlock(&device->mipi->lock);
	218	clk_disable(device->mipi->clk);
	219
	220	return err;
	221	}
	222	EXPORT_SYMBOL(tegra_mipi_calibrate);
	223
	224	static int tegra_mipi_probe(struct platform_device *pdev)
	225	{
	226	struct tegra_mipi *mipi;
	227	struct resource *res;
	228	int err;
	229
	230	mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
	231	if (!mipi)
	232	return -ENOMEM;
	233
	234	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	235	mipi->regs = devm_ioremap_resource(&pdev->dev, res);
	236	if (IS_ERR(mipi->regs))
	237	return PTR_ERR(mipi->regs);
	238
	239	mutex_init(&mipi->lock);
	240
	241	mipi->clk = devm_clk_get(&pdev->dev, NULL);
	242	if (IS_ERR(mipi->clk)) {
	243	dev_err(&pdev->dev, "failed to get clock\n");
	244	return PTR_ERR(mipi->clk);
	245	}
	246
	247	err = clk_prepare(mipi->clk);
	248	if (err < 0)
	249	return err;
	250
	251	platform_set_drvdata(pdev, mipi);
	252
	253	return 0;
	254	}
	255
	256	static int tegra_mipi_remove(struct platform_device *pdev)
	257	{
	258	struct tegra_mipi *mipi = platform_get_drvdata(pdev);
	259
	260	clk_unprepare(mipi->clk);
	261
	262	return 0;
	263	}
	264
	265	static struct of_device_id tegra_mipi_of_match[] = {
	266	{ .compatible = "nvidia,tegra114-mipi", },
	267	{ },
	268	};
	269
	270	struct platform_driver tegra_mipi_driver = {
	271	.driver = {
	272	.name = "tegra-mipi",
	273	.of_match_table = tegra_mipi_of_match,
	274	},
	275	.probe = tegra_mipi_probe,
	276	.remove = tegra_mipi_remove,
	277	};