]>
Commit | Line | Data |
---|---|---|
aecfbdb1 SH |
1 | /* |
2 | * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | */ | |
15 | #include <linux/module.h> | |
16 | #include <linux/export.h> | |
17 | #include <linux/types.h> | |
6c64155d | 18 | #include <linux/reset.h> |
aecfbdb1 SH |
19 | #include <linux/platform_device.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/irq.h> | |
de88cbb7 | 28 | #include <linux/irqchip/chained_irq.h> |
b728766c | 29 | #include <linux/irqdomain.h> |
aecfbdb1 | 30 | #include <linux/of_device.h> |
aecfbdb1 | 31 | |
7cb17797 PZ |
32 | #include <drm/drm_fourcc.h> |
33 | ||
39b9004d | 34 | #include <video/imx-ipu-v3.h> |
aecfbdb1 SH |
35 | #include "ipu-prv.h" |
36 | ||
37 | static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) | |
38 | { | |
39 | return readl(ipu->cm_reg + offset); | |
40 | } | |
41 | ||
42 | static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) | |
43 | { | |
44 | writel(value, ipu->cm_reg + offset); | |
45 | } | |
46 | ||
aecfbdb1 SH |
47 | void ipu_srm_dp_sync_update(struct ipu_soc *ipu) |
48 | { | |
49 | u32 val; | |
50 | ||
51 | val = ipu_cm_read(ipu, IPU_SRM_PRI2); | |
52 | val |= 0x8; | |
53 | ipu_cm_write(ipu, val, IPU_SRM_PRI2); | |
54 | } | |
55 | EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); | |
56 | ||
7cb17797 PZ |
57 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) |
58 | { | |
59 | switch (drm_fourcc) { | |
60 | case DRM_FORMAT_RGB565: | |
61 | case DRM_FORMAT_BGR565: | |
62 | case DRM_FORMAT_RGB888: | |
63 | case DRM_FORMAT_BGR888: | |
64 | case DRM_FORMAT_XRGB8888: | |
65 | case DRM_FORMAT_XBGR8888: | |
66 | case DRM_FORMAT_RGBX8888: | |
67 | case DRM_FORMAT_BGRX8888: | |
68 | case DRM_FORMAT_ARGB8888: | |
69 | case DRM_FORMAT_ABGR8888: | |
70 | case DRM_FORMAT_RGBA8888: | |
71 | case DRM_FORMAT_BGRA8888: | |
72 | return IPUV3_COLORSPACE_RGB; | |
73 | case DRM_FORMAT_YUYV: | |
74 | case DRM_FORMAT_UYVY: | |
75 | case DRM_FORMAT_YUV420: | |
76 | case DRM_FORMAT_YVU420: | |
77 | return IPUV3_COLORSPACE_YUV; | |
78 | default: | |
79 | return IPUV3_COLORSPACE_UNKNOWN; | |
80 | } | |
81 | } | |
82 | EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); | |
83 | ||
aecfbdb1 SH |
84 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) |
85 | { | |
86 | switch (pixelformat) { | |
87 | case V4L2_PIX_FMT_YUV420: | |
d3e4e610 | 88 | case V4L2_PIX_FMT_YVU420: |
aecfbdb1 | 89 | case V4L2_PIX_FMT_UYVY: |
c096ae13 | 90 | case V4L2_PIX_FMT_YUYV: |
aecfbdb1 SH |
91 | return IPUV3_COLORSPACE_YUV; |
92 | case V4L2_PIX_FMT_RGB32: | |
93 | case V4L2_PIX_FMT_BGR32: | |
94 | case V4L2_PIX_FMT_RGB24: | |
95 | case V4L2_PIX_FMT_BGR24: | |
96 | case V4L2_PIX_FMT_RGB565: | |
97 | return IPUV3_COLORSPACE_RGB; | |
98 | default: | |
99 | return IPUV3_COLORSPACE_UNKNOWN; | |
100 | } | |
101 | } | |
102 | EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); | |
103 | ||
104 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) | |
105 | { | |
106 | struct ipuv3_channel *channel; | |
107 | ||
108 | dev_dbg(ipu->dev, "%s %d\n", __func__, num); | |
109 | ||
110 | if (num > 63) | |
111 | return ERR_PTR(-ENODEV); | |
112 | ||
113 | mutex_lock(&ipu->channel_lock); | |
114 | ||
115 | channel = &ipu->channel[num]; | |
116 | ||
117 | if (channel->busy) { | |
118 | channel = ERR_PTR(-EBUSY); | |
119 | goto out; | |
120 | } | |
121 | ||
89bc5be7 | 122 | channel->busy = true; |
aecfbdb1 SH |
123 | channel->num = num; |
124 | ||
125 | out: | |
126 | mutex_unlock(&ipu->channel_lock); | |
127 | ||
128 | return channel; | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(ipu_idmac_get); | |
131 | ||
132 | void ipu_idmac_put(struct ipuv3_channel *channel) | |
133 | { | |
134 | struct ipu_soc *ipu = channel->ipu; | |
135 | ||
136 | dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); | |
137 | ||
138 | mutex_lock(&ipu->channel_lock); | |
139 | ||
89bc5be7 | 140 | channel->busy = false; |
aecfbdb1 SH |
141 | |
142 | mutex_unlock(&ipu->channel_lock); | |
143 | } | |
144 | EXPORT_SYMBOL_GPL(ipu_idmac_put); | |
145 | ||
146 | #define idma_mask(ch) (1 << (ch & 0x1f)) | |
147 | ||
148 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, | |
149 | bool doublebuffer) | |
150 | { | |
151 | struct ipu_soc *ipu = channel->ipu; | |
152 | unsigned long flags; | |
153 | u32 reg; | |
154 | ||
155 | spin_lock_irqsave(&ipu->lock, flags); | |
156 | ||
157 | reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); | |
158 | if (doublebuffer) | |
159 | reg |= idma_mask(channel->num); | |
160 | else | |
161 | reg &= ~idma_mask(channel->num); | |
162 | ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); | |
163 | ||
164 | spin_unlock_irqrestore(&ipu->lock, flags); | |
165 | } | |
166 | EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); | |
167 | ||
168 | int ipu_module_enable(struct ipu_soc *ipu, u32 mask) | |
169 | { | |
170 | unsigned long lock_flags; | |
171 | u32 val; | |
172 | ||
173 | spin_lock_irqsave(&ipu->lock, lock_flags); | |
174 | ||
175 | val = ipu_cm_read(ipu, IPU_DISP_GEN); | |
176 | ||
177 | if (mask & IPU_CONF_DI0_EN) | |
178 | val |= IPU_DI0_COUNTER_RELEASE; | |
179 | if (mask & IPU_CONF_DI1_EN) | |
180 | val |= IPU_DI1_COUNTER_RELEASE; | |
181 | ||
182 | ipu_cm_write(ipu, val, IPU_DISP_GEN); | |
183 | ||
184 | val = ipu_cm_read(ipu, IPU_CONF); | |
185 | val |= mask; | |
186 | ipu_cm_write(ipu, val, IPU_CONF); | |
187 | ||
188 | spin_unlock_irqrestore(&ipu->lock, lock_flags); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | EXPORT_SYMBOL_GPL(ipu_module_enable); | |
193 | ||
194 | int ipu_module_disable(struct ipu_soc *ipu, u32 mask) | |
195 | { | |
196 | unsigned long lock_flags; | |
197 | u32 val; | |
198 | ||
199 | spin_lock_irqsave(&ipu->lock, lock_flags); | |
200 | ||
201 | val = ipu_cm_read(ipu, IPU_CONF); | |
202 | val &= ~mask; | |
203 | ipu_cm_write(ipu, val, IPU_CONF); | |
204 | ||
205 | val = ipu_cm_read(ipu, IPU_DISP_GEN); | |
206 | ||
207 | if (mask & IPU_CONF_DI0_EN) | |
208 | val &= ~IPU_DI0_COUNTER_RELEASE; | |
209 | if (mask & IPU_CONF_DI1_EN) | |
210 | val &= ~IPU_DI1_COUNTER_RELEASE; | |
211 | ||
212 | ipu_cm_write(ipu, val, IPU_DISP_GEN); | |
213 | ||
214 | spin_unlock_irqrestore(&ipu->lock, lock_flags); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(ipu_module_disable); | |
219 | ||
3f5a8a94 PZ |
220 | int ipu_smfc_enable(struct ipu_soc *ipu) |
221 | { | |
222 | return ipu_module_enable(ipu, IPU_CONF_SMFC_EN); | |
223 | } | |
224 | EXPORT_SYMBOL_GPL(ipu_smfc_enable); | |
225 | ||
226 | int ipu_smfc_disable(struct ipu_soc *ipu) | |
227 | { | |
228 | return ipu_module_disable(ipu, IPU_CONF_SMFC_EN); | |
229 | } | |
230 | EXPORT_SYMBOL_GPL(ipu_smfc_disable); | |
231 | ||
e9046097 PZ |
232 | int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) |
233 | { | |
234 | struct ipu_soc *ipu = channel->ipu; | |
235 | unsigned int chno = channel->num; | |
236 | ||
237 | return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); | |
240 | ||
aecfbdb1 SH |
241 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) |
242 | { | |
243 | struct ipu_soc *ipu = channel->ipu; | |
244 | unsigned int chno = channel->num; | |
245 | unsigned long flags; | |
246 | ||
247 | spin_lock_irqsave(&ipu->lock, flags); | |
248 | ||
249 | /* Mark buffer as ready. */ | |
250 | if (buf_num == 0) | |
251 | ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); | |
252 | else | |
253 | ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); | |
254 | ||
255 | spin_unlock_irqrestore(&ipu->lock, flags); | |
256 | } | |
257 | EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); | |
258 | ||
259 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel) | |
260 | { | |
261 | struct ipu_soc *ipu = channel->ipu; | |
262 | u32 val; | |
263 | unsigned long flags; | |
264 | ||
265 | spin_lock_irqsave(&ipu->lock, flags); | |
266 | ||
267 | val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); | |
268 | val |= idma_mask(channel->num); | |
269 | ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); | |
270 | ||
271 | spin_unlock_irqrestore(&ipu->lock, flags); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); | |
276 | ||
17075504 PZ |
277 | bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) |
278 | { | |
279 | return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); | |
280 | } | |
281 | EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy); | |
282 | ||
fb822a39 | 283 | int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) |
aecfbdb1 SH |
284 | { |
285 | struct ipu_soc *ipu = channel->ipu; | |
aecfbdb1 SH |
286 | unsigned long timeout; |
287 | ||
fb822a39 | 288 | timeout = jiffies + msecs_to_jiffies(ms); |
aecfbdb1 SH |
289 | while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & |
290 | idma_mask(channel->num)) { | |
fb822a39 SH |
291 | if (time_after(jiffies, timeout)) |
292 | return -ETIMEDOUT; | |
aecfbdb1 SH |
293 | cpu_relax(); |
294 | } | |
295 | ||
fb822a39 SH |
296 | return 0; |
297 | } | |
298 | EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); | |
299 | ||
17075504 PZ |
300 | int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms) |
301 | { | |
302 | unsigned long timeout; | |
303 | ||
304 | timeout = jiffies + msecs_to_jiffies(ms); | |
305 | ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32)); | |
306 | while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) { | |
307 | if (time_after(jiffies, timeout)) | |
308 | return -ETIMEDOUT; | |
309 | cpu_relax(); | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | EXPORT_SYMBOL_GPL(ipu_wait_interrupt); | |
315 | ||
fb822a39 SH |
316 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel) |
317 | { | |
318 | struct ipu_soc *ipu = channel->ipu; | |
319 | u32 val; | |
320 | unsigned long flags; | |
321 | ||
aecfbdb1 SH |
322 | spin_lock_irqsave(&ipu->lock, flags); |
323 | ||
324 | /* Disable DMA channel(s) */ | |
325 | val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); | |
326 | val &= ~idma_mask(channel->num); | |
327 | ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); | |
328 | ||
329 | /* Set channel buffers NOT to be ready */ | |
330 | ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ | |
331 | ||
332 | if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & | |
333 | idma_mask(channel->num)) { | |
334 | ipu_cm_write(ipu, idma_mask(channel->num), | |
335 | IPU_CHA_BUF0_RDY(channel->num)); | |
336 | } | |
337 | ||
338 | if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & | |
339 | idma_mask(channel->num)) { | |
340 | ipu_cm_write(ipu, idma_mask(channel->num), | |
341 | IPU_CHA_BUF1_RDY(channel->num)); | |
342 | } | |
343 | ||
344 | ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ | |
345 | ||
346 | /* Reset the double buffer */ | |
347 | val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); | |
348 | val &= ~idma_mask(channel->num); | |
349 | ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); | |
350 | ||
351 | spin_unlock_irqrestore(&ipu->lock, flags); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); | |
356 | ||
6c64155d | 357 | static int ipu_memory_reset(struct ipu_soc *ipu) |
aecfbdb1 SH |
358 | { |
359 | unsigned long timeout; | |
360 | ||
361 | ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); | |
362 | ||
363 | timeout = jiffies + msecs_to_jiffies(1000); | |
364 | while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { | |
365 | if (time_after(jiffies, timeout)) | |
366 | return -ETIME; | |
367 | cpu_relax(); | |
368 | } | |
369 | ||
aecfbdb1 SH |
370 | return 0; |
371 | } | |
372 | ||
ba07975f SL |
373 | /* |
374 | * Set the source mux for the given CSI. Selects either parallel or | |
375 | * MIPI CSI2 sources. | |
376 | */ | |
377 | void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) | |
378 | { | |
379 | unsigned long flags; | |
380 | u32 val, mask; | |
381 | ||
382 | mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : | |
383 | IPU_CONF_CSI0_DATA_SOURCE; | |
384 | ||
385 | spin_lock_irqsave(&ipu->lock, flags); | |
386 | ||
387 | val = ipu_cm_read(ipu, IPU_CONF); | |
388 | if (mipi_csi2) | |
389 | val |= mask; | |
390 | else | |
391 | val &= ~mask; | |
392 | ipu_cm_write(ipu, val, IPU_CONF); | |
393 | ||
394 | spin_unlock_irqrestore(&ipu->lock, flags); | |
395 | } | |
396 | EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); | |
397 | ||
398 | /* | |
399 | * Set the source mux for the IC. Selects either CSI[01] or the VDI. | |
400 | */ | |
401 | void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) | |
402 | { | |
403 | unsigned long flags; | |
404 | u32 val; | |
405 | ||
406 | spin_lock_irqsave(&ipu->lock, flags); | |
407 | ||
408 | val = ipu_cm_read(ipu, IPU_CONF); | |
409 | if (vdi) { | |
410 | val |= IPU_CONF_IC_INPUT; | |
411 | } else { | |
412 | val &= ~IPU_CONF_IC_INPUT; | |
413 | if (csi_id == 1) | |
414 | val |= IPU_CONF_CSI_SEL; | |
415 | else | |
416 | val &= ~IPU_CONF_CSI_SEL; | |
417 | } | |
418 | ipu_cm_write(ipu, val, IPU_CONF); | |
419 | ||
420 | spin_unlock_irqrestore(&ipu->lock, flags); | |
421 | } | |
422 | EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); | |
423 | ||
aecfbdb1 SH |
424 | struct ipu_devtype { |
425 | const char *name; | |
426 | unsigned long cm_ofs; | |
427 | unsigned long cpmem_ofs; | |
428 | unsigned long srm_ofs; | |
429 | unsigned long tpm_ofs; | |
2ffd48f2 SL |
430 | unsigned long csi0_ofs; |
431 | unsigned long csi1_ofs; | |
aecfbdb1 SH |
432 | unsigned long disp0_ofs; |
433 | unsigned long disp1_ofs; | |
434 | unsigned long dc_tmpl_ofs; | |
435 | unsigned long vdi_ofs; | |
436 | enum ipuv3_type type; | |
437 | }; | |
438 | ||
439 | static struct ipu_devtype ipu_type_imx51 = { | |
440 | .name = "IPUv3EX", | |
441 | .cm_ofs = 0x1e000000, | |
442 | .cpmem_ofs = 0x1f000000, | |
443 | .srm_ofs = 0x1f040000, | |
444 | .tpm_ofs = 0x1f060000, | |
2ffd48f2 SL |
445 | .csi0_ofs = 0x1f030000, |
446 | .csi1_ofs = 0x1f038000, | |
aecfbdb1 SH |
447 | .disp0_ofs = 0x1e040000, |
448 | .disp1_ofs = 0x1e048000, | |
449 | .dc_tmpl_ofs = 0x1f080000, | |
450 | .vdi_ofs = 0x1e068000, | |
451 | .type = IPUV3EX, | |
452 | }; | |
453 | ||
454 | static struct ipu_devtype ipu_type_imx53 = { | |
455 | .name = "IPUv3M", | |
456 | .cm_ofs = 0x06000000, | |
457 | .cpmem_ofs = 0x07000000, | |
458 | .srm_ofs = 0x07040000, | |
459 | .tpm_ofs = 0x07060000, | |
2ffd48f2 SL |
460 | .csi0_ofs = 0x07030000, |
461 | .csi1_ofs = 0x07038000, | |
aecfbdb1 SH |
462 | .disp0_ofs = 0x06040000, |
463 | .disp1_ofs = 0x06048000, | |
464 | .dc_tmpl_ofs = 0x07080000, | |
465 | .vdi_ofs = 0x06068000, | |
466 | .type = IPUV3M, | |
467 | }; | |
468 | ||
469 | static struct ipu_devtype ipu_type_imx6q = { | |
470 | .name = "IPUv3H", | |
471 | .cm_ofs = 0x00200000, | |
472 | .cpmem_ofs = 0x00300000, | |
473 | .srm_ofs = 0x00340000, | |
474 | .tpm_ofs = 0x00360000, | |
2ffd48f2 SL |
475 | .csi0_ofs = 0x00230000, |
476 | .csi1_ofs = 0x00238000, | |
aecfbdb1 SH |
477 | .disp0_ofs = 0x00240000, |
478 | .disp1_ofs = 0x00248000, | |
479 | .dc_tmpl_ofs = 0x00380000, | |
480 | .vdi_ofs = 0x00268000, | |
481 | .type = IPUV3H, | |
482 | }; | |
483 | ||
484 | static const struct of_device_id imx_ipu_dt_ids[] = { | |
485 | { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, | |
486 | { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, | |
487 | { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, | |
488 | { /* sentinel */ } | |
489 | }; | |
490 | MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); | |
491 | ||
492 | static int ipu_submodules_init(struct ipu_soc *ipu, | |
493 | struct platform_device *pdev, unsigned long ipu_base, | |
494 | struct clk *ipu_clk) | |
495 | { | |
496 | char *unit; | |
497 | int ret; | |
498 | struct device *dev = &pdev->dev; | |
499 | const struct ipu_devtype *devtype = ipu->devtype; | |
500 | ||
7d2691da SL |
501 | ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); |
502 | if (ret) { | |
503 | unit = "cpmem"; | |
504 | goto err_cpmem; | |
505 | } | |
506 | ||
2ffd48f2 SL |
507 | ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, |
508 | IPU_CONF_CSI0_EN, ipu_clk); | |
509 | if (ret) { | |
510 | unit = "csi0"; | |
511 | goto err_csi_0; | |
512 | } | |
513 | ||
514 | ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, | |
515 | IPU_CONF_CSI1_EN, ipu_clk); | |
516 | if (ret) { | |
517 | unit = "csi1"; | |
518 | goto err_csi_1; | |
519 | } | |
520 | ||
aecfbdb1 SH |
521 | ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, |
522 | IPU_CONF_DI0_EN, ipu_clk); | |
523 | if (ret) { | |
524 | unit = "di0"; | |
525 | goto err_di_0; | |
526 | } | |
527 | ||
528 | ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, | |
529 | IPU_CONF_DI1_EN, ipu_clk); | |
530 | if (ret) { | |
531 | unit = "di1"; | |
532 | goto err_di_1; | |
533 | } | |
534 | ||
535 | ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + | |
536 | IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); | |
537 | if (ret) { | |
538 | unit = "dc_template"; | |
539 | goto err_dc; | |
540 | } | |
541 | ||
542 | ret = ipu_dmfc_init(ipu, dev, ipu_base + | |
543 | devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); | |
544 | if (ret) { | |
545 | unit = "dmfc"; | |
546 | goto err_dmfc; | |
547 | } | |
548 | ||
549 | ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); | |
550 | if (ret) { | |
551 | unit = "dp"; | |
552 | goto err_dp; | |
553 | } | |
554 | ||
35de925f PZ |
555 | ret = ipu_smfc_init(ipu, dev, ipu_base + |
556 | devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); | |
557 | if (ret) { | |
558 | unit = "smfc"; | |
559 | goto err_smfc; | |
560 | } | |
561 | ||
aecfbdb1 SH |
562 | return 0; |
563 | ||
35de925f PZ |
564 | err_smfc: |
565 | ipu_dp_exit(ipu); | |
aecfbdb1 SH |
566 | err_dp: |
567 | ipu_dmfc_exit(ipu); | |
568 | err_dmfc: | |
569 | ipu_dc_exit(ipu); | |
570 | err_dc: | |
571 | ipu_di_exit(ipu, 1); | |
572 | err_di_1: | |
573 | ipu_di_exit(ipu, 0); | |
574 | err_di_0: | |
2ffd48f2 SL |
575 | ipu_csi_exit(ipu, 1); |
576 | err_csi_1: | |
577 | ipu_csi_exit(ipu, 0); | |
578 | err_csi_0: | |
7d2691da SL |
579 | ipu_cpmem_exit(ipu); |
580 | err_cpmem: | |
aecfbdb1 SH |
581 | dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); |
582 | return ret; | |
583 | } | |
584 | ||
585 | static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) | |
586 | { | |
587 | unsigned long status; | |
b728766c | 588 | int i, bit, irq; |
aecfbdb1 SH |
589 | |
590 | for (i = 0; i < num_regs; i++) { | |
591 | ||
592 | status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); | |
593 | status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); | |
594 | ||
b728766c | 595 | for_each_set_bit(bit, &status, 32) { |
838201aa ASC |
596 | irq = irq_linear_revmap(ipu->domain, |
597 | regs[i] * 32 + bit); | |
b728766c PZ |
598 | if (irq) |
599 | generic_handle_irq(irq); | |
600 | } | |
aecfbdb1 SH |
601 | } |
602 | } | |
603 | ||
604 | static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc) | |
605 | { | |
606 | struct ipu_soc *ipu = irq_desc_get_handler_data(desc); | |
607 | const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; | |
608 | struct irq_chip *chip = irq_get_chip(irq); | |
609 | ||
610 | chained_irq_enter(chip, desc); | |
611 | ||
612 | ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); | |
613 | ||
614 | chained_irq_exit(chip, desc); | |
615 | } | |
616 | ||
617 | static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc) | |
618 | { | |
619 | struct ipu_soc *ipu = irq_desc_get_handler_data(desc); | |
620 | const int int_reg[] = { 4, 5, 8, 9}; | |
621 | struct irq_chip *chip = irq_get_chip(irq); | |
622 | ||
623 | chained_irq_enter(chip, desc); | |
624 | ||
625 | ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); | |
626 | ||
627 | chained_irq_exit(chip, desc); | |
628 | } | |
629 | ||
861a50c1 | 630 | int ipu_map_irq(struct ipu_soc *ipu, int irq) |
aecfbdb1 | 631 | { |
861a50c1 | 632 | int virq; |
b728766c | 633 | |
861a50c1 PZ |
634 | virq = irq_linear_revmap(ipu->domain, irq); |
635 | if (!virq) | |
636 | virq = irq_create_mapping(ipu->domain, irq); | |
b728766c | 637 | |
861a50c1 PZ |
638 | return virq; |
639 | } | |
640 | EXPORT_SYMBOL_GPL(ipu_map_irq); | |
b728766c | 641 | |
861a50c1 PZ |
642 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, |
643 | enum ipu_channel_irq irq_type) | |
644 | { | |
645 | return ipu_map_irq(ipu, irq_type + channel->num); | |
aecfbdb1 SH |
646 | } |
647 | EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); | |
648 | ||
649 | static void ipu_submodules_exit(struct ipu_soc *ipu) | |
650 | { | |
35de925f | 651 | ipu_smfc_exit(ipu); |
aecfbdb1 SH |
652 | ipu_dp_exit(ipu); |
653 | ipu_dmfc_exit(ipu); | |
654 | ipu_dc_exit(ipu); | |
655 | ipu_di_exit(ipu, 1); | |
656 | ipu_di_exit(ipu, 0); | |
2ffd48f2 SL |
657 | ipu_csi_exit(ipu, 1); |
658 | ipu_csi_exit(ipu, 0); | |
7d2691da | 659 | ipu_cpmem_exit(ipu); |
aecfbdb1 SH |
660 | } |
661 | ||
662 | static int platform_remove_devices_fn(struct device *dev, void *unused) | |
663 | { | |
664 | struct platform_device *pdev = to_platform_device(dev); | |
665 | ||
666 | platform_device_unregister(pdev); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static void platform_device_unregister_children(struct platform_device *pdev) | |
672 | { | |
673 | device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); | |
674 | } | |
675 | ||
676 | struct ipu_platform_reg { | |
677 | struct ipu_client_platformdata pdata; | |
678 | const char *name; | |
d6ca8ca7 | 679 | int reg_offset; |
aecfbdb1 SH |
680 | }; |
681 | ||
682 | static const struct ipu_platform_reg client_reg[] = { | |
683 | { | |
684 | .pdata = { | |
685 | .di = 0, | |
686 | .dc = 5, | |
687 | .dp = IPU_DP_FLOW_SYNC_BG, | |
688 | .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, | |
b8d181e4 | 689 | .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, |
aecfbdb1 SH |
690 | }, |
691 | .name = "imx-ipuv3-crtc", | |
692 | }, { | |
693 | .pdata = { | |
694 | .di = 1, | |
695 | .dc = 1, | |
696 | .dp = -EINVAL, | |
697 | .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, | |
698 | .dma[1] = -EINVAL, | |
699 | }, | |
700 | .name = "imx-ipuv3-crtc", | |
d6ca8ca7 PZ |
701 | }, { |
702 | .pdata = { | |
703 | .csi = 0, | |
704 | .dma[0] = IPUV3_CHANNEL_CSI0, | |
705 | .dma[1] = -EINVAL, | |
706 | }, | |
707 | .reg_offset = IPU_CM_CSI0_REG_OFS, | |
708 | .name = "imx-ipuv3-camera", | |
709 | }, { | |
710 | .pdata = { | |
711 | .csi = 1, | |
712 | .dma[0] = IPUV3_CHANNEL_CSI1, | |
713 | .dma[1] = -EINVAL, | |
714 | }, | |
715 | .reg_offset = IPU_CM_CSI1_REG_OFS, | |
716 | .name = "imx-ipuv3-camera", | |
aecfbdb1 SH |
717 | }, |
718 | }; | |
719 | ||
4ae078d5 | 720 | static DEFINE_MUTEX(ipu_client_id_mutex); |
aecfbdb1 SH |
721 | static int ipu_client_id; |
722 | ||
d6ca8ca7 | 723 | static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) |
aecfbdb1 | 724 | { |
4ae078d5 RK |
725 | struct device *dev = ipu->dev; |
726 | unsigned i; | |
727 | int id, ret; | |
728 | ||
729 | mutex_lock(&ipu_client_id_mutex); | |
730 | id = ipu_client_id; | |
731 | ipu_client_id += ARRAY_SIZE(client_reg); | |
732 | mutex_unlock(&ipu_client_id_mutex); | |
aecfbdb1 SH |
733 | |
734 | for (i = 0; i < ARRAY_SIZE(client_reg); i++) { | |
735 | const struct ipu_platform_reg *reg = &client_reg[i]; | |
4ae078d5 | 736 | struct platform_device *pdev; |
d6ca8ca7 PZ |
737 | struct resource res; |
738 | ||
739 | if (reg->reg_offset) { | |
740 | memset(&res, 0, sizeof(res)); | |
741 | res.flags = IORESOURCE_MEM; | |
742 | res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset; | |
743 | res.end = res.start + PAGE_SIZE - 1; | |
744 | pdev = platform_device_register_resndata(dev, reg->name, | |
745 | id++, &res, 1, ®->pdata, sizeof(reg->pdata)); | |
746 | } else { | |
747 | pdev = platform_device_register_data(dev, reg->name, | |
748 | id++, ®->pdata, sizeof(reg->pdata)); | |
749 | } | |
4ae078d5 RK |
750 | |
751 | if (IS_ERR(pdev)) | |
aecfbdb1 SH |
752 | goto err_register; |
753 | } | |
754 | ||
755 | return 0; | |
756 | ||
757 | err_register: | |
4ae078d5 | 758 | platform_device_unregister_children(to_platform_device(dev)); |
aecfbdb1 SH |
759 | |
760 | return ret; | |
761 | } | |
762 | ||
aecfbdb1 | 763 | |
b728766c PZ |
764 | static int ipu_irq_init(struct ipu_soc *ipu) |
765 | { | |
379cdec3 PZ |
766 | struct irq_chip_generic *gc; |
767 | struct irq_chip_type *ct; | |
37f85b26 PZ |
768 | unsigned long unused[IPU_NUM_IRQS / 32] = { |
769 | 0x400100d0, 0xffe000fd, | |
770 | 0x400100d0, 0xffe000fd, | |
771 | 0x400100d0, 0xffe000fd, | |
772 | 0x4077ffff, 0xffe7e1fd, | |
773 | 0x23fffffe, 0x8880fff0, | |
774 | 0xf98fe7d0, 0xfff81fff, | |
775 | 0x400100d0, 0xffe000fd, | |
776 | 0x00000000, | |
777 | }; | |
379cdec3 PZ |
778 | int ret, i; |
779 | ||
b728766c | 780 | ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, |
379cdec3 | 781 | &irq_generic_chip_ops, ipu); |
b728766c PZ |
782 | if (!ipu->domain) { |
783 | dev_err(ipu->dev, "failed to add irq domain\n"); | |
784 | return -ENODEV; | |
aecfbdb1 SH |
785 | } |
786 | ||
379cdec3 | 787 | ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", |
838201aa ASC |
788 | handle_level_irq, 0, |
789 | IRQF_VALID, 0); | |
379cdec3 PZ |
790 | if (ret < 0) { |
791 | dev_err(ipu->dev, "failed to alloc generic irq chips\n"); | |
792 | irq_domain_remove(ipu->domain); | |
793 | return ret; | |
794 | } | |
795 | ||
796 | for (i = 0; i < IPU_NUM_IRQS; i += 32) { | |
797 | gc = irq_get_domain_generic_chip(ipu->domain, i); | |
798 | gc->reg_base = ipu->cm_reg; | |
37f85b26 | 799 | gc->unused = unused[i / 32]; |
379cdec3 PZ |
800 | ct = gc->chip_types; |
801 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
802 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
803 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
804 | ct->regs.ack = IPU_INT_STAT(i / 32); | |
805 | ct->regs.mask = IPU_INT_CTRL(i / 32); | |
806 | } | |
807 | ||
aecfbdb1 SH |
808 | irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler); |
809 | irq_set_handler_data(ipu->irq_sync, ipu); | |
810 | irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler); | |
811 | irq_set_handler_data(ipu->irq_err, ipu); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
816 | static void ipu_irq_exit(struct ipu_soc *ipu) | |
817 | { | |
b728766c | 818 | int i, irq; |
aecfbdb1 SH |
819 | |
820 | irq_set_chained_handler(ipu->irq_err, NULL); | |
821 | irq_set_handler_data(ipu->irq_err, NULL); | |
822 | irq_set_chained_handler(ipu->irq_sync, NULL); | |
823 | irq_set_handler_data(ipu->irq_sync, NULL); | |
824 | ||
379cdec3 PZ |
825 | /* TODO: remove irq_domain_generic_chips */ |
826 | ||
b728766c PZ |
827 | for (i = 0; i < IPU_NUM_IRQS; i++) { |
828 | irq = irq_linear_revmap(ipu->domain, i); | |
829 | if (irq) | |
830 | irq_dispose_mapping(irq); | |
aecfbdb1 SH |
831 | } |
832 | ||
b728766c | 833 | irq_domain_remove(ipu->domain); |
aecfbdb1 SH |
834 | } |
835 | ||
c4aabf8d | 836 | static int ipu_probe(struct platform_device *pdev) |
aecfbdb1 SH |
837 | { |
838 | const struct of_device_id *of_id = | |
839 | of_match_device(imx_ipu_dt_ids, &pdev->dev); | |
840 | struct ipu_soc *ipu; | |
841 | struct resource *res; | |
842 | unsigned long ipu_base; | |
843 | int i, ret, irq_sync, irq_err; | |
844 | const struct ipu_devtype *devtype; | |
845 | ||
846 | devtype = of_id->data; | |
847 | ||
aecfbdb1 SH |
848 | irq_sync = platform_get_irq(pdev, 0); |
849 | irq_err = platform_get_irq(pdev, 1); | |
850 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
851 | ||
fd563dbb | 852 | dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", |
aecfbdb1 SH |
853 | irq_sync, irq_err); |
854 | ||
855 | if (!res || irq_sync < 0 || irq_err < 0) | |
856 | return -ENODEV; | |
857 | ||
858 | ipu_base = res->start; | |
859 | ||
860 | ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); | |
861 | if (!ipu) | |
862 | return -ENODEV; | |
863 | ||
864 | for (i = 0; i < 64; i++) | |
865 | ipu->channel[i].ipu = ipu; | |
866 | ipu->devtype = devtype; | |
867 | ipu->ipu_type = devtype->type; | |
868 | ||
869 | spin_lock_init(&ipu->lock); | |
870 | mutex_init(&ipu->channel_lock); | |
871 | ||
fd563dbb | 872 | dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", |
aecfbdb1 | 873 | ipu_base + devtype->cm_ofs); |
fd563dbb | 874 | dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", |
aecfbdb1 | 875 | ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); |
fd563dbb | 876 | dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", |
aecfbdb1 | 877 | ipu_base + devtype->cpmem_ofs); |
2ffd48f2 SL |
878 | dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", |
879 | ipu_base + devtype->csi0_ofs); | |
880 | dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", | |
881 | ipu_base + devtype->csi1_ofs); | |
fd563dbb | 882 | dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", |
aecfbdb1 | 883 | ipu_base + devtype->disp0_ofs); |
fd563dbb | 884 | dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", |
aecfbdb1 | 885 | ipu_base + devtype->disp1_ofs); |
fd563dbb | 886 | dev_dbg(&pdev->dev, "srm: 0x%08lx\n", |
aecfbdb1 | 887 | ipu_base + devtype->srm_ofs); |
fd563dbb | 888 | dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", |
aecfbdb1 | 889 | ipu_base + devtype->tpm_ofs); |
fd563dbb | 890 | dev_dbg(&pdev->dev, "dc: 0x%08lx\n", |
aecfbdb1 | 891 | ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); |
fd563dbb | 892 | dev_dbg(&pdev->dev, "ic: 0x%08lx\n", |
aecfbdb1 | 893 | ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); |
fd563dbb | 894 | dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", |
aecfbdb1 | 895 | ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); |
fd563dbb | 896 | dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", |
aecfbdb1 SH |
897 | ipu_base + devtype->vdi_ofs); |
898 | ||
899 | ipu->cm_reg = devm_ioremap(&pdev->dev, | |
900 | ipu_base + devtype->cm_ofs, PAGE_SIZE); | |
901 | ipu->idmac_reg = devm_ioremap(&pdev->dev, | |
902 | ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, | |
903 | PAGE_SIZE); | |
aecfbdb1 | 904 | |
7d2691da | 905 | if (!ipu->cm_reg || !ipu->idmac_reg) |
be798b2b | 906 | return -ENOMEM; |
aecfbdb1 SH |
907 | |
908 | ipu->clk = devm_clk_get(&pdev->dev, "bus"); | |
909 | if (IS_ERR(ipu->clk)) { | |
910 | ret = PTR_ERR(ipu->clk); | |
911 | dev_err(&pdev->dev, "clk_get failed with %d", ret); | |
be798b2b | 912 | return ret; |
aecfbdb1 SH |
913 | } |
914 | ||
915 | platform_set_drvdata(pdev, ipu); | |
916 | ||
62645a27 FE |
917 | ret = clk_prepare_enable(ipu->clk); |
918 | if (ret) { | |
919 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); | |
920 | return ret; | |
921 | } | |
aecfbdb1 SH |
922 | |
923 | ipu->dev = &pdev->dev; | |
924 | ipu->irq_sync = irq_sync; | |
925 | ipu->irq_err = irq_err; | |
926 | ||
927 | ret = ipu_irq_init(ipu); | |
928 | if (ret) | |
929 | goto out_failed_irq; | |
930 | ||
6c64155d PZ |
931 | ret = device_reset(&pdev->dev); |
932 | if (ret) { | |
933 | dev_err(&pdev->dev, "failed to reset: %d\n", ret); | |
934 | goto out_failed_reset; | |
935 | } | |
936 | ret = ipu_memory_reset(ipu); | |
4d27b2ca LW |
937 | if (ret) |
938 | goto out_failed_reset; | |
aecfbdb1 SH |
939 | |
940 | /* Set MCU_T to divide MCU access window into 2 */ | |
941 | ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), | |
942 | IPU_DISP_GEN); | |
943 | ||
944 | ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); | |
945 | if (ret) | |
946 | goto failed_submodules_init; | |
947 | ||
d6ca8ca7 | 948 | ret = ipu_add_client_devices(ipu, ipu_base); |
aecfbdb1 SH |
949 | if (ret) { |
950 | dev_err(&pdev->dev, "adding client devices failed with %d\n", | |
951 | ret); | |
952 | goto failed_add_clients; | |
953 | } | |
954 | ||
9c2c438c FE |
955 | dev_info(&pdev->dev, "%s probed\n", devtype->name); |
956 | ||
aecfbdb1 SH |
957 | return 0; |
958 | ||
959 | failed_add_clients: | |
960 | ipu_submodules_exit(ipu); | |
961 | failed_submodules_init: | |
4d27b2ca | 962 | out_failed_reset: |
6c64155d | 963 | ipu_irq_exit(ipu); |
aecfbdb1 SH |
964 | out_failed_irq: |
965 | clk_disable_unprepare(ipu->clk); | |
aecfbdb1 SH |
966 | return ret; |
967 | } | |
968 | ||
8aa1be45 | 969 | static int ipu_remove(struct platform_device *pdev) |
aecfbdb1 SH |
970 | { |
971 | struct ipu_soc *ipu = platform_get_drvdata(pdev); | |
aecfbdb1 SH |
972 | |
973 | platform_device_unregister_children(pdev); | |
974 | ipu_submodules_exit(ipu); | |
975 | ipu_irq_exit(ipu); | |
976 | ||
977 | clk_disable_unprepare(ipu->clk); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | static struct platform_driver imx_ipu_driver = { | |
983 | .driver = { | |
984 | .name = "imx-ipuv3", | |
985 | .of_match_table = imx_ipu_dt_ids, | |
986 | }, | |
987 | .probe = ipu_probe, | |
99c28f10 | 988 | .remove = ipu_remove, |
aecfbdb1 SH |
989 | }; |
990 | ||
991 | module_platform_driver(imx_ipu_driver); | |
992 | ||
10f2268d | 993 | MODULE_ALIAS("platform:imx-ipuv3"); |
aecfbdb1 SH |
994 | MODULE_DESCRIPTION("i.MX IPU v3 driver"); |
995 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | |
996 | MODULE_LICENSE("GPL"); |