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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
aecfbdb1 SH |
2 | /* |
3 | * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> | |
4 | * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. | |
aecfbdb1 SH |
5 | */ |
6 | #include <linux/export.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/types.h> | |
9 | #include <linux/errno.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/platform_device.h> | |
aecfbdb1 | 13 | |
39b9004d | 14 | #include <video/imx-ipu-v3.h> |
aecfbdb1 SH |
15 | #include "ipu-prv.h" |
16 | ||
17 | struct ipu_di { | |
18 | void __iomem *base; | |
19 | int id; | |
20 | u32 module; | |
21 | struct clk *clk_di; /* display input clock */ | |
22 | struct clk *clk_ipu; /* IPU bus clock */ | |
23 | struct clk *clk_di_pixel; /* resulting pixel clock */ | |
aecfbdb1 | 24 | bool inuse; |
aecfbdb1 SH |
25 | struct ipu_soc *ipu; |
26 | }; | |
27 | ||
28 | static DEFINE_MUTEX(di_mutex); | |
29 | ||
30 | struct di_sync_config { | |
31 | int run_count; | |
32 | int run_src; | |
33 | int offset_count; | |
34 | int offset_src; | |
35 | int repeat_count; | |
36 | int cnt_clr_src; | |
37 | int cnt_polarity_gen_en; | |
38 | int cnt_polarity_clr_src; | |
39 | int cnt_polarity_trigger_src; | |
40 | int cnt_up; | |
41 | int cnt_down; | |
42 | }; | |
43 | ||
44 | enum di_pins { | |
45 | DI_PIN11 = 0, | |
46 | DI_PIN12 = 1, | |
47 | DI_PIN13 = 2, | |
48 | DI_PIN14 = 3, | |
49 | DI_PIN15 = 4, | |
50 | DI_PIN16 = 5, | |
51 | DI_PIN17 = 6, | |
52 | DI_PIN_CS = 7, | |
53 | ||
54 | DI_PIN_SER_CLK = 0, | |
55 | DI_PIN_SER_RS = 1, | |
56 | }; | |
57 | ||
58 | enum di_sync_wave { | |
59 | DI_SYNC_NONE = 0, | |
60 | DI_SYNC_CLK = 1, | |
61 | DI_SYNC_INT_HSYNC = 2, | |
62 | DI_SYNC_HSYNC = 3, | |
63 | DI_SYNC_VSYNC = 4, | |
64 | DI_SYNC_DE = 6, | |
aefa627f RK |
65 | |
66 | DI_SYNC_CNT1 = 2, /* counter >= 2 only */ | |
67 | DI_SYNC_CNT4 = 5, /* counter >= 5 only */ | |
68 | DI_SYNC_CNT5 = 6, /* counter >= 6 only */ | |
aecfbdb1 SH |
69 | }; |
70 | ||
71 | #define SYNC_WAVE 0 | |
72 | ||
73 | #define DI_GENERAL 0x0000 | |
74 | #define DI_BS_CLKGEN0 0x0004 | |
75 | #define DI_BS_CLKGEN1 0x0008 | |
76 | #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) | |
77 | #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) | |
78 | #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) | |
79 | #define DI_SYNC_AS_GEN 0x0054 | |
80 | #define DI_DW_GEN(gen) (0x0058 + 4 * (gen)) | |
81 | #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set))) | |
82 | #define DI_SER_CONF 0x015c | |
83 | #define DI_SSC 0x0160 | |
84 | #define DI_POL 0x0164 | |
85 | #define DI_AW0 0x0168 | |
86 | #define DI_AW1 0x016c | |
87 | #define DI_SCR_CONF 0x0170 | |
88 | #define DI_STAT 0x0174 | |
89 | ||
90 | #define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19) | |
91 | #define DI_SW_GEN0_RUN_SRC(x) ((x) << 16) | |
92 | #define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3) | |
93 | #define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0) | |
94 | ||
95 | #define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29) | |
96 | #define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25) | |
97 | #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12) | |
98 | #define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9) | |
99 | #define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16) | |
100 | #define DI_SW_GEN1_CNT_UP(x) (x) | |
101 | #define DI_SW_GEN1_AUTO_RELOAD (0x10000000) | |
102 | ||
103 | #define DI_DW_GEN_ACCESS_SIZE_OFFSET 24 | |
104 | #define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16 | |
105 | ||
106 | #define DI_GEN_POLARITY_1 (1 << 0) | |
107 | #define DI_GEN_POLARITY_2 (1 << 1) | |
108 | #define DI_GEN_POLARITY_3 (1 << 2) | |
109 | #define DI_GEN_POLARITY_4 (1 << 3) | |
110 | #define DI_GEN_POLARITY_5 (1 << 4) | |
111 | #define DI_GEN_POLARITY_6 (1 << 5) | |
112 | #define DI_GEN_POLARITY_7 (1 << 6) | |
113 | #define DI_GEN_POLARITY_8 (1 << 7) | |
114 | #define DI_GEN_POLARITY_DISP_CLK (1 << 17) | |
115 | #define DI_GEN_DI_CLK_EXT (1 << 20) | |
116 | #define DI_GEN_DI_VSYNC_EXT (1 << 21) | |
117 | ||
118 | #define DI_POL_DRDY_DATA_POLARITY (1 << 7) | |
119 | #define DI_POL_DRDY_POLARITY_15 (1 << 4) | |
120 | ||
121 | #define DI_VSYNC_SEL_OFFSET 13 | |
122 | ||
123 | static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset) | |
124 | { | |
125 | return readl(di->base + offset); | |
126 | } | |
127 | ||
128 | static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset) | |
129 | { | |
130 | writel(value, di->base + offset); | |
131 | } | |
132 | ||
aecfbdb1 SH |
133 | static void ipu_di_data_wave_config(struct ipu_di *di, |
134 | int wave_gen, | |
135 | int access_size, int component_size) | |
136 | { | |
137 | u32 reg; | |
138 | reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | | |
139 | (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); | |
140 | ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); | |
141 | } | |
142 | ||
143 | static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, | |
144 | int set, int up, int down) | |
145 | { | |
146 | u32 reg; | |
147 | ||
148 | reg = ipu_di_read(di, DI_DW_GEN(wave_gen)); | |
149 | reg &= ~(0x3 << (di_pin * 2)); | |
150 | reg |= set << (di_pin * 2); | |
151 | ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); | |
152 | ||
153 | ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); | |
154 | } | |
155 | ||
156 | static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config, | |
157 | int start, int count) | |
158 | { | |
159 | u32 reg; | |
160 | int i; | |
161 | ||
162 | for (i = 0; i < count; i++) { | |
163 | struct di_sync_config *c = &config[i]; | |
164 | int wave_gen = start + i + 1; | |
165 | ||
166 | if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || | |
167 | (c->repeat_count >= 0x1000) || | |
168 | (c->cnt_up >= 0x400) || | |
169 | (c->cnt_down >= 0x400)) { | |
170 | dev_err(di->ipu->dev, "DI%d counters out of range.\n", | |
171 | di->id); | |
172 | return; | |
173 | } | |
174 | ||
175 | reg = DI_SW_GEN0_RUN_COUNT(c->run_count) | | |
176 | DI_SW_GEN0_RUN_SRC(c->run_src) | | |
177 | DI_SW_GEN0_OFFSET_COUNT(c->offset_count) | | |
178 | DI_SW_GEN0_OFFSET_SRC(c->offset_src); | |
179 | ipu_di_write(di, reg, DI_SW_GEN0(wave_gen)); | |
180 | ||
181 | reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) | | |
182 | DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) | | |
183 | DI_SW_GEN1_CNT_POL_TRIGGER_SRC( | |
184 | c->cnt_polarity_trigger_src) | | |
185 | DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) | | |
186 | DI_SW_GEN1_CNT_DOWN(c->cnt_down) | | |
187 | DI_SW_GEN1_CNT_UP(c->cnt_up); | |
188 | ||
189 | /* Enable auto reload */ | |
190 | if (c->repeat_count == 0) | |
191 | reg |= DI_SW_GEN1_AUTO_RELOAD; | |
192 | ||
193 | ipu_di_write(di, reg, DI_SW_GEN1(wave_gen)); | |
194 | ||
195 | reg = ipu_di_read(di, DI_STP_REP(wave_gen)); | |
196 | reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1))); | |
197 | reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1)); | |
198 | ipu_di_write(di, reg, DI_STP_REP(wave_gen)); | |
199 | } | |
200 | } | |
201 | ||
202 | static void ipu_di_sync_config_interlaced(struct ipu_di *di, | |
203 | struct ipu_di_signal_cfg *sig) | |
204 | { | |
b6835a71 SL |
205 | u32 h_total = sig->mode.hactive + sig->mode.hsync_len + |
206 | sig->mode.hback_porch + sig->mode.hfront_porch; | |
207 | u32 v_total = sig->mode.vactive + sig->mode.vsync_len + | |
208 | sig->mode.vback_porch + sig->mode.vfront_porch; | |
aecfbdb1 SH |
209 | struct di_sync_config cfg[] = { |
210 | { | |
aefa627f RK |
211 | /* 1: internal VSYNC for each frame */ |
212 | .run_count = v_total * 2 - 1, | |
213 | .run_src = 3, /* == counter 7 */ | |
aecfbdb1 | 214 | }, { |
aefa627f RK |
215 | /* PIN2: HSYNC waveform */ |
216 | .run_count = h_total - 1, | |
aecfbdb1 | 217 | .run_src = DI_SYNC_CLK, |
aefa627f RK |
218 | .cnt_polarity_gen_en = 1, |
219 | .cnt_polarity_trigger_src = DI_SYNC_CLK, | |
220 | .cnt_down = sig->mode.hsync_len * 2, | |
aecfbdb1 | 221 | }, { |
aefa627f RK |
222 | /* PIN3: VSYNC waveform */ |
223 | .run_count = v_total - 1, | |
224 | .run_src = 4, /* == counter 7 */ | |
225 | .cnt_polarity_gen_en = 1, | |
226 | .cnt_polarity_trigger_src = 4, /* == counter 7 */ | |
227 | .cnt_down = sig->mode.vsync_len * 2, | |
228 | .cnt_clr_src = DI_SYNC_CNT1, | |
aecfbdb1 | 229 | }, { |
aefa627f RK |
230 | /* 4: Field */ |
231 | .run_count = v_total / 2, | |
aecfbdb1 | 232 | .run_src = DI_SYNC_HSYNC, |
aefa627f RK |
233 | .offset_count = h_total / 2, |
234 | .offset_src = DI_SYNC_CLK, | |
aecfbdb1 | 235 | .repeat_count = 2, |
aefa627f | 236 | .cnt_clr_src = DI_SYNC_CNT1, |
aecfbdb1 | 237 | }, { |
aefa627f | 238 | /* 5: Active lines */ |
aecfbdb1 | 239 | .run_src = DI_SYNC_HSYNC, |
aefa627f RK |
240 | .offset_count = (sig->mode.vsync_len + |
241 | sig->mode.vback_porch) / 2, | |
aecfbdb1 | 242 | .offset_src = DI_SYNC_HSYNC, |
aefa627f RK |
243 | .repeat_count = sig->mode.vactive / 2, |
244 | .cnt_clr_src = DI_SYNC_CNT4, | |
aecfbdb1 | 245 | }, { |
aefa627f | 246 | /* 6: Active pixel, referenced by DC */ |
aecfbdb1 | 247 | .run_src = DI_SYNC_CLK, |
aefa627f RK |
248 | .offset_count = sig->mode.hsync_len + |
249 | sig->mode.hback_porch, | |
aecfbdb1 | 250 | .offset_src = DI_SYNC_CLK, |
b6835a71 | 251 | .repeat_count = sig->mode.hactive, |
aefa627f | 252 | .cnt_clr_src = DI_SYNC_CNT5, |
aecfbdb1 | 253 | }, { |
aefa627f RK |
254 | /* 7: Half line HSYNC */ |
255 | .run_count = h_total / 2 - 1, | |
256 | .run_src = DI_SYNC_CLK, | |
aecfbdb1 SH |
257 | } |
258 | }; | |
259 | ||
260 | ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); | |
261 | ||
aecfbdb1 SH |
262 | ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); |
263 | } | |
264 | ||
265 | static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, | |
266 | struct ipu_di_signal_cfg *sig, int div) | |
267 | { | |
b6835a71 SL |
268 | u32 h_total = sig->mode.hactive + sig->mode.hsync_len + |
269 | sig->mode.hback_porch + sig->mode.hfront_porch; | |
270 | u32 v_total = sig->mode.vactive + sig->mode.vsync_len + | |
271 | sig->mode.vback_porch + sig->mode.vfront_porch; | |
aecfbdb1 SH |
272 | struct di_sync_config cfg[] = { |
273 | { | |
db5225d4 | 274 | /* 1: INT_HSYNC */ |
aecfbdb1 SH |
275 | .run_count = h_total - 1, |
276 | .run_src = DI_SYNC_CLK, | |
277 | } , { | |
db5225d4 | 278 | /* PIN2: HSYNC */ |
aecfbdb1 SH |
279 | .run_count = h_total - 1, |
280 | .run_src = DI_SYNC_CLK, | |
281 | .offset_count = div * sig->v_to_h_sync, | |
282 | .offset_src = DI_SYNC_CLK, | |
283 | .cnt_polarity_gen_en = 1, | |
284 | .cnt_polarity_trigger_src = DI_SYNC_CLK, | |
b6835a71 | 285 | .cnt_down = sig->mode.hsync_len * 2, |
aecfbdb1 | 286 | } , { |
db5225d4 | 287 | /* PIN3: VSYNC */ |
aecfbdb1 SH |
288 | .run_count = v_total - 1, |
289 | .run_src = DI_SYNC_INT_HSYNC, | |
290 | .cnt_polarity_gen_en = 1, | |
291 | .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, | |
b6835a71 | 292 | .cnt_down = sig->mode.vsync_len * 2, |
aecfbdb1 | 293 | } , { |
db5225d4 | 294 | /* 4: Line Active */ |
aecfbdb1 | 295 | .run_src = DI_SYNC_HSYNC, |
b6835a71 SL |
296 | .offset_count = sig->mode.vsync_len + |
297 | sig->mode.vback_porch, | |
aecfbdb1 | 298 | .offset_src = DI_SYNC_HSYNC, |
b6835a71 | 299 | .repeat_count = sig->mode.vactive, |
aecfbdb1 SH |
300 | .cnt_clr_src = DI_SYNC_VSYNC, |
301 | } , { | |
2ea42608 | 302 | /* 5: Pixel Active, referenced by DC */ |
aecfbdb1 | 303 | .run_src = DI_SYNC_CLK, |
b6835a71 SL |
304 | .offset_count = sig->mode.hsync_len + |
305 | sig->mode.hback_porch, | |
aecfbdb1 | 306 | .offset_src = DI_SYNC_CLK, |
b6835a71 | 307 | .repeat_count = sig->mode.hactive, |
db5225d4 PZ |
308 | .cnt_clr_src = 5, /* Line Active */ |
309 | } , { | |
310 | /* unused */ | |
aecfbdb1 SH |
311 | } , { |
312 | /* unused */ | |
2ea42608 PZ |
313 | }, |
314 | }; | |
315 | /* can't use #7 and #8 for line active and pixel active counters */ | |
316 | struct di_sync_config cfg_vga[] = { | |
317 | { | |
318 | /* 1: INT_HSYNC */ | |
319 | .run_count = h_total - 1, | |
320 | .run_src = DI_SYNC_CLK, | |
321 | } , { | |
322 | /* 2: VSYNC */ | |
323 | .run_count = v_total - 1, | |
324 | .run_src = DI_SYNC_INT_HSYNC, | |
325 | } , { | |
326 | /* 3: Line Active */ | |
327 | .run_src = DI_SYNC_INT_HSYNC, | |
b6835a71 SL |
328 | .offset_count = sig->mode.vsync_len + |
329 | sig->mode.vback_porch, | |
2ea42608 | 330 | .offset_src = DI_SYNC_INT_HSYNC, |
b6835a71 | 331 | .repeat_count = sig->mode.vactive, |
2ea42608 PZ |
332 | .cnt_clr_src = 3 /* VSYNC */, |
333 | } , { | |
334 | /* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */ | |
335 | .run_count = h_total - 1, | |
336 | .run_src = DI_SYNC_CLK, | |
337 | .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ | |
338 | .offset_src = DI_SYNC_CLK, | |
339 | .cnt_polarity_gen_en = 1, | |
340 | .cnt_polarity_trigger_src = DI_SYNC_CLK, | |
b6835a71 | 341 | .cnt_down = sig->mode.hsync_len * 2, |
2ea42608 PZ |
342 | } , { |
343 | /* 5: Pixel Active signal to DC */ | |
344 | .run_src = DI_SYNC_CLK, | |
b6835a71 SL |
345 | .offset_count = sig->mode.hsync_len + |
346 | sig->mode.hback_porch, | |
2ea42608 | 347 | .offset_src = DI_SYNC_CLK, |
b6835a71 | 348 | .repeat_count = sig->mode.hactive, |
2ea42608 PZ |
349 | .cnt_clr_src = 4, /* Line Active */ |
350 | } , { | |
351 | /* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */ | |
352 | .run_count = v_total - 1, | |
353 | .run_src = DI_SYNC_INT_HSYNC, | |
354 | .offset_count = 1, /* magic value from Freescale TVE driver */ | |
355 | .offset_src = DI_SYNC_INT_HSYNC, | |
356 | .cnt_polarity_gen_en = 1, | |
357 | .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, | |
b6835a71 | 358 | .cnt_down = sig->mode.vsync_len * 2, |
2ea42608 PZ |
359 | } , { |
360 | /* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ | |
361 | .run_count = h_total - 1, | |
362 | .run_src = DI_SYNC_CLK, | |
363 | .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ | |
364 | .offset_src = DI_SYNC_CLK, | |
365 | .cnt_polarity_gen_en = 1, | |
366 | .cnt_polarity_trigger_src = DI_SYNC_CLK, | |
b6835a71 | 367 | .cnt_down = sig->mode.hsync_len * 2, |
2ea42608 PZ |
368 | } , { |
369 | /* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ | |
370 | .run_count = v_total - 1, | |
371 | .run_src = DI_SYNC_INT_HSYNC, | |
372 | .offset_count = 1, /* magic value from Freescale TVE driver */ | |
373 | .offset_src = DI_SYNC_INT_HSYNC, | |
374 | .cnt_polarity_gen_en = 1, | |
375 | .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, | |
b6835a71 | 376 | .cnt_down = sig->mode.vsync_len * 2, |
aecfbdb1 SH |
377 | } , { |
378 | /* unused */ | |
379 | }, | |
380 | }; | |
381 | ||
382 | ipu_di_write(di, v_total - 1, DI_SCR_CONF); | |
2ea42608 PZ |
383 | if (sig->hsync_pin == 2 && sig->vsync_pin == 3) |
384 | ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); | |
385 | else | |
386 | ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga)); | |
aecfbdb1 SH |
387 | } |
388 | ||
0721feee RK |
389 | static void ipu_di_config_clock(struct ipu_di *di, |
390 | const struct ipu_di_signal_cfg *sig) | |
aecfbdb1 | 391 | { |
0721feee RK |
392 | struct clk *clk; |
393 | unsigned clkgen0; | |
394 | uint32_t val; | |
aecfbdb1 | 395 | |
0721feee RK |
396 | if (sig->clkflags & IPU_DI_CLKMODE_EXT) { |
397 | /* | |
398 | * CLKMODE_EXT means we must use the DI clock: this is | |
399 | * needed for things like LVDS which needs to feed the | |
400 | * DI and LDB with the same pixel clock. | |
401 | */ | |
402 | clk = di->clk_di; | |
403 | ||
404 | if (sig->clkflags & IPU_DI_CLKMODE_SYNC) { | |
405 | /* | |
406 | * CLKMODE_SYNC means that we want the DI to be | |
407 | * clocked at the same rate as the parent clock. | |
408 | * This is needed (eg) for LDB which needs to be | |
409 | * fed with the same pixel clock. We assume that | |
410 | * the LDB clock has already been set correctly. | |
411 | */ | |
412 | clkgen0 = 1 << 4; | |
413 | } else { | |
414 | /* | |
415 | * We can use the divider. We should really have | |
416 | * a flag here indicating whether the bridge can | |
417 | * cope with a fractional divider or not. For the | |
418 | * time being, let's go for simplicitly and | |
419 | * reliability. | |
420 | */ | |
421 | unsigned long in_rate; | |
422 | unsigned div; | |
aecfbdb1 | 423 | |
b6835a71 | 424 | clk_set_rate(clk, sig->mode.pixelclock); |
aecfbdb1 | 425 | |
0721feee | 426 | in_rate = clk_get_rate(clk); |
503f1631 | 427 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
f7089d92 | 428 | div = clamp(div, 1U, 255U); |
24013ea8 | 429 | |
0721feee RK |
430 | clkgen0 = div << 4; |
431 | } | |
370b1815 | 432 | } else { |
0721feee RK |
433 | /* |
434 | * For other interfaces, we can arbitarily select between | |
435 | * the DI specific clock and the internal IPU clock. See | |
436 | * DI_GENERAL bit 20. We select the IPU clock if it can | |
437 | * give us a clock rate within 1% of the requested frequency, | |
438 | * otherwise we use the DI clock. | |
439 | */ | |
24013ea8 RK |
440 | unsigned long rate, clkrate; |
441 | unsigned div, error; | |
442 | ||
443 | clkrate = clk_get_rate(di->clk_ipu); | |
503f1631 | 444 | div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); |
f7089d92 | 445 | div = clamp(div, 1U, 255U); |
24013ea8 RK |
446 | rate = clkrate / div; |
447 | ||
b6835a71 | 448 | error = rate / (sig->mode.pixelclock / 1000); |
24013ea8 | 449 | |
7d005f57 LR |
450 | dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %c%d.%d%%\n", |
451 | rate, div, error < 1000 ? '-' : '+', | |
452 | abs(error - 1000) / 10, abs(error - 1000) % 10); | |
24013ea8 RK |
453 | |
454 | /* Allow a 1% error */ | |
455 | if (error < 1010 && error >= 990) { | |
0721feee RK |
456 | clk = di->clk_ipu; |
457 | ||
458 | clkgen0 = div << 4; | |
24013ea8 | 459 | } else { |
0721feee RK |
460 | unsigned long in_rate; |
461 | unsigned div; | |
462 | ||
463 | clk = di->clk_di; | |
24013ea8 | 464 | |
b6835a71 | 465 | clk_set_rate(clk, sig->mode.pixelclock); |
370b1815 | 466 | |
0721feee | 467 | in_rate = clk_get_rate(clk); |
503f1631 | 468 | div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
f7089d92 | 469 | div = clamp(div, 1U, 255U); |
0721feee RK |
470 | |
471 | clkgen0 = div << 4; | |
24013ea8 RK |
472 | } |
473 | } | |
aecfbdb1 | 474 | |
0721feee RK |
475 | di->clk_di_pixel = clk; |
476 | ||
477 | /* Set the divider */ | |
478 | ipu_di_write(di, clkgen0, DI_BS_CLKGEN0); | |
aecfbdb1 | 479 | |
24013ea8 | 480 | /* |
0721feee RK |
481 | * Set the high/low periods. Bits 24:16 give us the falling edge, |
482 | * and bits 8:0 give the rising edge. LSB is fraction, and is | |
483 | * based on the divider above. We want a 50% duty cycle, so set | |
484 | * the falling edge to be half the divider. | |
24013ea8 | 485 | */ |
0721feee | 486 | ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1); |
aecfbdb1 | 487 | |
0721feee RK |
488 | /* Finally select the input clock */ |
489 | val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT; | |
490 | if (clk == di->clk_di) | |
491 | val |= DI_GEN_DI_CLK_EXT; | |
492 | ipu_di_write(di, val, DI_GENERAL); | |
aecfbdb1 | 493 | |
0721feee | 494 | dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n", |
b6835a71 | 495 | sig->mode.pixelclock, |
24013ea8 RK |
496 | clk_get_rate(di->clk_ipu), |
497 | clk_get_rate(di->clk_di), | |
0721feee RK |
498 | clk == di->clk_di ? "DI" : "IPU", |
499 | clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4)); | |
500 | } | |
501 | ||
6541d710 JW |
502 | /* |
503 | * This function is called to adjust a video mode to IPU restrictions. | |
504 | * It is meant to be called from drm crtc mode_fixup() methods. | |
505 | */ | |
506 | int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode) | |
507 | { | |
508 | u32 diff; | |
509 | ||
94dfec48 SR |
510 | if (!IS_ALIGNED(mode->hactive, 8) && |
511 | mode->hfront_porch < ALIGN(mode->hactive, 8) - mode->hactive) { | |
512 | dev_err(di->ipu->dev, "hactive %d is not aligned to 8 and front porch is too small to compensate\n", | |
513 | mode->hactive); | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
6541d710 JW |
517 | if (mode->vfront_porch >= 2) |
518 | return 0; | |
519 | ||
520 | diff = 2 - mode->vfront_porch; | |
521 | ||
522 | if (mode->vback_porch >= diff) { | |
523 | mode->vfront_porch = 2; | |
524 | mode->vback_porch -= diff; | |
525 | } else if (mode->vsync_len > diff) { | |
526 | mode->vfront_porch = 2; | |
527 | mode->vsync_len = mode->vsync_len - diff; | |
528 | } else { | |
529 | dev_warn(di->ipu->dev, "failed to adjust videomode\n"); | |
530 | return -EINVAL; | |
531 | } | |
532 | ||
b5b457b3 | 533 | dev_dbg(di->ipu->dev, "videomode adapted for IPU restrictions\n"); |
6541d710 JW |
534 | return 0; |
535 | } | |
536 | EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode); | |
537 | ||
f94ab604 RK |
538 | static u32 ipu_di_gen_polarity(int pin) |
539 | { | |
540 | switch (pin) { | |
541 | case 1: | |
542 | return DI_GEN_POLARITY_1; | |
543 | case 2: | |
544 | return DI_GEN_POLARITY_2; | |
545 | case 3: | |
546 | return DI_GEN_POLARITY_3; | |
547 | case 4: | |
548 | return DI_GEN_POLARITY_4; | |
549 | case 5: | |
550 | return DI_GEN_POLARITY_5; | |
551 | case 6: | |
552 | return DI_GEN_POLARITY_6; | |
553 | case 7: | |
554 | return DI_GEN_POLARITY_7; | |
555 | case 8: | |
556 | return DI_GEN_POLARITY_8; | |
557 | } | |
558 | return 0; | |
559 | } | |
560 | ||
0721feee RK |
561 | int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) |
562 | { | |
563 | u32 reg; | |
564 | u32 di_gen, vsync_cnt; | |
565 | u32 div; | |
0721feee RK |
566 | |
567 | dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n", | |
b6835a71 | 568 | di->id, sig->mode.hactive, sig->mode.vactive); |
0721feee | 569 | |
0721feee RK |
570 | dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n", |
571 | clk_get_rate(di->clk_ipu), | |
572 | clk_get_rate(di->clk_di), | |
b6835a71 | 573 | sig->mode.pixelclock); |
0721feee | 574 | |
aecfbdb1 SH |
575 | mutex_lock(&di_mutex); |
576 | ||
0721feee RK |
577 | ipu_di_config_clock(di, sig); |
578 | ||
aecfbdb1 SH |
579 | div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff; |
580 | div = div / 16; /* Now divider is integer portion */ | |
581 | ||
582 | /* Setup pixel clock timing */ | |
583 | /* Down time is half of period */ | |
584 | ipu_di_write(di, (div << 16), DI_BS_CLKGEN1); | |
585 | ||
586 | ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1); | |
587 | ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); | |
588 | ||
589 | di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT; | |
590 | di_gen |= DI_GEN_DI_VSYNC_EXT; | |
591 | ||
b6835a71 | 592 | if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) { |
aecfbdb1 SH |
593 | ipu_di_sync_config_interlaced(di, sig); |
594 | ||
595 | /* set y_sel = 1 */ | |
596 | di_gen |= 0x10000000; | |
aecfbdb1 | 597 | |
aefa627f | 598 | vsync_cnt = 3; |
aecfbdb1 SH |
599 | } else { |
600 | ipu_di_sync_config_noninterlaced(di, sig, div); | |
601 | ||
602 | vsync_cnt = 3; | |
2ea42608 | 603 | if (di->id == 1) |
722ae534 MN |
604 | /* |
605 | * TODO: change only for TVEv2, parallel display | |
606 | * uses pin 2 / 3 | |
607 | */ | |
608 | if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3)) | |
609 | vsync_cnt = 6; | |
aecfbdb1 SH |
610 | } |
611 | ||
f94ab604 RK |
612 | if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) |
613 | di_gen |= ipu_di_gen_polarity(sig->hsync_pin); | |
614 | if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) | |
615 | di_gen |= ipu_di_gen_polarity(sig->vsync_pin); | |
616 | ||
85de9d17 | 617 | if (sig->clk_pol) |
aecfbdb1 SH |
618 | di_gen |= DI_GEN_POLARITY_DISP_CLK; |
619 | ||
620 | ipu_di_write(di, di_gen, DI_GENERAL); | |
621 | ||
622 | ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002, | |
623 | DI_SYNC_AS_GEN); | |
624 | ||
625 | reg = ipu_di_read(di, DI_POL); | |
626 | reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); | |
627 | ||
628 | if (sig->enable_pol) | |
629 | reg |= DI_POL_DRDY_POLARITY_15; | |
630 | if (sig->data_pol) | |
631 | reg |= DI_POL_DRDY_DATA_POLARITY; | |
632 | ||
633 | ipu_di_write(di, reg, DI_POL); | |
634 | ||
635 | mutex_unlock(&di_mutex); | |
636 | ||
637 | return 0; | |
638 | } | |
639 | EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel); | |
640 | ||
641 | int ipu_di_enable(struct ipu_di *di) | |
642 | { | |
0721feee RK |
643 | int ret; |
644 | ||
645 | WARN_ON(IS_ERR(di->clk_di_pixel)); | |
646 | ||
647 | ret = clk_prepare_enable(di->clk_di_pixel); | |
85d0b780 FE |
648 | if (ret) |
649 | return ret; | |
aecfbdb1 SH |
650 | |
651 | ipu_module_enable(di->ipu, di->module); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | EXPORT_SYMBOL_GPL(ipu_di_enable); | |
656 | ||
657 | int ipu_di_disable(struct ipu_di *di) | |
658 | { | |
0721feee RK |
659 | WARN_ON(IS_ERR(di->clk_di_pixel)); |
660 | ||
aecfbdb1 SH |
661 | ipu_module_disable(di->ipu, di->module); |
662 | ||
663 | clk_disable_unprepare(di->clk_di_pixel); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | EXPORT_SYMBOL_GPL(ipu_di_disable); | |
668 | ||
669 | int ipu_di_get_num(struct ipu_di *di) | |
670 | { | |
671 | return di->id; | |
672 | } | |
673 | EXPORT_SYMBOL_GPL(ipu_di_get_num); | |
674 | ||
675 | static DEFINE_MUTEX(ipu_di_lock); | |
676 | ||
677 | struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) | |
678 | { | |
679 | struct ipu_di *di; | |
680 | ||
681 | if (disp > 1) | |
682 | return ERR_PTR(-EINVAL); | |
683 | ||
684 | di = ipu->di_priv[disp]; | |
685 | ||
686 | mutex_lock(&ipu_di_lock); | |
687 | ||
688 | if (di->inuse) { | |
689 | di = ERR_PTR(-EBUSY); | |
690 | goto out; | |
691 | } | |
692 | ||
693 | di->inuse = true; | |
694 | out: | |
695 | mutex_unlock(&ipu_di_lock); | |
696 | ||
697 | return di; | |
698 | } | |
699 | EXPORT_SYMBOL_GPL(ipu_di_get); | |
700 | ||
701 | void ipu_di_put(struct ipu_di *di) | |
702 | { | |
703 | mutex_lock(&ipu_di_lock); | |
704 | ||
705 | di->inuse = false; | |
706 | ||
707 | mutex_unlock(&ipu_di_lock); | |
708 | } | |
709 | EXPORT_SYMBOL_GPL(ipu_di_put); | |
710 | ||
711 | int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, | |
712 | unsigned long base, | |
713 | u32 module, struct clk *clk_ipu) | |
714 | { | |
715 | struct ipu_di *di; | |
aecfbdb1 SH |
716 | |
717 | if (id > 1) | |
718 | return -ENODEV; | |
719 | ||
720 | di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL); | |
721 | if (!di) | |
722 | return -ENOMEM; | |
723 | ||
724 | ipu->di_priv[id] = di; | |
725 | ||
726 | di->clk_di = devm_clk_get(dev, id ? "di1" : "di0"); | |
727 | if (IS_ERR(di->clk_di)) | |
728 | return PTR_ERR(di->clk_di); | |
729 | ||
730 | di->module = module; | |
731 | di->id = id; | |
732 | di->clk_ipu = clk_ipu; | |
733 | di->base = devm_ioremap(dev, base, PAGE_SIZE); | |
734 | if (!di->base) | |
735 | return -ENOMEM; | |
736 | ||
aecfbdb1 SH |
737 | ipu_di_write(di, 0x10, DI_BS_CLKGEN0); |
738 | ||
ed73591a | 739 | dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n", |
aecfbdb1 SH |
740 | id, base, di->base); |
741 | di->inuse = false; | |
742 | di->ipu = ipu; | |
743 | ||
744 | return 0; | |
aecfbdb1 SH |
745 | } |
746 | ||
747 | void ipu_di_exit(struct ipu_soc *ipu, int id) | |
748 | { | |
aecfbdb1 | 749 | } |