[mirror_ubuntu-artful-kernel.git] / drivers / gpu / ipu-v3 / ipu-pre.c

/*
 * Copyright (c) 2017 Lucas Stach, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <drm/drm_fourcc.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/genalloc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <video/imx-ipu-v3.h>

#include "ipu-prv.h"

#define IPU_PRE_MAX_WIDTH	2048
#define IPU_PRE_NUM_SCANLINES	8

#define IPU_PRE_CTRL					0x000
#define IPU_PRE_CTRL_SET				0x004
#define  IPU_PRE_CTRL_ENABLE				(1 << 0)
#define  IPU_PRE_CTRL_BLOCK_EN				(1 << 1)
#define  IPU_PRE_CTRL_BLOCK_16				(1 << 2)
#define  IPU_PRE_CTRL_SDW_UPDATE			(1 << 4)
#define  IPU_PRE_CTRL_VFLIP				(1 << 5)
#define  IPU_PRE_CTRL_SO				(1 << 6)
#define  IPU_PRE_CTRL_INTERLACED_FIELD			(1 << 7)
#define  IPU_PRE_CTRL_HANDSHAKE_EN			(1 << 8)
#define  IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v)		((v & 0x3) << 9)
#define  IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN		(1 << 11)
#define  IPU_PRE_CTRL_EN_REPEAT				(1 << 28)
#define  IPU_PRE_CTRL_TPR_REST_SEL			(1 << 29)
#define  IPU_PRE_CTRL_CLKGATE				(1 << 30)
#define  IPU_PRE_CTRL_SFTRST				(1 << 31)

#define IPU_PRE_CUR_BUF					0x030

#define IPU_PRE_NEXT_BUF				0x040

#define IPU_PRE_TPR_CTRL				0x070
#define  IPU_PRE_TPR_CTRL_TILE_FORMAT(v)		((v & 0xff) << 0)
#define  IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK		0xff

#define IPU_PRE_PREFETCH_ENG_CTRL			0x080
#define  IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN		(1 << 0)
#define  IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v)		((v & 0x7) << 1)
#define  IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v)	((v & 0x3) << 4)
#define  IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v)	((v & 0x7) << 8)
#define  IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS		(1 << 11)
#define  IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE		(1 << 12)
#define  IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP		(1 << 14)
#define  IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN	(1 << 15)

#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE			0x0a0
#define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v)	((v & 0xffff) << 0)
#define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v)	((v & 0xffff) << 16)

#define IPU_PRE_PREFETCH_ENG_PITCH			0x0d0
#define  IPU_PRE_PREFETCH_ENG_PITCH_Y(v)		((v & 0xffff) << 0)
#define  IPU_PRE_PREFETCH_ENG_PITCH_UV(v)		((v & 0xffff) << 16)

#define IPU_PRE_STORE_ENG_CTRL				0x110
#define  IPU_PRE_STORE_ENG_CTRL_STORE_EN		(1 << 0)
#define  IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v)		((v & 0x7) << 1)
#define  IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v)	((v & 0x3) << 4)

#define IPU_PRE_STORE_ENG_SIZE				0x130
#define  IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v)		((v & 0xffff) << 0)
#define  IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v)		((v & 0xffff) << 16)

#define IPU_PRE_STORE_ENG_PITCH				0x140
#define  IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v)		((v & 0xffff) << 0)

#define IPU_PRE_STORE_ENG_ADDR				0x150

struct ipu_pre {
	struct list_head	list;
	struct device		*dev;

	void __iomem		*regs;
	struct clk		*clk_axi;
	struct gen_pool		*iram;

	dma_addr_t		buffer_paddr;
	void			*buffer_virt;
	bool			in_use;
};

static DEFINE_MUTEX(ipu_pre_list_mutex);
static LIST_HEAD(ipu_pre_list);
static int available_pres;

int ipu_pre_get_available_count(void)
{
	return available_pres;
}

struct ipu_pre *
ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
{
	struct device_node *pre_node = of_parse_phandle(dev->of_node,
							name, index);
	struct ipu_pre *pre;

	mutex_lock(&ipu_pre_list_mutex);
	list_for_each_entry(pre, &ipu_pre_list, list) {
		if (pre_node == pre->dev->of_node) {
			mutex_unlock(&ipu_pre_list_mutex);
			device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
			return pre;
		}
	}
	mutex_unlock(&ipu_pre_list_mutex);

	return NULL;
}

int ipu_pre_get(struct ipu_pre *pre)
{
	u32 val;

	if (pre->in_use)
		return -EBUSY;

	/* first get the engine out of reset and remove clock gating */
	writel(0, pre->regs + IPU_PRE_CTRL);

	/* init defaults that should be applied to all streams */
	val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
	      IPU_PRE_CTRL_HANDSHAKE_EN |
	      IPU_PRE_CTRL_TPR_REST_SEL |
	      IPU_PRE_CTRL_BLOCK_16 | IPU_PRE_CTRL_SDW_UPDATE;
	writel(val, pre->regs + IPU_PRE_CTRL);

	pre->in_use = true;
	return 0;
}

void ipu_pre_put(struct ipu_pre *pre)
{
	writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);

	pre->in_use = false;
}

void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
		       unsigned int height, unsigned int stride, u32 format,
		       unsigned int bufaddr)
{
	const struct drm_format_info *info = drm_format_info(format);
	u32 active_bpp = info->cpp[0] >> 1;
	u32 val;

	writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);

	val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
	      IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
	      IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
	      IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
	      IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);

	val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
	      IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);

	val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);

	val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
	      IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
	      IPU_PRE_STORE_ENG_CTRL_STORE_EN;
	writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);

	val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
	      IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
	writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);

	val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
	writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);

	writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);

	val = readl(pre->regs + IPU_PRE_CTRL);
	val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
	       IPU_PRE_CTRL_SDW_UPDATE;
	writel(val, pre->regs + IPU_PRE_CTRL);
}

void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
{
	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
	writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
}

u32 ipu_pre_get_baddr(struct ipu_pre *pre)
{
	return (u32)pre->buffer_paddr;
}

static int ipu_pre_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct ipu_pre *pre;

	pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
	if (!pre)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pre->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pre->regs))
		return PTR_ERR(pre->regs);

	pre->clk_axi = devm_clk_get(dev, "axi");
	if (IS_ERR(pre->clk_axi))
		return PTR_ERR(pre->clk_axi);

	pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
	if (!pre->iram)
		return -EPROBE_DEFER;

	/*
	 * Allocate IRAM buffer with maximum size. This could be made dynamic,
	 * but as there is no other user of this IRAM region and we can fit all
	 * max sized buffers into it, there is no need yet.
	 */
	pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
					      IPU_PRE_NUM_SCANLINES * 4,
					      &pre->buffer_paddr);
	if (!pre->buffer_virt)
		return -ENOMEM;

	clk_prepare_enable(pre->clk_axi);

	pre->dev = dev;
	platform_set_drvdata(pdev, pre);
	mutex_lock(&ipu_pre_list_mutex);
	list_add(&pre->list, &ipu_pre_list);
	available_pres++;
	mutex_unlock(&ipu_pre_list_mutex);

	return 0;
}

static int ipu_pre_remove(struct platform_device *pdev)
{
	struct ipu_pre *pre = platform_get_drvdata(pdev);

	mutex_lock(&ipu_pre_list_mutex);
	list_del(&pre->list);
	available_pres--;
	mutex_unlock(&ipu_pre_list_mutex);

	clk_disable_unprepare(pre->clk_axi);

	if (pre->buffer_virt)
		gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
			      IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
	return 0;
}

static const struct of_device_id ipu_pre_dt_ids[] = {
	{ .compatible = "fsl,imx6qp-pre", },
	{ /* sentinel */ },
};

struct platform_driver ipu_pre_drv = {
	.probe		= ipu_pre_probe,
	.remove		= ipu_pre_remove,
	.driver		= {
		.name	= "imx-ipu-pre",
		.of_match_table = ipu_pre_dt_ids,
	},
};
Commit	Line	Data
d2a34232 LS	1	/*
	2	* Copyright (c) 2017 Lucas Stach, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#include <drm/drm_fourcc.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/genalloc.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/platform_device.h>
	21	#include <video/imx-ipu-v3.h>
	22
	23	#include "ipu-prv.h"
	24
	25	#define IPU_PRE_MAX_WIDTH 2048
	26	#define IPU_PRE_NUM_SCANLINES 8
	27
	28	#define IPU_PRE_CTRL 0x000
	29	#define IPU_PRE_CTRL_SET 0x004
	30	#define IPU_PRE_CTRL_ENABLE (1 << 0)
	31	#define IPU_PRE_CTRL_BLOCK_EN (1 << 1)
	32	#define IPU_PRE_CTRL_BLOCK_16 (1 << 2)
	33	#define IPU_PRE_CTRL_SDW_UPDATE (1 << 4)
	34	#define IPU_PRE_CTRL_VFLIP (1 << 5)
	35	#define IPU_PRE_CTRL_SO (1 << 6)
	36	#define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7)
	37	#define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8)
	38	#define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
	39	#define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11)
	40	#define IPU_PRE_CTRL_EN_REPEAT (1 << 28)
	41	#define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29)
	42	#define IPU_PRE_CTRL_CLKGATE (1 << 30)
	43	#define IPU_PRE_CTRL_SFTRST (1 << 31)
	44
	45	#define IPU_PRE_CUR_BUF 0x030
	46
	47	#define IPU_PRE_NEXT_BUF 0x040
	48
	49	#define IPU_PRE_TPR_CTRL 0x070
	50	#define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
	51	#define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff
	52
	53	#define IPU_PRE_PREFETCH_ENG_CTRL 0x080
	54	#define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0)
	55	#define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
	56	#define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
	57	#define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
	58	#define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11)
	59	#define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12)
	60	#define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14)
	61	#define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15)
	62
	63	#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0
	64	#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
65	#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
66
67	#define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0
68	#define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
69	#define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
70
71	#define IPU_PRE_STORE_ENG_CTRL 0x110
72	#define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0)
73	#define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
74	#define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
75
76	#define IPU_PRE_STORE_ENG_SIZE 0x130
77	#define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
78	#define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
79
80	#define IPU_PRE_STORE_ENG_PITCH 0x140
81	#define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
82
83	#define IPU_PRE_STORE_ENG_ADDR 0x150
84
85	struct ipu_pre {
86	struct list_head list;
87	struct device *dev;
88
89	void __iomem *regs;
90	struct clk *clk_axi;
91	struct gen_pool *iram;
92
93	dma_addr_t buffer_paddr;
94	void *buffer_virt;
95	bool in_use;
96	};
97
98	static DEFINE_MUTEX(ipu_pre_list_mutex);
99	static LIST_HEAD(ipu_pre_list);
100	static int available_pres;
101
102	int ipu_pre_get_available_count(void)
103	{
104	return available_pres;
105	}
106
107	struct ipu_pre *
108	ipu_pre_lookup_by_phandle(struct device dev, const char name, int index)
109	{
110	struct device_node *pre_node = of_parse_phandle(dev->of_node,
111	name, index);
112	struct ipu_pre *pre;
113
114	mutex_lock(&ipu_pre_list_mutex);
115	list_for_each_entry(pre, &ipu_pre_list, list) {
116	if (pre_node == pre->dev->of_node) {
117	mutex_unlock(&ipu_pre_list_mutex);
118	device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
119	return pre;
120	}
121	}
122	mutex_unlock(&ipu_pre_list_mutex);
123
124	return NULL;
125	}
126
127	int ipu_pre_get(struct ipu_pre *pre)
128	{
129	u32 val;
130
131	if (pre->in_use)
132	return -EBUSY;
133
d2a34232 LS	134	/* first get the engine out of reset and remove clock gating */
	135	writel(0, pre->regs + IPU_PRE_CTRL);
	136
	137	/* init defaults that should be applied to all streams */
	138	val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN \|
	139	IPU_PRE_CTRL_HANDSHAKE_EN \|
	140	IPU_PRE_CTRL_TPR_REST_SEL \|
	141	IPU_PRE_CTRL_BLOCK_16 \| IPU_PRE_CTRL_SDW_UPDATE;
	142	writel(val, pre->regs + IPU_PRE_CTRL);
	143
	144	pre->in_use = true;
	145	return 0;
	146	}
	147
	148	void ipu_pre_put(struct ipu_pre *pre)
	149	{
47c298f7	150	writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
d2a34232 LS	151
	152	pre->in_use = false;
	153	}
	154
	155	void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
	156	unsigned int height, unsigned int stride, u32 format,
	157	unsigned int bufaddr)
	158	{
	159	const struct drm_format_info *info = drm_format_info(format);
	160	u32 active_bpp = info->cpp[0] >> 1;
	161	u32 val;
	162
	163	writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
	164	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
	165
	166	val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) \|
	167	IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) \|
	168	IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) \|
	169	IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS \|
	170	IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
	171	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
	172
	173	val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) \|
	174	IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
	175	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
	176
	177	val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
	178	writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
	179
	180	val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) \|
	181	IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) \|
	182	IPU_PRE_STORE_ENG_CTRL_STORE_EN;
	183	writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
	184
	185	val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) \|
	186	IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
	187	writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
	188
	189	val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
	190	writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
	191
	192	writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
	193
	194	val = readl(pre->regs + IPU_PRE_CTRL);
	195	val \|= IPU_PRE_CTRL_EN_REPEAT \| IPU_PRE_CTRL_ENABLE \|
	196	IPU_PRE_CTRL_SDW_UPDATE;
	197	writel(val, pre->regs + IPU_PRE_CTRL);
	198	}
	199
	200	void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
	201	{
	202	writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
	203	writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
	204	}
	205
	206	u32 ipu_pre_get_baddr(struct ipu_pre *pre)
	207	{
	208	return (u32)pre->buffer_paddr;
	209	}
	210
	211	static int ipu_pre_probe(struct platform_device *pdev)
	212	{
	213	struct device *dev = &pdev->dev;
	214	struct resource *res;
215	struct ipu_pre *pre;
216
217	pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
218	if (!pre)
219	return -ENOMEM;
220
221	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
222	pre->regs = devm_ioremap_resource(&pdev->dev, res);
223	if (IS_ERR(pre->regs))
224	return PTR_ERR(pre->regs);
225
226	pre->clk_axi = devm_clk_get(dev, "axi");
227	if (IS_ERR(pre->clk_axi))
228	return PTR_ERR(pre->clk_axi);
229
230	pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
231	if (!pre->iram)
232	return -EPROBE_DEFER;
233
234	/*
235	* Allocate IRAM buffer with maximum size. This could be made dynamic,
236	* but as there is no other user of this IRAM region and we can fit all
237	* max sized buffers into it, there is no need yet.
238	*/
239	pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
240	IPU_PRE_NUM_SCANLINES * 4,
241	&pre->buffer_paddr);
242	if (!pre->buffer_virt)
243	return -ENOMEM;
244
47c298f7 LS	245	clk_prepare_enable(pre->clk_axi);
47c298f7 LS	246
d2a34232 LS	247	pre->dev = dev;
	248	platform_set_drvdata(pdev, pre);
	249	mutex_lock(&ipu_pre_list_mutex);
	250	list_add(&pre->list, &ipu_pre_list);
	251	available_pres++;
	252	mutex_unlock(&ipu_pre_list_mutex);
	253
	254	return 0;
	255	}
	256
	257	static int ipu_pre_remove(struct platform_device *pdev)
	258	{
	259	struct ipu_pre *pre = platform_get_drvdata(pdev);
	260
	261	mutex_lock(&ipu_pre_list_mutex);
	262	list_del(&pre->list);
	263	available_pres--;
	264	mutex_unlock(&ipu_pre_list_mutex);
	265
47c298f7 LS	266	clk_disable_unprepare(pre->clk_axi);
47c298f7 LS	267
d2a34232 LS	268	if (pre->buffer_virt)
	269	gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
	270	IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
	271	return 0;
	272	}
	273
	274	static const struct of_device_id ipu_pre_dt_ids[] = {
	275	{ .compatible = "fsl,imx6qp-pre", },
	276	{ /* sentinel */ },
	277	};
	278
	279	struct platform_driver ipu_pre_drv = {
	280	.probe = ipu_pre_probe,
	281	.remove = ipu_pre_remove,
	282	.driver = {
	283	.name = "imx-ipu-pre",
	284	.of_match_table = ipu_pre_dt_ids,
	285	},
	286	};