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ae02e5d4 SP |
1 | /* |
2 | * H/W layer of ISHTP provider device (ISH) | |
3 | * | |
4 | * Copyright (c) 2014-2016, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | */ | |
15 | ||
16 | #ifndef _ISHTP_HW_ISH_H_ | |
17 | #define _ISHTP_HW_ISH_H_ | |
18 | ||
19 | #include <linux/pci.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include "hw-ish-regs.h" | |
22 | #include "ishtp-dev.h" | |
23 | ||
24 | #define CHV_DEVICE_ID 0x22D8 | |
25 | #define BXT_Ax_DEVICE_ID 0x0AA2 | |
26 | #define BXT_Bx_DEVICE_ID 0x1AA2 | |
27 | #define APL_Ax_DEVICE_ID 0x5AA2 | |
28 | #define SPT_Ax_DEVICE_ID 0x9D35 | |
1e3b74a2 | 29 | #define CNL_Ax_DEVICE_ID 0x9DFC |
ae02e5d4 SP |
30 | |
31 | #define REVISION_ID_CHT_A0 0x6 | |
32 | #define REVISION_ID_CHT_Ax_SI 0x0 | |
33 | #define REVISION_ID_CHT_Bx_SI 0x10 | |
34 | #define REVISION_ID_CHT_Kx_SI 0x20 | |
35 | #define REVISION_ID_CHT_Dx_SI 0x30 | |
36 | #define REVISION_ID_CHT_B0 0xB0 | |
37 | #define REVISION_ID_SI_MASK 0x70 | |
38 | ||
39 | struct ipc_rst_payload_type { | |
40 | uint16_t reset_id; | |
41 | uint16_t reserved; | |
42 | }; | |
43 | ||
44 | struct time_sync_format { | |
45 | uint8_t ts1_source; | |
46 | uint8_t ts2_source; | |
47 | uint16_t reserved; | |
48 | } __packed; | |
49 | ||
50 | struct ipc_time_update_msg { | |
51 | uint64_t primary_host_time; | |
52 | struct time_sync_format sync_info; | |
53 | uint64_t secondary_host_time; | |
54 | } __packed; | |
55 | ||
56 | enum { | |
57 | HOST_UTC_TIME_USEC = 0, | |
58 | HOST_SYSTEM_TIME_USEC = 1 | |
59 | }; | |
60 | ||
61 | struct ish_hw { | |
62 | void __iomem *mem_addr; | |
63 | }; | |
64 | ||
291e9e3f EX |
65 | /* |
66 | * ISH FW status type | |
67 | */ | |
68 | enum { | |
69 | FWSTS_AFTER_RESET = 0, | |
70 | FWSTS_WAIT_FOR_HOST = 4, | |
71 | FWSTS_START_KERNEL_DMA = 5, | |
72 | FWSTS_FW_IS_RUNNING = 7, | |
73 | FWSTS_SENSOR_APP_LOADED = 8, | |
74 | FWSTS_SENSOR_APP_RUNNING = 15 | |
75 | }; | |
76 | ||
ae02e5d4 SP |
77 | #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw) |
78 | ||
79 | irqreturn_t ish_irq_handler(int irq, void *dev_id); | |
80 | struct ishtp_device *ish_dev_init(struct pci_dev *pdev); | |
81 | int ish_hw_start(struct ishtp_device *dev); | |
82 | void ish_device_disable(struct ishtp_device *dev); | |
83 | ||
84 | #endif /* _ISHTP_HW_ISH_H_ */ |