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Commit | Line | Data |
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3e7ee490 | 1 | /* |
3e7ee490 HJ |
2 | * Copyright (c) 2009, Microsoft Corporation. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Authors: | |
18 | * Haiyang Zhang <haiyangz@microsoft.com> | |
19 | * Hank Janssen <hjanssen@microsoft.com> | |
20 | * | |
21 | */ | |
0a46618d HJ |
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
23 | ||
a0086dc5 GKH |
24 | #include <linux/kernel.h> |
25 | #include <linux/mm.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
b7c947f0 | 27 | #include <linux/vmalloc.h> |
46a97191 | 28 | #include <linux/hyperv.h> |
83ba0c4f | 29 | #include <linux/version.h> |
db11f12a | 30 | #include <linux/interrupt.h> |
4061ed9e | 31 | #include <linux/clockchips.h> |
407dd164 | 32 | #include <asm/hyperv.h> |
4061ed9e | 33 | #include <asm/mshyperv.h> |
0f2a6619 | 34 | #include "hyperv_vmbus.h" |
3e7ee490 | 35 | |
2400c988 TG |
36 | #ifndef PKG_ABI |
37 | /* | |
38 | * Preserve the ability to 'make deb-pkg' since PKG_ABI is provided | |
39 | * by the Ubuntu build rules. | |
40 | */ | |
41 | #define PKG_ABI 0 | |
42 | #endif | |
43 | ||
454f18a9 | 44 | /* The one and only */ |
6a0aaa18 HZ |
45 | struct hv_context hv_context = { |
46 | .synic_initialized = false, | |
47 | .hypercall_page = NULL, | |
3e7ee490 HJ |
48 | }; |
49 | ||
4061ed9e S |
50 | #define HV_TIMER_FREQUENCY (10 * 1000 * 1000) /* 100ns period */ |
51 | #define HV_MAX_MAX_DELTA_TICKS 0xffffffff | |
52 | #define HV_MIN_DELTA_TICKS 1 | |
53 | ||
3e189519 | 54 | /* |
d44890c8 | 55 | * query_hypervisor_info - Get version info of the windows hypervisor |
0831ad04 | 56 | */ |
5fbebb2d S |
57 | unsigned int host_info_eax; |
58 | unsigned int host_info_ebx; | |
59 | unsigned int host_info_ecx; | |
60 | unsigned int host_info_edx; | |
61 | ||
d44890c8 | 62 | static int query_hypervisor_info(void) |
0831ad04 GKH |
63 | { |
64 | unsigned int eax; | |
65 | unsigned int ebx; | |
66 | unsigned int ecx; | |
67 | unsigned int edx; | |
b8dfb264 | 68 | unsigned int max_leaf; |
0831ad04 | 69 | unsigned int op; |
3e7ee490 | 70 | |
0831ad04 GKH |
71 | /* |
72 | * Its assumed that this is called after confirming that Viridian | |
73 | * is present. Query id and revision. | |
74 | */ | |
75 | eax = 0; | |
76 | ebx = 0; | |
77 | ecx = 0; | |
78 | edx = 0; | |
f6feebe0 | 79 | op = HVCPUID_VENDOR_MAXFUNCTION; |
0831ad04 | 80 | cpuid(op, &eax, &ebx, &ecx, &edx); |
3e7ee490 | 81 | |
b8dfb264 | 82 | max_leaf = eax; |
0831ad04 | 83 | |
b8dfb264 | 84 | if (max_leaf >= HVCPUID_VERSION) { |
0831ad04 GKH |
85 | eax = 0; |
86 | ebx = 0; | |
87 | ecx = 0; | |
88 | edx = 0; | |
f6feebe0 | 89 | op = HVCPUID_VERSION; |
0831ad04 | 90 | cpuid(op, &eax, &ebx, &ecx, &edx); |
5fbebb2d S |
91 | host_info_eax = eax; |
92 | host_info_ebx = ebx; | |
93 | host_info_ecx = ecx; | |
94 | host_info_edx = edx; | |
0831ad04 | 95 | } |
b8dfb264 | 96 | return max_leaf; |
0831ad04 | 97 | } |
3e7ee490 | 98 | |
3e189519 | 99 | /* |
a108393d | 100 | * hv_do_hypercall- Invoke the specified hypercall |
0831ad04 | 101 | */ |
a108393d | 102 | u64 hv_do_hypercall(u64 control, void *input, void *output) |
3e7ee490 | 103 | { |
b8dfb264 HZ |
104 | u64 input_address = (input) ? virt_to_phys(input) : 0; |
105 | u64 output_address = (output) ? virt_to_phys(output) : 0; | |
dec317fd | 106 | void *hypercall_page = hv_context.hypercall_page; |
d7646eaa VK |
107 | #ifdef CONFIG_X86_64 |
108 | u64 hv_status = 0; | |
109 | ||
110 | if (!hypercall_page) | |
111 | return (u64)ULLONG_MAX; | |
3e7ee490 | 112 | |
b8dfb264 HZ |
113 | __asm__ __volatile__("mov %0, %%r8" : : "r" (output_address) : "r8"); |
114 | __asm__ __volatile__("call *%3" : "=a" (hv_status) : | |
115 | "c" (control), "d" (input_address), | |
116 | "m" (hypercall_page)); | |
3e7ee490 | 117 | |
b8dfb264 | 118 | return hv_status; |
3e7ee490 HJ |
119 | |
120 | #else | |
121 | ||
b8dfb264 HZ |
122 | u32 control_hi = control >> 32; |
123 | u32 control_lo = control & 0xFFFFFFFF; | |
124 | u32 hv_status_hi = 1; | |
125 | u32 hv_status_lo = 1; | |
b8dfb264 HZ |
126 | u32 input_address_hi = input_address >> 32; |
127 | u32 input_address_lo = input_address & 0xFFFFFFFF; | |
b8dfb264 HZ |
128 | u32 output_address_hi = output_address >> 32; |
129 | u32 output_address_lo = output_address & 0xFFFFFFFF; | |
d7646eaa VK |
130 | |
131 | if (!hypercall_page) | |
132 | return (u64)ULLONG_MAX; | |
3e7ee490 | 133 | |
b8dfb264 HZ |
134 | __asm__ __volatile__ ("call *%8" : "=d"(hv_status_hi), |
135 | "=a"(hv_status_lo) : "d" (control_hi), | |
136 | "a" (control_lo), "b" (input_address_hi), | |
137 | "c" (input_address_lo), "D"(output_address_hi), | |
138 | "S"(output_address_lo), "m" (hypercall_page)); | |
3e7ee490 | 139 | |
b8dfb264 | 140 | return hv_status_lo | ((u64)hv_status_hi << 32); |
0831ad04 | 141 | #endif /* !x86_64 */ |
3e7ee490 | 142 | } |
a108393d | 143 | EXPORT_SYMBOL_GPL(hv_do_hypercall); |
3e7ee490 | 144 | |
ca9357bd | 145 | #ifdef CONFIG_X86_64 |
a5a1d1c2 | 146 | static u64 read_hv_clock_tsc(struct clocksource *arg) |
ca9357bd | 147 | { |
a5a1d1c2 | 148 | u64 current_tick; |
ca9357bd S |
149 | struct ms_hyperv_tsc_page *tsc_pg = hv_context.tsc_page; |
150 | ||
c35b82ef | 151 | if (tsc_pg->tsc_sequence != 0) { |
ca9357bd S |
152 | /* |
153 | * Use the tsc page to compute the value. | |
154 | */ | |
155 | ||
156 | while (1) { | |
a5a1d1c2 | 157 | u64 tmp; |
ca9357bd S |
158 | u32 sequence = tsc_pg->tsc_sequence; |
159 | u64 cur_tsc; | |
160 | u64 scale = tsc_pg->tsc_scale; | |
161 | s64 offset = tsc_pg->tsc_offset; | |
162 | ||
163 | rdtscll(cur_tsc); | |
164 | /* current_tick = ((cur_tsc *scale) >> 64) + offset */ | |
165 | asm("mulq %3" | |
166 | : "=d" (current_tick), "=a" (tmp) | |
167 | : "a" (cur_tsc), "r" (scale)); | |
168 | ||
169 | current_tick += offset; | |
170 | if (tsc_pg->tsc_sequence == sequence) | |
171 | return current_tick; | |
172 | ||
c35b82ef | 173 | if (tsc_pg->tsc_sequence != 0) |
ca9357bd S |
174 | continue; |
175 | /* | |
176 | * Fallback using MSR method. | |
177 | */ | |
178 | break; | |
179 | } | |
180 | } | |
181 | rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); | |
182 | return current_tick; | |
183 | } | |
184 | ||
185 | static struct clocksource hyperv_cs_tsc = { | |
186 | .name = "hyperv_clocksource_tsc_page", | |
187 | .rating = 425, | |
188 | .read = read_hv_clock_tsc, | |
189 | .mask = CLOCKSOURCE_MASK(64), | |
190 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
191 | }; | |
192 | #endif | |
193 | ||
194 | ||
3e189519 | 195 | /* |
d44890c8 | 196 | * hv_init - Main initialization routine. |
0831ad04 GKH |
197 | * |
198 | * This routine must be called before any other routines in here are called | |
199 | */ | |
d44890c8 | 200 | int hv_init(void) |
3e7ee490 | 201 | { |
b8dfb264 HZ |
202 | int max_leaf; |
203 | union hv_x64_msr_hypercall_contents hypercall_msr; | |
204 | void *virtaddr = NULL; | |
3e7ee490 | 205 | |
14c1bf8a | 206 | memset(hv_context.synic_event_page, 0, sizeof(void *) * NR_CPUS); |
6a0aaa18 | 207 | memset(hv_context.synic_message_page, 0, |
14c1bf8a | 208 | sizeof(void *) * NR_CPUS); |
b29ef354 S |
209 | memset(hv_context.post_msg_page, 0, |
210 | sizeof(void *) * NR_CPUS); | |
917ea427 S |
211 | memset(hv_context.vp_index, 0, |
212 | sizeof(int) * NR_CPUS); | |
db11f12a S |
213 | memset(hv_context.event_dpc, 0, |
214 | sizeof(void *) * NR_CPUS); | |
d81274aa S |
215 | memset(hv_context.msg_dpc, 0, |
216 | sizeof(void *) * NR_CPUS); | |
4061ed9e S |
217 | memset(hv_context.clk_evt, 0, |
218 | sizeof(void *) * NR_CPUS); | |
3e7ee490 | 219 | |
d44890c8 | 220 | max_leaf = query_hypervisor_info(); |
3e7ee490 | 221 | |
83ba0c4f S |
222 | /* |
223 | * Write our OS ID. | |
224 | */ | |
2400c988 | 225 | hv_context.guestid = generate_guest_id(0x80 /*Canonical*/, LINUX_VERSION_CODE, PKG_ABI); |
83ba0c4f | 226 | wrmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid); |
a73e6b7c | 227 | |
454f18a9 | 228 | /* See if the hypercall page is already set */ |
b8dfb264 | 229 | rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); |
3e7ee490 | 230 | |
71a5a055 | 231 | virtaddr = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL_RX); |
3e7ee490 | 232 | |
98e08702 | 233 | if (!virtaddr) |
44939d37 | 234 | goto cleanup; |
3e7ee490 | 235 | |
b8dfb264 | 236 | hypercall_msr.enable = 1; |
a73e6b7c | 237 | |
b8dfb264 HZ |
238 | hypercall_msr.guest_physical_address = vmalloc_to_pfn(virtaddr); |
239 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
a73e6b7c HJ |
240 | |
241 | /* Confirm that hypercall page did get setup. */ | |
b8dfb264 HZ |
242 | hypercall_msr.as_uint64 = 0; |
243 | rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
a73e6b7c | 244 | |
98e08702 | 245 | if (!hypercall_msr.enable) |
44939d37 | 246 | goto cleanup; |
3e7ee490 | 247 | |
b8dfb264 | 248 | hv_context.hypercall_page = virtaddr; |
a73e6b7c | 249 | |
ca9357bd S |
250 | #ifdef CONFIG_X86_64 |
251 | if (ms_hyperv.features & HV_X64_MSR_REFERENCE_TSC_AVAILABLE) { | |
9220e39b SM |
252 | union hv_x64_msr_hypercall_contents tsc_msr; |
253 | void *va_tsc; | |
254 | ||
ca9357bd S |
255 | va_tsc = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL); |
256 | if (!va_tsc) | |
257 | goto cleanup; | |
258 | hv_context.tsc_page = va_tsc; | |
259 | ||
260 | rdmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); | |
261 | ||
262 | tsc_msr.enable = 1; | |
263 | tsc_msr.guest_physical_address = vmalloc_to_pfn(va_tsc); | |
264 | ||
265 | wrmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); | |
266 | clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100); | |
267 | } | |
268 | #endif | |
5433e003 | 269 | return 0; |
3e7ee490 | 270 | |
44939d37 | 271 | cleanup: |
b8dfb264 HZ |
272 | if (virtaddr) { |
273 | if (hypercall_msr.enable) { | |
274 | hypercall_msr.as_uint64 = 0; | |
275 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
3e7ee490 HJ |
276 | } |
277 | ||
b8dfb264 | 278 | vfree(virtaddr); |
3e7ee490 | 279 | } |
5433e003 S |
280 | |
281 | return -ENOTSUPP; | |
3e7ee490 HJ |
282 | } |
283 | ||
3e189519 | 284 | /* |
d44890c8 | 285 | * hv_cleanup - Cleanup routine. |
0831ad04 GKH |
286 | * |
287 | * This routine is called normally during driver unloading or exiting. | |
288 | */ | |
a9f61ca7 | 289 | void hv_cleanup(bool crash) |
3e7ee490 | 290 | { |
b8dfb264 | 291 | union hv_x64_msr_hypercall_contents hypercall_msr; |
3e7ee490 | 292 | |
93e5bd06 S |
293 | /* Reset our OS id */ |
294 | wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); | |
295 | ||
6a0aaa18 | 296 | if (hv_context.hypercall_page) { |
b8dfb264 HZ |
297 | hypercall_msr.as_uint64 = 0; |
298 | wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); | |
a9f61ca7 VK |
299 | if (!crash) |
300 | vfree(hv_context.hypercall_page); | |
6a0aaa18 | 301 | hv_context.hypercall_page = NULL; |
3e7ee490 | 302 | } |
ca9357bd S |
303 | |
304 | #ifdef CONFIG_X86_64 | |
305 | /* | |
306 | * Cleanup the TSC page based CS. | |
307 | */ | |
308 | if (ms_hyperv.features & HV_X64_MSR_REFERENCE_TSC_AVAILABLE) { | |
3ccb4fd8 VK |
309 | /* |
310 | * Crash can happen in an interrupt context and unregistering | |
311 | * a clocksource is impossible and redundant in this case. | |
312 | */ | |
313 | if (!oops_in_progress) { | |
314 | clocksource_change_rating(&hyperv_cs_tsc, 10); | |
315 | clocksource_unregister(&hyperv_cs_tsc); | |
316 | } | |
ca9357bd S |
317 | |
318 | hypercall_msr.as_uint64 = 0; | |
319 | wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64); | |
a541e7dc | 320 | if (!crash) |
a9f61ca7 | 321 | vfree(hv_context.tsc_page); |
a541e7dc | 322 | hv_context.tsc_page = NULL; |
ca9357bd S |
323 | } |
324 | #endif | |
3e7ee490 HJ |
325 | } |
326 | ||
3e189519 | 327 | /* |
d44890c8 | 328 | * hv_post_message - Post a message using the hypervisor message IPC. |
0831ad04 GKH |
329 | * |
330 | * This involves a hypercall. | |
331 | */ | |
415f0a02 | 332 | int hv_post_message(union hv_connection_id connection_id, |
b8dfb264 HZ |
333 | enum hv_message_type message_type, |
334 | void *payload, size_t payload_size) | |
3e7ee490 | 335 | { |
3e7ee490 | 336 | |
b8dfb264 | 337 | struct hv_input_post_message *aligned_msg; |
a108393d | 338 | u64 status; |
3e7ee490 | 339 | |
b8dfb264 | 340 | if (payload_size > HV_MESSAGE_PAYLOAD_BYTE_COUNT) |
39594abc | 341 | return -EMSGSIZE; |
3e7ee490 | 342 | |
b8dfb264 | 343 | aligned_msg = (struct hv_input_post_message *) |
b29ef354 | 344 | hv_context.post_msg_page[get_cpu()]; |
3e7ee490 | 345 | |
b8dfb264 | 346 | aligned_msg->connectionid = connection_id; |
b29ef354 | 347 | aligned_msg->reserved = 0; |
b8dfb264 HZ |
348 | aligned_msg->message_type = message_type; |
349 | aligned_msg->payload_size = payload_size; | |
350 | memcpy((void *)aligned_msg->payload, payload, payload_size); | |
3e7ee490 | 351 | |
a108393d | 352 | status = hv_do_hypercall(HVCALL_POST_MESSAGE, aligned_msg, NULL); |
3e7ee490 | 353 | |
b29ef354 | 354 | put_cpu(); |
a108393d | 355 | return status & 0xFFFF; |
3e7ee490 HJ |
356 | } |
357 | ||
4061ed9e S |
358 | static int hv_ce_set_next_event(unsigned long delta, |
359 | struct clock_event_device *evt) | |
360 | { | |
a5a1d1c2 | 361 | u64 current_tick; |
4061ed9e | 362 | |
bc609cb4 | 363 | WARN_ON(!clockevent_state_oneshot(evt)); |
4061ed9e S |
364 | |
365 | rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick); | |
366 | current_tick += delta; | |
367 | wrmsrl(HV_X64_MSR_STIMER0_COUNT, current_tick); | |
368 | return 0; | |
369 | } | |
370 | ||
bc609cb4 VK |
371 | static int hv_ce_shutdown(struct clock_event_device *evt) |
372 | { | |
373 | wrmsrl(HV_X64_MSR_STIMER0_COUNT, 0); | |
374 | wrmsrl(HV_X64_MSR_STIMER0_CONFIG, 0); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int hv_ce_set_oneshot(struct clock_event_device *evt) | |
4061ed9e S |
380 | { |
381 | union hv_timer_config timer_cfg; | |
382 | ||
bc609cb4 VK |
383 | timer_cfg.enable = 1; |
384 | timer_cfg.auto_enable = 1; | |
385 | timer_cfg.sintx = VMBUS_MESSAGE_SINT; | |
386 | wrmsrl(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64); | |
387 | ||
388 | return 0; | |
4061ed9e S |
389 | } |
390 | ||
391 | static void hv_init_clockevent_device(struct clock_event_device *dev, int cpu) | |
392 | { | |
393 | dev->name = "Hyper-V clockevent"; | |
394 | dev->features = CLOCK_EVT_FEAT_ONESHOT; | |
395 | dev->cpumask = cpumask_of(cpu); | |
396 | dev->rating = 1000; | |
e086748c VK |
397 | /* |
398 | * Avoid settint dev->owner = THIS_MODULE deliberately as doing so will | |
399 | * result in clockevents_config_and_register() taking additional | |
400 | * references to the hv_vmbus module making it impossible to unload. | |
401 | */ | |
4061ed9e | 402 | |
bc609cb4 VK |
403 | dev->set_state_shutdown = hv_ce_shutdown; |
404 | dev->set_state_oneshot = hv_ce_set_oneshot; | |
4061ed9e S |
405 | dev->set_next_event = hv_ce_set_next_event; |
406 | } | |
407 | ||
2608fb65 JW |
408 | |
409 | int hv_synic_alloc(void) | |
410 | { | |
411 | size_t size = sizeof(struct tasklet_struct); | |
4061ed9e | 412 | size_t ced_size = sizeof(struct clock_event_device); |
2608fb65 JW |
413 | int cpu; |
414 | ||
9f01ec53 S |
415 | hv_context.hv_numa_map = kzalloc(sizeof(struct cpumask) * nr_node_ids, |
416 | GFP_ATOMIC); | |
417 | if (hv_context.hv_numa_map == NULL) { | |
418 | pr_err("Unable to allocate NUMA map\n"); | |
419 | goto err; | |
420 | } | |
421 | ||
6d5ad8d8 | 422 | for_each_online_cpu(cpu) { |
2608fb65 JW |
423 | hv_context.event_dpc[cpu] = kmalloc(size, GFP_ATOMIC); |
424 | if (hv_context.event_dpc[cpu] == NULL) { | |
425 | pr_err("Unable to allocate event dpc\n"); | |
426 | goto err; | |
427 | } | |
428 | tasklet_init(hv_context.event_dpc[cpu], vmbus_on_event, cpu); | |
429 | ||
d81274aa S |
430 | hv_context.msg_dpc[cpu] = kmalloc(size, GFP_ATOMIC); |
431 | if (hv_context.msg_dpc[cpu] == NULL) { | |
432 | pr_err("Unable to allocate event dpc\n"); | |
433 | goto err; | |
434 | } | |
435 | tasklet_init(hv_context.msg_dpc[cpu], vmbus_on_msg_dpc, cpu); | |
436 | ||
4061ed9e S |
437 | hv_context.clk_evt[cpu] = kzalloc(ced_size, GFP_ATOMIC); |
438 | if (hv_context.clk_evt[cpu] == NULL) { | |
439 | pr_err("Unable to allocate clock event device\n"); | |
440 | goto err; | |
441 | } | |
9f01ec53 | 442 | |
4061ed9e S |
443 | hv_init_clockevent_device(hv_context.clk_evt[cpu], cpu); |
444 | ||
2608fb65 JW |
445 | hv_context.synic_message_page[cpu] = |
446 | (void *)get_zeroed_page(GFP_ATOMIC); | |
447 | ||
448 | if (hv_context.synic_message_page[cpu] == NULL) { | |
449 | pr_err("Unable to allocate SYNIC message page\n"); | |
450 | goto err; | |
451 | } | |
452 | ||
453 | hv_context.synic_event_page[cpu] = | |
454 | (void *)get_zeroed_page(GFP_ATOMIC); | |
455 | ||
456 | if (hv_context.synic_event_page[cpu] == NULL) { | |
457 | pr_err("Unable to allocate SYNIC event page\n"); | |
458 | goto err; | |
459 | } | |
b29ef354 S |
460 | |
461 | hv_context.post_msg_page[cpu] = | |
462 | (void *)get_zeroed_page(GFP_ATOMIC); | |
463 | ||
464 | if (hv_context.post_msg_page[cpu] == NULL) { | |
465 | pr_err("Unable to allocate post msg page\n"); | |
466 | goto err; | |
467 | } | |
db60c8d6 VK |
468 | |
469 | INIT_LIST_HEAD(&hv_context.percpu_list[cpu]); | |
2608fb65 JW |
470 | } |
471 | ||
472 | return 0; | |
473 | err: | |
474 | return -ENOMEM; | |
475 | } | |
476 | ||
8712954d | 477 | static void hv_synic_free_cpu(int cpu) |
2608fb65 JW |
478 | { |
479 | kfree(hv_context.event_dpc[cpu]); | |
d81274aa | 480 | kfree(hv_context.msg_dpc[cpu]); |
4061ed9e | 481 | kfree(hv_context.clk_evt[cpu]); |
fdf91dae | 482 | if (hv_context.synic_event_page[cpu]) |
2608fb65 JW |
483 | free_page((unsigned long)hv_context.synic_event_page[cpu]); |
484 | if (hv_context.synic_message_page[cpu]) | |
485 | free_page((unsigned long)hv_context.synic_message_page[cpu]); | |
b29ef354 S |
486 | if (hv_context.post_msg_page[cpu]) |
487 | free_page((unsigned long)hv_context.post_msg_page[cpu]); | |
2608fb65 JW |
488 | } |
489 | ||
490 | void hv_synic_free(void) | |
491 | { | |
492 | int cpu; | |
493 | ||
9f01ec53 | 494 | kfree(hv_context.hv_numa_map); |
6d5ad8d8 | 495 | for_each_online_cpu(cpu) |
2608fb65 JW |
496 | hv_synic_free_cpu(cpu); |
497 | } | |
498 | ||
3e189519 | 499 | /* |
d44890c8 | 500 | * hv_synic_init - Initialize the Synthethic Interrupt Controller. |
0831ad04 GKH |
501 | * |
502 | * If it is already initialized by another entity (ie x2v shim), we need to | |
503 | * retrieve the initialized message and event pages. Otherwise, we create and | |
504 | * initialize the message and event pages. | |
505 | */ | |
302a3c0f | 506 | void hv_synic_init(void *arg) |
3e7ee490 | 507 | { |
0831ad04 | 508 | u64 version; |
eacb1b4d GKH |
509 | union hv_synic_simp simp; |
510 | union hv_synic_siefp siefp; | |
b8dfb264 | 511 | union hv_synic_sint shared_sint; |
eacb1b4d | 512 | union hv_synic_scontrol sctrl; |
917ea427 | 513 | u64 vp_index; |
a73e6b7c | 514 | |
7692fd4d | 515 | int cpu = smp_processor_id(); |
3e7ee490 | 516 | |
6a0aaa18 | 517 | if (!hv_context.hypercall_page) |
7692fd4d | 518 | return; |
3e7ee490 | 519 | |
454f18a9 | 520 | /* Check the version */ |
a51ed7d6 | 521 | rdmsrl(HV_X64_MSR_SVERSION, version); |
3e7ee490 | 522 | |
a73e6b7c | 523 | /* Setup the Synic's message page */ |
f6feebe0 HZ |
524 | rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
525 | simp.simp_enabled = 1; | |
6a0aaa18 | 526 | simp.base_simp_gpa = virt_to_phys(hv_context.synic_message_page[cpu]) |
a73e6b7c | 527 | >> PAGE_SHIFT; |
3e7ee490 | 528 | |
f6feebe0 | 529 | wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
3e7ee490 | 530 | |
a73e6b7c | 531 | /* Setup the Synic's event page */ |
f6feebe0 HZ |
532 | rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
533 | siefp.siefp_enabled = 1; | |
6a0aaa18 | 534 | siefp.base_siefp_gpa = virt_to_phys(hv_context.synic_event_page[cpu]) |
a73e6b7c HJ |
535 | >> PAGE_SHIFT; |
536 | ||
f6feebe0 | 537 | wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
0831ad04 | 538 | |
0831ad04 | 539 | /* Setup the shared SINT. */ |
b8dfb264 | 540 | rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 541 | |
b8dfb264 | 542 | shared_sint.as_uint64 = 0; |
302a3c0f | 543 | shared_sint.vector = HYPERVISOR_CALLBACK_VECTOR; |
b8dfb264 | 544 | shared_sint.masked = false; |
b0209501 | 545 | shared_sint.auto_eoi = true; |
3e7ee490 | 546 | |
b8dfb264 | 547 | wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 548 | |
454f18a9 | 549 | /* Enable the global synic bit */ |
f6feebe0 HZ |
550 | rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); |
551 | sctrl.enable = 1; | |
3e7ee490 | 552 | |
f6feebe0 | 553 | wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); |
3e7ee490 | 554 | |
6a0aaa18 | 555 | hv_context.synic_initialized = true; |
917ea427 S |
556 | |
557 | /* | |
558 | * Setup the mapping between Hyper-V's notion | |
559 | * of cpuid and Linux' notion of cpuid. | |
560 | * This array will be indexed using Linux cpuid. | |
561 | */ | |
562 | rdmsrl(HV_X64_MSR_VP_INDEX, vp_index); | |
563 | hv_context.vp_index[cpu] = (u32)vp_index; | |
3a28fa35 | 564 | |
4061ed9e S |
565 | /* |
566 | * Register the per-cpu clockevent source. | |
567 | */ | |
568 | if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE) | |
569 | clockevents_config_and_register(hv_context.clk_evt[cpu], | |
570 | HV_TIMER_FREQUENCY, | |
571 | HV_MIN_DELTA_TICKS, | |
572 | HV_MAX_MAX_DELTA_TICKS); | |
7692fd4d | 573 | return; |
3e7ee490 HJ |
574 | } |
575 | ||
e086748c VK |
576 | /* |
577 | * hv_synic_clockevents_cleanup - Cleanup clockevent devices | |
578 | */ | |
579 | void hv_synic_clockevents_cleanup(void) | |
580 | { | |
581 | int cpu; | |
582 | ||
583 | if (!(ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE)) | |
584 | return; | |
585 | ||
6ffc4b85 | 586 | for_each_present_cpu(cpu) |
e086748c VK |
587 | clockevents_unbind_device(hv_context.clk_evt[cpu], cpu); |
588 | } | |
589 | ||
3e189519 | 590 | /* |
d44890c8 | 591 | * hv_synic_cleanup - Cleanup routine for hv_synic_init(). |
0831ad04 | 592 | */ |
d44890c8 | 593 | void hv_synic_cleanup(void *arg) |
3e7ee490 | 594 | { |
b8dfb264 | 595 | union hv_synic_sint shared_sint; |
eacb1b4d GKH |
596 | union hv_synic_simp simp; |
597 | union hv_synic_siefp siefp; | |
e72e7ac5 | 598 | union hv_synic_scontrol sctrl; |
7692fd4d | 599 | int cpu = smp_processor_id(); |
3e7ee490 | 600 | |
6a0aaa18 | 601 | if (!hv_context.synic_initialized) |
3e7ee490 | 602 | return; |
3e7ee490 | 603 | |
e086748c | 604 | /* Turn off clockevent device */ |
6ffc4b85 VK |
605 | if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE) { |
606 | clockevents_unbind_device(hv_context.clk_evt[cpu], cpu); | |
bc609cb4 | 607 | hv_ce_shutdown(hv_context.clk_evt[cpu]); |
6ffc4b85 | 608 | } |
e086748c | 609 | |
b8dfb264 | 610 | rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 611 | |
b8dfb264 | 612 | shared_sint.masked = 1; |
3e7ee490 | 613 | |
7692fd4d | 614 | /* Need to correctly cleanup in the case of SMP!!! */ |
454f18a9 | 615 | /* Disable the interrupt */ |
b8dfb264 | 616 | wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64); |
3e7ee490 | 617 | |
f6feebe0 HZ |
618 | rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
619 | simp.simp_enabled = 0; | |
620 | simp.base_simp_gpa = 0; | |
3e7ee490 | 621 | |
f6feebe0 | 622 | wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64); |
3e7ee490 | 623 | |
f6feebe0 HZ |
624 | rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
625 | siefp.siefp_enabled = 0; | |
626 | siefp.base_siefp_gpa = 0; | |
3e7ee490 | 627 | |
f6feebe0 | 628 | wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64); |
3e7ee490 | 629 | |
e72e7ac5 VK |
630 | /* Disable the global synic bit */ |
631 | rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); | |
632 | sctrl.enable = 0; | |
633 | wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64); | |
3e7ee490 | 634 | } |