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bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
4cc45275 | 37 | #include <linux/smp.h> |
a45a8c85 | 38 | #include <linux/moduleparam.h> |
14513ee6 | 39 | #include <linux/pci.h> |
bebe4678 RM |
40 | #include <asm/msr.h> |
41 | #include <asm/processor.h> | |
9b38096f | 42 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
43 | |
44 | #define DRVNAME "coretemp" | |
45 | ||
a45a8c85 JD |
46 | /* |
47 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
48 | * When set, it replaces the driver's suboptimal heuristic. | |
49 | */ | |
50 | static int force_tjmax; | |
51 | module_param_named(tjmax, force_tjmax, int, 0444); | |
52 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
53 | ||
723f5734 | 54 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 55 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 56 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 57 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 58 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 59 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
60 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
61 | ||
780affe0 | 62 | #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) |
141168c3 KW |
63 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) |
64 | ||
65 | #ifdef CONFIG_SMP | |
19a34eea BG |
66 | #define for_each_sibling(i, cpu) \ |
67 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 68 | #else |
bb74e8ca | 69 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 70 | #endif |
bebe4678 RM |
71 | |
72 | /* | |
199e0de7 D |
73 | * Per-Core Temperature Data |
74 | * @last_updated: The time when the current temperature value was updated | |
75 | * earlier (in jiffies). | |
76 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
77 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
78 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
79 | * from where the temperature values should be read. | |
c814a4c7 | 80 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
81 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
82 | * Otherwise, temp_data holds coretemp data. | |
83 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 84 | */ |
199e0de7 | 85 | struct temp_data { |
bebe4678 | 86 | int temp; |
6369a288 | 87 | int ttarget; |
199e0de7 D |
88 | int tjmax; |
89 | unsigned long last_updated; | |
90 | unsigned int cpu; | |
91 | u32 cpu_core_id; | |
92 | u32 status_reg; | |
c814a4c7 | 93 | int attr_size; |
199e0de7 D |
94 | bool is_pkg_data; |
95 | bool valid; | |
c814a4c7 D |
96 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
97 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
98 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
99 | struct attribute_group attr_group; | |
199e0de7 | 100 | struct mutex update_lock; |
bebe4678 RM |
101 | }; |
102 | ||
199e0de7 D |
103 | /* Platform Data per Physical CPU */ |
104 | struct platform_data { | |
e1b370b6 | 105 | struct device *hwmon_dev; |
71266846 | 106 | u16 pkg_id; |
e1b370b6 TG |
107 | struct cpumask cpumask; |
108 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
109 | struct device_attribute name_attr; |
110 | }; | |
bebe4678 | 111 | |
71266846 TG |
112 | /* Keep track of how many package pointers we allocated in init() */ |
113 | static int max_packages __read_mostly; | |
114 | /* Array of package pointers. Serialized by cpu hotplug lock */ | |
115 | static struct platform_device **pkg_devices; | |
199e0de7 | 116 | |
199e0de7 D |
117 | static ssize_t show_label(struct device *dev, |
118 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 119 | { |
bebe4678 | 120 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
121 | struct platform_data *pdata = dev_get_drvdata(dev); |
122 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
123 | ||
124 | if (tdata->is_pkg_data) | |
71266846 | 125 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); |
bebe4678 | 126 | |
199e0de7 | 127 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
128 | } |
129 | ||
199e0de7 D |
130 | static ssize_t show_crit_alarm(struct device *dev, |
131 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 132 | { |
199e0de7 D |
133 | u32 eax, edx; |
134 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
135 | struct platform_data *pdata = dev_get_drvdata(dev); | |
136 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
137 | ||
723f5734 | 138 | mutex_lock(&tdata->update_lock); |
199e0de7 | 139 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); |
723f5734 | 140 | mutex_unlock(&tdata->update_lock); |
199e0de7 D |
141 | |
142 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
143 | } |
144 | ||
199e0de7 D |
145 | static ssize_t show_tjmax(struct device *dev, |
146 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
147 | { |
148 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 149 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 150 | |
199e0de7 | 151 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
152 | } |
153 | ||
199e0de7 D |
154 | static ssize_t show_ttarget(struct device *dev, |
155 | struct device_attribute *devattr, char *buf) | |
156 | { | |
157 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
158 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 159 | |
199e0de7 D |
160 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
161 | } | |
bebe4678 | 162 | |
199e0de7 D |
163 | static ssize_t show_temp(struct device *dev, |
164 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 165 | { |
199e0de7 D |
166 | u32 eax, edx; |
167 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
168 | struct platform_data *pdata = dev_get_drvdata(dev); | |
169 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 170 | |
199e0de7 | 171 | mutex_lock(&tdata->update_lock); |
bebe4678 | 172 | |
199e0de7 D |
173 | /* Check whether the time interval has elapsed */ |
174 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
175 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
bf6ea084 GR |
176 | /* |
177 | * Ignore the valid bit. In all observed cases the register | |
178 | * value is either low or zero if the valid bit is 0. | |
179 | * Return it instead of reporting an error which doesn't | |
180 | * really help at all. | |
181 | */ | |
182 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
183 | tdata->valid = 1; | |
199e0de7 | 184 | tdata->last_updated = jiffies; |
bebe4678 RM |
185 | } |
186 | ||
199e0de7 | 187 | mutex_unlock(&tdata->update_lock); |
bf6ea084 | 188 | return sprintf(buf, "%d\n", tdata->temp); |
bebe4678 RM |
189 | } |
190 | ||
14513ee6 GR |
191 | struct tjmax_pci { |
192 | unsigned int device; | |
193 | int tjmax; | |
194 | }; | |
195 | ||
196 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 197 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
198 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
199 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
200 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
201 | }; | |
202 | ||
41e58a1f GR |
203 | struct tjmax { |
204 | char const *id; | |
205 | int tjmax; | |
206 | }; | |
207 | ||
d23e2ae1 | 208 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
209 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
210 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
211 | }; |
212 | ||
2fa5222e GR |
213 | struct tjmax_model { |
214 | u8 model; | |
215 | u8 mask; | |
216 | int tjmax; | |
217 | }; | |
218 | ||
219 | #define ANY 0xff | |
220 | ||
d23e2ae1 | 221 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 222 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
223 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
224 | * Note: Also matches 230 and 330, | |
225 | * which are covered by tjmax_table | |
226 | */ | |
227 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
228 | * Note: TjMax for E6xxT is 110C, but CPU type | |
229 | * is undetectable by software | |
230 | */ | |
231 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
232 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
233 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
234 | * Also matches S12x0 (stepping 9), covered by | |
235 | * PCI table | |
236 | */ | |
2fa5222e GR |
237 | }; |
238 | ||
d23e2ae1 | 239 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
240 | { |
241 | /* The 100C is default for both mobile and non mobile CPUs */ | |
242 | ||
243 | int tjmax = 100000; | |
eccfed42 | 244 | int tjmax_ee = 85000; |
708a62bc | 245 | int usemsr_ee = 1; |
118a8871 RM |
246 | int err; |
247 | u32 eax, edx; | |
41e58a1f | 248 | int i; |
b9ccff23 SK |
249 | u16 devfn = PCI_DEVFN(0, 0); |
250 | struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); | |
14513ee6 GR |
251 | |
252 | /* | |
253 | * Explicit tjmax table entries override heuristics. | |
254 | * First try PCI host bridge IDs, followed by model ID strings | |
255 | * and model/stepping information. | |
256 | */ | |
257 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
258 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
259 | if (host_bridge->device == tjmax_pci_table[i].device) | |
260 | return tjmax_pci_table[i].tjmax; | |
261 | } | |
262 | } | |
41e58a1f | 263 | |
41e58a1f GR |
264 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
265 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
266 | return tjmax_table[i].tjmax; | |
267 | } | |
118a8871 | 268 | |
2fa5222e GR |
269 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
270 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
271 | if (c->x86_model == tm->model && | |
272 | (tm->mask == ANY || c->x86_mask == tm->mask)) | |
273 | return tm->tjmax; | |
72cbdddc | 274 | } |
1fe63ab4 | 275 | |
72cbdddc | 276 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 277 | |
72cbdddc | 278 | if (c->x86_model == 0xf && c->x86_mask < 4) |
5592906f | 279 | usemsr_ee = 0; |
708a62bc | 280 | |
4cc45275 | 281 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 282 | u8 platform_id; |
118a8871 | 283 | |
4cc45275 GR |
284 | /* |
285 | * Now we can detect the mobile CPU using Intel provided table | |
286 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
287 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
288 | */ | |
118a8871 RM |
289 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
290 | if (err) { | |
291 | dev_warn(dev, | |
292 | "Unable to access MSR 0x17, assuming desktop" | |
293 | " CPU\n"); | |
708a62bc | 294 | usemsr_ee = 0; |
eccfed42 | 295 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
296 | /* |
297 | * Trust bit 28 up to Penryn, I could not find any | |
298 | * documentation on that; if you happen to know | |
299 | * someone at Intel please ask | |
300 | */ | |
708a62bc | 301 | usemsr_ee = 0; |
eccfed42 RM |
302 | } else { |
303 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
304 | platform_id = (edx >> 18) & 0x7; | |
305 | ||
4cc45275 GR |
306 | /* |
307 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
308 | * (guesswork) | |
309 | */ | |
310 | if (c->x86_model == 0x17 && | |
311 | (platform_id == 5 || platform_id == 7)) { | |
312 | /* | |
313 | * If MSR EE bit is set, set it to 90 degrees C, | |
314 | * otherwise 105 degrees C | |
315 | */ | |
eccfed42 RM |
316 | tjmax_ee = 90000; |
317 | tjmax = 105000; | |
318 | } | |
118a8871 RM |
319 | } |
320 | } | |
321 | ||
708a62bc | 322 | if (usemsr_ee) { |
118a8871 RM |
323 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
324 | if (err) { | |
325 | dev_warn(dev, | |
326 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 327 | " at default\n"); |
118a8871 | 328 | } else if (eax & 0x40000000) { |
eccfed42 | 329 | tjmax = tjmax_ee; |
118a8871 | 330 | } |
708a62bc | 331 | } else if (tjmax == 100000) { |
4cc45275 GR |
332 | /* |
333 | * If we don't use msr EE it means we are desktop CPU | |
334 | * (with exeception of Atom) | |
335 | */ | |
118a8871 RM |
336 | dev_warn(dev, "Using relative temperature scale!\n"); |
337 | } | |
338 | ||
339 | return tjmax; | |
340 | } | |
341 | ||
1c2faa22 GR |
342 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
343 | { | |
344 | u8 model = c->x86_model; | |
345 | ||
346 | return model > 0xe && | |
347 | model != 0x1c && | |
348 | model != 0x26 && | |
349 | model != 0x27 && | |
350 | model != 0x35 && | |
351 | model != 0x36; | |
352 | } | |
353 | ||
d23e2ae1 | 354 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 355 | { |
a321cedb CE |
356 | int err; |
357 | u32 eax, edx; | |
358 | u32 val; | |
359 | ||
4cc45275 GR |
360 | /* |
361 | * A new feature of current Intel(R) processors, the | |
362 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
363 | */ | |
a321cedb CE |
364 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
365 | if (err) { | |
1c2faa22 | 366 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 367 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 368 | } else { |
c0940e95 | 369 | val = (eax >> 16) & 0xff; |
a321cedb CE |
370 | /* |
371 | * If the TjMax is not plausible, an assumption | |
372 | * will be used | |
373 | */ | |
c0940e95 | 374 | if (val) { |
6bf9e9b0 | 375 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
376 | return val * 1000; |
377 | } | |
378 | } | |
379 | ||
a45a8c85 JD |
380 | if (force_tjmax) { |
381 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
382 | force_tjmax); | |
383 | return force_tjmax * 1000; | |
384 | } | |
385 | ||
a321cedb CE |
386 | /* |
387 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 388 | * NOTE: the calculated value may not be correct. |
a321cedb | 389 | */ |
4f5f71a7 | 390 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
391 | } |
392 | ||
d23e2ae1 PG |
393 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
394 | int attr_no) | |
199e0de7 | 395 | { |
1075305d | 396 | int i; |
e3204ed3 | 397 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 398 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 399 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 400 | show_ttarget }; |
1055b5f9 RV |
401 | static const char *const suffixes[TOTAL_ATTRS] = { |
402 | "label", "crit_alarm", "input", "crit", "max" | |
403 | }; | |
199e0de7 | 404 | |
c814a4c7 | 405 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
406 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
407 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 408 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 D |
409 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
410 | tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO; | |
411 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; | |
199e0de7 | 412 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 413 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 414 | } |
1075305d GR |
415 | tdata->attr_group.attrs = tdata->attrs; |
416 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
417 | } |
418 | ||
199e0de7 | 419 | |
d23e2ae1 | 420 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 421 | { |
0eb9782a | 422 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 423 | |
199e0de7 D |
424 | /* |
425 | * Check if we have problem with errata AE18 of Core processors: | |
426 | * Readings might stop update when processor visited too deep sleep, | |
427 | * fixed for stepping D0 (6EC). | |
428 | */ | |
ca8bc8dc | 429 | if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) { |
b55f3757 | 430 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 431 | return -ENODEV; |
67f363b1 | 432 | } |
199e0de7 D |
433 | return 0; |
434 | } | |
435 | ||
d23e2ae1 | 436 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 437 | { |
71266846 | 438 | int pkgid = topology_logical_package_id(cpu); |
199e0de7 | 439 | |
71266846 TG |
440 | if (pkgid >= 0 && pkgid < max_packages) |
441 | return pkg_devices[pkgid]; | |
199e0de7 D |
442 | return NULL; |
443 | } | |
444 | ||
d23e2ae1 | 445 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
446 | { |
447 | struct temp_data *tdata; | |
448 | ||
449 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
450 | if (!tdata) | |
451 | return NULL; | |
452 | ||
453 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
454 | MSR_IA32_THERM_STATUS; | |
455 | tdata->is_pkg_data = pkg_flag; | |
456 | tdata->cpu = cpu; | |
457 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
c814a4c7 | 458 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
459 | mutex_init(&tdata->update_lock); |
460 | return tdata; | |
461 | } | |
67f363b1 | 462 | |
d23e2ae1 PG |
463 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
464 | int pkg_flag) | |
199e0de7 D |
465 | { |
466 | struct temp_data *tdata; | |
2f1c3db0 | 467 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
468 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
469 | u32 eax, edx; | |
470 | int err, attr_no; | |
bebe4678 | 471 | |
a321cedb | 472 | /* |
199e0de7 D |
473 | * Find attr number for sysfs: |
474 | * We map the attr number to core id of the CPU | |
475 | * The attr number is always core id + 2 | |
476 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 477 | */ |
723f5734 | 478 | attr_no = pkg_flag ? PKG_SYSFS_ATTR_NO : TO_ATTR_NO(cpu); |
6369a288 | 479 | |
199e0de7 D |
480 | if (attr_no > MAX_CORE_DATA - 1) |
481 | return -ERANGE; | |
482 | ||
199e0de7 D |
483 | tdata = init_temp_data(cpu, pkg_flag); |
484 | if (!tdata) | |
485 | return -ENOMEM; | |
bebe4678 | 486 | |
199e0de7 D |
487 | /* Test if we can access the status register */ |
488 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
489 | if (err) | |
490 | goto exit_free; | |
491 | ||
492 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 493 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 494 | |
c814a4c7 | 495 | /* |
f4af6fd6 GR |
496 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
497 | * The target temperature is available on older CPUs but not in this | |
498 | * register. Atoms don't have the register at all. | |
c814a4c7 | 499 | */ |
f4af6fd6 GR |
500 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
501 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
502 | &eax, &edx); | |
503 | if (!err) { | |
504 | tdata->ttarget | |
505 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
506 | tdata->attr_size++; | |
507 | } | |
c814a4c7 D |
508 | } |
509 | ||
199e0de7 D |
510 | pdata->core_data[attr_no] = tdata; |
511 | ||
512 | /* Create sysfs interfaces */ | |
d72d19c2 | 513 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
514 | if (err) |
515 | goto exit_free; | |
bebe4678 RM |
516 | |
517 | return 0; | |
199e0de7 | 518 | exit_free: |
20ecb499 | 519 | pdata->core_data[attr_no] = NULL; |
199e0de7 D |
520 | kfree(tdata); |
521 | return err; | |
522 | } | |
523 | ||
4b138cf7 TG |
524 | static void |
525 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 526 | { |
4b138cf7 | 527 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
528 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
529 | } | |
530 | ||
4b138cf7 | 531 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 532 | { |
199e0de7 D |
533 | struct temp_data *tdata = pdata->core_data[indx]; |
534 | ||
535 | /* Remove the sysfs attributes */ | |
d72d19c2 | 536 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
537 | |
538 | kfree(pdata->core_data[indx]); | |
539 | pdata->core_data[indx] = NULL; | |
540 | } | |
541 | ||
6c931ae1 | 542 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 543 | { |
c503a811 | 544 | struct device *dev = &pdev->dev; |
199e0de7 | 545 | struct platform_data *pdata; |
bebe4678 | 546 | |
199e0de7 | 547 | /* Initialize the per-package data structures */ |
c503a811 | 548 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
549 | if (!pdata) |
550 | return -ENOMEM; | |
551 | ||
71266846 | 552 | pdata->pkg_id = pdev->id; |
199e0de7 D |
553 | platform_set_drvdata(pdev, pdata); |
554 | ||
d72d19c2 GR |
555 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
556 | pdata, NULL); | |
557 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
558 | } |
559 | ||
281dfd0b | 560 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 561 | { |
199e0de7 D |
562 | struct platform_data *pdata = platform_get_drvdata(pdev); |
563 | int i; | |
bebe4678 | 564 | |
199e0de7 D |
565 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
566 | if (pdata->core_data[i]) | |
d72d19c2 | 567 | coretemp_remove_core(pdata, i); |
199e0de7 | 568 | |
bebe4678 RM |
569 | return 0; |
570 | } | |
571 | ||
572 | static struct platform_driver coretemp_driver = { | |
573 | .driver = { | |
bebe4678 RM |
574 | .name = DRVNAME, |
575 | }, | |
576 | .probe = coretemp_probe, | |
9e5e9b7a | 577 | .remove = coretemp_remove, |
bebe4678 RM |
578 | }; |
579 | ||
71266846 | 580 | static struct platform_device *coretemp_device_add(unsigned int cpu) |
bebe4678 | 581 | { |
71266846 | 582 | int err, pkgid = topology_logical_package_id(cpu); |
bebe4678 | 583 | struct platform_device *pdev; |
d883b9f0 | 584 | |
71266846 TG |
585 | if (pkgid < 0) |
586 | return ERR_PTR(-ENOMEM); | |
d883b9f0 | 587 | |
71266846 TG |
588 | pdev = platform_device_alloc(DRVNAME, pkgid); |
589 | if (!pdev) | |
590 | return ERR_PTR(-ENOMEM); | |
bebe4678 RM |
591 | |
592 | err = platform_device_add(pdev); | |
593 | if (err) { | |
71266846 TG |
594 | platform_device_put(pdev); |
595 | return ERR_PTR(err); | |
bebe4678 RM |
596 | } |
597 | ||
71266846 TG |
598 | pkg_devices[pkgid] = pdev; |
599 | return pdev; | |
bebe4678 RM |
600 | } |
601 | ||
e00ca5df | 602 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 603 | { |
199e0de7 | 604 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
605 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
606 | struct platform_data *pdata; | |
199e0de7 | 607 | |
90b4f30b TG |
608 | /* |
609 | * Don't execute this on resume as the offline callback did | |
610 | * not get executed on suspend. | |
611 | */ | |
612 | if (cpuhp_tasks_frozen) | |
613 | return 0; | |
614 | ||
199e0de7 D |
615 | /* |
616 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
617 | * sensors. We check this bit only, all the early CPUs | |
618 | * without thermal sensors will be filtered out. | |
619 | */ | |
4ad33411 | 620 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 621 | return -ENODEV; |
199e0de7 D |
622 | |
623 | if (!pdev) { | |
0eb9782a JD |
624 | /* Check the microcode version of the CPU */ |
625 | if (chk_ucode_version(cpu)) | |
2195c31b | 626 | return -EINVAL; |
0eb9782a | 627 | |
199e0de7 D |
628 | /* |
629 | * Alright, we have DTS support. | |
630 | * We are bringing the _first_ core in this pkg | |
631 | * online. So, initialize per-pkg data structures and | |
632 | * then bring this core online. | |
633 | */ | |
71266846 TG |
634 | pdev = coretemp_device_add(cpu); |
635 | if (IS_ERR(pdev)) | |
636 | return PTR_ERR(pdev); | |
e1b370b6 | 637 | |
199e0de7 D |
638 | /* |
639 | * Check whether pkgtemp support is available. | |
640 | * If so, add interfaces for pkgtemp. | |
641 | */ | |
642 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 643 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 644 | } |
e1b370b6 TG |
645 | |
646 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 647 | /* |
e1b370b6 TG |
648 | * Check whether a thread sibling is already online. If not add the |
649 | * interface for this CPU core. | |
199e0de7 | 650 | */ |
e1b370b6 | 651 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 652 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
653 | |
654 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 655 | return 0; |
199e0de7 D |
656 | } |
657 | ||
e00ca5df | 658 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 659 | { |
199e0de7 | 660 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 661 | struct platform_data *pd; |
723f5734 | 662 | struct temp_data *tdata; |
e1b370b6 | 663 | int indx, target; |
199e0de7 | 664 | |
90b4f30b TG |
665 | /* |
666 | * Don't execute this on suspend as the device remove locks | |
667 | * up the machine. | |
668 | */ | |
669 | if (cpuhp_tasks_frozen) | |
670 | return 0; | |
671 | ||
199e0de7 D |
672 | /* If the physical CPU device does not exist, just return */ |
673 | if (!pdev) | |
e00ca5df | 674 | return 0; |
199e0de7 | 675 | |
b7048711 | 676 | /* The core id is too big, just return */ |
e1b370b6 | 677 | indx = TO_ATTR_NO(cpu); |
b7048711 | 678 | if (indx > MAX_CORE_DATA - 1) |
e00ca5df | 679 | return 0; |
b7048711 | 680 | |
e1b370b6 TG |
681 | pd = platform_get_drvdata(pdev); |
682 | tdata = pd->core_data[indx]; | |
683 | ||
684 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 685 | |
f4e0bcf0 | 686 | /* |
e1b370b6 TG |
687 | * If this is the last thread sibling, remove the CPU core |
688 | * interface, If there is still a sibling online, transfer the | |
689 | * target cpu of that core interface to it. | |
f4e0bcf0 | 690 | */ |
e1b370b6 TG |
691 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
692 | if (target >= nr_cpu_ids) { | |
693 | coretemp_remove_core(pd, indx); | |
694 | } else if (tdata && tdata->cpu == cpu) { | |
695 | mutex_lock(&tdata->update_lock); | |
696 | tdata->cpu = target; | |
697 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 698 | } |
e1b370b6 | 699 | |
199e0de7 | 700 | /* |
71266846 TG |
701 | * If all cores in this pkg are offline, remove the device. This |
702 | * will invoke the platform driver remove function, which cleans up | |
703 | * the rest. | |
199e0de7 | 704 | */ |
e1b370b6 | 705 | if (cpumask_empty(&pd->cpumask)) { |
71266846 TG |
706 | pkg_devices[topology_logical_package_id(cpu)] = NULL; |
707 | platform_device_unregister(pdev); | |
e00ca5df | 708 | return 0; |
723f5734 | 709 | } |
71266846 | 710 | |
723f5734 TG |
711 | /* |
712 | * Check whether this core is the target for the package | |
713 | * interface. We need to assign it to some other cpu. | |
714 | */ | |
e1b370b6 | 715 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 716 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 717 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
718 | mutex_lock(&tdata->update_lock); |
719 | tdata->cpu = target; | |
720 | mutex_unlock(&tdata->update_lock); | |
721 | } | |
e00ca5df | 722 | return 0; |
199e0de7 | 723 | } |
e273bd98 | 724 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
4ad33411 | 725 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM }, |
9b38096f AK |
726 | {} |
727 | }; | |
728 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
729 | ||
e00ca5df TG |
730 | static enum cpuhp_state coretemp_hp_online; |
731 | ||
bebe4678 RM |
732 | static int __init coretemp_init(void) |
733 | { | |
e00ca5df | 734 | int err; |
bebe4678 | 735 | |
9b38096f AK |
736 | /* |
737 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
738 | * sensors. We check this bit only, all the early CPUs | |
739 | * without thermal sensors will be filtered out. | |
740 | */ | |
741 | if (!x86_match_cpu(coretemp_ids)) | |
742 | return -ENODEV; | |
bebe4678 | 743 | |
71266846 TG |
744 | max_packages = topology_max_packages(); |
745 | pkg_devices = kzalloc(max_packages * sizeof(struct platform_device *), | |
746 | GFP_KERNEL); | |
747 | if (!pkg_devices) | |
748 | return -ENOMEM; | |
749 | ||
bebe4678 RM |
750 | err = platform_driver_register(&coretemp_driver); |
751 | if (err) | |
e00ca5df | 752 | return err; |
bebe4678 | 753 | |
e00ca5df TG |
754 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
755 | coretemp_cpu_online, coretemp_cpu_offline); | |
756 | if (err < 0) | |
2195c31b | 757 | goto outdrv; |
e00ca5df | 758 | coretemp_hp_online = err; |
bebe4678 RM |
759 | return 0; |
760 | ||
2195c31b | 761 | outdrv: |
bebe4678 | 762 | platform_driver_unregister(&coretemp_driver); |
71266846 | 763 | kfree(pkg_devices); |
bebe4678 RM |
764 | return err; |
765 | } | |
e00ca5df | 766 | module_init(coretemp_init) |
bebe4678 RM |
767 | |
768 | static void __exit coretemp_exit(void) | |
769 | { | |
e00ca5df | 770 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 | 771 | platform_driver_unregister(&coretemp_driver); |
71266846 | 772 | kfree(pkg_devices); |
bebe4678 | 773 | } |
e00ca5df | 774 | module_exit(coretemp_exit) |
bebe4678 RM |
775 | |
776 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
777 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
778 | MODULE_LICENSE("GPL"); |