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bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
4cc45275 | 37 | #include <linux/smp.h> |
a45a8c85 | 38 | #include <linux/moduleparam.h> |
14513ee6 | 39 | #include <linux/pci.h> |
bebe4678 RM |
40 | #include <asm/msr.h> |
41 | #include <asm/processor.h> | |
9b38096f | 42 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
43 | |
44 | #define DRVNAME "coretemp" | |
45 | ||
a45a8c85 JD |
46 | /* |
47 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
48 | * When set, it replaces the driver's suboptimal heuristic. | |
49 | */ | |
50 | static int force_tjmax; | |
51 | module_param_named(tjmax, force_tjmax, int, 0444); | |
52 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
53 | ||
723f5734 | 54 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 55 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 56 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 57 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 58 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 59 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
60 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
61 | ||
780affe0 GR |
62 | #define TO_PHYS_ID(cpu) (cpu_data(cpu).phys_proc_id) |
63 | #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) | |
141168c3 KW |
64 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) |
65 | ||
66 | #ifdef CONFIG_SMP | |
19a34eea BG |
67 | #define for_each_sibling(i, cpu) \ |
68 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 69 | #else |
bb74e8ca | 70 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 71 | #endif |
bebe4678 RM |
72 | |
73 | /* | |
199e0de7 D |
74 | * Per-Core Temperature Data |
75 | * @last_updated: The time when the current temperature value was updated | |
76 | * earlier (in jiffies). | |
77 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
78 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
79 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
80 | * from where the temperature values should be read. | |
c814a4c7 | 81 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
82 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
83 | * Otherwise, temp_data holds coretemp data. | |
84 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 85 | */ |
199e0de7 | 86 | struct temp_data { |
bebe4678 | 87 | int temp; |
6369a288 | 88 | int ttarget; |
199e0de7 D |
89 | int tjmax; |
90 | unsigned long last_updated; | |
91 | unsigned int cpu; | |
92 | u32 cpu_core_id; | |
93 | u32 status_reg; | |
c814a4c7 | 94 | int attr_size; |
199e0de7 D |
95 | bool is_pkg_data; |
96 | bool valid; | |
c814a4c7 D |
97 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
98 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
99 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
100 | struct attribute_group attr_group; | |
199e0de7 | 101 | struct mutex update_lock; |
bebe4678 RM |
102 | }; |
103 | ||
199e0de7 D |
104 | /* Platform Data per Physical CPU */ |
105 | struct platform_data { | |
e1b370b6 TG |
106 | struct device *hwmon_dev; |
107 | u16 phys_proc_id; | |
108 | struct cpumask cpumask; | |
109 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
110 | struct device_attribute name_attr; |
111 | }; | |
bebe4678 | 112 | |
199e0de7 D |
113 | struct pdev_entry { |
114 | struct list_head list; | |
115 | struct platform_device *pdev; | |
199e0de7 | 116 | u16 phys_proc_id; |
199e0de7 D |
117 | }; |
118 | ||
119 | static LIST_HEAD(pdev_list); | |
120 | static DEFINE_MUTEX(pdev_list_mutex); | |
121 | ||
199e0de7 D |
122 | static ssize_t show_label(struct device *dev, |
123 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 124 | { |
bebe4678 | 125 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
126 | struct platform_data *pdata = dev_get_drvdata(dev); |
127 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
128 | ||
129 | if (tdata->is_pkg_data) | |
130 | return sprintf(buf, "Physical id %u\n", pdata->phys_proc_id); | |
bebe4678 | 131 | |
199e0de7 | 132 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
133 | } |
134 | ||
199e0de7 D |
135 | static ssize_t show_crit_alarm(struct device *dev, |
136 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 137 | { |
199e0de7 D |
138 | u32 eax, edx; |
139 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
140 | struct platform_data *pdata = dev_get_drvdata(dev); | |
141 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
142 | ||
723f5734 | 143 | mutex_lock(&tdata->update_lock); |
199e0de7 | 144 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); |
723f5734 | 145 | mutex_unlock(&tdata->update_lock); |
199e0de7 D |
146 | |
147 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
148 | } |
149 | ||
199e0de7 D |
150 | static ssize_t show_tjmax(struct device *dev, |
151 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
152 | { |
153 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 154 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 155 | |
199e0de7 | 156 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
157 | } |
158 | ||
199e0de7 D |
159 | static ssize_t show_ttarget(struct device *dev, |
160 | struct device_attribute *devattr, char *buf) | |
161 | { | |
162 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
163 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 164 | |
199e0de7 D |
165 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
166 | } | |
bebe4678 | 167 | |
199e0de7 D |
168 | static ssize_t show_temp(struct device *dev, |
169 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 170 | { |
199e0de7 D |
171 | u32 eax, edx; |
172 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
173 | struct platform_data *pdata = dev_get_drvdata(dev); | |
174 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 175 | |
199e0de7 | 176 | mutex_lock(&tdata->update_lock); |
bebe4678 | 177 | |
199e0de7 D |
178 | /* Check whether the time interval has elapsed */ |
179 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
180 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
bf6ea084 GR |
181 | /* |
182 | * Ignore the valid bit. In all observed cases the register | |
183 | * value is either low or zero if the valid bit is 0. | |
184 | * Return it instead of reporting an error which doesn't | |
185 | * really help at all. | |
186 | */ | |
187 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
188 | tdata->valid = 1; | |
199e0de7 | 189 | tdata->last_updated = jiffies; |
bebe4678 RM |
190 | } |
191 | ||
199e0de7 | 192 | mutex_unlock(&tdata->update_lock); |
bf6ea084 | 193 | return sprintf(buf, "%d\n", tdata->temp); |
bebe4678 RM |
194 | } |
195 | ||
14513ee6 GR |
196 | struct tjmax_pci { |
197 | unsigned int device; | |
198 | int tjmax; | |
199 | }; | |
200 | ||
201 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 202 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
203 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
204 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
205 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
206 | }; | |
207 | ||
41e58a1f GR |
208 | struct tjmax { |
209 | char const *id; | |
210 | int tjmax; | |
211 | }; | |
212 | ||
d23e2ae1 | 213 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
214 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
215 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
216 | }; |
217 | ||
2fa5222e GR |
218 | struct tjmax_model { |
219 | u8 model; | |
220 | u8 mask; | |
221 | int tjmax; | |
222 | }; | |
223 | ||
224 | #define ANY 0xff | |
225 | ||
d23e2ae1 | 226 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 227 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
228 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
229 | * Note: Also matches 230 and 330, | |
230 | * which are covered by tjmax_table | |
231 | */ | |
232 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
233 | * Note: TjMax for E6xxT is 110C, but CPU type | |
234 | * is undetectable by software | |
235 | */ | |
236 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
237 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
238 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
239 | * Also matches S12x0 (stepping 9), covered by | |
240 | * PCI table | |
241 | */ | |
2fa5222e GR |
242 | }; |
243 | ||
d23e2ae1 | 244 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
245 | { |
246 | /* The 100C is default for both mobile and non mobile CPUs */ | |
247 | ||
248 | int tjmax = 100000; | |
eccfed42 | 249 | int tjmax_ee = 85000; |
708a62bc | 250 | int usemsr_ee = 1; |
118a8871 RM |
251 | int err; |
252 | u32 eax, edx; | |
41e58a1f | 253 | int i; |
14513ee6 GR |
254 | struct pci_dev *host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
255 | ||
256 | /* | |
257 | * Explicit tjmax table entries override heuristics. | |
258 | * First try PCI host bridge IDs, followed by model ID strings | |
259 | * and model/stepping information. | |
260 | */ | |
261 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
262 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
263 | if (host_bridge->device == tjmax_pci_table[i].device) | |
264 | return tjmax_pci_table[i].tjmax; | |
265 | } | |
266 | } | |
41e58a1f | 267 | |
41e58a1f GR |
268 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
269 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
270 | return tjmax_table[i].tjmax; | |
271 | } | |
118a8871 | 272 | |
2fa5222e GR |
273 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
274 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
275 | if (c->x86_model == tm->model && | |
276 | (tm->mask == ANY || c->x86_mask == tm->mask)) | |
277 | return tm->tjmax; | |
72cbdddc | 278 | } |
1fe63ab4 | 279 | |
72cbdddc | 280 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 281 | |
72cbdddc | 282 | if (c->x86_model == 0xf && c->x86_mask < 4) |
5592906f | 283 | usemsr_ee = 0; |
708a62bc | 284 | |
4cc45275 | 285 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 286 | u8 platform_id; |
118a8871 | 287 | |
4cc45275 GR |
288 | /* |
289 | * Now we can detect the mobile CPU using Intel provided table | |
290 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
291 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
292 | */ | |
118a8871 RM |
293 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
294 | if (err) { | |
295 | dev_warn(dev, | |
296 | "Unable to access MSR 0x17, assuming desktop" | |
297 | " CPU\n"); | |
708a62bc | 298 | usemsr_ee = 0; |
eccfed42 | 299 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
300 | /* |
301 | * Trust bit 28 up to Penryn, I could not find any | |
302 | * documentation on that; if you happen to know | |
303 | * someone at Intel please ask | |
304 | */ | |
708a62bc | 305 | usemsr_ee = 0; |
eccfed42 RM |
306 | } else { |
307 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
308 | platform_id = (edx >> 18) & 0x7; | |
309 | ||
4cc45275 GR |
310 | /* |
311 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
312 | * (guesswork) | |
313 | */ | |
314 | if (c->x86_model == 0x17 && | |
315 | (platform_id == 5 || platform_id == 7)) { | |
316 | /* | |
317 | * If MSR EE bit is set, set it to 90 degrees C, | |
318 | * otherwise 105 degrees C | |
319 | */ | |
eccfed42 RM |
320 | tjmax_ee = 90000; |
321 | tjmax = 105000; | |
322 | } | |
118a8871 RM |
323 | } |
324 | } | |
325 | ||
708a62bc | 326 | if (usemsr_ee) { |
118a8871 RM |
327 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
328 | if (err) { | |
329 | dev_warn(dev, | |
330 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 331 | " at default\n"); |
118a8871 | 332 | } else if (eax & 0x40000000) { |
eccfed42 | 333 | tjmax = tjmax_ee; |
118a8871 | 334 | } |
708a62bc | 335 | } else if (tjmax == 100000) { |
4cc45275 GR |
336 | /* |
337 | * If we don't use msr EE it means we are desktop CPU | |
338 | * (with exeception of Atom) | |
339 | */ | |
118a8871 RM |
340 | dev_warn(dev, "Using relative temperature scale!\n"); |
341 | } | |
342 | ||
343 | return tjmax; | |
344 | } | |
345 | ||
1c2faa22 GR |
346 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
347 | { | |
348 | u8 model = c->x86_model; | |
349 | ||
350 | return model > 0xe && | |
351 | model != 0x1c && | |
352 | model != 0x26 && | |
353 | model != 0x27 && | |
354 | model != 0x35 && | |
355 | model != 0x36; | |
356 | } | |
357 | ||
d23e2ae1 | 358 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 359 | { |
a321cedb CE |
360 | int err; |
361 | u32 eax, edx; | |
362 | u32 val; | |
363 | ||
4cc45275 GR |
364 | /* |
365 | * A new feature of current Intel(R) processors, the | |
366 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
367 | */ | |
a321cedb CE |
368 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
369 | if (err) { | |
1c2faa22 | 370 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 371 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 372 | } else { |
c0940e95 | 373 | val = (eax >> 16) & 0xff; |
a321cedb CE |
374 | /* |
375 | * If the TjMax is not plausible, an assumption | |
376 | * will be used | |
377 | */ | |
c0940e95 | 378 | if (val) { |
6bf9e9b0 | 379 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
380 | return val * 1000; |
381 | } | |
382 | } | |
383 | ||
a45a8c85 JD |
384 | if (force_tjmax) { |
385 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
386 | force_tjmax); | |
387 | return force_tjmax * 1000; | |
388 | } | |
389 | ||
a321cedb CE |
390 | /* |
391 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 392 | * NOTE: the calculated value may not be correct. |
a321cedb | 393 | */ |
4f5f71a7 | 394 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
395 | } |
396 | ||
d23e2ae1 PG |
397 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
398 | int attr_no) | |
199e0de7 | 399 | { |
1075305d | 400 | int i; |
e3204ed3 | 401 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 402 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 403 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 404 | show_ttarget }; |
1055b5f9 RV |
405 | static const char *const suffixes[TOTAL_ATTRS] = { |
406 | "label", "crit_alarm", "input", "crit", "max" | |
407 | }; | |
199e0de7 | 408 | |
c814a4c7 | 409 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
410 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
411 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 412 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 D |
413 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
414 | tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO; | |
415 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; | |
199e0de7 | 416 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 417 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 418 | } |
1075305d GR |
419 | tdata->attr_group.attrs = tdata->attrs; |
420 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
421 | } |
422 | ||
199e0de7 | 423 | |
d23e2ae1 | 424 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 425 | { |
0eb9782a | 426 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 427 | |
199e0de7 D |
428 | /* |
429 | * Check if we have problem with errata AE18 of Core processors: | |
430 | * Readings might stop update when processor visited too deep sleep, | |
431 | * fixed for stepping D0 (6EC). | |
432 | */ | |
ca8bc8dc | 433 | if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) { |
b55f3757 | 434 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 435 | return -ENODEV; |
67f363b1 | 436 | } |
199e0de7 D |
437 | return 0; |
438 | } | |
439 | ||
d23e2ae1 | 440 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 D |
441 | { |
442 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
443 | struct pdev_entry *p; | |
444 | ||
445 | mutex_lock(&pdev_list_mutex); | |
446 | ||
447 | list_for_each_entry(p, &pdev_list, list) | |
448 | if (p->phys_proc_id == phys_proc_id) { | |
449 | mutex_unlock(&pdev_list_mutex); | |
450 | return p->pdev; | |
451 | } | |
452 | ||
453 | mutex_unlock(&pdev_list_mutex); | |
454 | return NULL; | |
455 | } | |
456 | ||
d23e2ae1 | 457 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
458 | { |
459 | struct temp_data *tdata; | |
460 | ||
461 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
462 | if (!tdata) | |
463 | return NULL; | |
464 | ||
465 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
466 | MSR_IA32_THERM_STATUS; | |
467 | tdata->is_pkg_data = pkg_flag; | |
468 | tdata->cpu = cpu; | |
469 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
c814a4c7 | 470 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
471 | mutex_init(&tdata->update_lock); |
472 | return tdata; | |
473 | } | |
67f363b1 | 474 | |
d23e2ae1 PG |
475 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
476 | int pkg_flag) | |
199e0de7 D |
477 | { |
478 | struct temp_data *tdata; | |
2f1c3db0 | 479 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
480 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
481 | u32 eax, edx; | |
482 | int err, attr_no; | |
bebe4678 | 483 | |
a321cedb | 484 | /* |
199e0de7 D |
485 | * Find attr number for sysfs: |
486 | * We map the attr number to core id of the CPU | |
487 | * The attr number is always core id + 2 | |
488 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 489 | */ |
723f5734 | 490 | attr_no = pkg_flag ? PKG_SYSFS_ATTR_NO : TO_ATTR_NO(cpu); |
6369a288 | 491 | |
199e0de7 D |
492 | if (attr_no > MAX_CORE_DATA - 1) |
493 | return -ERANGE; | |
494 | ||
199e0de7 D |
495 | tdata = init_temp_data(cpu, pkg_flag); |
496 | if (!tdata) | |
497 | return -ENOMEM; | |
bebe4678 | 498 | |
199e0de7 D |
499 | /* Test if we can access the status register */ |
500 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
501 | if (err) | |
502 | goto exit_free; | |
503 | ||
504 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 505 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 506 | |
c814a4c7 | 507 | /* |
f4af6fd6 GR |
508 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
509 | * The target temperature is available on older CPUs but not in this | |
510 | * register. Atoms don't have the register at all. | |
c814a4c7 | 511 | */ |
f4af6fd6 GR |
512 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
513 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
514 | &eax, &edx); | |
515 | if (!err) { | |
516 | tdata->ttarget | |
517 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
518 | tdata->attr_size++; | |
519 | } | |
c814a4c7 D |
520 | } |
521 | ||
199e0de7 D |
522 | pdata->core_data[attr_no] = tdata; |
523 | ||
524 | /* Create sysfs interfaces */ | |
d72d19c2 | 525 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
526 | if (err) |
527 | goto exit_free; | |
bebe4678 RM |
528 | |
529 | return 0; | |
199e0de7 | 530 | exit_free: |
20ecb499 | 531 | pdata->core_data[attr_no] = NULL; |
199e0de7 D |
532 | kfree(tdata); |
533 | return err; | |
534 | } | |
535 | ||
4b138cf7 TG |
536 | static void |
537 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 538 | { |
4b138cf7 | 539 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
540 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
541 | } | |
542 | ||
4b138cf7 | 543 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 544 | { |
199e0de7 D |
545 | struct temp_data *tdata = pdata->core_data[indx]; |
546 | ||
547 | /* Remove the sysfs attributes */ | |
d72d19c2 | 548 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
549 | |
550 | kfree(pdata->core_data[indx]); | |
551 | pdata->core_data[indx] = NULL; | |
552 | } | |
553 | ||
6c931ae1 | 554 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 555 | { |
c503a811 | 556 | struct device *dev = &pdev->dev; |
199e0de7 | 557 | struct platform_data *pdata; |
bebe4678 | 558 | |
199e0de7 | 559 | /* Initialize the per-package data structures */ |
c503a811 | 560 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
561 | if (!pdata) |
562 | return -ENOMEM; | |
563 | ||
b3a242a6 | 564 | pdata->phys_proc_id = pdev->id; |
199e0de7 D |
565 | platform_set_drvdata(pdev, pdata); |
566 | ||
d72d19c2 GR |
567 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
568 | pdata, NULL); | |
569 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
570 | } |
571 | ||
281dfd0b | 572 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 573 | { |
199e0de7 D |
574 | struct platform_data *pdata = platform_get_drvdata(pdev); |
575 | int i; | |
bebe4678 | 576 | |
199e0de7 D |
577 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
578 | if (pdata->core_data[i]) | |
d72d19c2 | 579 | coretemp_remove_core(pdata, i); |
199e0de7 | 580 | |
bebe4678 RM |
581 | return 0; |
582 | } | |
583 | ||
584 | static struct platform_driver coretemp_driver = { | |
585 | .driver = { | |
bebe4678 RM |
586 | .name = DRVNAME, |
587 | }, | |
588 | .probe = coretemp_probe, | |
9e5e9b7a | 589 | .remove = coretemp_remove, |
bebe4678 RM |
590 | }; |
591 | ||
d23e2ae1 | 592 | static int coretemp_device_add(unsigned int cpu) |
bebe4678 RM |
593 | { |
594 | int err; | |
595 | struct platform_device *pdev; | |
596 | struct pdev_entry *pdev_entry; | |
d883b9f0 JD |
597 | |
598 | mutex_lock(&pdev_list_mutex); | |
599 | ||
b3a242a6 | 600 | pdev = platform_device_alloc(DRVNAME, TO_PHYS_ID(cpu)); |
bebe4678 RM |
601 | if (!pdev) { |
602 | err = -ENOMEM; | |
f8bb8925 | 603 | pr_err("Device allocation failed\n"); |
bebe4678 RM |
604 | goto exit; |
605 | } | |
606 | ||
607 | pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL); | |
608 | if (!pdev_entry) { | |
609 | err = -ENOMEM; | |
610 | goto exit_device_put; | |
611 | } | |
612 | ||
613 | err = platform_device_add(pdev); | |
614 | if (err) { | |
f8bb8925 | 615 | pr_err("Device addition failed (%d)\n", err); |
bebe4678 RM |
616 | goto exit_device_free; |
617 | } | |
618 | ||
619 | pdev_entry->pdev = pdev; | |
0eb9782a | 620 | pdev_entry->phys_proc_id = pdev->id; |
199e0de7 | 621 | |
bebe4678 RM |
622 | list_add_tail(&pdev_entry->list, &pdev_list); |
623 | mutex_unlock(&pdev_list_mutex); | |
624 | ||
625 | return 0; | |
626 | ||
627 | exit_device_free: | |
628 | kfree(pdev_entry); | |
629 | exit_device_put: | |
630 | platform_device_put(pdev); | |
631 | exit: | |
d883b9f0 | 632 | mutex_unlock(&pdev_list_mutex); |
bebe4678 RM |
633 | return err; |
634 | } | |
635 | ||
d23e2ae1 | 636 | static void coretemp_device_remove(unsigned int cpu) |
bebe4678 | 637 | { |
199e0de7 D |
638 | struct pdev_entry *p, *n; |
639 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
e40cc4bd | 640 | |
bebe4678 | 641 | mutex_lock(&pdev_list_mutex); |
199e0de7 D |
642 | list_for_each_entry_safe(p, n, &pdev_list, list) { |
643 | if (p->phys_proc_id != phys_proc_id) | |
e40cc4bd | 644 | continue; |
e40cc4bd JB |
645 | platform_device_unregister(p->pdev); |
646 | list_del(&p->list); | |
e40cc4bd | 647 | kfree(p); |
bebe4678 RM |
648 | } |
649 | mutex_unlock(&pdev_list_mutex); | |
650 | } | |
651 | ||
e00ca5df | 652 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 653 | { |
199e0de7 | 654 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
655 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
656 | struct platform_data *pdata; | |
199e0de7 D |
657 | int err; |
658 | ||
659 | /* | |
660 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
661 | * sensors. We check this bit only, all the early CPUs | |
662 | * without thermal sensors will be filtered out. | |
663 | */ | |
4ad33411 | 664 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 665 | return -ENODEV; |
199e0de7 D |
666 | |
667 | if (!pdev) { | |
0eb9782a JD |
668 | /* Check the microcode version of the CPU */ |
669 | if (chk_ucode_version(cpu)) | |
2195c31b | 670 | return -EINVAL; |
0eb9782a | 671 | |
199e0de7 D |
672 | /* |
673 | * Alright, we have DTS support. | |
674 | * We are bringing the _first_ core in this pkg | |
675 | * online. So, initialize per-pkg data structures and | |
676 | * then bring this core online. | |
677 | */ | |
678 | err = coretemp_device_add(cpu); | |
679 | if (err) | |
2195c31b | 680 | return err; |
e1b370b6 TG |
681 | |
682 | pdev = coretemp_get_pdev(cpu); | |
199e0de7 D |
683 | /* |
684 | * Check whether pkgtemp support is available. | |
685 | * If so, add interfaces for pkgtemp. | |
686 | */ | |
687 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 688 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 689 | } |
e1b370b6 TG |
690 | |
691 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 692 | /* |
e1b370b6 TG |
693 | * Check whether a thread sibling is already online. If not add the |
694 | * interface for this CPU core. | |
199e0de7 | 695 | */ |
e1b370b6 | 696 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 697 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
698 | |
699 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 700 | return 0; |
199e0de7 D |
701 | } |
702 | ||
e00ca5df | 703 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 704 | { |
199e0de7 | 705 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 706 | struct platform_data *pd; |
723f5734 | 707 | struct temp_data *tdata; |
e1b370b6 | 708 | int indx, target; |
199e0de7 D |
709 | |
710 | /* If the physical CPU device does not exist, just return */ | |
711 | if (!pdev) | |
e00ca5df | 712 | return 0; |
199e0de7 | 713 | |
b7048711 | 714 | /* The core id is too big, just return */ |
e1b370b6 | 715 | indx = TO_ATTR_NO(cpu); |
b7048711 | 716 | if (indx > MAX_CORE_DATA - 1) |
e00ca5df | 717 | return 0; |
b7048711 | 718 | |
e1b370b6 TG |
719 | pd = platform_get_drvdata(pdev); |
720 | tdata = pd->core_data[indx]; | |
721 | ||
722 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 723 | |
f4e0bcf0 | 724 | /* |
e1b370b6 TG |
725 | * If this is the last thread sibling, remove the CPU core |
726 | * interface, If there is still a sibling online, transfer the | |
727 | * target cpu of that core interface to it. | |
f4e0bcf0 | 728 | */ |
e1b370b6 TG |
729 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
730 | if (target >= nr_cpu_ids) { | |
731 | coretemp_remove_core(pd, indx); | |
732 | } else if (tdata && tdata->cpu == cpu) { | |
733 | mutex_lock(&tdata->update_lock); | |
734 | tdata->cpu = target; | |
735 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 736 | } |
e1b370b6 | 737 | |
199e0de7 D |
738 | /* |
739 | * If all cores in this pkg are offline, remove the device. | |
740 | * coretemp_device_remove calls unregister_platform_device, | |
741 | * which in turn calls coretemp_remove. This removes the | |
742 | * pkgtemp entry and does other clean ups. | |
743 | */ | |
e1b370b6 | 744 | if (cpumask_empty(&pd->cpumask)) { |
199e0de7 | 745 | coretemp_device_remove(cpu); |
e00ca5df | 746 | return 0; |
723f5734 TG |
747 | } |
748 | /* | |
749 | * Check whether this core is the target for the package | |
750 | * interface. We need to assign it to some other cpu. | |
751 | */ | |
e1b370b6 | 752 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 753 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 754 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
755 | mutex_lock(&tdata->update_lock); |
756 | tdata->cpu = target; | |
757 | mutex_unlock(&tdata->update_lock); | |
758 | } | |
e00ca5df | 759 | return 0; |
199e0de7 | 760 | } |
e273bd98 | 761 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
4ad33411 | 762 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM }, |
9b38096f AK |
763 | {} |
764 | }; | |
765 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
766 | ||
e00ca5df TG |
767 | static enum cpuhp_state coretemp_hp_online; |
768 | ||
bebe4678 RM |
769 | static int __init coretemp_init(void) |
770 | { | |
e00ca5df | 771 | int err; |
bebe4678 | 772 | |
9b38096f AK |
773 | /* |
774 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
775 | * sensors. We check this bit only, all the early CPUs | |
776 | * without thermal sensors will be filtered out. | |
777 | */ | |
778 | if (!x86_match_cpu(coretemp_ids)) | |
779 | return -ENODEV; | |
bebe4678 RM |
780 | |
781 | err = platform_driver_register(&coretemp_driver); | |
782 | if (err) | |
e00ca5df | 783 | return err; |
bebe4678 | 784 | |
e00ca5df TG |
785 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
786 | coretemp_cpu_online, coretemp_cpu_offline); | |
787 | if (err < 0) | |
2195c31b | 788 | goto outdrv; |
e00ca5df | 789 | coretemp_hp_online = err; |
bebe4678 RM |
790 | return 0; |
791 | ||
2195c31b | 792 | outdrv: |
bebe4678 | 793 | platform_driver_unregister(&coretemp_driver); |
bebe4678 RM |
794 | return err; |
795 | } | |
e00ca5df | 796 | module_init(coretemp_init) |
bebe4678 RM |
797 | |
798 | static void __exit coretemp_exit(void) | |
799 | { | |
e00ca5df | 800 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 RM |
801 | platform_driver_unregister(&coretemp_driver); |
802 | } | |
e00ca5df | 803 | module_exit(coretemp_exit) |
bebe4678 RM |
804 | |
805 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
806 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
807 | MODULE_LICENSE("GPL"); |