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935912c5 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
bebe4678 RM |
2 | /* |
3 | * coretemp.c - Linux kernel module for hardware monitoring | |
4 | * | |
5 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
6 | * | |
7 | * Inspired from many hwmon drivers | |
bebe4678 RM |
8 | */ |
9 | ||
f8bb8925 JP |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
bebe4678 | 12 | #include <linux/module.h> |
bebe4678 RM |
13 | #include <linux/init.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/hwmon.h> | |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/hwmon-sysfs.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/mutex.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/cpu.h> | |
4cc45275 | 24 | #include <linux/smp.h> |
a45a8c85 | 25 | #include <linux/moduleparam.h> |
14513ee6 | 26 | #include <linux/pci.h> |
bebe4678 RM |
27 | #include <asm/msr.h> |
28 | #include <asm/processor.h> | |
9b38096f | 29 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
30 | |
31 | #define DRVNAME "coretemp" | |
32 | ||
a45a8c85 JD |
33 | /* |
34 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
35 | * When set, it replaces the driver's suboptimal heuristic. | |
36 | */ | |
37 | static int force_tjmax; | |
38 | module_param_named(tjmax, force_tjmax, int, 0444); | |
39 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
40 | ||
723f5734 | 41 | #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ |
199e0de7 | 42 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
cc904f9c | 43 | #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ |
3f9aec76 | 44 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 45 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 46 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
47 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
48 | ||
141168c3 | 49 | #ifdef CONFIG_SMP |
19a34eea BG |
50 | #define for_each_sibling(i, cpu) \ |
51 | for_each_cpu(i, topology_sibling_cpumask(cpu)) | |
199e0de7 | 52 | #else |
bb74e8ca | 53 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 54 | #endif |
bebe4678 RM |
55 | |
56 | /* | |
199e0de7 D |
57 | * Per-Core Temperature Data |
58 | * @last_updated: The time when the current temperature value was updated | |
59 | * earlier (in jiffies). | |
60 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
61 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
62 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
63 | * from where the temperature values should be read. | |
c814a4c7 | 64 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
65 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
66 | * Otherwise, temp_data holds coretemp data. | |
bebe4678 | 67 | */ |
199e0de7 | 68 | struct temp_data { |
bebe4678 | 69 | int temp; |
6369a288 | 70 | int ttarget; |
199e0de7 D |
71 | int tjmax; |
72 | unsigned long last_updated; | |
73 | unsigned int cpu; | |
74 | u32 cpu_core_id; | |
75 | u32 status_reg; | |
c814a4c7 | 76 | int attr_size; |
199e0de7 | 77 | bool is_pkg_data; |
c814a4c7 D |
78 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
79 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
80 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
81 | struct attribute_group attr_group; | |
199e0de7 | 82 | struct mutex update_lock; |
bebe4678 RM |
83 | }; |
84 | ||
199e0de7 D |
85 | /* Platform Data per Physical CPU */ |
86 | struct platform_data { | |
e1b370b6 | 87 | struct device *hwmon_dev; |
71266846 | 88 | u16 pkg_id; |
7108b80a ZR |
89 | u16 cpu_map[NUM_REAL_CORES]; |
90 | struct ida ida; | |
e1b370b6 TG |
91 | struct cpumask cpumask; |
92 | struct temp_data *core_data[MAX_CORE_DATA]; | |
199e0de7 D |
93 | struct device_attribute name_attr; |
94 | }; | |
bebe4678 | 95 | |
14513ee6 GR |
96 | struct tjmax_pci { |
97 | unsigned int device; | |
98 | int tjmax; | |
99 | }; | |
100 | ||
101 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 102 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
103 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
104 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
105 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
106 | }; | |
107 | ||
41e58a1f GR |
108 | struct tjmax { |
109 | char const *id; | |
110 | int tjmax; | |
111 | }; | |
112 | ||
d23e2ae1 | 113 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
114 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
115 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
116 | }; |
117 | ||
2fa5222e GR |
118 | struct tjmax_model { |
119 | u8 model; | |
120 | u8 mask; | |
121 | int tjmax; | |
122 | }; | |
123 | ||
124 | #define ANY 0xff | |
125 | ||
d23e2ae1 | 126 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 127 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
128 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
129 | * Note: Also matches 230 and 330, | |
130 | * which are covered by tjmax_table | |
131 | */ | |
132 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
133 | * Note: TjMax for E6xxT is 110C, but CPU type | |
134 | * is undetectable by software | |
135 | */ | |
136 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
137 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
138 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
139 | * Also matches S12x0 (stepping 9), covered by | |
140 | * PCI table | |
141 | */ | |
2fa5222e GR |
142 | }; |
143 | ||
d23e2ae1 | 144 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
145 | { |
146 | /* The 100C is default for both mobile and non mobile CPUs */ | |
147 | ||
148 | int tjmax = 100000; | |
eccfed42 | 149 | int tjmax_ee = 85000; |
708a62bc | 150 | int usemsr_ee = 1; |
118a8871 RM |
151 | int err; |
152 | u32 eax, edx; | |
41e58a1f | 153 | int i; |
b9ccff23 SK |
154 | u16 devfn = PCI_DEVFN(0, 0); |
155 | struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn); | |
14513ee6 GR |
156 | |
157 | /* | |
158 | * Explicit tjmax table entries override heuristics. | |
159 | * First try PCI host bridge IDs, followed by model ID strings | |
160 | * and model/stepping information. | |
161 | */ | |
162 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
163 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
7dec1453 YY |
164 | if (host_bridge->device == tjmax_pci_table[i].device) { |
165 | pci_dev_put(host_bridge); | |
14513ee6 | 166 | return tjmax_pci_table[i].tjmax; |
7dec1453 | 167 | } |
14513ee6 GR |
168 | } |
169 | } | |
7dec1453 | 170 | pci_dev_put(host_bridge); |
41e58a1f | 171 | |
41e58a1f GR |
172 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
173 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
174 | return tjmax_table[i].tjmax; | |
175 | } | |
118a8871 | 176 | |
2fa5222e GR |
177 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
178 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
179 | if (c->x86_model == tm->model && | |
b399151c | 180 | (tm->mask == ANY || c->x86_stepping == tm->mask)) |
2fa5222e | 181 | return tm->tjmax; |
72cbdddc | 182 | } |
1fe63ab4 | 183 | |
72cbdddc | 184 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 185 | |
b399151c | 186 | if (c->x86_model == 0xf && c->x86_stepping < 4) |
5592906f | 187 | usemsr_ee = 0; |
708a62bc | 188 | |
4cc45275 | 189 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 190 | u8 platform_id; |
118a8871 | 191 | |
4cc45275 GR |
192 | /* |
193 | * Now we can detect the mobile CPU using Intel provided table | |
194 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
195 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
196 | */ | |
118a8871 RM |
197 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
198 | if (err) { | |
199 | dev_warn(dev, | |
200 | "Unable to access MSR 0x17, assuming desktop" | |
201 | " CPU\n"); | |
708a62bc | 202 | usemsr_ee = 0; |
eccfed42 | 203 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
204 | /* |
205 | * Trust bit 28 up to Penryn, I could not find any | |
206 | * documentation on that; if you happen to know | |
207 | * someone at Intel please ask | |
208 | */ | |
708a62bc | 209 | usemsr_ee = 0; |
eccfed42 RM |
210 | } else { |
211 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
212 | platform_id = (edx >> 18) & 0x7; | |
213 | ||
4cc45275 GR |
214 | /* |
215 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
216 | * (guesswork) | |
217 | */ | |
218 | if (c->x86_model == 0x17 && | |
219 | (platform_id == 5 || platform_id == 7)) { | |
220 | /* | |
221 | * If MSR EE bit is set, set it to 90 degrees C, | |
222 | * otherwise 105 degrees C | |
223 | */ | |
eccfed42 RM |
224 | tjmax_ee = 90000; |
225 | tjmax = 105000; | |
226 | } | |
118a8871 RM |
227 | } |
228 | } | |
229 | ||
708a62bc | 230 | if (usemsr_ee) { |
118a8871 RM |
231 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
232 | if (err) { | |
233 | dev_warn(dev, | |
234 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 235 | " at default\n"); |
118a8871 | 236 | } else if (eax & 0x40000000) { |
eccfed42 | 237 | tjmax = tjmax_ee; |
118a8871 | 238 | } |
708a62bc | 239 | } else if (tjmax == 100000) { |
4cc45275 GR |
240 | /* |
241 | * If we don't use msr EE it means we are desktop CPU | |
242 | * (with exeception of Atom) | |
243 | */ | |
118a8871 RM |
244 | dev_warn(dev, "Using relative temperature scale!\n"); |
245 | } | |
246 | ||
247 | return tjmax; | |
248 | } | |
249 | ||
1c2faa22 GR |
250 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
251 | { | |
252 | u8 model = c->x86_model; | |
253 | ||
254 | return model > 0xe && | |
255 | model != 0x1c && | |
256 | model != 0x26 && | |
257 | model != 0x27 && | |
258 | model != 0x35 && | |
259 | model != 0x36; | |
260 | } | |
261 | ||
d23e2ae1 | 262 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 263 | { |
a321cedb CE |
264 | int err; |
265 | u32 eax, edx; | |
266 | u32 val; | |
267 | ||
4cc45275 GR |
268 | /* |
269 | * A new feature of current Intel(R) processors, the | |
270 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
271 | */ | |
a321cedb CE |
272 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
273 | if (err) { | |
1c2faa22 | 274 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 275 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 276 | } else { |
c0940e95 | 277 | val = (eax >> 16) & 0xff; |
a321cedb CE |
278 | /* |
279 | * If the TjMax is not plausible, an assumption | |
280 | * will be used | |
281 | */ | |
c0940e95 | 282 | if (val) { |
6bf9e9b0 | 283 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
284 | return val * 1000; |
285 | } | |
286 | } | |
287 | ||
a45a8c85 JD |
288 | if (force_tjmax) { |
289 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
290 | force_tjmax); | |
291 | return force_tjmax * 1000; | |
292 | } | |
293 | ||
a321cedb CE |
294 | /* |
295 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 296 | * NOTE: the calculated value may not be correct. |
a321cedb | 297 | */ |
4f5f71a7 | 298 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
299 | } |
300 | ||
2bc0e6d0 ZR |
301 | /* Keep track of how many zone pointers we allocated in init() */ |
302 | static int max_zones __read_mostly; | |
303 | /* Array of zone pointers. Serialized by cpu hotplug lock */ | |
304 | static struct platform_device **zone_devices; | |
305 | ||
306 | static ssize_t show_label(struct device *dev, | |
307 | struct device_attribute *devattr, char *buf) | |
308 | { | |
309 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
310 | struct platform_data *pdata = dev_get_drvdata(dev); | |
311 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
312 | ||
313 | if (tdata->is_pkg_data) | |
314 | return sprintf(buf, "Package id %u\n", pdata->pkg_id); | |
315 | ||
316 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); | |
317 | } | |
318 | ||
319 | static ssize_t show_crit_alarm(struct device *dev, | |
320 | struct device_attribute *devattr, char *buf) | |
321 | { | |
322 | u32 eax, edx; | |
323 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
324 | struct platform_data *pdata = dev_get_drvdata(dev); | |
325 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
326 | ||
327 | mutex_lock(&tdata->update_lock); | |
328 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
329 | mutex_unlock(&tdata->update_lock); | |
330 | ||
331 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
332 | } | |
333 | ||
334 | static ssize_t show_tjmax(struct device *dev, | |
335 | struct device_attribute *devattr, char *buf) | |
336 | { | |
337 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
338 | struct platform_data *pdata = dev_get_drvdata(dev); | |
339 | ||
340 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); | |
341 | } | |
342 | ||
343 | static ssize_t show_ttarget(struct device *dev, | |
344 | struct device_attribute *devattr, char *buf) | |
345 | { | |
346 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
347 | struct platform_data *pdata = dev_get_drvdata(dev); | |
348 | ||
349 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); | |
350 | } | |
351 | ||
352 | static ssize_t show_temp(struct device *dev, | |
353 | struct device_attribute *devattr, char *buf) | |
354 | { | |
355 | u32 eax, edx; | |
356 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
357 | struct platform_data *pdata = dev_get_drvdata(dev); | |
358 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
359 | ||
360 | mutex_lock(&tdata->update_lock); | |
361 | ||
362 | /* Check whether the time interval has elapsed */ | |
363 | if (time_after(jiffies, tdata->last_updated + HZ)) { | |
364 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
365 | /* | |
366 | * Ignore the valid bit. In all observed cases the register | |
367 | * value is either low or zero if the valid bit is 0. | |
368 | * Return it instead of reporting an error which doesn't | |
369 | * really help at all. | |
370 | */ | |
371 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
372 | tdata->last_updated = jiffies; | |
373 | } | |
374 | ||
375 | mutex_unlock(&tdata->update_lock); | |
376 | return sprintf(buf, "%d\n", tdata->temp); | |
377 | } | |
378 | ||
d23e2ae1 PG |
379 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
380 | int attr_no) | |
199e0de7 | 381 | { |
1075305d | 382 | int i; |
e3204ed3 | 383 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 384 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 385 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 386 | show_ttarget }; |
1055b5f9 RV |
387 | static const char *const suffixes[TOTAL_ATTRS] = { |
388 | "label", "crit_alarm", "input", "crit", "max" | |
389 | }; | |
199e0de7 | 390 | |
c814a4c7 | 391 | for (i = 0; i < tdata->attr_size; i++) { |
1055b5f9 RV |
392 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, |
393 | "temp%d_%s", attr_no, suffixes[i]); | |
4258781a | 394 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 | 395 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
0cd709d0 | 396 | tdata->sd_attrs[i].dev_attr.attr.mode = 0444; |
199e0de7 | 397 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; |
199e0de7 | 398 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 399 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 400 | } |
1075305d GR |
401 | tdata->attr_group.attrs = tdata->attrs; |
402 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
403 | } |
404 | ||
199e0de7 | 405 | |
d23e2ae1 | 406 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 407 | { |
0eb9782a | 408 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 409 | |
199e0de7 D |
410 | /* |
411 | * Check if we have problem with errata AE18 of Core processors: | |
412 | * Readings might stop update when processor visited too deep sleep, | |
413 | * fixed for stepping D0 (6EC). | |
414 | */ | |
b399151c | 415 | if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) { |
b55f3757 | 416 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 417 | return -ENODEV; |
67f363b1 | 418 | } |
199e0de7 D |
419 | return 0; |
420 | } | |
421 | ||
d23e2ae1 | 422 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 | 423 | { |
835896a5 | 424 | int id = topology_logical_die_id(cpu); |
199e0de7 | 425 | |
835896a5 LB |
426 | if (id >= 0 && id < max_zones) |
427 | return zone_devices[id]; | |
199e0de7 D |
428 | return NULL; |
429 | } | |
430 | ||
d23e2ae1 | 431 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
432 | { |
433 | struct temp_data *tdata; | |
434 | ||
435 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
436 | if (!tdata) | |
437 | return NULL; | |
438 | ||
439 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
440 | MSR_IA32_THERM_STATUS; | |
441 | tdata->is_pkg_data = pkg_flag; | |
442 | tdata->cpu = cpu; | |
7108b80a | 443 | tdata->cpu_core_id = topology_core_id(cpu); |
c814a4c7 | 444 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
445 | mutex_init(&tdata->update_lock); |
446 | return tdata; | |
447 | } | |
67f363b1 | 448 | |
d23e2ae1 PG |
449 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
450 | int pkg_flag) | |
199e0de7 D |
451 | { |
452 | struct temp_data *tdata; | |
2f1c3db0 | 453 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
454 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
455 | u32 eax, edx; | |
7108b80a | 456 | int err, index, attr_no; |
bebe4678 | 457 | |
a321cedb | 458 | /* |
199e0de7 D |
459 | * Find attr number for sysfs: |
460 | * We map the attr number to core id of the CPU | |
461 | * The attr number is always core id + 2 | |
462 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 463 | */ |
7108b80a ZR |
464 | if (pkg_flag) { |
465 | attr_no = PKG_SYSFS_ATTR_NO; | |
466 | } else { | |
467 | index = ida_alloc(&pdata->ida, GFP_KERNEL); | |
468 | if (index < 0) | |
469 | return index; | |
470 | pdata->cpu_map[index] = topology_core_id(cpu); | |
471 | attr_no = index + BASE_SYSFS_ATTR_NO; | |
472 | } | |
6369a288 | 473 | |
7108b80a ZR |
474 | if (attr_no > MAX_CORE_DATA - 1) { |
475 | err = -ERANGE; | |
476 | goto ida_free; | |
477 | } | |
199e0de7 | 478 | |
199e0de7 | 479 | tdata = init_temp_data(cpu, pkg_flag); |
7108b80a ZR |
480 | if (!tdata) { |
481 | err = -ENOMEM; | |
482 | goto ida_free; | |
483 | } | |
bebe4678 | 484 | |
199e0de7 D |
485 | /* Test if we can access the status register */ |
486 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
487 | if (err) | |
488 | goto exit_free; | |
489 | ||
490 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 491 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 492 | |
c814a4c7 | 493 | /* |
f4af6fd6 GR |
494 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
495 | * The target temperature is available on older CPUs but not in this | |
496 | * register. Atoms don't have the register at all. | |
c814a4c7 | 497 | */ |
f4af6fd6 GR |
498 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
499 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
500 | &eax, &edx); | |
501 | if (!err) { | |
502 | tdata->ttarget | |
503 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
504 | tdata->attr_size++; | |
505 | } | |
c814a4c7 D |
506 | } |
507 | ||
199e0de7 D |
508 | pdata->core_data[attr_no] = tdata; |
509 | ||
510 | /* Create sysfs interfaces */ | |
d72d19c2 | 511 | err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no); |
199e0de7 D |
512 | if (err) |
513 | goto exit_free; | |
bebe4678 RM |
514 | |
515 | return 0; | |
199e0de7 | 516 | exit_free: |
20ecb499 | 517 | pdata->core_data[attr_no] = NULL; |
199e0de7 | 518 | kfree(tdata); |
7108b80a ZR |
519 | ida_free: |
520 | if (!pkg_flag) | |
521 | ida_free(&pdata->ida, index); | |
199e0de7 D |
522 | return err; |
523 | } | |
524 | ||
4b138cf7 TG |
525 | static void |
526 | coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag) | |
199e0de7 | 527 | { |
4b138cf7 | 528 | if (create_core_data(pdev, cpu, pkg_flag)) |
199e0de7 D |
529 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); |
530 | } | |
531 | ||
4b138cf7 | 532 | static void coretemp_remove_core(struct platform_data *pdata, int indx) |
199e0de7 | 533 | { |
199e0de7 D |
534 | struct temp_data *tdata = pdata->core_data[indx]; |
535 | ||
a89ff5f5 PA |
536 | /* if we errored on add then this is already gone */ |
537 | if (!tdata) | |
538 | return; | |
539 | ||
199e0de7 | 540 | /* Remove the sysfs attributes */ |
d72d19c2 | 541 | sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group); |
199e0de7 D |
542 | |
543 | kfree(pdata->core_data[indx]); | |
544 | pdata->core_data[indx] = NULL; | |
7108b80a ZR |
545 | |
546 | if (indx >= BASE_SYSFS_ATTR_NO) | |
547 | ida_free(&pdata->ida, indx - BASE_SYSFS_ATTR_NO); | |
199e0de7 D |
548 | } |
549 | ||
6c931ae1 | 550 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 551 | { |
c503a811 | 552 | struct device *dev = &pdev->dev; |
199e0de7 | 553 | struct platform_data *pdata; |
bebe4678 | 554 | |
835896a5 | 555 | /* Initialize the per-zone data structures */ |
c503a811 | 556 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
557 | if (!pdata) |
558 | return -ENOMEM; | |
559 | ||
71266846 | 560 | pdata->pkg_id = pdev->id; |
7108b80a | 561 | ida_init(&pdata->ida); |
199e0de7 D |
562 | platform_set_drvdata(pdev, pdata); |
563 | ||
d72d19c2 GR |
564 | pdata->hwmon_dev = devm_hwmon_device_register_with_groups(dev, DRVNAME, |
565 | pdata, NULL); | |
566 | return PTR_ERR_OR_ZERO(pdata->hwmon_dev); | |
bebe4678 RM |
567 | } |
568 | ||
281dfd0b | 569 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 570 | { |
199e0de7 D |
571 | struct platform_data *pdata = platform_get_drvdata(pdev); |
572 | int i; | |
bebe4678 | 573 | |
199e0de7 D |
574 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
575 | if (pdata->core_data[i]) | |
d72d19c2 | 576 | coretemp_remove_core(pdata, i); |
199e0de7 | 577 | |
7108b80a | 578 | ida_destroy(&pdata->ida); |
bebe4678 RM |
579 | return 0; |
580 | } | |
581 | ||
582 | static struct platform_driver coretemp_driver = { | |
583 | .driver = { | |
bebe4678 RM |
584 | .name = DRVNAME, |
585 | }, | |
586 | .probe = coretemp_probe, | |
9e5e9b7a | 587 | .remove = coretemp_remove, |
bebe4678 RM |
588 | }; |
589 | ||
71266846 | 590 | static struct platform_device *coretemp_device_add(unsigned int cpu) |
bebe4678 | 591 | { |
835896a5 | 592 | int err, zoneid = topology_logical_die_id(cpu); |
bebe4678 | 593 | struct platform_device *pdev; |
d883b9f0 | 594 | |
835896a5 | 595 | if (zoneid < 0) |
71266846 | 596 | return ERR_PTR(-ENOMEM); |
d883b9f0 | 597 | |
835896a5 | 598 | pdev = platform_device_alloc(DRVNAME, zoneid); |
71266846 TG |
599 | if (!pdev) |
600 | return ERR_PTR(-ENOMEM); | |
bebe4678 RM |
601 | |
602 | err = platform_device_add(pdev); | |
603 | if (err) { | |
71266846 TG |
604 | platform_device_put(pdev); |
605 | return ERR_PTR(err); | |
bebe4678 RM |
606 | } |
607 | ||
835896a5 | 608 | zone_devices[zoneid] = pdev; |
71266846 | 609 | return pdev; |
bebe4678 RM |
610 | } |
611 | ||
e00ca5df | 612 | static int coretemp_cpu_online(unsigned int cpu) |
199e0de7 | 613 | { |
199e0de7 | 614 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 TG |
615 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
616 | struct platform_data *pdata; | |
199e0de7 | 617 | |
90b4f30b TG |
618 | /* |
619 | * Don't execute this on resume as the offline callback did | |
620 | * not get executed on suspend. | |
621 | */ | |
622 | if (cpuhp_tasks_frozen) | |
623 | return 0; | |
624 | ||
199e0de7 D |
625 | /* |
626 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
627 | * sensors. We check this bit only, all the early CPUs | |
628 | * without thermal sensors will be filtered out. | |
629 | */ | |
4ad33411 | 630 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
2195c31b | 631 | return -ENODEV; |
199e0de7 D |
632 | |
633 | if (!pdev) { | |
0eb9782a JD |
634 | /* Check the microcode version of the CPU */ |
635 | if (chk_ucode_version(cpu)) | |
2195c31b | 636 | return -EINVAL; |
0eb9782a | 637 | |
199e0de7 D |
638 | /* |
639 | * Alright, we have DTS support. | |
640 | * We are bringing the _first_ core in this pkg | |
641 | * online. So, initialize per-pkg data structures and | |
642 | * then bring this core online. | |
643 | */ | |
71266846 TG |
644 | pdev = coretemp_device_add(cpu); |
645 | if (IS_ERR(pdev)) | |
646 | return PTR_ERR(pdev); | |
e1b370b6 | 647 | |
199e0de7 D |
648 | /* |
649 | * Check whether pkgtemp support is available. | |
650 | * If so, add interfaces for pkgtemp. | |
651 | */ | |
652 | if (cpu_has(c, X86_FEATURE_PTS)) | |
4b138cf7 | 653 | coretemp_add_core(pdev, cpu, 1); |
199e0de7 | 654 | } |
e1b370b6 TG |
655 | |
656 | pdata = platform_get_drvdata(pdev); | |
199e0de7 | 657 | /* |
e1b370b6 TG |
658 | * Check whether a thread sibling is already online. If not add the |
659 | * interface for this CPU core. | |
199e0de7 | 660 | */ |
e1b370b6 | 661 | if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu))) |
4b138cf7 | 662 | coretemp_add_core(pdev, cpu, 0); |
e1b370b6 TG |
663 | |
664 | cpumask_set_cpu(cpu, &pdata->cpumask); | |
e00ca5df | 665 | return 0; |
199e0de7 D |
666 | } |
667 | ||
e00ca5df | 668 | static int coretemp_cpu_offline(unsigned int cpu) |
199e0de7 | 669 | { |
199e0de7 | 670 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
e1b370b6 | 671 | struct platform_data *pd; |
723f5734 | 672 | struct temp_data *tdata; |
7108b80a | 673 | int i, indx = -1, target; |
199e0de7 | 674 | |
90b4f30b TG |
675 | /* |
676 | * Don't execute this on suspend as the device remove locks | |
677 | * up the machine. | |
678 | */ | |
679 | if (cpuhp_tasks_frozen) | |
680 | return 0; | |
681 | ||
199e0de7 D |
682 | /* If the physical CPU device does not exist, just return */ |
683 | if (!pdev) | |
e00ca5df | 684 | return 0; |
199e0de7 | 685 | |
7108b80a ZR |
686 | pd = platform_get_drvdata(pdev); |
687 | ||
688 | for (i = 0; i < NUM_REAL_CORES; i++) { | |
689 | if (pd->cpu_map[i] == topology_core_id(cpu)) { | |
690 | indx = i + BASE_SYSFS_ATTR_NO; | |
691 | break; | |
692 | } | |
693 | } | |
694 | ||
695 | /* Too many cores and this core is not populated, just return */ | |
696 | if (indx < 0) | |
e00ca5df | 697 | return 0; |
b7048711 | 698 | |
e1b370b6 TG |
699 | tdata = pd->core_data[indx]; |
700 | ||
701 | cpumask_clear_cpu(cpu, &pd->cpumask); | |
199e0de7 | 702 | |
f4e0bcf0 | 703 | /* |
e1b370b6 TG |
704 | * If this is the last thread sibling, remove the CPU core |
705 | * interface, If there is still a sibling online, transfer the | |
706 | * target cpu of that core interface to it. | |
f4e0bcf0 | 707 | */ |
e1b370b6 TG |
708 | target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu)); |
709 | if (target >= nr_cpu_ids) { | |
710 | coretemp_remove_core(pd, indx); | |
711 | } else if (tdata && tdata->cpu == cpu) { | |
712 | mutex_lock(&tdata->update_lock); | |
713 | tdata->cpu = target; | |
714 | mutex_unlock(&tdata->update_lock); | |
199e0de7 | 715 | } |
e1b370b6 | 716 | |
199e0de7 | 717 | /* |
71266846 TG |
718 | * If all cores in this pkg are offline, remove the device. This |
719 | * will invoke the platform driver remove function, which cleans up | |
720 | * the rest. | |
199e0de7 | 721 | */ |
e1b370b6 | 722 | if (cpumask_empty(&pd->cpumask)) { |
835896a5 | 723 | zone_devices[topology_logical_die_id(cpu)] = NULL; |
71266846 | 724 | platform_device_unregister(pdev); |
e00ca5df | 725 | return 0; |
723f5734 | 726 | } |
71266846 | 727 | |
723f5734 TG |
728 | /* |
729 | * Check whether this core is the target for the package | |
730 | * interface. We need to assign it to some other cpu. | |
731 | */ | |
e1b370b6 | 732 | tdata = pd->core_data[PKG_SYSFS_ATTR_NO]; |
723f5734 | 733 | if (tdata && tdata->cpu == cpu) { |
e1b370b6 | 734 | target = cpumask_first(&pd->cpumask); |
723f5734 TG |
735 | mutex_lock(&tdata->update_lock); |
736 | tdata->cpu = target; | |
737 | mutex_unlock(&tdata->update_lock); | |
738 | } | |
e00ca5df | 739 | return 0; |
199e0de7 | 740 | } |
e273bd98 | 741 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
5cfc7ac7 | 742 | X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL), |
9b38096f AK |
743 | {} |
744 | }; | |
745 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
746 | ||
e00ca5df TG |
747 | static enum cpuhp_state coretemp_hp_online; |
748 | ||
bebe4678 RM |
749 | static int __init coretemp_init(void) |
750 | { | |
e00ca5df | 751 | int err; |
bebe4678 | 752 | |
9b38096f AK |
753 | /* |
754 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
755 | * sensors. We check this bit only, all the early CPUs | |
756 | * without thermal sensors will be filtered out. | |
757 | */ | |
758 | if (!x86_match_cpu(coretemp_ids)) | |
759 | return -ENODEV; | |
bebe4678 | 760 | |
835896a5 LB |
761 | max_zones = topology_max_packages() * topology_max_die_per_package(); |
762 | zone_devices = kcalloc(max_zones, sizeof(struct platform_device *), | |
71266846 | 763 | GFP_KERNEL); |
835896a5 | 764 | if (!zone_devices) |
71266846 TG |
765 | return -ENOMEM; |
766 | ||
bebe4678 RM |
767 | err = platform_driver_register(&coretemp_driver); |
768 | if (err) | |
e027a2de | 769 | goto outzone; |
bebe4678 | 770 | |
e00ca5df TG |
771 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online", |
772 | coretemp_cpu_online, coretemp_cpu_offline); | |
773 | if (err < 0) | |
2195c31b | 774 | goto outdrv; |
e00ca5df | 775 | coretemp_hp_online = err; |
bebe4678 RM |
776 | return 0; |
777 | ||
2195c31b | 778 | outdrv: |
bebe4678 | 779 | platform_driver_unregister(&coretemp_driver); |
e027a2de | 780 | outzone: |
835896a5 | 781 | kfree(zone_devices); |
bebe4678 RM |
782 | return err; |
783 | } | |
e00ca5df | 784 | module_init(coretemp_init) |
bebe4678 RM |
785 | |
786 | static void __exit coretemp_exit(void) | |
787 | { | |
e00ca5df | 788 | cpuhp_remove_state(coretemp_hp_online); |
bebe4678 | 789 | platform_driver_unregister(&coretemp_driver); |
835896a5 | 790 | kfree(zone_devices); |
bebe4678 | 791 | } |
e00ca5df | 792 | module_exit(coretemp_exit) |
bebe4678 RM |
793 | |
794 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
795 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
796 | MODULE_LICENSE("GPL"); |