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bebe4678 RM |
1 | /* |
2 | * coretemp.c - Linux kernel module for hardware monitoring | |
3 | * | |
4 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> | |
5 | * | |
6 | * Inspired from many hwmon drivers | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA. | |
21 | */ | |
22 | ||
f8bb8925 JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
bebe4678 | 25 | #include <linux/module.h> |
bebe4678 RM |
26 | #include <linux/init.h> |
27 | #include <linux/slab.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/hwmon.h> | |
30 | #include <linux/sysfs.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/mutex.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/cpu.h> | |
4cc45275 | 37 | #include <linux/smp.h> |
a45a8c85 | 38 | #include <linux/moduleparam.h> |
14513ee6 | 39 | #include <linux/pci.h> |
bebe4678 RM |
40 | #include <asm/msr.h> |
41 | #include <asm/processor.h> | |
9b38096f | 42 | #include <asm/cpu_device_id.h> |
bebe4678 RM |
43 | |
44 | #define DRVNAME "coretemp" | |
45 | ||
a45a8c85 JD |
46 | /* |
47 | * force_tjmax only matters when TjMax can't be read from the CPU itself. | |
48 | * When set, it replaces the driver's suboptimal heuristic. | |
49 | */ | |
50 | static int force_tjmax; | |
51 | module_param_named(tjmax, force_tjmax, int, 0444); | |
52 | MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); | |
53 | ||
199e0de7 | 54 | #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ |
bdc71c9a | 55 | #define NUM_REAL_CORES 32 /* Number of Real cores per cpu */ |
3f9aec76 | 56 | #define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ |
c814a4c7 | 57 | #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ |
f4af6fd6 | 58 | #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) |
199e0de7 D |
59 | #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) |
60 | ||
780affe0 GR |
61 | #define TO_PHYS_ID(cpu) (cpu_data(cpu).phys_proc_id) |
62 | #define TO_CORE_ID(cpu) (cpu_data(cpu).cpu_core_id) | |
141168c3 KW |
63 | #define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO) |
64 | ||
65 | #ifdef CONFIG_SMP | |
bb74e8ca | 66 | #define for_each_sibling(i, cpu) for_each_cpu(i, cpu_sibling_mask(cpu)) |
199e0de7 | 67 | #else |
bb74e8ca | 68 | #define for_each_sibling(i, cpu) for (i = 0; false; ) |
199e0de7 | 69 | #endif |
bebe4678 RM |
70 | |
71 | /* | |
199e0de7 D |
72 | * Per-Core Temperature Data |
73 | * @last_updated: The time when the current temperature value was updated | |
74 | * earlier (in jiffies). | |
75 | * @cpu_core_id: The CPU Core from which temperature values should be read | |
76 | * This value is passed as "id" field to rdmsr/wrmsr functions. | |
77 | * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS, | |
78 | * from where the temperature values should be read. | |
c814a4c7 | 79 | * @attr_size: Total number of pre-core attrs displayed in the sysfs. |
199e0de7 D |
80 | * @is_pkg_data: If this is 1, the temp_data holds pkgtemp data. |
81 | * Otherwise, temp_data holds coretemp data. | |
82 | * @valid: If this is 1, the current temperature is valid. | |
bebe4678 | 83 | */ |
199e0de7 | 84 | struct temp_data { |
bebe4678 | 85 | int temp; |
6369a288 | 86 | int ttarget; |
199e0de7 D |
87 | int tjmax; |
88 | unsigned long last_updated; | |
89 | unsigned int cpu; | |
90 | u32 cpu_core_id; | |
91 | u32 status_reg; | |
c814a4c7 | 92 | int attr_size; |
199e0de7 D |
93 | bool is_pkg_data; |
94 | bool valid; | |
c814a4c7 D |
95 | struct sensor_device_attribute sd_attrs[TOTAL_ATTRS]; |
96 | char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH]; | |
1075305d GR |
97 | struct attribute *attrs[TOTAL_ATTRS + 1]; |
98 | struct attribute_group attr_group; | |
199e0de7 | 99 | struct mutex update_lock; |
bebe4678 RM |
100 | }; |
101 | ||
199e0de7 D |
102 | /* Platform Data per Physical CPU */ |
103 | struct platform_data { | |
104 | struct device *hwmon_dev; | |
105 | u16 phys_proc_id; | |
106 | struct temp_data *core_data[MAX_CORE_DATA]; | |
107 | struct device_attribute name_attr; | |
108 | }; | |
bebe4678 | 109 | |
199e0de7 D |
110 | struct pdev_entry { |
111 | struct list_head list; | |
112 | struct platform_device *pdev; | |
199e0de7 | 113 | u16 phys_proc_id; |
199e0de7 D |
114 | }; |
115 | ||
116 | static LIST_HEAD(pdev_list); | |
117 | static DEFINE_MUTEX(pdev_list_mutex); | |
118 | ||
119 | static ssize_t show_name(struct device *dev, | |
120 | struct device_attribute *devattr, char *buf) | |
121 | { | |
122 | return sprintf(buf, "%s\n", DRVNAME); | |
123 | } | |
124 | ||
125 | static ssize_t show_label(struct device *dev, | |
126 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 127 | { |
bebe4678 | 128 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); |
199e0de7 D |
129 | struct platform_data *pdata = dev_get_drvdata(dev); |
130 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
131 | ||
132 | if (tdata->is_pkg_data) | |
133 | return sprintf(buf, "Physical id %u\n", pdata->phys_proc_id); | |
bebe4678 | 134 | |
199e0de7 | 135 | return sprintf(buf, "Core %u\n", tdata->cpu_core_id); |
bebe4678 RM |
136 | } |
137 | ||
199e0de7 D |
138 | static ssize_t show_crit_alarm(struct device *dev, |
139 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 140 | { |
199e0de7 D |
141 | u32 eax, edx; |
142 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
143 | struct platform_data *pdata = dev_get_drvdata(dev); | |
144 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
145 | ||
146 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
147 | ||
148 | return sprintf(buf, "%d\n", (eax >> 5) & 1); | |
bebe4678 RM |
149 | } |
150 | ||
199e0de7 D |
151 | static ssize_t show_tjmax(struct device *dev, |
152 | struct device_attribute *devattr, char *buf) | |
bebe4678 RM |
153 | { |
154 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
199e0de7 | 155 | struct platform_data *pdata = dev_get_drvdata(dev); |
bebe4678 | 156 | |
199e0de7 | 157 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tjmax); |
bebe4678 RM |
158 | } |
159 | ||
199e0de7 D |
160 | static ssize_t show_ttarget(struct device *dev, |
161 | struct device_attribute *devattr, char *buf) | |
162 | { | |
163 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
164 | struct platform_data *pdata = dev_get_drvdata(dev); | |
bebe4678 | 165 | |
199e0de7 D |
166 | return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget); |
167 | } | |
bebe4678 | 168 | |
199e0de7 D |
169 | static ssize_t show_temp(struct device *dev, |
170 | struct device_attribute *devattr, char *buf) | |
bebe4678 | 171 | { |
199e0de7 D |
172 | u32 eax, edx; |
173 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
174 | struct platform_data *pdata = dev_get_drvdata(dev); | |
175 | struct temp_data *tdata = pdata->core_data[attr->index]; | |
bebe4678 | 176 | |
199e0de7 | 177 | mutex_lock(&tdata->update_lock); |
bebe4678 | 178 | |
199e0de7 D |
179 | /* Check whether the time interval has elapsed */ |
180 | if (!tdata->valid || time_after(jiffies, tdata->last_updated + HZ)) { | |
181 | rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); | |
bf6ea084 GR |
182 | /* |
183 | * Ignore the valid bit. In all observed cases the register | |
184 | * value is either low or zero if the valid bit is 0. | |
185 | * Return it instead of reporting an error which doesn't | |
186 | * really help at all. | |
187 | */ | |
188 | tdata->temp = tdata->tjmax - ((eax >> 16) & 0x7f) * 1000; | |
189 | tdata->valid = 1; | |
199e0de7 | 190 | tdata->last_updated = jiffies; |
bebe4678 RM |
191 | } |
192 | ||
199e0de7 | 193 | mutex_unlock(&tdata->update_lock); |
bf6ea084 | 194 | return sprintf(buf, "%d\n", tdata->temp); |
bebe4678 RM |
195 | } |
196 | ||
14513ee6 GR |
197 | struct tjmax_pci { |
198 | unsigned int device; | |
199 | int tjmax; | |
200 | }; | |
201 | ||
202 | static const struct tjmax_pci tjmax_pci_table[] = { | |
347c16cf | 203 | { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */ |
14513ee6 GR |
204 | { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */ |
205 | { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */ | |
206 | { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */ | |
207 | }; | |
208 | ||
41e58a1f GR |
209 | struct tjmax { |
210 | char const *id; | |
211 | int tjmax; | |
212 | }; | |
213 | ||
d23e2ae1 | 214 | static const struct tjmax tjmax_table[] = { |
1102dcab GR |
215 | { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */ |
216 | { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */ | |
41e58a1f GR |
217 | }; |
218 | ||
2fa5222e GR |
219 | struct tjmax_model { |
220 | u8 model; | |
221 | u8 mask; | |
222 | int tjmax; | |
223 | }; | |
224 | ||
225 | #define ANY 0xff | |
226 | ||
d23e2ae1 | 227 | static const struct tjmax_model tjmax_model_table[] = { |
9e3970fb | 228 | { 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */ |
2fa5222e GR |
229 | { 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others |
230 | * Note: Also matches 230 and 330, | |
231 | * which are covered by tjmax_table | |
232 | */ | |
233 | { 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx) | |
234 | * Note: TjMax for E6xxT is 110C, but CPU type | |
235 | * is undetectable by software | |
236 | */ | |
237 | { 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */ | |
14513ee6 GR |
238 | { 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */ |
239 | { 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx) | |
240 | * Also matches S12x0 (stepping 9), covered by | |
241 | * PCI table | |
242 | */ | |
2fa5222e GR |
243 | }; |
244 | ||
d23e2ae1 | 245 | static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
118a8871 RM |
246 | { |
247 | /* The 100C is default for both mobile and non mobile CPUs */ | |
248 | ||
249 | int tjmax = 100000; | |
eccfed42 | 250 | int tjmax_ee = 85000; |
708a62bc | 251 | int usemsr_ee = 1; |
118a8871 RM |
252 | int err; |
253 | u32 eax, edx; | |
41e58a1f | 254 | int i; |
14513ee6 GR |
255 | struct pci_dev *host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
256 | ||
257 | /* | |
258 | * Explicit tjmax table entries override heuristics. | |
259 | * First try PCI host bridge IDs, followed by model ID strings | |
260 | * and model/stepping information. | |
261 | */ | |
262 | if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
263 | for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) { | |
264 | if (host_bridge->device == tjmax_pci_table[i].device) | |
265 | return tjmax_pci_table[i].tjmax; | |
266 | } | |
267 | } | |
41e58a1f | 268 | |
41e58a1f GR |
269 | for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) { |
270 | if (strstr(c->x86_model_id, tjmax_table[i].id)) | |
271 | return tjmax_table[i].tjmax; | |
272 | } | |
118a8871 | 273 | |
2fa5222e GR |
274 | for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) { |
275 | const struct tjmax_model *tm = &tjmax_model_table[i]; | |
276 | if (c->x86_model == tm->model && | |
277 | (tm->mask == ANY || c->x86_mask == tm->mask)) | |
278 | return tm->tjmax; | |
72cbdddc | 279 | } |
1fe63ab4 | 280 | |
72cbdddc | 281 | /* Early chips have no MSR for TjMax */ |
1fe63ab4 | 282 | |
72cbdddc | 283 | if (c->x86_model == 0xf && c->x86_mask < 4) |
5592906f | 284 | usemsr_ee = 0; |
708a62bc | 285 | |
4cc45275 | 286 | if (c->x86_model > 0xe && usemsr_ee) { |
eccfed42 | 287 | u8 platform_id; |
118a8871 | 288 | |
4cc45275 GR |
289 | /* |
290 | * Now we can detect the mobile CPU using Intel provided table | |
291 | * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm | |
292 | * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU | |
293 | */ | |
118a8871 RM |
294 | err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx); |
295 | if (err) { | |
296 | dev_warn(dev, | |
297 | "Unable to access MSR 0x17, assuming desktop" | |
298 | " CPU\n"); | |
708a62bc | 299 | usemsr_ee = 0; |
eccfed42 | 300 | } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) { |
4cc45275 GR |
301 | /* |
302 | * Trust bit 28 up to Penryn, I could not find any | |
303 | * documentation on that; if you happen to know | |
304 | * someone at Intel please ask | |
305 | */ | |
708a62bc | 306 | usemsr_ee = 0; |
eccfed42 RM |
307 | } else { |
308 | /* Platform ID bits 52:50 (EDX starts at bit 32) */ | |
309 | platform_id = (edx >> 18) & 0x7; | |
310 | ||
4cc45275 GR |
311 | /* |
312 | * Mobile Penryn CPU seems to be platform ID 7 or 5 | |
313 | * (guesswork) | |
314 | */ | |
315 | if (c->x86_model == 0x17 && | |
316 | (platform_id == 5 || platform_id == 7)) { | |
317 | /* | |
318 | * If MSR EE bit is set, set it to 90 degrees C, | |
319 | * otherwise 105 degrees C | |
320 | */ | |
eccfed42 RM |
321 | tjmax_ee = 90000; |
322 | tjmax = 105000; | |
323 | } | |
118a8871 RM |
324 | } |
325 | } | |
326 | ||
708a62bc | 327 | if (usemsr_ee) { |
118a8871 RM |
328 | err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx); |
329 | if (err) { | |
330 | dev_warn(dev, | |
331 | "Unable to access MSR 0xEE, for Tjmax, left" | |
4d7a5644 | 332 | " at default\n"); |
118a8871 | 333 | } else if (eax & 0x40000000) { |
eccfed42 | 334 | tjmax = tjmax_ee; |
118a8871 | 335 | } |
708a62bc | 336 | } else if (tjmax == 100000) { |
4cc45275 GR |
337 | /* |
338 | * If we don't use msr EE it means we are desktop CPU | |
339 | * (with exeception of Atom) | |
340 | */ | |
118a8871 RM |
341 | dev_warn(dev, "Using relative temperature scale!\n"); |
342 | } | |
343 | ||
344 | return tjmax; | |
345 | } | |
346 | ||
1c2faa22 GR |
347 | static bool cpu_has_tjmax(struct cpuinfo_x86 *c) |
348 | { | |
349 | u8 model = c->x86_model; | |
350 | ||
351 | return model > 0xe && | |
352 | model != 0x1c && | |
353 | model != 0x26 && | |
354 | model != 0x27 && | |
355 | model != 0x35 && | |
356 | model != 0x36; | |
357 | } | |
358 | ||
d23e2ae1 | 359 | static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev) |
a321cedb | 360 | { |
a321cedb CE |
361 | int err; |
362 | u32 eax, edx; | |
363 | u32 val; | |
364 | ||
4cc45275 GR |
365 | /* |
366 | * A new feature of current Intel(R) processors, the | |
367 | * IA32_TEMPERATURE_TARGET contains the TjMax value | |
368 | */ | |
a321cedb CE |
369 | err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); |
370 | if (err) { | |
1c2faa22 | 371 | if (cpu_has_tjmax(c)) |
6bf9e9b0 | 372 | dev_warn(dev, "Unable to read TjMax from CPU %u\n", id); |
a321cedb | 373 | } else { |
9fb6c9c7 | 374 | val = (eax >> 16) & 0x7f; |
a321cedb CE |
375 | /* |
376 | * If the TjMax is not plausible, an assumption | |
377 | * will be used | |
378 | */ | |
9fb6c9c7 | 379 | if (val >= 85) { |
6bf9e9b0 | 380 | dev_dbg(dev, "TjMax is %d degrees C\n", val); |
a321cedb CE |
381 | return val * 1000; |
382 | } | |
383 | } | |
384 | ||
a45a8c85 JD |
385 | if (force_tjmax) { |
386 | dev_notice(dev, "TjMax forced to %d degrees C by user\n", | |
387 | force_tjmax); | |
388 | return force_tjmax * 1000; | |
389 | } | |
390 | ||
a321cedb CE |
391 | /* |
392 | * An assumption is made for early CPUs and unreadable MSR. | |
4f5f71a7 | 393 | * NOTE: the calculated value may not be correct. |
a321cedb | 394 | */ |
4f5f71a7 | 395 | return adjust_tjmax(c, id, dev); |
a321cedb CE |
396 | } |
397 | ||
6c931ae1 | 398 | static int create_name_attr(struct platform_data *pdata, |
d6db23c7 | 399 | struct device *dev) |
199e0de7 | 400 | { |
4258781a | 401 | sysfs_attr_init(&pdata->name_attr.attr); |
199e0de7 D |
402 | pdata->name_attr.attr.name = "name"; |
403 | pdata->name_attr.attr.mode = S_IRUGO; | |
404 | pdata->name_attr.show = show_name; | |
405 | return device_create_file(dev, &pdata->name_attr); | |
406 | } | |
bebe4678 | 407 | |
d23e2ae1 PG |
408 | static int create_core_attrs(struct temp_data *tdata, struct device *dev, |
409 | int attr_no) | |
199e0de7 | 410 | { |
1075305d | 411 | int i; |
e3204ed3 | 412 | static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev, |
199e0de7 | 413 | struct device_attribute *devattr, char *buf) = { |
c814a4c7 | 414 | show_label, show_crit_alarm, show_temp, show_tjmax, |
f4af6fd6 | 415 | show_ttarget }; |
e3204ed3 | 416 | static const char *const names[TOTAL_ATTRS] = { |
199e0de7 | 417 | "temp%d_label", "temp%d_crit_alarm", |
c814a4c7 | 418 | "temp%d_input", "temp%d_crit", |
f4af6fd6 | 419 | "temp%d_max" }; |
199e0de7 | 420 | |
c814a4c7 | 421 | for (i = 0; i < tdata->attr_size; i++) { |
199e0de7 D |
422 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, names[i], |
423 | attr_no); | |
4258781a | 424 | sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr); |
199e0de7 D |
425 | tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i]; |
426 | tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO; | |
427 | tdata->sd_attrs[i].dev_attr.show = rd_ptr[i]; | |
199e0de7 | 428 | tdata->sd_attrs[i].index = attr_no; |
1075305d | 429 | tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr; |
bebe4678 | 430 | } |
1075305d GR |
431 | tdata->attr_group.attrs = tdata->attrs; |
432 | return sysfs_create_group(&dev->kobj, &tdata->attr_group); | |
199e0de7 D |
433 | } |
434 | ||
199e0de7 | 435 | |
d23e2ae1 | 436 | static int chk_ucode_version(unsigned int cpu) |
199e0de7 | 437 | { |
0eb9782a | 438 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
67f363b1 | 439 | |
199e0de7 D |
440 | /* |
441 | * Check if we have problem with errata AE18 of Core processors: | |
442 | * Readings might stop update when processor visited too deep sleep, | |
443 | * fixed for stepping D0 (6EC). | |
444 | */ | |
ca8bc8dc | 445 | if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) { |
b55f3757 | 446 | pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n"); |
ca8bc8dc | 447 | return -ENODEV; |
67f363b1 | 448 | } |
199e0de7 D |
449 | return 0; |
450 | } | |
451 | ||
d23e2ae1 | 452 | static struct platform_device *coretemp_get_pdev(unsigned int cpu) |
199e0de7 D |
453 | { |
454 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
455 | struct pdev_entry *p; | |
456 | ||
457 | mutex_lock(&pdev_list_mutex); | |
458 | ||
459 | list_for_each_entry(p, &pdev_list, list) | |
460 | if (p->phys_proc_id == phys_proc_id) { | |
461 | mutex_unlock(&pdev_list_mutex); | |
462 | return p->pdev; | |
463 | } | |
464 | ||
465 | mutex_unlock(&pdev_list_mutex); | |
466 | return NULL; | |
467 | } | |
468 | ||
d23e2ae1 | 469 | static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag) |
199e0de7 D |
470 | { |
471 | struct temp_data *tdata; | |
472 | ||
473 | tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL); | |
474 | if (!tdata) | |
475 | return NULL; | |
476 | ||
477 | tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS : | |
478 | MSR_IA32_THERM_STATUS; | |
479 | tdata->is_pkg_data = pkg_flag; | |
480 | tdata->cpu = cpu; | |
481 | tdata->cpu_core_id = TO_CORE_ID(cpu); | |
c814a4c7 | 482 | tdata->attr_size = MAX_CORE_ATTRS; |
199e0de7 D |
483 | mutex_init(&tdata->update_lock); |
484 | return tdata; | |
485 | } | |
67f363b1 | 486 | |
d23e2ae1 PG |
487 | static int create_core_data(struct platform_device *pdev, unsigned int cpu, |
488 | int pkg_flag) | |
199e0de7 D |
489 | { |
490 | struct temp_data *tdata; | |
2f1c3db0 | 491 | struct platform_data *pdata = platform_get_drvdata(pdev); |
199e0de7 D |
492 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
493 | u32 eax, edx; | |
494 | int err, attr_no; | |
bebe4678 | 495 | |
a321cedb | 496 | /* |
199e0de7 D |
497 | * Find attr number for sysfs: |
498 | * We map the attr number to core id of the CPU | |
499 | * The attr number is always core id + 2 | |
500 | * The Pkgtemp will always show up as temp1_*, if available | |
a321cedb | 501 | */ |
199e0de7 | 502 | attr_no = pkg_flag ? 1 : TO_ATTR_NO(cpu); |
6369a288 | 503 | |
199e0de7 D |
504 | if (attr_no > MAX_CORE_DATA - 1) |
505 | return -ERANGE; | |
506 | ||
f4e0bcf0 GR |
507 | /* |
508 | * Provide a single set of attributes for all HT siblings of a core | |
509 | * to avoid duplicate sensors (the processor ID and core ID of all | |
6777b9e4 GR |
510 | * HT siblings of a core are the same). |
511 | * Skip if a HT sibling of this core is already registered. | |
f4e0bcf0 GR |
512 | * This is not an error. |
513 | */ | |
199e0de7 D |
514 | if (pdata->core_data[attr_no] != NULL) |
515 | return 0; | |
6369a288 | 516 | |
199e0de7 D |
517 | tdata = init_temp_data(cpu, pkg_flag); |
518 | if (!tdata) | |
519 | return -ENOMEM; | |
bebe4678 | 520 | |
199e0de7 D |
521 | /* Test if we can access the status register */ |
522 | err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx); | |
523 | if (err) | |
524 | goto exit_free; | |
525 | ||
526 | /* We can access status register. Get Critical Temperature */ | |
6bf9e9b0 | 527 | tdata->tjmax = get_tjmax(c, cpu, &pdev->dev); |
199e0de7 | 528 | |
c814a4c7 | 529 | /* |
f4af6fd6 GR |
530 | * Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. |
531 | * The target temperature is available on older CPUs but not in this | |
532 | * register. Atoms don't have the register at all. | |
c814a4c7 | 533 | */ |
f4af6fd6 GR |
534 | if (c->x86_model > 0xe && c->x86_model != 0x1c) { |
535 | err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, | |
536 | &eax, &edx); | |
537 | if (!err) { | |
538 | tdata->ttarget | |
539 | = tdata->tjmax - ((eax >> 8) & 0xff) * 1000; | |
540 | tdata->attr_size++; | |
541 | } | |
c814a4c7 D |
542 | } |
543 | ||
199e0de7 D |
544 | pdata->core_data[attr_no] = tdata; |
545 | ||
546 | /* Create sysfs interfaces */ | |
547 | err = create_core_attrs(tdata, &pdev->dev, attr_no); | |
548 | if (err) | |
549 | goto exit_free; | |
bebe4678 RM |
550 | |
551 | return 0; | |
199e0de7 | 552 | exit_free: |
20ecb499 | 553 | pdata->core_data[attr_no] = NULL; |
199e0de7 D |
554 | kfree(tdata); |
555 | return err; | |
556 | } | |
557 | ||
d23e2ae1 | 558 | static void coretemp_add_core(unsigned int cpu, int pkg_flag) |
199e0de7 | 559 | { |
199e0de7 D |
560 | struct platform_device *pdev = coretemp_get_pdev(cpu); |
561 | int err; | |
562 | ||
563 | if (!pdev) | |
564 | return; | |
565 | ||
2f1c3db0 | 566 | err = create_core_data(pdev, cpu, pkg_flag); |
199e0de7 D |
567 | if (err) |
568 | dev_err(&pdev->dev, "Adding Core %u failed\n", cpu); | |
569 | } | |
570 | ||
571 | static void coretemp_remove_core(struct platform_data *pdata, | |
572 | struct device *dev, int indx) | |
573 | { | |
199e0de7 D |
574 | struct temp_data *tdata = pdata->core_data[indx]; |
575 | ||
576 | /* Remove the sysfs attributes */ | |
1075305d | 577 | sysfs_remove_group(&dev->kobj, &tdata->attr_group); |
199e0de7 D |
578 | |
579 | kfree(pdata->core_data[indx]); | |
580 | pdata->core_data[indx] = NULL; | |
581 | } | |
582 | ||
6c931ae1 | 583 | static int coretemp_probe(struct platform_device *pdev) |
199e0de7 | 584 | { |
c503a811 | 585 | struct device *dev = &pdev->dev; |
199e0de7 D |
586 | struct platform_data *pdata; |
587 | int err; | |
bebe4678 | 588 | |
199e0de7 | 589 | /* Initialize the per-package data structures */ |
c503a811 | 590 | pdata = devm_kzalloc(dev, sizeof(struct platform_data), GFP_KERNEL); |
199e0de7 D |
591 | if (!pdata) |
592 | return -ENOMEM; | |
593 | ||
c503a811 | 594 | err = create_name_attr(pdata, dev); |
199e0de7 | 595 | if (err) |
c503a811 | 596 | return err; |
199e0de7 | 597 | |
b3a242a6 | 598 | pdata->phys_proc_id = pdev->id; |
199e0de7 D |
599 | platform_set_drvdata(pdev, pdata); |
600 | ||
c503a811 | 601 | pdata->hwmon_dev = hwmon_device_register(dev); |
199e0de7 D |
602 | if (IS_ERR(pdata->hwmon_dev)) { |
603 | err = PTR_ERR(pdata->hwmon_dev); | |
604 | dev_err(&pdev->dev, "Class registration failed (%d)\n", err); | |
605 | goto exit_name; | |
606 | } | |
607 | return 0; | |
608 | ||
609 | exit_name: | |
610 | device_remove_file(&pdev->dev, &pdata->name_attr); | |
bebe4678 RM |
611 | return err; |
612 | } | |
613 | ||
281dfd0b | 614 | static int coretemp_remove(struct platform_device *pdev) |
bebe4678 | 615 | { |
199e0de7 D |
616 | struct platform_data *pdata = platform_get_drvdata(pdev); |
617 | int i; | |
bebe4678 | 618 | |
199e0de7 D |
619 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) |
620 | if (pdata->core_data[i]) | |
621 | coretemp_remove_core(pdata, &pdev->dev, i); | |
622 | ||
623 | device_remove_file(&pdev->dev, &pdata->name_attr); | |
624 | hwmon_device_unregister(pdata->hwmon_dev); | |
bebe4678 RM |
625 | return 0; |
626 | } | |
627 | ||
628 | static struct platform_driver coretemp_driver = { | |
629 | .driver = { | |
630 | .owner = THIS_MODULE, | |
631 | .name = DRVNAME, | |
632 | }, | |
633 | .probe = coretemp_probe, | |
9e5e9b7a | 634 | .remove = coretemp_remove, |
bebe4678 RM |
635 | }; |
636 | ||
d23e2ae1 | 637 | static int coretemp_device_add(unsigned int cpu) |
bebe4678 RM |
638 | { |
639 | int err; | |
640 | struct platform_device *pdev; | |
641 | struct pdev_entry *pdev_entry; | |
d883b9f0 JD |
642 | |
643 | mutex_lock(&pdev_list_mutex); | |
644 | ||
b3a242a6 | 645 | pdev = platform_device_alloc(DRVNAME, TO_PHYS_ID(cpu)); |
bebe4678 RM |
646 | if (!pdev) { |
647 | err = -ENOMEM; | |
f8bb8925 | 648 | pr_err("Device allocation failed\n"); |
bebe4678 RM |
649 | goto exit; |
650 | } | |
651 | ||
652 | pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL); | |
653 | if (!pdev_entry) { | |
654 | err = -ENOMEM; | |
655 | goto exit_device_put; | |
656 | } | |
657 | ||
658 | err = platform_device_add(pdev); | |
659 | if (err) { | |
f8bb8925 | 660 | pr_err("Device addition failed (%d)\n", err); |
bebe4678 RM |
661 | goto exit_device_free; |
662 | } | |
663 | ||
664 | pdev_entry->pdev = pdev; | |
0eb9782a | 665 | pdev_entry->phys_proc_id = pdev->id; |
199e0de7 | 666 | |
bebe4678 RM |
667 | list_add_tail(&pdev_entry->list, &pdev_list); |
668 | mutex_unlock(&pdev_list_mutex); | |
669 | ||
670 | return 0; | |
671 | ||
672 | exit_device_free: | |
673 | kfree(pdev_entry); | |
674 | exit_device_put: | |
675 | platform_device_put(pdev); | |
676 | exit: | |
d883b9f0 | 677 | mutex_unlock(&pdev_list_mutex); |
bebe4678 RM |
678 | return err; |
679 | } | |
680 | ||
d23e2ae1 | 681 | static void coretemp_device_remove(unsigned int cpu) |
bebe4678 | 682 | { |
199e0de7 D |
683 | struct pdev_entry *p, *n; |
684 | u16 phys_proc_id = TO_PHYS_ID(cpu); | |
e40cc4bd | 685 | |
bebe4678 | 686 | mutex_lock(&pdev_list_mutex); |
199e0de7 D |
687 | list_for_each_entry_safe(p, n, &pdev_list, list) { |
688 | if (p->phys_proc_id != phys_proc_id) | |
e40cc4bd | 689 | continue; |
e40cc4bd JB |
690 | platform_device_unregister(p->pdev); |
691 | list_del(&p->list); | |
e40cc4bd | 692 | kfree(p); |
bebe4678 RM |
693 | } |
694 | mutex_unlock(&pdev_list_mutex); | |
695 | } | |
696 | ||
d23e2ae1 | 697 | static bool is_any_core_online(struct platform_data *pdata) |
199e0de7 D |
698 | { |
699 | int i; | |
700 | ||
701 | /* Find online cores, except pkgtemp data */ | |
702 | for (i = MAX_CORE_DATA - 1; i >= 0; --i) { | |
703 | if (pdata->core_data[i] && | |
704 | !pdata->core_data[i]->is_pkg_data) { | |
705 | return true; | |
706 | } | |
707 | } | |
708 | return false; | |
709 | } | |
710 | ||
d23e2ae1 | 711 | static void get_core_online(unsigned int cpu) |
199e0de7 D |
712 | { |
713 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
714 | struct platform_device *pdev = coretemp_get_pdev(cpu); | |
715 | int err; | |
716 | ||
717 | /* | |
718 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
719 | * sensors. We check this bit only, all the early CPUs | |
720 | * without thermal sensors will be filtered out. | |
721 | */ | |
4ad33411 | 722 | if (!cpu_has(c, X86_FEATURE_DTHERM)) |
199e0de7 D |
723 | return; |
724 | ||
725 | if (!pdev) { | |
0eb9782a JD |
726 | /* Check the microcode version of the CPU */ |
727 | if (chk_ucode_version(cpu)) | |
728 | return; | |
729 | ||
199e0de7 D |
730 | /* |
731 | * Alright, we have DTS support. | |
732 | * We are bringing the _first_ core in this pkg | |
733 | * online. So, initialize per-pkg data structures and | |
734 | * then bring this core online. | |
735 | */ | |
736 | err = coretemp_device_add(cpu); | |
737 | if (err) | |
738 | return; | |
739 | /* | |
740 | * Check whether pkgtemp support is available. | |
741 | * If so, add interfaces for pkgtemp. | |
742 | */ | |
743 | if (cpu_has(c, X86_FEATURE_PTS)) | |
744 | coretemp_add_core(cpu, 1); | |
745 | } | |
746 | /* | |
747 | * Physical CPU device already exists. | |
748 | * So, just add interfaces for this core. | |
749 | */ | |
750 | coretemp_add_core(cpu, 0); | |
751 | } | |
752 | ||
d23e2ae1 | 753 | static void put_core_offline(unsigned int cpu) |
199e0de7 D |
754 | { |
755 | int i, indx; | |
756 | struct platform_data *pdata; | |
757 | struct platform_device *pdev = coretemp_get_pdev(cpu); | |
758 | ||
759 | /* If the physical CPU device does not exist, just return */ | |
760 | if (!pdev) | |
761 | return; | |
762 | ||
763 | pdata = platform_get_drvdata(pdev); | |
764 | ||
765 | indx = TO_ATTR_NO(cpu); | |
766 | ||
b7048711 KS |
767 | /* The core id is too big, just return */ |
768 | if (indx > MAX_CORE_DATA - 1) | |
769 | return; | |
770 | ||
199e0de7 D |
771 | if (pdata->core_data[indx] && pdata->core_data[indx]->cpu == cpu) |
772 | coretemp_remove_core(pdata, &pdev->dev, indx); | |
773 | ||
f4e0bcf0 | 774 | /* |
6777b9e4 GR |
775 | * If a HT sibling of a core is taken offline, but another HT sibling |
776 | * of the same core is still online, register the alternate sibling. | |
777 | * This ensures that exactly one set of attributes is provided as long | |
778 | * as at least one HT sibling of a core is online. | |
f4e0bcf0 | 779 | */ |
bb74e8ca | 780 | for_each_sibling(i, cpu) { |
199e0de7 D |
781 | if (i != cpu) { |
782 | get_core_online(i); | |
f4e0bcf0 GR |
783 | /* |
784 | * Display temperature sensor data for one HT sibling | |
785 | * per core only, so abort the loop after one such | |
786 | * sibling has been found. | |
787 | */ | |
199e0de7 D |
788 | break; |
789 | } | |
790 | } | |
791 | /* | |
792 | * If all cores in this pkg are offline, remove the device. | |
793 | * coretemp_device_remove calls unregister_platform_device, | |
794 | * which in turn calls coretemp_remove. This removes the | |
795 | * pkgtemp entry and does other clean ups. | |
796 | */ | |
797 | if (!is_any_core_online(pdata)) | |
798 | coretemp_device_remove(cpu); | |
799 | } | |
800 | ||
d23e2ae1 | 801 | static int coretemp_cpu_callback(struct notifier_block *nfb, |
bebe4678 RM |
802 | unsigned long action, void *hcpu) |
803 | { | |
804 | unsigned int cpu = (unsigned long) hcpu; | |
805 | ||
806 | switch (action) { | |
807 | case CPU_ONLINE: | |
561d9a96 | 808 | case CPU_DOWN_FAILED: |
199e0de7 | 809 | get_core_online(cpu); |
bebe4678 | 810 | break; |
561d9a96 | 811 | case CPU_DOWN_PREPARE: |
199e0de7 | 812 | put_core_offline(cpu); |
bebe4678 RM |
813 | break; |
814 | } | |
815 | return NOTIFY_OK; | |
816 | } | |
817 | ||
ba7c1927 | 818 | static struct notifier_block coretemp_cpu_notifier __refdata = { |
bebe4678 RM |
819 | .notifier_call = coretemp_cpu_callback, |
820 | }; | |
bebe4678 | 821 | |
e273bd98 | 822 | static const struct x86_cpu_id __initconst coretemp_ids[] = { |
4ad33411 | 823 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_DTHERM }, |
9b38096f AK |
824 | {} |
825 | }; | |
826 | MODULE_DEVICE_TABLE(x86cpu, coretemp_ids); | |
827 | ||
bebe4678 RM |
828 | static int __init coretemp_init(void) |
829 | { | |
1268a172 | 830 | int i, err; |
bebe4678 | 831 | |
9b38096f AK |
832 | /* |
833 | * CPUID.06H.EAX[0] indicates whether the CPU has thermal | |
834 | * sensors. We check this bit only, all the early CPUs | |
835 | * without thermal sensors will be filtered out. | |
836 | */ | |
837 | if (!x86_match_cpu(coretemp_ids)) | |
838 | return -ENODEV; | |
bebe4678 RM |
839 | |
840 | err = platform_driver_register(&coretemp_driver); | |
841 | if (err) | |
842 | goto exit; | |
843 | ||
641f1456 | 844 | get_online_cpus(); |
a4659053 | 845 | for_each_online_cpu(i) |
199e0de7 | 846 | get_core_online(i); |
89a3fd35 JB |
847 | |
848 | #ifndef CONFIG_HOTPLUG_CPU | |
bebe4678 | 849 | if (list_empty(&pdev_list)) { |
641f1456 | 850 | put_online_cpus(); |
bebe4678 RM |
851 | err = -ENODEV; |
852 | goto exit_driver_unreg; | |
853 | } | |
89a3fd35 | 854 | #endif |
bebe4678 | 855 | |
bebe4678 | 856 | register_hotcpu_notifier(&coretemp_cpu_notifier); |
641f1456 | 857 | put_online_cpus(); |
bebe4678 RM |
858 | return 0; |
859 | ||
0dca94ba | 860 | #ifndef CONFIG_HOTPLUG_CPU |
89a3fd35 | 861 | exit_driver_unreg: |
bebe4678 | 862 | platform_driver_unregister(&coretemp_driver); |
0dca94ba | 863 | #endif |
bebe4678 RM |
864 | exit: |
865 | return err; | |
866 | } | |
867 | ||
868 | static void __exit coretemp_exit(void) | |
869 | { | |
870 | struct pdev_entry *p, *n; | |
17c10d61 | 871 | |
641f1456 | 872 | get_online_cpus(); |
bebe4678 | 873 | unregister_hotcpu_notifier(&coretemp_cpu_notifier); |
bebe4678 RM |
874 | mutex_lock(&pdev_list_mutex); |
875 | list_for_each_entry_safe(p, n, &pdev_list, list) { | |
876 | platform_device_unregister(p->pdev); | |
877 | list_del(&p->list); | |
878 | kfree(p); | |
879 | } | |
880 | mutex_unlock(&pdev_list_mutex); | |
641f1456 | 881 | put_online_cpus(); |
bebe4678 RM |
882 | platform_driver_unregister(&coretemp_driver); |
883 | } | |
884 | ||
885 | MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); | |
886 | MODULE_DESCRIPTION("Intel Core temperature monitor"); | |
887 | MODULE_LICENSE("GPL"); | |
888 | ||
889 | module_init(coretemp_init) | |
890 | module_exit(coretemp_exit) |