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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / dme1737.c
CommitLineData
9431996f 1/*
ea694431
JH		 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
9431996f 6 *
e95c237d 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
549edb83 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
ea694431
JH		 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
9431996f
JH		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
9c6e13b4
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9431996f
JH		 30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/slab.h>
33#include <linux/jiffies.h>
34#include <linux/i2c.h>
e95c237d 35#include <linux/platform_device.h>
9431996f
JH		 36#include <linux/hwmon.h>
37#include <linux/hwmon-sysfs.h>
38#include <linux/hwmon-vid.h>
39#include <linux/err.h>
40#include <linux/mutex.h>
b9acb64a 41#include <linux/acpi.h>
6055fae8 42#include <linux/io.h>
9431996f 43
e95c237d
JH		 44/* ISA device, if found */
45static struct platform_device *pdev;
46
9431996f 47/* Module load parameters */
90ab5ee9 48static bool force_start;
9431996f
JH		 49module_param(force_start, bool, 0);
50MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
51
67b671bc
JD		 52static unsigned short force_id;
53module_param(force_id, ushort, 0);
54MODULE_PARM_DESC(force_id, "Override the detected device ID");
55
90ab5ee9 56static bool probe_all_addr;
92430b6f
JH		 57module_param(probe_all_addr, bool, 0);
58MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC "
59 "addresses");
60
9431996f 61/* Addresses to scan */
25e9c86d 62static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
9431996f 63
ea694431 64enum chips { dme1737, sch5027, sch311x, sch5127 };
9431996f
JH		 65
66/* ---------------------------------------------------------------------
67 * Registers
68 *
69 * The sensors are defined as follows:
70 *
71 * Voltages Temperatures
72 * -------- ------------
73 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
74 * in1 Vccp (proc core) temp2 Internal temp
75 * in2 VCC (internal +3.3V) temp3 Remote diode 2
76 * in3 +5V
77 * in4 +12V
78 * in5 VTR (+3.3V stby)
79 * in6 Vbat
d4b94e1f 80 * in7 Vtrip (sch5127 only)
9431996f
JH		 81 *
82 * --------------------------------------------------------------------- */
83
d4b94e1f 84/* Voltages (in) numbered 0-7 (ix) */
c8de8362 85#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
d4b94e1f
JH		 86 (ix) < 7 ? 0x94 + (ix) : \
87 0x1f)
c8de8362 88#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
9431996f 89 : 0x91 + (ix) * 2)
c8de8362 90#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
9431996f
JH		 91 : 0x92 + (ix) * 2)
92
93/* Temperatures (temp) numbered 0-2 (ix) */
94#define DME1737_REG_TEMP(ix) (0x25 + (ix))
95#define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
96#define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
97#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
98 : 0x1c + (ix))
99
c8de8362
GR		 100/*
101 * Voltage and temperature LSBs
9431996f
JH		 102 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
103 * IN_TEMP_LSB(0) = [in5, in6]
104 * IN_TEMP_LSB(1) = [temp3, temp1]
105 * IN_TEMP_LSB(2) = [in4, temp2]
106 * IN_TEMP_LSB(3) = [in3, in0]
d4b94e1f 107 * IN_TEMP_LSB(4) = [in2, in1]
c8de8362
GR		 108 * IN_TEMP_LSB(5) = [res, in7]
109 */
9431996f 110#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
d4b94e1f
JH		 111static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
112static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
9431996f
JH		 113static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
114static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
115
116/* Fans numbered 0-5 (ix) */
117#define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
118 : 0xa1 + (ix) * 2)
119#define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
120 : 0xa5 + (ix) * 2)
121#define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
122 : 0xb2 + (ix))
123#define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
124
125/* PWMs numbered 0-2, 4-5 (ix) */
126#define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
127 : 0xa1 + (ix))
128#define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
129#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
130#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
131 : 0xa3 + (ix))
c8de8362
GR		 132/*
133 * The layout of the ramp rate registers is different from the other pwm
9431996f
JH		 134 * registers. The bits for the 3 PWMs are stored in 2 registers:
135 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
c8de8362
GR		 136 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
137 */
9431996f
JH		 138#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
139
140/* Thermal zones 0-2 */
141#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
142#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
c8de8362
GR		 143/*
144 * The layout of the hysteresis registers is different from the other zone
9431996f
JH		 145 * registers. The bits for the 3 zones are stored in 2 registers:
146 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
c8de8362
GR		 147 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
148 */
9431996f
JH		 149#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
150
c8de8362
GR		 151/*
152 * Alarm registers and bit mapping
9431996f 153 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
c8de8362
GR		 154 * alarm value [0, ALARM3, ALARM2, ALARM1].
155 */
9431996f
JH		 156#define DME1737_REG_ALARM1 0x41
157#define DME1737_REG_ALARM2 0x42
158#define DME1737_REG_ALARM3 0x83
d4b94e1f 159static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
9431996f
JH		 160static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
161static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
162
163/* Miscellaneous registers */
e95c237d 164#define DME1737_REG_DEVICE 0x3d
9431996f
JH		 165#define DME1737_REG_COMPANY 0x3e
166#define DME1737_REG_VERSTEP 0x3f
167#define DME1737_REG_CONFIG 0x40
168#define DME1737_REG_CONFIG2 0x7f
169#define DME1737_REG_VID 0x43
170#define DME1737_REG_TACH_PWM 0x81
171
172/* ---------------------------------------------------------------------
173 * Misc defines
174 * --------------------------------------------------------------------- */
175
176/* Chip identification */
177#define DME1737_COMPANY_SMSC 0x5c
178#define DME1737_VERSTEP 0x88
179#define DME1737_VERSTEP_MASK 0xf8
e95c237d 180#define SCH311X_DEVICE 0x8c
549edb83 181#define SCH5027_VERSTEP 0x69
ea694431
JH		 182#define SCH5127_DEVICE 0x8e
183
184/* Device ID values (global configuration register index 0x20) */
185#define DME1737_ID_1 0x77
186#define DME1737_ID_2 0x78
187#define SCH3112_ID 0x7c
188#define SCH3114_ID 0x7d
189#define SCH3116_ID 0x7f
190#define SCH5027_ID 0x89
191#define SCH5127_ID 0x86
e95c237d
JH		 192
193/* Length of ISA address segment */
194#define DME1737_EXTENT 2
9431996f 195
ea694431
JH		 196/* chip-dependent features */
197#define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
198#define HAS_VID (1 << 1) /* bit 1 */
199#define HAS_ZONE3 (1 << 2) /* bit 2 */
200#define HAS_ZONE_HYST (1 << 3) /* bit 3 */
201#define HAS_PWM_MIN (1 << 4) /* bit 4 */
202#define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
203#define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
d4b94e1f 204#define HAS_IN7 (1 << 17) /* bit 17 */
ea694431 205
9431996f
JH		 206/* ---------------------------------------------------------------------
207 * Data structures and manipulation thereof
208 * --------------------------------------------------------------------- */
209
210struct dme1737_data {
dbc2bc25 211 struct i2c_client *client; /* for I2C devices only */
1beeffe4 212 struct device *hwmon_dev;
dbc2bc25
JD		 213 const char *name;
214 unsigned int addr; /* for ISA devices only */
9431996f
JH		 215
216 struct mutex update_lock;
217 int valid; /* !=0 if following fields are valid */
218 unsigned long last_update; /* in jiffies */
219 unsigned long last_vbat; /* in jiffies */
f994fb23 220 enum chips type;
549edb83 221 const int *in_nominal; /* pointer to IN_NOMINAL array */
9431996f
JH		 222
223 u8 vid;
224 u8 pwm_rr_en;
ea694431 225 u32 has_features;
9431996f
JH		 226
227 /* Register values */
d4b94e1f
JH		 228 u16 in[8];
229 u8 in_min[8];
230 u8 in_max[8];
9431996f
JH		 231 s16 temp[3];
232 s8 temp_min[3];
233 s8 temp_max[3];
234 s8 temp_offset[3];
235 u8 config;
236 u8 config2;
237 u8 vrm;
238 u16 fan[6];
239 u16 fan_min[6];
240 u8 fan_max[2];
241 u8 fan_opt[6];
242 u8 pwm[6];
243 u8 pwm_min[3];
244 u8 pwm_config[3];
245 u8 pwm_acz[3];
246 u8 pwm_freq[6];
247 u8 pwm_rr[2];
248 u8 zone_low[3];
249 u8 zone_abs[3];
250 u8 zone_hyst[2];
251 u32 alarms;
252};
253
254/* Nominal voltage values */
f994fb23
JH		 255static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
256 3300};
257static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
258 3300};
549edb83
JH		 259static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
260 3300};
ea694431 261static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
d4b94e1f 262 3300, 1500};
549edb83
JH		 263#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
264 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
ea694431 265 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
549edb83 266 IN_NOMINAL_DME1737)
9431996f 267
c8de8362
GR		 268/*
269 * Voltage input
9431996f 270 * Voltage inputs have 16 bits resolution, limit values have 8 bits
c8de8362
GR		 271 * resolution.
272 */
549edb83 273static inline int IN_FROM_REG(int reg, int nominal, int res)
9431996f 274{
549edb83 275 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
9431996f
JH		 276}
277
549edb83 278static inline int IN_TO_REG(int val, int nominal)
9431996f 279{
2a844c14 280 return clamp_val((val * 192 + nominal / 2) / nominal, 0, 255);
9431996f
JH		 281}
282
c8de8362
GR		 283/*
284 * Temperature input
9431996f
JH		 285 * The register values represent temperatures in 2's complement notation from
286 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
c8de8362
GR		 287 * values have 8 bits resolution.
288 */
9431996f
JH		 289static inline int TEMP_FROM_REG(int reg, int res)
290{
291 return (reg * 1000) >> (res - 8);
292}
293
294static inline int TEMP_TO_REG(int val)
295{
2a844c14 296 return clamp_val((val < 0 ? val - 500 : val + 500) / 1000, -128, 127);
9431996f
JH		 297}
298
299/* Temperature range */
300static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
301 10000, 13333, 16000, 20000, 26666, 32000,
302 40000, 53333, 80000};
303
304static inline int TEMP_RANGE_FROM_REG(int reg)
305{
306 return TEMP_RANGE[(reg >> 4) & 0x0f];
307}
308
309static int TEMP_RANGE_TO_REG(int val, int reg)
310{
311 int i;
312
313 for (i = 15; i > 0; i--) {
c8de8362 314 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
9431996f 315 break;
9431996f
JH		 316 }
317
318 return (reg & 0x0f) | (i << 4);
319}
320
c8de8362
GR		 321/*
322 * Temperature hysteresis
9431996f
JH		 323 * Register layout:
324 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
c8de8362
GR		 325 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
326 */
9431996f
JH		 327static inline int TEMP_HYST_FROM_REG(int reg, int ix)
328{
329 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
330}
331
332static inline int TEMP_HYST_TO_REG(int val, int ix, int reg)
333{
2a844c14 334 int hyst = clamp_val((val + 500) / 1000, 0, 15);
9431996f
JH		 335
336 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
337}
338
339/* Fan input RPM */
340static inline int FAN_FROM_REG(int reg, int tpc)
341{
c8de8362 342 if (tpc)
ff8421f7 343 return tpc * reg;
c8de8362 344 else
ff8421f7 345 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
9431996f
JH		 346}
347
348static inline int FAN_TO_REG(int val, int tpc)
349{
ff8421f7 350 if (tpc) {
2a844c14 351 return clamp_val(val / tpc, 0, 0xffff);
ff8421f7
JH		 352 } else {
353 return (val <= 0) ? 0xffff :
2a844c14 354 clamp_val(90000 * 60 / val, 0, 0xfffe);
ff8421f7 355 }
9431996f
JH		 356}
357
c8de8362
GR		 358/*
359 * Fan TPC (tach pulse count)
9431996f 360 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
c8de8362
GR		 361 * is configured in legacy (non-tpc) mode
362 */
9431996f
JH		 363static inline int FAN_TPC_FROM_REG(int reg)
364{
365 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
366}
367
c8de8362
GR		 368/*
369 * Fan type
9431996f 370 * The type of a fan is expressed in number of pulses-per-revolution that it
c8de8362
GR		 371 * emits
372 */
9431996f
JH		 373static inline int FAN_TYPE_FROM_REG(int reg)
374{
375 int edge = (reg >> 1) & 0x03;
376
377 return (edge > 0) ? 1 << (edge - 1) : 0;
378}
379
380static inline int FAN_TYPE_TO_REG(int val, int reg)
381{
382 int edge = (val == 4) ? 3 : val;
383
384 return (reg & 0xf9) | (edge << 1);
385}
386
387/* Fan max RPM */
388static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
389 0x11, 0x0f, 0x0e};
390
391static int FAN_MAX_FROM_REG(int reg)
392{
393 int i;
394
395 for (i = 10; i > 0; i--) {
c8de8362 396 if (reg == FAN_MAX[i])
9431996f 397 break;
9431996f
JH		 398 }
399
400 return 1000 + i * 500;
401}
402
403static int FAN_MAX_TO_REG(int val)
404{
405 int i;
406
407 for (i = 10; i > 0; i--) {
c8de8362 408 if (val > (1000 + (i - 1) * 500))
9431996f 409 break;
9431996f
JH		 410 }
411
412 return FAN_MAX[i];
413}
414
c8de8362
GR		 415/*
416 * PWM enable
9431996f
JH		 417 * Register to enable mapping:
418 * 000: 2 fan on zone 1 auto
419 * 001: 2 fan on zone 2 auto
420 * 010: 2 fan on zone 3 auto
421 * 011: 0 fan full on
422 * 100: -1 fan disabled
423 * 101: 2 fan on hottest of zones 2,3 auto
424 * 110: 2 fan on hottest of zones 1,2,3 auto
c8de8362
GR		 425 * 111: 1 fan in manual mode
426 */
9431996f
JH		 427static inline int PWM_EN_FROM_REG(int reg)
428{
429 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
430
431 return en[(reg >> 5) & 0x07];
432}
433
434static inline int PWM_EN_TO_REG(int val, int reg)
435{
436 int en = (val == 1) ? 7 : 3;
437
438 return (reg & 0x1f) | ((en & 0x07) << 5);
439}
440
c8de8362
GR		 441/*
442 * PWM auto channels zone
9431996f
JH		 443 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
444 * corresponding to zone x+1):
445 * 000: 001 fan on zone 1 auto
446 * 001: 010 fan on zone 2 auto
447 * 010: 100 fan on zone 3 auto
448 * 011: 000 fan full on
449 * 100: 000 fan disabled
450 * 101: 110 fan on hottest of zones 2,3 auto
451 * 110: 111 fan on hottest of zones 1,2,3 auto
c8de8362
GR		 452 * 111: 000 fan in manual mode
453 */
9431996f
JH		 454static inline int PWM_ACZ_FROM_REG(int reg)
455{
456 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
457
458 return acz[(reg >> 5) & 0x07];
459}
460
461static inline int PWM_ACZ_TO_REG(int val, int reg)
462{
463 int acz = (val == 4) ? 2 : val - 1;
464
465 return (reg & 0x1f) | ((acz & 0x07) << 5);
466}
467
468/* PWM frequency */
469static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
470 15000, 20000, 30000, 25000, 0, 0, 0, 0};
471
472static inline int PWM_FREQ_FROM_REG(int reg)
473{
474 return PWM_FREQ[reg & 0x0f];
475}
476
477static int PWM_FREQ_TO_REG(int val, int reg)
478{
479 int i;
480
481 /* the first two cases are special - stupid chip design! */
482 if (val > 27500) {
483 i = 10;
484 } else if (val > 22500) {
485 i = 11;
486 } else {
487 for (i = 9; i > 0; i--) {
c8de8362 488 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
9431996f 489 break;
9431996f
JH		 490 }
491 }
492
493 return (reg & 0xf0) | i;
494}
495
c8de8362
GR		 496/*
497 * PWM ramp rate
9431996f
JH		 498 * Register layout:
499 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
c8de8362
GR		 500 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
501 */
9431996f
JH		 502static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
503
504static inline int PWM_RR_FROM_REG(int reg, int ix)
505{
506 int rr = (ix == 1) ? reg >> 4 : reg;
507
508 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
509}
510
511static int PWM_RR_TO_REG(int val, int ix, int reg)
512{
513 int i;
514
515 for (i = 0; i < 7; i++) {
c8de8362 516 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
9431996f 517 break;
9431996f
JH		 518 }
519
520 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
521}
522
523/* PWM ramp rate enable */
524static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
525{
526 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
527}
528
529static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg)
530{
531 int en = (ix == 1) ? 0x80 : 0x08;
532
533 return val ? reg | en : reg & ~en;
534}
535
c8de8362
GR		 536/*
537 * PWM min/off
9431996f 538 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
c8de8362
GR		 539 * the register layout).
540 */
9431996f
JH		 541static inline int PWM_OFF_FROM_REG(int reg, int ix)
542{
543 return (reg >> (ix + 5)) & 0x01;
544}
545
546static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
547{
548 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
549}
550
551/* ---------------------------------------------------------------------
552 * Device I/O access
e95c237d
JH		 553 *
554 * ISA access is performed through an index/data register pair and needs to
555 * be protected by a mutex during runtime (not required for initialization).
556 * We use data->update_lock for this and need to ensure that we acquire it
557 * before calling dme1737_read or dme1737_write.
9431996f
JH		 558 * --------------------------------------------------------------------- */
559
dbc2bc25 560static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
9431996f 561{
dbc2bc25 562 struct i2c_client *client = data->client;
e95c237d 563 s32 val;
9431996f 564
dbc2bc25 565 if (client) { /* I2C device */
e95c237d
JH		 566 val = i2c_smbus_read_byte_data(client, reg);
567
568 if (val < 0) {
569 dev_warn(&client->dev, "Read from register "
570 "0x%02x failed! Please report to the driver "
571 "maintainer.\n", reg);
572 }
573 } else { /* ISA device */
dbc2bc25
JD		 574 outb(reg, data->addr);
575 val = inb(data->addr + 1);
9431996f
JH		 576 }
577
578 return val;
579}
580
dbc2bc25 581static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
9431996f 582{
dbc2bc25 583 struct i2c_client *client = data->client;
e95c237d
JH		 584 s32 res = 0;
585
dbc2bc25 586 if (client) { /* I2C device */
e95c237d 587 res = i2c_smbus_write_byte_data(client, reg, val);
9431996f 588
e95c237d
JH		 589 if (res < 0) {
590 dev_warn(&client->dev, "Write to register "
591 "0x%02x failed! Please report to the driver "
592 "maintainer.\n", reg);
593 }
594 } else { /* ISA device */
dbc2bc25
JD		 595 outb(reg, data->addr);
596 outb(val, data->addr + 1);
9431996f
JH		 597 }
598
599 return res;
600}
601
602static struct dme1737_data *dme1737_update_device(struct device *dev)
603{
b237eb25 604 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f 605 int ix;
d4b94e1f 606 u8 lsb[6];
9431996f
JH		 607
608 mutex_lock(&data->update_lock);
609
610 /* Enable a Vbat monitoring cycle every 10 mins */
611 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
dbc2bc25 612 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
9431996f
JH		 613 DME1737_REG_CONFIG) | 0x10);
614 data->last_vbat = jiffies;
615 }
616
617 /* Sample register contents every 1 sec */
618 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
ea694431 619 if (data->has_features & HAS_VID) {
dbc2bc25 620 data->vid = dme1737_read(data, DME1737_REG_VID) &
549edb83
JH		 621 0x3f;
622 }
9431996f
JH		 623
624 /* In (voltage) registers */
625 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
c8de8362
GR		 626 /*
627 * Voltage inputs are stored as 16 bit values even
9431996f 628 * though they have only 12 bits resolution. This is
c8de8362
GR		 629 * to make it consistent with the temp inputs.
630 */
631 if (ix == 7 && !(data->has_features & HAS_IN7))
d4b94e1f 632 continue;
dbc2bc25 633 data->in[ix] = dme1737_read(data,
9431996f 634 DME1737_REG_IN(ix)) << 8;
dbc2bc25 635 data->in_min[ix] = dme1737_read(data,
9431996f 636 DME1737_REG_IN_MIN(ix));
dbc2bc25 637 data->in_max[ix] = dme1737_read(data,
9431996f
JH		 638 DME1737_REG_IN_MAX(ix));
639 }
640
641 /* Temp registers */
642 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
c8de8362
GR		 643 /*
644 * Temp inputs are stored as 16 bit values even
9431996f
JH		 645 * though they have only 12 bits resolution. This is
646 * to take advantage of implicit conversions between
647 * register values (2's complement) and temp values
c8de8362
GR		 648 * (signed decimal).
649 */
dbc2bc25 650 data->temp[ix] = dme1737_read(data,
9431996f 651 DME1737_REG_TEMP(ix)) << 8;
dbc2bc25 652 data->temp_min[ix] = dme1737_read(data,
9431996f 653 DME1737_REG_TEMP_MIN(ix));
dbc2bc25 654 data->temp_max[ix] = dme1737_read(data,
9431996f 655 DME1737_REG_TEMP_MAX(ix));
ea694431 656 if (data->has_features & HAS_TEMP_OFFSET) {
dbc2bc25 657 data->temp_offset[ix] = dme1737_read(data,
549edb83
JH		 658 DME1737_REG_TEMP_OFFSET(ix));
659 }
9431996f
JH		 660 }
661
c8de8362
GR		 662 /*
663 * In and temp LSB registers
9431996f
JH		 664 * The LSBs are latched when the MSBs are read, so the order in
665 * which the registers are read (MSB first, then LSB) is
c8de8362
GR		 666 * important!
667 */
9431996f 668 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
c8de8362 669 if (ix == 5 && !(data->has_features & HAS_IN7))
d4b94e1f 670 continue;
dbc2bc25 671 lsb[ix] = dme1737_read(data,
9431996f
JH		 672 DME1737_REG_IN_TEMP_LSB(ix));
673 }
674 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
c8de8362 675 if (ix == 7 && !(data->has_features & HAS_IN7))
d4b94e1f 676 continue;
9431996f
JH		 677 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
678 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
679 }
680 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
681 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
682 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
683 }
684
685 /* Fan registers */
686 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
c8de8362
GR		 687 /*
688 * Skip reading registers if optional fans are not
689 * present
690 */
691 if (!(data->has_features & HAS_FAN(ix)))
9431996f 692 continue;
dbc2bc25 693 data->fan[ix] = dme1737_read(data,
9431996f 694 DME1737_REG_FAN(ix));
dbc2bc25 695 data->fan[ix] |= dme1737_read(data,
9431996f 696 DME1737_REG_FAN(ix) + 1) << 8;
dbc2bc25 697 data->fan_min[ix] = dme1737_read(data,
9431996f 698 DME1737_REG_FAN_MIN(ix));
dbc2bc25 699 data->fan_min[ix] |= dme1737_read(data,
9431996f 700 DME1737_REG_FAN_MIN(ix) + 1) << 8;
dbc2bc25 701 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 702 DME1737_REG_FAN_OPT(ix));
703 /* fan_max exists only for fan[5-6] */
704 if (ix > 3) {
dbc2bc25 705 data->fan_max[ix - 4] = dme1737_read(data,
9431996f
JH		 706 DME1737_REG_FAN_MAX(ix));
707 }
708 }
709
710 /* PWM registers */
711 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
c8de8362
GR		 712 /*
713 * Skip reading registers if optional PWMs are not
714 * present
715 */
716 if (!(data->has_features & HAS_PWM(ix)))
9431996f 717 continue;
dbc2bc25 718 data->pwm[ix] = dme1737_read(data,
9431996f 719 DME1737_REG_PWM(ix));
dbc2bc25 720 data->pwm_freq[ix] = dme1737_read(data,
9431996f
JH		 721 DME1737_REG_PWM_FREQ(ix));
722 /* pwm_config and pwm_min exist only for pwm[1-3] */
723 if (ix < 3) {
dbc2bc25 724 data->pwm_config[ix] = dme1737_read(data,
9431996f 725 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 726 data->pwm_min[ix] = dme1737_read(data,
9431996f
JH		 727 DME1737_REG_PWM_MIN(ix));
728 }
729 }
730 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
dbc2bc25 731 data->pwm_rr[ix] = dme1737_read(data,
9431996f
JH		 732 DME1737_REG_PWM_RR(ix));
733 }
734
735 /* Thermal zone registers */
736 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
ea694431 737 /* Skip reading registers if zone3 is not present */
c8de8362 738 if ((ix == 2) && !(data->has_features & HAS_ZONE3))
ea694431 739 continue;
ea694431
JH		 740 /* sch5127 zone2 registers are special */
741 if ((ix == 1) && (data->type == sch5127)) {
742 data->zone_low[1] = dme1737_read(data,
743 DME1737_REG_ZONE_LOW(2));
744 data->zone_abs[1] = dme1737_read(data,
745 DME1737_REG_ZONE_ABS(2));
746 } else {
747 data->zone_low[ix] = dme1737_read(data,
748 DME1737_REG_ZONE_LOW(ix));
749 data->zone_abs[ix] = dme1737_read(data,
750 DME1737_REG_ZONE_ABS(ix));
751 }
9431996f 752 }
ea694431 753 if (data->has_features & HAS_ZONE_HYST) {
549edb83 754 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
dbc2bc25 755 data->zone_hyst[ix] = dme1737_read(data,
9431996f 756 DME1737_REG_ZONE_HYST(ix));
549edb83 757 }
9431996f
JH		 758 }
759
760 /* Alarm registers */
dbc2bc25 761 data->alarms = dme1737_read(data,
9431996f 762 DME1737_REG_ALARM1);
c8de8362
GR		 763 /*
764 * Bit 7 tells us if the other alarm registers are non-zero and
765 * therefore also need to be read
766 */
9431996f 767 if (data->alarms & 0x80) {
dbc2bc25 768 data->alarms |= dme1737_read(data,
9431996f 769 DME1737_REG_ALARM2) << 8;
dbc2bc25 770 data->alarms |= dme1737_read(data,
9431996f
JH		 771 DME1737_REG_ALARM3) << 16;
772 }
773
c8de8362
GR		 774 /*
775 * The ISA chips require explicit clearing of alarm bits.
e95c237d 776 * Don't worry, an alarm will come back if the condition
c8de8362
GR		 777 * that causes it still exists
778 */
dbc2bc25 779 if (!data->client) {
c8de8362
GR		 780 if (data->alarms & 0xff0000)
781 dme1737_write(data, DME1737_REG_ALARM3, 0xff);
782 if (data->alarms & 0xff00)
783 dme1737_write(data, DME1737_REG_ALARM2, 0xff);
784 if (data->alarms & 0xff)
785 dme1737_write(data, DME1737_REG_ALARM1, 0xff);
e95c237d
JH		 786 }
787
9431996f
JH		 788 data->last_update = jiffies;
789 data->valid = 1;
790 }
791
792 mutex_unlock(&data->update_lock);
793
794 return data;
795}
796
797/* ---------------------------------------------------------------------
798 * Voltage sysfs attributes
d4b94e1f 799 * ix = [0-7]
9431996f
JH		 800 * --------------------------------------------------------------------- */
801
802#define SYS_IN_INPUT 0
803#define SYS_IN_MIN 1
804#define SYS_IN_MAX 2
805#define SYS_IN_ALARM 3
806
807static ssize_t show_in(struct device *dev, struct device_attribute *attr,
808 char *buf)
809{
810 struct dme1737_data *data = dme1737_update_device(dev);
811 struct sensor_device_attribute_2
812 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
813 int ix = sensor_attr_2->index;
814 int fn = sensor_attr_2->nr;
815 int res;
816
817 switch (fn) {
818 case SYS_IN_INPUT:
549edb83 819 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
9431996f
JH		 820 break;
821 case SYS_IN_MIN:
549edb83 822 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
9431996f
JH		 823 break;
824 case SYS_IN_MAX:
549edb83 825 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
9431996f
JH		 826 break;
827 case SYS_IN_ALARM:
828 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
829 break;
830 default:
831 res = 0;
b237eb25 832 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 833 }
834
835 return sprintf(buf, "%d\n", res);
836}
837
838static ssize_t set_in(struct device *dev, struct device_attribute *attr,
839 const char *buf, size_t count)
840{
b237eb25 841 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 842 struct sensor_device_attribute_2
843 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
844 int ix = sensor_attr_2->index;
845 int fn = sensor_attr_2->nr;
c8de8362
GR		 846 long val;
847 int err;
848
849 err = kstrtol(buf, 10, &val);
850 if (err)
851 return err;
9431996f
JH		 852
853 mutex_lock(&data->update_lock);
854 switch (fn) {
855 case SYS_IN_MIN:
549edb83 856 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 857 dme1737_write(data, DME1737_REG_IN_MIN(ix),
9431996f
JH		 858 data->in_min[ix]);
859 break;
860 case SYS_IN_MAX:
549edb83 861 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 862 dme1737_write(data, DME1737_REG_IN_MAX(ix),
9431996f
JH		 863 data->in_max[ix]);
864 break;
865 default:
b237eb25 866 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 867 }
868 mutex_unlock(&data->update_lock);
869
870 return count;
871}
872
873/* ---------------------------------------------------------------------
874 * Temperature sysfs attributes
875 * ix = [0-2]
876 * --------------------------------------------------------------------- */
877
878#define SYS_TEMP_INPUT 0
879#define SYS_TEMP_MIN 1
880#define SYS_TEMP_MAX 2
881#define SYS_TEMP_OFFSET 3
882#define SYS_TEMP_ALARM 4
883#define SYS_TEMP_FAULT 5
884
885static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
886 char *buf)
887{
888 struct dme1737_data *data = dme1737_update_device(dev);
889 struct sensor_device_attribute_2
890 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
891 int ix = sensor_attr_2->index;
892 int fn = sensor_attr_2->nr;
893 int res;
894
895 switch (fn) {
896 case SYS_TEMP_INPUT:
897 res = TEMP_FROM_REG(data->temp[ix], 16);
898 break;
899 case SYS_TEMP_MIN:
900 res = TEMP_FROM_REG(data->temp_min[ix], 8);
901 break;
902 case SYS_TEMP_MAX:
903 res = TEMP_FROM_REG(data->temp_max[ix], 8);
904 break;
905 case SYS_TEMP_OFFSET:
906 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
907 break;
908 case SYS_TEMP_ALARM:
909 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
910 break;
911 case SYS_TEMP_FAULT:
c0f31403 912 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
9431996f
JH		 913 break;
914 default:
915 res = 0;
b237eb25 916 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 917 }
918
919 return sprintf(buf, "%d\n", res);
920}
921
922static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
923 const char *buf, size_t count)
924{
b237eb25 925 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 926 struct sensor_device_attribute_2
927 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
928 int ix = sensor_attr_2->index;
929 int fn = sensor_attr_2->nr;
c8de8362
GR		 930 long val;
931 int err;
932
933 err = kstrtol(buf, 10, &val);
934 if (err)
935 return err;
9431996f
JH		 936
937 mutex_lock(&data->update_lock);
938 switch (fn) {
939 case SYS_TEMP_MIN:
940 data->temp_min[ix] = TEMP_TO_REG(val);
dbc2bc25 941 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
9431996f
JH		 942 data->temp_min[ix]);
943 break;
944 case SYS_TEMP_MAX:
945 data->temp_max[ix] = TEMP_TO_REG(val);
dbc2bc25 946 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
9431996f
JH		 947 data->temp_max[ix]);
948 break;
949 case SYS_TEMP_OFFSET:
950 data->temp_offset[ix] = TEMP_TO_REG(val);
dbc2bc25 951 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
9431996f
JH		 952 data->temp_offset[ix]);
953 break;
954 default:
b237eb25 955 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 956 }
957 mutex_unlock(&data->update_lock);
958
959 return count;
960}
961
962/* ---------------------------------------------------------------------
963 * Zone sysfs attributes
964 * ix = [0-2]
965 * --------------------------------------------------------------------- */
966
967#define SYS_ZONE_AUTO_CHANNELS_TEMP 0
968#define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
969#define SYS_ZONE_AUTO_POINT1_TEMP 2
970#define SYS_ZONE_AUTO_POINT2_TEMP 3
971#define SYS_ZONE_AUTO_POINT3_TEMP 4
972
973static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
974 char *buf)
975{
976 struct dme1737_data *data = dme1737_update_device(dev);
977 struct sensor_device_attribute_2
978 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
979 int ix = sensor_attr_2->index;
980 int fn = sensor_attr_2->nr;
981 int res;
982
983 switch (fn) {
984 case SYS_ZONE_AUTO_CHANNELS_TEMP:
985 /* check config2 for non-standard temp-to-zone mapping */
c8de8362 986 if ((ix == 1) && (data->config2 & 0x02))
9431996f 987 res = 4;
c8de8362 988 else
9431996f 989 res = 1 << ix;
9431996f
JH		 990 break;
991 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
992 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
993 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
994 break;
995 case SYS_ZONE_AUTO_POINT1_TEMP:
996 res = TEMP_FROM_REG(data->zone_low[ix], 8);
997 break;
998 case SYS_ZONE_AUTO_POINT2_TEMP:
999 /* pwm_freq holds the temp range bits in the upper nibble */
1000 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
1001 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
1002 break;
1003 case SYS_ZONE_AUTO_POINT3_TEMP:
1004 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
1005 break;
1006 default:
1007 res = 0;
b237eb25 1008 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1009 }
1010
1011 return sprintf(buf, "%d\n", res);
1012}
1013
1014static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
1015 const char *buf, size_t count)
1016{
b237eb25 1017 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1018 struct sensor_device_attribute_2
1019 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1020 int ix = sensor_attr_2->index;
1021 int fn = sensor_attr_2->nr;
c8de8362
GR		 1022 long val;
1023 int err;
1024
1025 err = kstrtol(buf, 10, &val);
1026 if (err)
1027 return err;
9431996f
JH		 1028
1029 mutex_lock(&data->update_lock);
1030 switch (fn) {
1031 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
1032 /* Refresh the cache */
dbc2bc25 1033 data->zone_low[ix] = dme1737_read(data,
9431996f
JH		 1034 DME1737_REG_ZONE_LOW(ix));
1035 /* Modify the temp hyst value */
1036 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
1037 TEMP_FROM_REG(data->zone_low[ix], 8) -
dbc2bc25 1038 val, ix, dme1737_read(data,
9431996f 1039 DME1737_REG_ZONE_HYST(ix == 2)));
dbc2bc25 1040 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
9431996f
JH		 1041 data->zone_hyst[ix == 2]);
1042 break;
1043 case SYS_ZONE_AUTO_POINT1_TEMP:
1044 data->zone_low[ix] = TEMP_TO_REG(val);
dbc2bc25 1045 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
9431996f
JH		 1046 data->zone_low[ix]);
1047 break;
1048 case SYS_ZONE_AUTO_POINT2_TEMP:
1049 /* Refresh the cache */
dbc2bc25 1050 data->zone_low[ix] = dme1737_read(data,
9431996f 1051 DME1737_REG_ZONE_LOW(ix));
c8de8362
GR		 1052 /*
1053 * Modify the temp range value (which is stored in the upper
1054 * nibble of the pwm_freq register)
1055 */
9431996f
JH		 1056 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1057 TEMP_FROM_REG(data->zone_low[ix], 8),
dbc2bc25 1058 dme1737_read(data,
9431996f 1059 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1060 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1061 data->pwm_freq[ix]);
1062 break;
1063 case SYS_ZONE_AUTO_POINT3_TEMP:
1064 data->zone_abs[ix] = TEMP_TO_REG(val);
dbc2bc25 1065 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
9431996f
JH		 1066 data->zone_abs[ix]);
1067 break;
1068 default:
b237eb25 1069 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1070 }
1071 mutex_unlock(&data->update_lock);
1072
1073 return count;
1074}
1075
1076/* ---------------------------------------------------------------------
1077 * Fan sysfs attributes
1078 * ix = [0-5]
1079 * --------------------------------------------------------------------- */
1080
1081#define SYS_FAN_INPUT 0
1082#define SYS_FAN_MIN 1
1083#define SYS_FAN_MAX 2
1084#define SYS_FAN_ALARM 3
1085#define SYS_FAN_TYPE 4
1086
1087static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1088 char *buf)
1089{
1090 struct dme1737_data *data = dme1737_update_device(dev);
1091 struct sensor_device_attribute_2
1092 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1093 int ix = sensor_attr_2->index;
1094 int fn = sensor_attr_2->nr;
1095 int res;
1096
1097 switch (fn) {
1098 case SYS_FAN_INPUT:
1099 res = FAN_FROM_REG(data->fan[ix],
1100 ix < 4 ? 0 :
1101 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1102 break;
1103 case SYS_FAN_MIN:
1104 res = FAN_FROM_REG(data->fan_min[ix],
1105 ix < 4 ? 0 :
1106 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1107 break;
1108 case SYS_FAN_MAX:
1109 /* only valid for fan[5-6] */
1110 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1111 break;
1112 case SYS_FAN_ALARM:
1113 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1114 break;
1115 case SYS_FAN_TYPE:
1116 /* only valid for fan[1-4] */
1117 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1118 break;
1119 default:
1120 res = 0;
b237eb25 1121 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1122 }
1123
1124 return sprintf(buf, "%d\n", res);
1125}
1126
1127static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1128 const char *buf, size_t count)
1129{
b237eb25 1130 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1131 struct sensor_device_attribute_2
1132 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1133 int ix = sensor_attr_2->index;
1134 int fn = sensor_attr_2->nr;
c8de8362
GR		 1135 long val;
1136 int err;
1137
1138 err = kstrtol(buf, 10, &val);
1139 if (err)
1140 return err;
9431996f
JH		 1141
1142 mutex_lock(&data->update_lock);
1143 switch (fn) {
1144 case SYS_FAN_MIN:
1145 if (ix < 4) {
1146 data->fan_min[ix] = FAN_TO_REG(val, 0);
1147 } else {
1148 /* Refresh the cache */
dbc2bc25 1149 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 1150 DME1737_REG_FAN_OPT(ix));
1151 /* Modify the fan min value */
1152 data->fan_min[ix] = FAN_TO_REG(val,
1153 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1154 }
dbc2bc25 1155 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
9431996f 1156 data->fan_min[ix] & 0xff);
dbc2bc25 1157 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
9431996f
JH		 1158 data->fan_min[ix] >> 8);
1159 break;
1160 case SYS_FAN_MAX:
1161 /* Only valid for fan[5-6] */
1162 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
dbc2bc25 1163 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
9431996f
JH		 1164 data->fan_max[ix - 4]);
1165 break;
1166 case SYS_FAN_TYPE:
1167 /* Only valid for fan[1-4] */
1168 if (!(val == 1 || val == 2 || val == 4)) {
1169 count = -EINVAL;
e95c237d 1170 dev_warn(dev, "Fan type value %ld not "
9431996f
JH		 1171 "supported. Choose one of 1, 2, or 4.\n",
1172 val);
1173 goto exit;
1174 }
dbc2bc25 1175 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
9431996f 1176 DME1737_REG_FAN_OPT(ix)));
dbc2bc25 1177 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
9431996f
JH		 1178 data->fan_opt[ix]);
1179 break;
1180 default:
b237eb25 1181 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1182 }
1183exit:
1184 mutex_unlock(&data->update_lock);
1185
1186 return count;
1187}
1188
1189/* ---------------------------------------------------------------------
1190 * PWM sysfs attributes
1191 * ix = [0-4]
1192 * --------------------------------------------------------------------- */
1193
1194#define SYS_PWM 0
1195#define SYS_PWM_FREQ 1
1196#define SYS_PWM_ENABLE 2
1197#define SYS_PWM_RAMP_RATE 3
1198#define SYS_PWM_AUTO_CHANNELS_ZONE 4
1199#define SYS_PWM_AUTO_PWM_MIN 5
1200#define SYS_PWM_AUTO_POINT1_PWM 6
1201#define SYS_PWM_AUTO_POINT2_PWM 7
1202
1203static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1204 char *buf)
1205{
1206 struct dme1737_data *data = dme1737_update_device(dev);
1207 struct sensor_device_attribute_2
1208 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1209 int ix = sensor_attr_2->index;
1210 int fn = sensor_attr_2->nr;
1211 int res;
1212
1213 switch (fn) {
1214 case SYS_PWM:
c8de8362 1215 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
9431996f 1216 res = 255;
c8de8362 1217 else
9431996f 1218 res = data->pwm[ix];
9431996f
JH		 1219 break;
1220 case SYS_PWM_FREQ:
1221 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1222 break;
1223 case SYS_PWM_ENABLE:
c8de8362 1224 if (ix >= 3)
9431996f 1225 res = 1; /* pwm[5-6] hard-wired to manual mode */
c8de8362 1226 else
9431996f 1227 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
9431996f
JH		 1228 break;
1229 case SYS_PWM_RAMP_RATE:
1230 /* Only valid for pwm[1-3] */
1231 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1232 break;
1233 case SYS_PWM_AUTO_CHANNELS_ZONE:
1234 /* Only valid for pwm[1-3] */
c8de8362 1235 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
9431996f 1236 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
c8de8362 1237 else
9431996f 1238 res = data->pwm_acz[ix];
9431996f
JH		 1239 break;
1240 case SYS_PWM_AUTO_PWM_MIN:
1241 /* Only valid for pwm[1-3] */
c8de8362 1242 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
9431996f 1243 res = data->pwm_min[ix];
c8de8362 1244 else
9431996f 1245 res = 0;
9431996f
JH		 1246 break;
1247 case SYS_PWM_AUTO_POINT1_PWM:
1248 /* Only valid for pwm[1-3] */
1249 res = data->pwm_min[ix];
1250 break;
1251 case SYS_PWM_AUTO_POINT2_PWM:
1252 /* Only valid for pwm[1-3] */
1253 res = 255; /* hard-wired */
1254 break;
1255 default:
1256 res = 0;
b237eb25 1257 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1258 }
1259
1260 return sprintf(buf, "%d\n", res);
1261}
1262
73ce48f6 1263static struct attribute *dme1737_pwm_chmod_attr[];
48176a97 1264static void dme1737_chmod_file(struct device*, struct attribute*, umode_t);
9431996f
JH		 1265
1266static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1267 const char *buf, size_t count)
1268{
b237eb25 1269 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1270 struct sensor_device_attribute_2
1271 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1272 int ix = sensor_attr_2->index;
1273 int fn = sensor_attr_2->nr;
c8de8362
GR		 1274 long val;
1275 int err;
1276
1277 err = kstrtol(buf, 10, &val);
1278 if (err)
1279 return err;
9431996f
JH		 1280
1281 mutex_lock(&data->update_lock);
1282 switch (fn) {
1283 case SYS_PWM:
2a844c14 1284 data->pwm[ix] = clamp_val(val, 0, 255);
dbc2bc25 1285 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
9431996f
JH		 1286 break;
1287 case SYS_PWM_FREQ:
dbc2bc25 1288 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
9431996f 1289 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1290 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1291 data->pwm_freq[ix]);
1292 break;
1293 case SYS_PWM_ENABLE:
1294 /* Only valid for pwm[1-3] */
1295 if (val < 0 || val > 2) {
1296 count = -EINVAL;
e95c237d 1297 dev_warn(dev, "PWM enable %ld not "
9431996f
JH		 1298 "supported. Choose one of 0, 1, or 2.\n",
1299 val);
1300 goto exit;
1301 }
1302 /* Refresh the cache */
dbc2bc25 1303 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1304 DME1737_REG_PWM_CONFIG(ix));
1305 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1306 /* Bail out if no change */
1307 goto exit;
1308 }
1309 /* Do some housekeeping if we are currently in auto mode */
1310 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1311 /* Save the current zone channel assignment */
1312 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1313 data->pwm_config[ix]);
1314 /* Save the current ramp rate state and disable it */
dbc2bc25 1315 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1316 DME1737_REG_PWM_RR(ix > 0));
1317 data->pwm_rr_en &= ~(1 << ix);
1318 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1319 data->pwm_rr_en |= (1 << ix);
1320 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1321 data->pwm_rr[ix > 0]);
dbc2bc25 1322 dme1737_write(data,
9431996f
JH		 1323 DME1737_REG_PWM_RR(ix > 0),
1324 data->pwm_rr[ix > 0]);
1325 }
1326 }
1327 /* Set the new PWM mode */
1328 switch (val) {
1329 case 0:
1330 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1331 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1332 S_IRUGO);
1333 /* Turn fan fully on */
1334 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1335 data->pwm_config[ix]);
dbc2bc25 1336 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1337 data->pwm_config[ix]);
1338 break;
1339 case 1:
1340 /* Turn on manual mode */
1341 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1342 data->pwm_config[ix]);
dbc2bc25 1343 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1344 data->pwm_config[ix]);
1345 /* Change permissions of pwm[ix] to read-writeable */
73ce48f6 1346 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1347 S_IRUGO | S_IWUSR);
1348 break;
1349 case 2:
1350 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1351 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f 1352 S_IRUGO);
c8de8362
GR		 1353 /*
1354 * Turn on auto mode using the saved zone channel
1355 * assignment
1356 */
9431996f
JH		 1357 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1358 data->pwm_acz[ix],
1359 data->pwm_config[ix]);
dbc2bc25 1360 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1361 data->pwm_config[ix]);
1362 /* Enable PWM ramp rate if previously enabled */
1363 if (data->pwm_rr_en & (1 << ix)) {
1364 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
dbc2bc25 1365 dme1737_read(data,
9431996f 1366 DME1737_REG_PWM_RR(ix > 0)));
dbc2bc25 1367 dme1737_write(data,
9431996f
JH		 1368 DME1737_REG_PWM_RR(ix > 0),
1369 data->pwm_rr[ix > 0]);
1370 }
1371 break;
1372 }
1373 break;
1374 case SYS_PWM_RAMP_RATE:
1375 /* Only valid for pwm[1-3] */
1376 /* Refresh the cache */
dbc2bc25 1377 data->pwm_config[ix] = dme1737_read(data,
9431996f 1378 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 1379 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1380 DME1737_REG_PWM_RR(ix > 0));
1381 /* Set the ramp rate value */
1382 if (val > 0) {
1383 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1384 data->pwm_rr[ix > 0]);
1385 }
c8de8362
GR		 1386 /*
1387 * Enable/disable the feature only if the associated PWM
1388 * output is in automatic mode.
1389 */
9431996f
JH		 1390 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1391 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1392 data->pwm_rr[ix > 0]);
1393 }
dbc2bc25 1394 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
9431996f
JH		 1395 data->pwm_rr[ix > 0]);
1396 break;
1397 case SYS_PWM_AUTO_CHANNELS_ZONE:
1398 /* Only valid for pwm[1-3] */
1399 if (!(val == 1 || val == 2 || val == 4 ||
1400 val == 6 || val == 7)) {
1401 count = -EINVAL;
e95c237d 1402 dev_warn(dev, "PWM auto channels zone %ld "
9431996f
JH		 1403 "not supported. Choose one of 1, 2, 4, 6, "
1404 "or 7.\n", val);
1405 goto exit;
1406 }
1407 /* Refresh the cache */
dbc2bc25 1408 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1409 DME1737_REG_PWM_CONFIG(ix));
1410 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
c8de8362
GR		 1411 /*
1412 * PWM is already in auto mode so update the temp
1413 * channel assignment
1414 */
9431996f
JH		 1415 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1416 data->pwm_config[ix]);
dbc2bc25 1417 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1418 data->pwm_config[ix]);
1419 } else {
c8de8362
GR		 1420 /*
1421 * PWM is not in auto mode so we save the temp
1422 * channel assignment for later use
1423 */
9431996f
JH		 1424 data->pwm_acz[ix] = val;
1425 }
1426 break;
1427 case SYS_PWM_AUTO_PWM_MIN:
1428 /* Only valid for pwm[1-3] */
1429 /* Refresh the cache */
dbc2bc25 1430 data->pwm_min[ix] = dme1737_read(data,
9431996f 1431 DME1737_REG_PWM_MIN(ix));
c8de8362
GR		 1432 /*
1433 * There are only 2 values supported for the auto_pwm_min
9431996f
JH		 1434 * value: 0 or auto_point1_pwm. So if the temperature drops
1435 * below the auto_point1_temp_hyst value, the fan either turns
c8de8362
GR		 1436 * off or runs at auto_point1_pwm duty-cycle.
1437 */
9431996f
JH		 1438 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1439 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
dbc2bc25 1440 dme1737_read(data,
9431996f 1441 DME1737_REG_PWM_RR(0)));
9431996f
JH		 1442 } else {
1443 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
dbc2bc25 1444 dme1737_read(data,
9431996f 1445 DME1737_REG_PWM_RR(0)));
9431996f 1446 }
dbc2bc25 1447 dme1737_write(data, DME1737_REG_PWM_RR(0),
9431996f
JH		 1448 data->pwm_rr[0]);
1449 break;
1450 case SYS_PWM_AUTO_POINT1_PWM:
1451 /* Only valid for pwm[1-3] */
2a844c14 1452 data->pwm_min[ix] = clamp_val(val, 0, 255);
dbc2bc25 1453 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
9431996f
JH		 1454 data->pwm_min[ix]);
1455 break;
1456 default:
b237eb25 1457 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1458 }
1459exit:
1460 mutex_unlock(&data->update_lock);
1461
1462 return count;
1463}
1464
1465/* ---------------------------------------------------------------------
1466 * Miscellaneous sysfs attributes
1467 * --------------------------------------------------------------------- */
1468
1469static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1470 char *buf)
1471{
1472 struct i2c_client *client = to_i2c_client(dev);
1473 struct dme1737_data *data = i2c_get_clientdata(client);
1474
1475 return sprintf(buf, "%d\n", data->vrm);
1476}
1477
1478static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1479 const char *buf, size_t count)
1480{
b237eb25 1481 struct dme1737_data *data = dev_get_drvdata(dev);
c8de8362
GR		 1482 long val;
1483 int err;
1484
1485 err = kstrtol(buf, 10, &val);
1486 if (err)
1487 return err;
9431996f
JH		 1488
1489 data->vrm = val;
1490 return count;
1491}
1492
1493static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1494 char *buf)
1495{
1496 struct dme1737_data *data = dme1737_update_device(dev);
1497
1498 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1499}
1500
e95c237d
JH		 1501static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1502 char *buf)
1503{
1504 struct dme1737_data *data = dev_get_drvdata(dev);
1505
dbc2bc25 1506 return sprintf(buf, "%s\n", data->name);
e95c237d
JH		 1507}
1508
9431996f
JH		 1509/* ---------------------------------------------------------------------
1510 * Sysfs device attribute defines and structs
1511 * --------------------------------------------------------------------- */
1512
d4b94e1f 1513/* Voltages 0-7 */
9431996f
JH		 1514
1515#define SENSOR_DEVICE_ATTR_IN(ix) \
1516static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
b237eb25 1517 show_in, NULL, SYS_IN_INPUT, ix); \
9431996f 1518static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1519 show_in, set_in, SYS_IN_MIN, ix); \
9431996f 1520static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1521 show_in, set_in, SYS_IN_MAX, ix); \
9431996f 1522static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
b237eb25 1523 show_in, NULL, SYS_IN_ALARM, ix)
9431996f
JH		 1524
1525SENSOR_DEVICE_ATTR_IN(0);
1526SENSOR_DEVICE_ATTR_IN(1);
1527SENSOR_DEVICE_ATTR_IN(2);
1528SENSOR_DEVICE_ATTR_IN(3);
1529SENSOR_DEVICE_ATTR_IN(4);
1530SENSOR_DEVICE_ATTR_IN(5);
1531SENSOR_DEVICE_ATTR_IN(6);
d4b94e1f 1532SENSOR_DEVICE_ATTR_IN(7);
9431996f
JH		 1533
1534/* Temperatures 1-3 */
1535
1536#define SENSOR_DEVICE_ATTR_TEMP(ix) \
1537static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
b237eb25 1538 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
9431996f 1539static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1540 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
9431996f 1541static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1542 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
9431996f 1543static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
b237eb25 1544 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
9431996f 1545static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
b237eb25 1546 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
9431996f 1547static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
b237eb25 1548 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
9431996f
JH		 1549
1550SENSOR_DEVICE_ATTR_TEMP(1);
1551SENSOR_DEVICE_ATTR_TEMP(2);
1552SENSOR_DEVICE_ATTR_TEMP(3);
1553
1554/* Zones 1-3 */
1555
1556#define SENSOR_DEVICE_ATTR_ZONE(ix) \
1557static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
b237eb25 1558 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
9431996f 1559static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
b237eb25 1560 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
9431996f 1561static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
b237eb25 1562 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
9431996f 1563static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
b237eb25 1564 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
9431996f 1565static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
b237eb25 1566 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
9431996f
JH		 1567
1568SENSOR_DEVICE_ATTR_ZONE(1);
1569SENSOR_DEVICE_ATTR_ZONE(2);
1570SENSOR_DEVICE_ATTR_ZONE(3);
1571
1572/* Fans 1-4 */
1573
1574#define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1575static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1576 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1577static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1578 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1579static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1580 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1581static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
b237eb25 1582 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
9431996f
JH		 1583
1584SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1585SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1586SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1587SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1588
1589/* Fans 5-6 */
1590
1591#define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1592static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1593 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1594static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1595 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1596static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1597 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1598static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1599 show_fan, set_fan, SYS_FAN_MAX, ix-1)
9431996f
JH		 1600
1601SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1602SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1603
1604/* PWMs 1-3 */
1605
1606#define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1607static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1608 show_pwm, set_pwm, SYS_PWM, ix-1); \
9431996f 1609static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1610 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1611static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1612 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
9431996f 1613static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
b237eb25 1614 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
9431996f 1615static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
b237eb25 1616 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
9431996f 1617static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
b237eb25 1618 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
9431996f 1619static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
b237eb25 1620 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
9431996f 1621static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
b237eb25 1622 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
9431996f
JH		 1623
1624SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1625SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1626SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1627
1628/* PWMs 5-6 */
1629
1630#define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
9b257714 1631static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1632 show_pwm, set_pwm, SYS_PWM, ix-1); \
9b257714 1633static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1634 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1635static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1636 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
9431996f
JH		 1637
1638SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1639SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1640
1641/* Misc */
1642
1643static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1644static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
e95c237d 1645static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
9431996f 1646
c8de8362
GR		 1647/*
1648 * This struct holds all the attributes that are always present and need to be
9431996f
JH		 1649 * created unconditionally. The attributes that need modification of their
1650 * permissions are created read-only and write permissions are added or removed
c8de8362
GR		 1651 * on the fly when required
1652 */
06f3d9fb 1653static struct attribute *dme1737_attr[] = {
b237eb25 1654 /* Voltages */
9b257714
JH		 1655 &sensor_dev_attr_in0_input.dev_attr.attr,
1656 &sensor_dev_attr_in0_min.dev_attr.attr,
1657 &sensor_dev_attr_in0_max.dev_attr.attr,
1658 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1659 &sensor_dev_attr_in1_input.dev_attr.attr,
1660 &sensor_dev_attr_in1_min.dev_attr.attr,
1661 &sensor_dev_attr_in1_max.dev_attr.attr,
1662 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1663 &sensor_dev_attr_in2_input.dev_attr.attr,
1664 &sensor_dev_attr_in2_min.dev_attr.attr,
1665 &sensor_dev_attr_in2_max.dev_attr.attr,
1666 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1667 &sensor_dev_attr_in3_input.dev_attr.attr,
1668 &sensor_dev_attr_in3_min.dev_attr.attr,
1669 &sensor_dev_attr_in3_max.dev_attr.attr,
1670 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1671 &sensor_dev_attr_in4_input.dev_attr.attr,
1672 &sensor_dev_attr_in4_min.dev_attr.attr,
1673 &sensor_dev_attr_in4_max.dev_attr.attr,
1674 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1675 &sensor_dev_attr_in5_input.dev_attr.attr,
1676 &sensor_dev_attr_in5_min.dev_attr.attr,
1677 &sensor_dev_attr_in5_max.dev_attr.attr,
1678 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1679 &sensor_dev_attr_in6_input.dev_attr.attr,
1680 &sensor_dev_attr_in6_min.dev_attr.attr,
1681 &sensor_dev_attr_in6_max.dev_attr.attr,
1682 &sensor_dev_attr_in6_alarm.dev_attr.attr,
b237eb25 1683 /* Temperatures */
9b257714
JH		 1684 &sensor_dev_attr_temp1_input.dev_attr.attr,
1685 &sensor_dev_attr_temp1_min.dev_attr.attr,
1686 &sensor_dev_attr_temp1_max.dev_attr.attr,
1687 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1688 &sensor_dev_attr_temp1_fault.dev_attr.attr,
9b257714
JH		 1689 &sensor_dev_attr_temp2_input.dev_attr.attr,
1690 &sensor_dev_attr_temp2_min.dev_attr.attr,
1691 &sensor_dev_attr_temp2_max.dev_attr.attr,
1692 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1693 &sensor_dev_attr_temp2_fault.dev_attr.attr,
9b257714
JH		 1694 &sensor_dev_attr_temp3_input.dev_attr.attr,
1695 &sensor_dev_attr_temp3_min.dev_attr.attr,
1696 &sensor_dev_attr_temp3_max.dev_attr.attr,
1697 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1698 &sensor_dev_attr_temp3_fault.dev_attr.attr,
b237eb25 1699 /* Zones */
9b257714
JH		 1700 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1701 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1702 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1703 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
9b257714
JH		 1704 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1705 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1706 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1707 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
549edb83
JH		 1708 NULL
1709};
1710
1711static const struct attribute_group dme1737_group = {
1712 .attrs = dme1737_attr,
1713};
1714
c8de8362
GR		 1715/*
1716 * The following struct holds temp offset attributes, which are not available
ea694431 1717 * in all chips. The following chips support them:
c8de8362
GR		 1718 * DME1737, SCH311x
1719 */
ea694431 1720static struct attribute *dme1737_temp_offset_attr[] = {
549edb83
JH		 1721 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1722 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1723 &sensor_dev_attr_temp3_offset.dev_attr.attr,
9431996f
JH		 1724 NULL
1725};
1726
ea694431
JH		 1727static const struct attribute_group dme1737_temp_offset_group = {
1728 .attrs = dme1737_temp_offset_attr,
9431996f
JH		 1729};
1730
c8de8362
GR		 1731/*
1732 * The following struct holds VID related attributes, which are not available
ea694431 1733 * in all chips. The following chips support them:
c8de8362
GR		 1734 * DME1737
1735 */
9d091446
JD		 1736static struct attribute *dme1737_vid_attr[] = {
1737 &dev_attr_vrm.attr,
1738 &dev_attr_cpu0_vid.attr,
1739 NULL
1740};
1741
1742static const struct attribute_group dme1737_vid_group = {
1743 .attrs = dme1737_vid_attr,
1744};
1745
c8de8362
GR		 1746/*
1747 * The following struct holds temp zone 3 related attributes, which are not
ea694431 1748 * available in all chips. The following chips support them:
c8de8362
GR		 1749 * DME1737, SCH311x, SCH5027
1750 */
ea694431
JH		 1751static struct attribute *dme1737_zone3_attr[] = {
1752 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1753 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1754 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1755 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1756 NULL
1757};
1758
1759static const struct attribute_group dme1737_zone3_group = {
1760 .attrs = dme1737_zone3_attr,
1761};
1762
1763
c8de8362
GR		 1764/*
1765 * The following struct holds temp zone hysteresis related attributes, which
ea694431 1766 * are not available in all chips. The following chips support them:
c8de8362
GR		 1767 * DME1737, SCH311x
1768 */
ea694431
JH		 1769static struct attribute *dme1737_zone_hyst_attr[] = {
1770 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1771 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1772 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1773 NULL
1774};
1775
1776static const struct attribute_group dme1737_zone_hyst_group = {
1777 .attrs = dme1737_zone_hyst_attr,
1778};
1779
c8de8362
GR		 1780/*
1781 * The following struct holds voltage in7 related attributes, which
d4b94e1f 1782 * are not available in all chips. The following chips support them:
c8de8362
GR		 1783 * SCH5127
1784 */
d4b94e1f
JH		 1785static struct attribute *dme1737_in7_attr[] = {
1786 &sensor_dev_attr_in7_input.dev_attr.attr,
1787 &sensor_dev_attr_in7_min.dev_attr.attr,
1788 &sensor_dev_attr_in7_max.dev_attr.attr,
1789 &sensor_dev_attr_in7_alarm.dev_attr.attr,
1790 NULL
1791};
1792
1793static const struct attribute_group dme1737_in7_group = {
1794 .attrs = dme1737_in7_attr,
1795};
1796
c8de8362
GR		 1797/*
1798 * The following structs hold the PWM attributes, some of which are optional.
9431996f 1799 * Their creation depends on the chip configuration which is determined during
c8de8362
GR		 1800 * module load.
1801 */
73ce48f6 1802static struct attribute *dme1737_pwm1_attr[] = {
9b257714
JH		 1803 &sensor_dev_attr_pwm1.dev_attr.attr,
1804 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1805 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1806 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1807 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1808 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1809 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1810 NULL
1811};
73ce48f6 1812static struct attribute *dme1737_pwm2_attr[] = {
9b257714
JH		 1813 &sensor_dev_attr_pwm2.dev_attr.attr,
1814 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1815 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1816 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1817 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1818 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1819 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1820 NULL
1821};
73ce48f6 1822static struct attribute *dme1737_pwm3_attr[] = {
9b257714
JH		 1823 &sensor_dev_attr_pwm3.dev_attr.attr,
1824 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1825 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1826 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1827 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1828 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1829 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1830 NULL
1831};
73ce48f6 1832static struct attribute *dme1737_pwm5_attr[] = {
9b257714
JH		 1833 &sensor_dev_attr_pwm5.dev_attr.attr,
1834 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1835 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
9431996f
JH		 1836 NULL
1837};
73ce48f6 1838static struct attribute *dme1737_pwm6_attr[] = {
9b257714
JH		 1839 &sensor_dev_attr_pwm6.dev_attr.attr,
1840 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1841 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
9431996f
JH		 1842 NULL
1843};
1844
1845static const struct attribute_group dme1737_pwm_group[] = {
73ce48f6
JH		 1846 { .attrs = dme1737_pwm1_attr },
1847 { .attrs = dme1737_pwm2_attr },
1848 { .attrs = dme1737_pwm3_attr },
9431996f 1849 { .attrs = NULL },
73ce48f6
JH		 1850 { .attrs = dme1737_pwm5_attr },
1851 { .attrs = dme1737_pwm6_attr },
9431996f
JH		 1852};
1853
c8de8362
GR		 1854/*
1855 * The following struct holds auto PWM min attributes, which are not available
ea694431 1856 * in all chips. Their creation depends on the chip type which is determined
c8de8362
GR		 1857 * during module load.
1858 */
ea694431 1859static struct attribute *dme1737_auto_pwm_min_attr[] = {
549edb83
JH		 1860 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1861 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1862 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1863};
1864
c8de8362
GR		 1865/*
1866 * The following structs hold the fan attributes, some of which are optional.
9431996f 1867 * Their creation depends on the chip configuration which is determined during
c8de8362
GR		 1868 * module load.
1869 */
73ce48f6 1870static struct attribute *dme1737_fan1_attr[] = {
9b257714
JH		 1871 &sensor_dev_attr_fan1_input.dev_attr.attr,
1872 &sensor_dev_attr_fan1_min.dev_attr.attr,
1873 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1874 &sensor_dev_attr_fan1_type.dev_attr.attr,
9431996f
JH		 1875 NULL
1876};
73ce48f6 1877static struct attribute *dme1737_fan2_attr[] = {
9b257714
JH		 1878 &sensor_dev_attr_fan2_input.dev_attr.attr,
1879 &sensor_dev_attr_fan2_min.dev_attr.attr,
1880 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1881 &sensor_dev_attr_fan2_type.dev_attr.attr,
9431996f
JH		 1882 NULL
1883};
73ce48f6 1884static struct attribute *dme1737_fan3_attr[] = {
9b257714
JH		 1885 &sensor_dev_attr_fan3_input.dev_attr.attr,
1886 &sensor_dev_attr_fan3_min.dev_attr.attr,
1887 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1888 &sensor_dev_attr_fan3_type.dev_attr.attr,
9431996f
JH		 1889 NULL
1890};
73ce48f6 1891static struct attribute *dme1737_fan4_attr[] = {
9b257714
JH		 1892 &sensor_dev_attr_fan4_input.dev_attr.attr,
1893 &sensor_dev_attr_fan4_min.dev_attr.attr,
1894 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1895 &sensor_dev_attr_fan4_type.dev_attr.attr,
9431996f
JH		 1896 NULL
1897};
73ce48f6 1898static struct attribute *dme1737_fan5_attr[] = {
9b257714
JH		 1899 &sensor_dev_attr_fan5_input.dev_attr.attr,
1900 &sensor_dev_attr_fan5_min.dev_attr.attr,
1901 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1902 &sensor_dev_attr_fan5_max.dev_attr.attr,
9431996f
JH		 1903 NULL
1904};
73ce48f6 1905static struct attribute *dme1737_fan6_attr[] = {
9b257714
JH		 1906 &sensor_dev_attr_fan6_input.dev_attr.attr,
1907 &sensor_dev_attr_fan6_min.dev_attr.attr,
1908 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1909 &sensor_dev_attr_fan6_max.dev_attr.attr,
9431996f
JH		 1910 NULL
1911};
1912
1913static const struct attribute_group dme1737_fan_group[] = {
73ce48f6
JH		 1914 { .attrs = dme1737_fan1_attr },
1915 { .attrs = dme1737_fan2_attr },
1916 { .attrs = dme1737_fan3_attr },
1917 { .attrs = dme1737_fan4_attr },
1918 { .attrs = dme1737_fan5_attr },
1919 { .attrs = dme1737_fan6_attr },
9431996f
JH		 1920};
1921
c8de8362
GR		 1922/*
1923 * The permissions of the following zone attributes are changed to read-
1924 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1925 */
549edb83 1926static struct attribute *dme1737_zone_chmod_attr[] = {
9b257714
JH		 1927 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1928 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1929 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
9b257714
JH		 1930 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1931 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1932 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
ea694431
JH		 1933 NULL
1934};
1935
1936static const struct attribute_group dme1737_zone_chmod_group = {
1937 .attrs = dme1737_zone_chmod_attr,
1938};
1939
1940
c8de8362
GR		 1941/*
1942 * The permissions of the following zone 3 attributes are changed to read-
1943 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1944 */
ea694431 1945static struct attribute *dme1737_zone3_chmod_attr[] = {
9b257714
JH		 1946 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1947 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1948 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
9431996f
JH		 1949 NULL
1950};
1951
ea694431
JH		 1952static const struct attribute_group dme1737_zone3_chmod_group = {
1953 .attrs = dme1737_zone3_chmod_attr,
9431996f
JH		 1954};
1955
c8de8362
GR		 1956/*
1957 * The permissions of the following PWM attributes are changed to read-
9431996f 1958 * writeable if the chip is *not* locked and the respective PWM is available.
c8de8362
GR		 1959 * Otherwise they stay read-only.
1960 */
73ce48f6 1961static struct attribute *dme1737_pwm1_chmod_attr[] = {
9b257714
JH		 1962 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1963 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1964 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1965 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714 1966 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1967 NULL
1968};
73ce48f6 1969static struct attribute *dme1737_pwm2_chmod_attr[] = {
9b257714
JH		 1970 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1971 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1972 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1973 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714 1974 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1975 NULL
1976};
73ce48f6 1977static struct attribute *dme1737_pwm3_chmod_attr[] = {
9b257714
JH		 1978 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1979 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1980 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1981 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714 1982 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1983 NULL
1984};
73ce48f6 1985static struct attribute *dme1737_pwm5_chmod_attr[] = {
9b257714
JH		 1986 &sensor_dev_attr_pwm5.dev_attr.attr,
1987 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
9431996f
JH		 1988 NULL
1989};
73ce48f6 1990static struct attribute *dme1737_pwm6_chmod_attr[] = {
9b257714
JH		 1991 &sensor_dev_attr_pwm6.dev_attr.attr,
1992 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
9431996f
JH		 1993 NULL
1994};
1995
73ce48f6
JH		 1996static const struct attribute_group dme1737_pwm_chmod_group[] = {
1997 { .attrs = dme1737_pwm1_chmod_attr },
1998 { .attrs = dme1737_pwm2_chmod_attr },
1999 { .attrs = dme1737_pwm3_chmod_attr },
9431996f 2000 { .attrs = NULL },
73ce48f6
JH		 2001 { .attrs = dme1737_pwm5_chmod_attr },
2002 { .attrs = dme1737_pwm6_chmod_attr },
9431996f
JH		 2003};
2004
c8de8362
GR		 2005/*
2006 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
2007 * chip is not locked. Otherwise they are read-only.
2008 */
73ce48f6 2009static struct attribute *dme1737_pwm_chmod_attr[] = {
9431996f
JH		 2010 &sensor_dev_attr_pwm1.dev_attr.attr,
2011 &sensor_dev_attr_pwm2.dev_attr.attr,
2012 &sensor_dev_attr_pwm3.dev_attr.attr,
2013};
2014
2015/* ---------------------------------------------------------------------
2016 * Super-IO functions
2017 * --------------------------------------------------------------------- */
2018
b237eb25
JH		 2019static inline void dme1737_sio_enter(int sio_cip)
2020{
2021 outb(0x55, sio_cip);
2022}
2023
2024static inline void dme1737_sio_exit(int sio_cip)
2025{
2026 outb(0xaa, sio_cip);
2027}
2028
9431996f
JH		 2029static inline int dme1737_sio_inb(int sio_cip, int reg)
2030{
2031 outb(reg, sio_cip);
2032 return inb(sio_cip + 1);
2033}
2034
2035static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
2036{
2037 outb(reg, sio_cip);
2038 outb(val, sio_cip + 1);
2039}
2040
9431996f 2041/* ---------------------------------------------------------------------
e95c237d 2042 * Device initialization
9431996f
JH		 2043 * --------------------------------------------------------------------- */
2044
67e2f328 2045static int dme1737_i2c_get_features(int, struct dme1737_data*);
9431996f 2046
b237eb25 2047static void dme1737_chmod_file(struct device *dev,
48176a97 2048 struct attribute *attr, umode_t mode)
9431996f 2049{
b237eb25
JH		 2050 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
2051 dev_warn(dev, "Failed to change permissions of %s.\n",
9431996f
JH		 2052 attr->name);
2053 }
2054}
2055
b237eb25 2056static void dme1737_chmod_group(struct device *dev,
9431996f 2057 const struct attribute_group *group,
48176a97 2058 umode_t mode)
9431996f
JH		 2059{
2060 struct attribute **attr;
2061
c8de8362 2062 for (attr = group->attrs; *attr; attr++)
b237eb25 2063 dme1737_chmod_file(dev, *attr, mode);
9431996f
JH		 2064}
2065
b237eb25 2066static void dme1737_remove_files(struct device *dev)
9431996f 2067{
b237eb25
JH		 2068 struct dme1737_data *data = dev_get_drvdata(dev);
2069 int ix;
2070
2071 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 2072 if (data->has_features & HAS_FAN(ix)) {
b237eb25
JH		 2073 sysfs_remove_group(&dev->kobj,
2074 &dme1737_fan_group[ix]);
2075 }
2076 }
2077
2078 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 2079 if (data->has_features & HAS_PWM(ix)) {
b237eb25
JH		 2080 sysfs_remove_group(&dev->kobj,
2081 &dme1737_pwm_group[ix]);
ea694431 2082 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
549edb83 2083 sysfs_remove_file(&dev->kobj,
ea694431 2084 dme1737_auto_pwm_min_attr[ix]);
549edb83 2085 }
b237eb25
JH		 2086 }
2087 }
2088
c8de8362 2089 if (data->has_features & HAS_TEMP_OFFSET)
ea694431 2090 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
c8de8362 2091 if (data->has_features & HAS_VID)
9d091446 2092 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
c8de8362 2093 if (data->has_features & HAS_ZONE3)
ea694431 2094 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
c8de8362 2095 if (data->has_features & HAS_ZONE_HYST)
ea694431 2096 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
c8de8362 2097 if (data->has_features & HAS_IN7)
d4b94e1f 2098 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
b237eb25 2099 sysfs_remove_group(&dev->kobj, &dme1737_group);
e95c237d 2100
c8de8362 2101 if (!data->client)
e95c237d 2102 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
b237eb25
JH		 2103}
2104
2105static int dme1737_create_files(struct device *dev)
2106{
2107 struct dme1737_data *data = dev_get_drvdata(dev);
2108 int err, ix;
2109
e95c237d 2110 /* Create a name attribute for ISA devices */
06f3d9fb
JH		 2111 if (!data->client) {
2112 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
c8de8362 2113 if (err)
06f3d9fb 2114 goto exit;
e95c237d
JH		 2115 }
2116
b237eb25 2117 /* Create standard sysfs attributes */
06f3d9fb 2118 err = sysfs_create_group(&dev->kobj, &dme1737_group);
c8de8362 2119 if (err)
e95c237d 2120 goto exit_remove;
b237eb25 2121
ea694431 2122 /* Create chip-dependent sysfs attributes */
06f3d9fb
JH		 2123 if (data->has_features & HAS_TEMP_OFFSET) {
2124 err = sysfs_create_group(&dev->kobj,
2125 &dme1737_temp_offset_group);
c8de8362 2126 if (err)
06f3d9fb 2127 goto exit_remove;
549edb83 2128 }
06f3d9fb
JH		 2129 if (data->has_features & HAS_VID) {
2130 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
c8de8362 2131 if (err)
06f3d9fb 2132 goto exit_remove;
9d091446 2133 }
06f3d9fb
JH		 2134 if (data->has_features & HAS_ZONE3) {
2135 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
c8de8362 2136 if (err)
06f3d9fb 2137 goto exit_remove;
ea694431 2138 }
06f3d9fb
JH		 2139 if (data->has_features & HAS_ZONE_HYST) {
2140 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
c8de8362 2141 if (err)
06f3d9fb 2142 goto exit_remove;
ea694431 2143 }
d4b94e1f
JH		 2144 if (data->has_features & HAS_IN7) {
2145 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
c8de8362 2146 if (err)
d4b94e1f 2147 goto exit_remove;
d4b94e1f 2148 }
9d091446 2149
b237eb25
JH		 2150 /* Create fan sysfs attributes */
2151 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 2152 if (data->has_features & HAS_FAN(ix)) {
06f3d9fb
JH		 2153 err = sysfs_create_group(&dev->kobj,
2154 &dme1737_fan_group[ix]);
c8de8362 2155 if (err)
b237eb25 2156 goto exit_remove;
b237eb25
JH		 2157 }
2158 }
2159
2160 /* Create PWM sysfs attributes */
2161 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 2162 if (data->has_features & HAS_PWM(ix)) {
06f3d9fb
JH		 2163 err = sysfs_create_group(&dev->kobj,
2164 &dme1737_pwm_group[ix]);
c8de8362 2165 if (err)
b237eb25 2166 goto exit_remove;
06f3d9fb
JH		 2167 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2168 err = sysfs_create_file(&dev->kobj,
2169 dme1737_auto_pwm_min_attr[ix]);
c8de8362 2170 if (err)
06f3d9fb 2171 goto exit_remove;
549edb83 2172 }
b237eb25
JH		 2173 }
2174 }
2175
c8de8362
GR		 2176 /*
2177 * Inform if the device is locked. Otherwise change the permissions of
2178 * selected attributes from read-only to read-writeable.
2179 */
b237eb25
JH		 2180 if (data->config & 0x02) {
2181 dev_info(dev, "Device is locked. Some attributes "
2182 "will be read-only.\n");
2183 } else {
549edb83
JH		 2184 /* Change permissions of zone sysfs attributes */
2185 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
b237eb25
JH		 2186 S_IRUGO | S_IWUSR);
2187
ea694431
JH		 2188 /* Change permissions of chip-dependent sysfs attributes */
2189 if (data->has_features & HAS_TEMP_OFFSET) {
2190 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2191 S_IRUGO | S_IWUSR);
2192 }
2193 if (data->has_features & HAS_ZONE3) {
2194 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2195 S_IRUGO | S_IWUSR);
2196 }
2197 if (data->has_features & HAS_ZONE_HYST) {
2198 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
549edb83
JH		 2199 S_IRUGO | S_IWUSR);
2200 }
2201
73ce48f6
JH		 2202 /* Change permissions of PWM sysfs attributes */
2203 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
ea694431 2204 if (data->has_features & HAS_PWM(ix)) {
b237eb25 2205 dme1737_chmod_group(dev,
73ce48f6 2206 &dme1737_pwm_chmod_group[ix],
b237eb25 2207 S_IRUGO | S_IWUSR);
ea694431
JH		 2208 if ((data->has_features & HAS_PWM_MIN) &&
2209 ix < 3) {
549edb83 2210 dme1737_chmod_file(dev,
ea694431 2211 dme1737_auto_pwm_min_attr[ix],
549edb83
JH		 2212 S_IRUGO | S_IWUSR);
2213 }
b237eb25
JH		 2214 }
2215 }
2216
2217 /* Change permissions of pwm[1-3] if in manual mode */
2218 for (ix = 0; ix < 3; ix++) {
ea694431 2219 if ((data->has_features & HAS_PWM(ix)) &&
b237eb25
JH		 2220 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2221 dme1737_chmod_file(dev,
73ce48f6 2222 dme1737_pwm_chmod_attr[ix],
b237eb25
JH		 2223 S_IRUGO | S_IWUSR);
2224 }
2225 }
2226 }
2227
2228 return 0;
2229
2230exit_remove:
2231 dme1737_remove_files(dev);
2232exit:
2233 return err;
2234}
2235
2236static int dme1737_init_device(struct device *dev)
2237{
2238 struct dme1737_data *data = dev_get_drvdata(dev);
dbc2bc25 2239 struct i2c_client *client = data->client;
9431996f
JH		 2240 int ix;
2241 u8 reg;
2242
549edb83
JH		 2243 /* Point to the right nominal voltages array */
2244 data->in_nominal = IN_NOMINAL(data->type);
2245
dbc2bc25 2246 data->config = dme1737_read(data, DME1737_REG_CONFIG);
b237eb25
JH		 2247 /* Inform if part is not monitoring/started */
2248 if (!(data->config & 0x01)) {
2249 if (!force_start) {
2250 dev_err(dev, "Device is not monitoring. "
2251 "Use the force_start load parameter to "
2252 "override.\n");
2253 return -EFAULT;
2254 }
2255
2256 /* Force monitoring */
2257 data->config |= 0x01;
dbc2bc25 2258 dme1737_write(data, DME1737_REG_CONFIG, data->config);
b237eb25 2259 }
9431996f
JH		 2260 /* Inform if part is not ready */
2261 if (!(data->config & 0x04)) {
b237eb25 2262 dev_err(dev, "Device is not ready.\n");
9431996f
JH		 2263 return -EFAULT;
2264 }
2265
c8de8362
GR		 2266 /*
2267 * Determine which optional fan and pwm features are enabled (only
2268 * valid for I2C devices)
2269 */
dbc2bc25
JD		 2270 if (client) { /* I2C chip */
2271 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
e95c237d 2272 /* Check if optional fan3 input is enabled */
c8de8362 2273 if (data->config2 & 0x04)
ea694431 2274 data->has_features |= HAS_FAN(2);
9431996f 2275
c8de8362
GR		 2276 /*
2277 * Fan4 and pwm3 are only available if the client's I2C address
e95c237d 2278 * is the default 0x2e. Otherwise the I/Os associated with
c8de8362
GR		 2279 * these functions are used for addr enable/select.
2280 */
2281 if (client->addr == 0x2e)
ea694431 2282 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
9431996f 2283
c8de8362
GR		 2284 /*
2285 * Determine which of the optional fan[5-6] and pwm[5-6]
e95c237d
JH		 2286 * features are enabled. For this, we need to query the runtime
2287 * registers through the Super-IO LPC interface. Try both
c8de8362
GR		 2288 * config ports 0x2e and 0x4e.
2289 */
e95c237d
JH		 2290 if (dme1737_i2c_get_features(0x2e, data) &&
2291 dme1737_i2c_get_features(0x4e, data)) {
2292 dev_warn(dev, "Failed to query Super-IO for optional "
2293 "features.\n");
2294 }
9431996f
JH		 2295 }
2296
ea694431
JH		 2297 /* Fan[1-2] and pwm[1-2] are present in all chips */
2298 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2299
2300 /* Chip-dependent features */
2301 switch (data->type) {
2302 case dme1737:
2303 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2304 HAS_ZONE_HYST | HAS_PWM_MIN;
2305 break;
2306 case sch311x:
2307 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2308 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2309 break;
2310 case sch5027:
2311 data->has_features |= HAS_ZONE3;
2312 break;
2313 case sch5127:
d4b94e1f 2314 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7;
ea694431
JH		 2315 break;
2316 default:
2317 break;
2318 }
9431996f 2319
b237eb25 2320 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, "
9431996f 2321 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
ea694431
JH		 2322 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2323 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2324 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2325 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2326 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2327 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2328 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
9431996f 2329
dbc2bc25 2330 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
9431996f 2331 /* Inform if fan-to-pwm mapping differs from the default */
dbc2bc25 2332 if (client && reg != 0xa4) { /* I2C chip */
b237eb25 2333 dev_warn(dev, "Non-standard fan to pwm mapping: "
9431996f
JH		 2334 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, "
2335 "fan4->pwm%d. Please report to the driver "
2336 "maintainer.\n",
2337 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2338 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1);
dbc2bc25 2339 } else if (!client && reg != 0x24) { /* ISA chip */
e95c237d
JH		 2340 dev_warn(dev, "Non-standard fan to pwm mapping: "
2341 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. "
2342 "Please report to the driver maintainer.\n",
2343 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
2344 ((reg >> 4) & 0x03) + 1);
9431996f
JH		 2345 }
2346
c8de8362
GR		 2347 /*
2348 * Switch pwm[1-3] to manual mode if they are currently disabled and
9431996f 2349 * set the duty-cycles to 0% (which is identical to the PWMs being
c8de8362
GR		 2350 * disabled).
2351 */
9431996f
JH		 2352 if (!(data->config & 0x02)) {
2353 for (ix = 0; ix < 3; ix++) {
dbc2bc25 2354 data->pwm_config[ix] = dme1737_read(data,
9431996f 2355 DME1737_REG_PWM_CONFIG(ix));
ea694431 2356 if ((data->has_features & HAS_PWM(ix)) &&
9431996f 2357 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
b237eb25 2358 dev_info(dev, "Switching pwm%d to "
9431996f
JH		 2359 "manual mode.\n", ix + 1);
2360 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2361 data->pwm_config[ix]);
dbc2bc25
JD		 2362 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2363 dme1737_write(data,
9431996f
JH		 2364 DME1737_REG_PWM_CONFIG(ix),
2365 data->pwm_config[ix]);
2366 }
2367 }
2368 }
2369
2370 /* Initialize the default PWM auto channels zone (acz) assignments */
2371 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2372 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2373 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2374
2375 /* Set VRM */
c8de8362 2376 if (data->has_features & HAS_VID)
549edb83 2377 data->vrm = vid_which_vrm();
9431996f
JH		 2378
2379 return 0;
2380}
2381
67e2f328
JH		 2382/* ---------------------------------------------------------------------
2383 * I2C device detection and registration
2384 * --------------------------------------------------------------------- */
2385
2386static struct i2c_driver dme1737_i2c_driver;
2387
2388static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2389{
2390 int err = 0, reg;
2391 u16 addr;
2392
2393 dme1737_sio_enter(sio_cip);
2394
c8de8362
GR		 2395 /*
2396 * Check device ID
2397 * We currently know about two kinds of DME1737 and SCH5027.
2398 */
345a2224 2399 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2400 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2401 reg == SCH5027_ID)) {
67e2f328
JH		 2402 err = -ENODEV;
2403 goto exit;
2404 }
2405
2406 /* Select logical device A (runtime registers) */
2407 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2408
2409 /* Get the base address of the runtime registers */
06f3d9fb
JH		 2410 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2411 dme1737_sio_inb(sio_cip, 0x61);
2412 if (!addr) {
67e2f328
JH		 2413 err = -ENODEV;
2414 goto exit;
2415 }
2416
c8de8362
GR		 2417 /*
2418 * Read the runtime registers to determine which optional features
67e2f328 2419 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
c8de8362
GR		 2420 * to '10' if the respective feature is enabled.
2421 */
2422 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
ea694431 2423 data->has_features |= HAS_FAN(5);
c8de8362 2424 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
ea694431 2425 data->has_features |= HAS_PWM(5);
c8de8362 2426 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
ea694431 2427 data->has_features |= HAS_FAN(4);
c8de8362 2428 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
ea694431 2429 data->has_features |= HAS_PWM(4);
67e2f328
JH		 2430
2431exit:
2432 dme1737_sio_exit(sio_cip);
2433
2434 return err;
2435}
2436
67a37308 2437/* Return 0 if detection is successful, -ENODEV otherwise */
310ec792 2438static int dme1737_i2c_detect(struct i2c_client *client,
67a37308 2439 struct i2c_board_info *info)
9431996f 2440{
67a37308
JD		 2441 struct i2c_adapter *adapter = client->adapter;
2442 struct device *dev = &adapter->dev;
9431996f 2443 u8 company, verstep = 0;
9431996f
JH		 2444 const char *name;
2445
c8de8362 2446 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
67a37308 2447 return -ENODEV;
9431996f 2448
52df6440
JD		 2449 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2450 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
9431996f 2451
52df6440
JD		 2452 if (company == DME1737_COMPANY_SMSC &&
2453 verstep == SCH5027_VERSTEP) {
549edb83 2454 name = "sch5027";
52df6440
JD		 2455 } else if (company == DME1737_COMPANY_SMSC &&
2456 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
549edb83 2457 name = "dme1737";
52df6440
JD		 2458 } else {
2459 return -ENODEV;
549edb83 2460 }
9431996f 2461
549edb83 2462 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
52df6440
JD		 2463 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2464 client->addr, verstep);
67a37308
JD		 2465 strlcpy(info->type, name, I2C_NAME_SIZE);
2466
2467 return 0;
2468}
2469
2470static int dme1737_i2c_probe(struct i2c_client *client,
2471 const struct i2c_device_id *id)
2472{
2473 struct dme1737_data *data;
2474 struct device *dev = &client->dev;
2475 int err;
2476
805fd8c5
GR		 2477 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2478 if (!data)
2479 return -ENOMEM;
67a37308
JD		 2480
2481 i2c_set_clientdata(client, data);
2482 data->type = id->driver_data;
2483 data->client = client;
2484 data->name = client->name;
2485 mutex_init(&data->update_lock);
b237eb25 2486
9431996f 2487 /* Initialize the DME1737 chip */
06f3d9fb
JH		 2488 err = dme1737_init_device(dev);
2489 if (err) {
b237eb25 2490 dev_err(dev, "Failed to initialize device.\n");
805fd8c5 2491 return err;
9431996f
JH		 2492 }
2493
b237eb25 2494 /* Create sysfs files */
06f3d9fb
JH		 2495 err = dme1737_create_files(dev);
2496 if (err) {
b237eb25 2497 dev_err(dev, "Failed to create sysfs files.\n");
805fd8c5 2498 return err;
9431996f
JH		 2499 }
2500
2501 /* Register device */
62ee3e10 2502 data->hwmon_dev = hwmon_device_register(dev);
1beeffe4 2503 if (IS_ERR(data->hwmon_dev)) {
b237eb25 2504 dev_err(dev, "Failed to register device.\n");
1beeffe4 2505 err = PTR_ERR(data->hwmon_dev);
9431996f
JH		 2506 goto exit_remove;
2507 }
2508
9431996f
JH		 2509 return 0;
2510
2511exit_remove:
b237eb25 2512 dme1737_remove_files(dev);
9431996f
JH		 2513 return err;
2514}
2515
67a37308 2516static int dme1737_i2c_remove(struct i2c_client *client)
9431996f
JH		 2517{
2518 struct dme1737_data *data = i2c_get_clientdata(client);
9431996f 2519
1beeffe4 2520 hwmon_device_unregister(data->hwmon_dev);
b237eb25 2521 dme1737_remove_files(&client->dev);
9431996f 2522
9431996f
JH		 2523 return 0;
2524}
2525
67a37308
JD		 2526static const struct i2c_device_id dme1737_id[] = {
2527 { "dme1737", dme1737 },
2528 { "sch5027", sch5027 },
2529 { }
2530};
2531MODULE_DEVICE_TABLE(i2c, dme1737_id);
2532
b237eb25 2533static struct i2c_driver dme1737_i2c_driver = {
67a37308 2534 .class = I2C_CLASS_HWMON,
9431996f
JH		 2535 .driver = {
2536 .name = "dme1737",
2537 },
67a37308
JD		 2538 .probe = dme1737_i2c_probe,
2539 .remove = dme1737_i2c_remove,
2540 .id_table = dme1737_id,
2541 .detect = dme1737_i2c_detect,
c3813d6a 2542 .address_list = normal_i2c,
9431996f
JH		 2543};
2544
e95c237d
JH		 2545/* ---------------------------------------------------------------------
2546 * ISA device detection and registration
2547 * --------------------------------------------------------------------- */
2548
2549static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2550{
2551 int err = 0, reg;
2552 unsigned short base_addr;
2553
2554 dme1737_sio_enter(sio_cip);
2555
c8de8362
GR		 2556 /*
2557 * Check device ID
2558 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
2559 */
67b671bc 2560 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2561 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2562 reg == SCH5127_ID)) {
e95c237d
JH		 2563 err = -ENODEV;
2564 goto exit;
2565 }
2566
2567 /* Select logical device A (runtime registers) */
2568 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2569
2570 /* Get the base address of the runtime registers */
06f3d9fb
JH		 2571 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2572 dme1737_sio_inb(sio_cip, 0x61);
2573 if (!base_addr) {
9c6e13b4 2574 pr_err("Base address not set\n");
e95c237d
JH		 2575 err = -ENODEV;
2576 goto exit;
2577 }
2578
c8de8362
GR		 2579 /*
2580 * Access to the hwmon registers is through an index/data register
2581 * pair located at offset 0x70/0x71.
2582 */
e95c237d
JH		 2583 *addr = base_addr + 0x70;
2584
2585exit:
2586 dme1737_sio_exit(sio_cip);
2587 return err;
2588}
2589
2590static int __init dme1737_isa_device_add(unsigned short addr)
2591{
2592 struct resource res = {
2593 .start = addr,
2594 .end = addr + DME1737_EXTENT - 1,
2595 .name = "dme1737",
2596 .flags = IORESOURCE_IO,
2597 };
2598 int err;
2599
b9acb64a
JD		 2600 err = acpi_check_resource_conflict(&res);
2601 if (err)
2602 goto exit;
2603
06f3d9fb
JH		 2604 pdev = platform_device_alloc("dme1737", addr);
2605 if (!pdev) {
9c6e13b4 2606 pr_err("Failed to allocate device\n");
e95c237d
JH		 2607 err = -ENOMEM;
2608 goto exit;
2609 }
2610
06f3d9fb
JH		 2611 err = platform_device_add_resources(pdev, &res, 1);
2612 if (err) {
9c6e13b4 2613 pr_err("Failed to add device resource (err = %d)\n", err);
e95c237d
JH		 2614 goto exit_device_put;
2615 }
2616
06f3d9fb
JH		 2617 err = platform_device_add(pdev);
2618 if (err) {
9c6e13b4 2619 pr_err("Failed to add device (err = %d)\n", err);
e95c237d
JH		 2620 goto exit_device_put;
2621 }
2622
2623 return 0;
2624
2625exit_device_put:
2626 platform_device_put(pdev);
2627 pdev = NULL;
2628exit:
2629 return err;
2630}
2631
6c931ae1 2632static int dme1737_isa_probe(struct platform_device *pdev)
e95c237d
JH		 2633{
2634 u8 company, device;
2635 struct resource *res;
e95c237d
JH		 2636 struct dme1737_data *data;
2637 struct device *dev = &pdev->dev;
2638 int err;
2639
2640 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
805fd8c5 2641 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) {
e95c237d
JH		 2642 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2643 (unsigned short)res->start,
2644 (unsigned short)res->start + DME1737_EXTENT - 1);
805fd8c5 2645 return -EBUSY;
06f3d9fb 2646 }
e95c237d 2647
805fd8c5
GR		 2648 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2649 if (!data)
2650 return -ENOMEM;
e95c237d 2651
dbc2bc25 2652 data->addr = res->start;
e95c237d
JH		 2653 platform_set_drvdata(pdev, data);
2654
55d68d75 2655 /* Skip chip detection if module is loaded with force_id parameter */
ea694431
JH		 2656 switch (force_id) {
2657 case SCH3112_ID:
2658 case SCH3114_ID:
2659 case SCH3116_ID:
2660 data->type = sch311x;
2661 break;
2662 case SCH5127_ID:
2663 data->type = sch5127;
2664 break;
2665 default:
dbc2bc25
JD		 2666 company = dme1737_read(data, DME1737_REG_COMPANY);
2667 device = dme1737_read(data, DME1737_REG_DEVICE);
e95c237d 2668
ea694431
JH		 2669 if ((company == DME1737_COMPANY_SMSC) &&
2670 (device == SCH311X_DEVICE)) {
2671 data->type = sch311x;
2672 } else if ((company == DME1737_COMPANY_SMSC) &&
2673 (device == SCH5127_DEVICE)) {
2674 data->type = sch5127;
2675 } else {
805fd8c5 2676 return -ENODEV;
55d68d75 2677 }
e95c237d
JH		 2678 }
2679
c8de8362 2680 if (data->type == sch5127)
ea694431 2681 data->name = "sch5127";
c8de8362 2682 else
ea694431 2683 data->name = "sch311x";
ea694431
JH		 2684
2685 /* Initialize the mutex */
e95c237d
JH		 2686 mutex_init(&data->update_lock);
2687
ea694431
JH		 2688 dev_info(dev, "Found a %s chip at 0x%04x\n",
2689 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
e95c237d
JH		 2690
2691 /* Initialize the chip */
06f3d9fb
JH		 2692 err = dme1737_init_device(dev);
2693 if (err) {
e95c237d 2694 dev_err(dev, "Failed to initialize device.\n");
805fd8c5 2695 return err;
e95c237d
JH		 2696 }
2697
2698 /* Create sysfs files */
06f3d9fb
JH		 2699 err = dme1737_create_files(dev);
2700 if (err) {
e95c237d 2701 dev_err(dev, "Failed to create sysfs files.\n");
805fd8c5 2702 return err;
e95c237d
JH		 2703 }
2704
2705 /* Register device */
2706 data->hwmon_dev = hwmon_device_register(dev);
2707 if (IS_ERR(data->hwmon_dev)) {
2708 dev_err(dev, "Failed to register device.\n");
2709 err = PTR_ERR(data->hwmon_dev);
2710 goto exit_remove_files;
2711 }
2712
2713 return 0;
2714
2715exit_remove_files:
2716 dme1737_remove_files(dev);
e95c237d
JH		 2717 return err;
2718}
2719
281dfd0b 2720static int dme1737_isa_remove(struct platform_device *pdev)
e95c237d
JH		 2721{
2722 struct dme1737_data *data = platform_get_drvdata(pdev);
2723
2724 hwmon_device_unregister(data->hwmon_dev);
2725 dme1737_remove_files(&pdev->dev);
e95c237d
JH		 2726
2727 return 0;
2728}
2729
2730static struct platform_driver dme1737_isa_driver = {
2731 .driver = {
2732 .owner = THIS_MODULE,
2733 .name = "dme1737",
2734 },
2735 .probe = dme1737_isa_probe,
9e5e9b7a 2736 .remove = dme1737_isa_remove,
e95c237d
JH		 2737};
2738
67e2f328
JH		 2739/* ---------------------------------------------------------------------
2740 * Module initialization and cleanup
2741 * --------------------------------------------------------------------- */
2742
9431996f
JH		 2743static int __init dme1737_init(void)
2744{
e95c237d
JH		 2745 int err;
2746 unsigned short addr;
2747
06f3d9fb 2748 err = i2c_add_driver(&dme1737_i2c_driver);
c8de8362 2749 if (err)
e95c237d 2750 goto exit;
e95c237d
JH		 2751
2752 if (dme1737_isa_detect(0x2e, &addr) &&
92430b6f
JH		 2753 dme1737_isa_detect(0x4e, &addr) &&
2754 (!probe_all_addr ||
2755 (dme1737_isa_detect(0x162e, &addr) &&
2756 dme1737_isa_detect(0x164e, &addr)))) {
e95c237d
JH		 2757 /* Return 0 if we didn't find an ISA device */
2758 return 0;
2759 }
2760
06f3d9fb 2761 err = platform_driver_register(&dme1737_isa_driver);
c8de8362 2762 if (err)
e95c237d 2763 goto exit_del_i2c_driver;
e95c237d
JH		 2764
2765 /* Sets global pdev as a side effect */
06f3d9fb 2766 err = dme1737_isa_device_add(addr);
c8de8362 2767 if (err)
e95c237d 2768 goto exit_del_isa_driver;
e95c237d
JH		 2769
2770 return 0;
2771
2772exit_del_isa_driver:
2773 platform_driver_unregister(&dme1737_isa_driver);
2774exit_del_i2c_driver:
2775 i2c_del_driver(&dme1737_i2c_driver);
2776exit:
2777 return err;
9431996f
JH		 2778}
2779
2780static void __exit dme1737_exit(void)
2781{
e95c237d
JH		 2782 if (pdev) {
2783 platform_device_unregister(pdev);
2784 platform_driver_unregister(&dme1737_isa_driver);
2785 }
2786
b237eb25 2787 i2c_del_driver(&dme1737_i2c_driver);
9431996f
JH		 2788}
2789
2790MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2791MODULE_DESCRIPTION("DME1737 sensors");
2792MODULE_LICENSE("GPL");
2793
2794module_init(dme1737_init);
2795module_exit(dme1737_exit);
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