[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / fam15h_power.c

/*
 * fam15h_power.c - AMD Family 15h processor power monitoring
 *
 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/time.h>
#include <linux/sched.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
MODULE_LICENSE("GPL");

/* D18F3 */
#define REG_NORTHBRIDGE_CAP		0xe8

/* D18F4 */
#define REG_PROCESSOR_TDP		0x1b8

/* D18F5 */
#define REG_TDP_RUNNING_AVERAGE		0xe0
#define REG_TDP_LIMIT3			0xe8

#define FAM15H_MIN_NUM_ATTRS		2
#define FAM15H_NUM_GROUPS		2
#define MAX_CUS				8

/* set maximum interval as 1 second */
#define MAX_INTERVAL			1000

#define MSR_F15H_CU_PWR_ACCUMULATOR	0xc001007a
#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR	0xc001007b
#define MSR_F15H_PTSC			0xc0010280

#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4

struct fam15h_power_data {
	struct pci_dev *pdev;
	unsigned int tdp_to_watts;
	unsigned int base_tdp;
	unsigned int processor_pwr_watts;
	unsigned int cpu_pwr_sample_ratio;
	const struct attribute_group *groups[FAM15H_NUM_GROUPS];
	struct attribute_group group;
	/* maximum accumulated power of a compute unit */
	u64 max_cu_acc_power;
	/* accumulated power of the compute units */
	u64 cu_acc_power[MAX_CUS];
	/* performance timestamp counter */
	u64 cpu_sw_pwr_ptsc[MAX_CUS];
	/* online/offline status of current compute unit */
	int cu_on[MAX_CUS];
	unsigned long power_period;
};

static bool is_carrizo_or_later(void)
{
	return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
}

static ssize_t power1_input_show(struct device *dev,
				 struct device_attribute *attr, char *buf)
{
	u32 val, tdp_limit, running_avg_range;
	s32 running_avg_capture;
	u64 curr_pwr_watts;
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	struct pci_dev *f4 = data->pdev;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_RUNNING_AVERAGE, &val);

	/*
	 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
	 * is extended to 4:31 from 4:25.
	 */
	if (is_carrizo_or_later()) {
		running_avg_capture = val >> 4;
		running_avg_capture = sign_extend32(running_avg_capture, 27);
	} else {
		running_avg_capture = (val >> 4) & 0x3fffff;
		running_avg_capture = sign_extend32(running_avg_capture, 21);
	}

	running_avg_range = (val & 0xf) + 1;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_LIMIT3, &val);

	/*
	 * On Carrizo and later platforms, ApmTdpLimit bit field
	 * is extended to 16:31 from 16:28.
	 */
	if (is_carrizo_or_later())
		tdp_limit = val >> 16;
	else
		tdp_limit = (val >> 16) & 0x1fff;

	curr_pwr_watts = ((u64)(tdp_limit +
				data->base_tdp)) << running_avg_range;
	curr_pwr_watts -= running_avg_capture;
	curr_pwr_watts *= data->tdp_to_watts;

	/*
	 * Convert to microWatt
	 *
	 * power is in Watt provided as fixed point integer with
	 * scaling factor 1/(2^16).  For conversion we use
	 * (10^6)/(2^16) = 15625/(2^10)
	 */
	curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
	return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
}
static DEVICE_ATTR_RO(power1_input);

static ssize_t power1_crit_show(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);

	return sprintf(buf, "%u\n", data->processor_pwr_watts);
}
static DEVICE_ATTR_RO(power1_crit);

static void do_read_registers_on_cu(void *_data)
{
	struct fam15h_power_data *data = _data;
	int cpu, cu;

	cpu = smp_processor_id();

	/*
	 * With the new x86 topology modelling, cpu core id actually
	 * is compute unit id.
	 */
	cu = cpu_data(cpu).cpu_core_id;

	rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
	rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);

	data->cu_on[cu] = 1;
}

/*
 * This function is only able to be called when CPUID
 * Fn8000_0007:EDX[12] is set.
 */
static int read_registers(struct fam15h_power_data *data)
{
	int core, this_core;
	cpumask_var_t mask;
	int ret, cpu;

	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
	if (!ret)
		return -ENOMEM;

	memset(data->cu_on, 0, sizeof(int) * MAX_CUS);

	get_online_cpus();

	/*
	 * Choose the first online core of each compute unit, and then
	 * read their MSR value of power and ptsc in a single IPI,
	 * because the MSR value of CPU core represent the compute
	 * unit's.
	 */
	core = -1;

	for_each_online_cpu(cpu) {
		this_core = topology_core_id(cpu);

		if (this_core == core)
			continue;

		core = this_core;

		/* get any CPU on this compute unit */
		cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
	}

	on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);

	put_online_cpus();
	free_cpumask_var(mask);

	return 0;
}

static ssize_t power1_average_show(struct device *dev,
				   struct device_attribute *attr, char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
	    jdelta[MAX_CUS];
	u64 tdelta, avg_acc;
	int cu, cu_num, ret;
	signed long leftover;

	/*
	 * With the new x86 topology modelling, x86_max_cores is the
	 * compute unit number.
	 */
	cu_num = boot_cpu_data.x86_max_cores;

	ret = read_registers(data);
	if (ret)
		return 0;

	for (cu = 0; cu < cu_num; cu++) {
		prev_cu_acc_power[cu] = data->cu_acc_power[cu];
		prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
	}

	leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
	if (leftover)
		return 0;

	ret = read_registers(data);
	if (ret)
		return 0;

	for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
		/* check if current compute unit is online */
		if (data->cu_on[cu] == 0)
			continue;

		if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
			jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
			jdelta[cu] -= prev_cu_acc_power[cu];
		} else {
			jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
		}
		tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
		jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
		do_div(jdelta[cu], tdelta);

		/* the unit is microWatt */
		avg_acc += jdelta[cu];
	}

	return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
}
static DEVICE_ATTR_RO(power1_average);

static ssize_t power1_average_interval_show(struct device *dev,
					    struct device_attribute *attr,
					    char *buf)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);

	return sprintf(buf, "%lu\n", data->power_period);
}

static ssize_t power1_average_interval_store(struct device *dev,
					     struct device_attribute *attr,
					     const char *buf, size_t count)
{
	struct fam15h_power_data *data = dev_get_drvdata(dev);
	unsigned long temp;
	int ret;

	ret = kstrtoul(buf, 10, &temp);
	if (ret)
		return ret;

	if (temp > MAX_INTERVAL)
		return -EINVAL;

	/* the interval value should be greater than 0 */
	if (temp <= 0)
		return -EINVAL;

	data->power_period = temp;

	return count;
}
static DEVICE_ATTR_RW(power1_average_interval);

static int fam15h_power_init_attrs(struct pci_dev *pdev,
				   struct fam15h_power_data *data)
{
	int n = FAM15H_MIN_NUM_ATTRS;
	struct attribute **fam15h_power_attrs;
	struct cpuinfo_x86 *c = &boot_cpu_data;

	if (c->x86 == 0x15 &&
	    (c->x86_model <= 0xf ||
	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
		n += 1;

	/* check if processor supports accumulated power */
	if (boot_cpu_has(X86_FEATURE_ACC_POWER))
		n += 2;

	fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
					  sizeof(*fam15h_power_attrs),
					  GFP_KERNEL);

	if (!fam15h_power_attrs)
		return -ENOMEM;

	n = 0;
	fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
	if (c->x86 == 0x15 &&
	    (c->x86_model <= 0xf ||
	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
		fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;

	if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
		fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
		fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
	}

	data->group.attrs = fam15h_power_attrs;

	return 0;
}

static bool should_load_on_this_node(struct pci_dev *f4)
{
	u32 val;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
				  REG_NORTHBRIDGE_CAP, &val);
	if ((val & BIT(29)) && ((val >> 30) & 3))
		return false;

	return true;
}

/*
 * Newer BKDG versions have an updated recommendation on how to properly
 * initialize the running average range (was: 0xE, now: 0x9). This avoids
 * counter saturations resulting in bogus power readings.
 * We correct this value ourselves to cope with older BIOSes.
 */
static const struct pci_device_id affected_device[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ 0 }
};

static void tweak_runavg_range(struct pci_dev *pdev)
{
	u32 val;

	/*
	 * let this quirk apply only to the current version of the
	 * northbridge, since future versions may change the behavior
	 */
	if (!pci_match_id(affected_device, pdev))
		return;

	pci_bus_read_config_dword(pdev->bus,
		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
		REG_TDP_RUNNING_AVERAGE, &val);
	if ((val & 0xf) != 0xe)
		return;

	val &= ~0xf;
	val |=  0x9;
	pci_bus_write_config_dword(pdev->bus,
		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
		REG_TDP_RUNNING_AVERAGE, val);
}

#ifdef CONFIG_PM
static int fam15h_power_resume(struct pci_dev *pdev)
{
	tweak_runavg_range(pdev);
	return 0;
}
#else
#define fam15h_power_resume NULL
#endif

static int fam15h_power_init_data(struct pci_dev *f4,
				  struct fam15h_power_data *data)
{
	u32 val;
	u64 tmp;
	int ret;

	pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
	data->base_tdp = val >> 16;
	tmp = val & 0xffff;

	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
				  REG_TDP_LIMIT3, &val);

	data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
	tmp *= data->tdp_to_watts;

	/* result not allowed to be >= 256W */
	if ((tmp >> 16) >= 256)
		dev_warn(&f4->dev,
			 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
			 (unsigned int) (tmp >> 16));

	/* convert to microWatt */
	data->processor_pwr_watts = (tmp * 15625) >> 10;

	ret = fam15h_power_init_attrs(f4, data);
	if (ret)
		return ret;


	/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
	if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
		return 0;

	/*
	 * determine the ratio of the compute unit power accumulator
	 * sample period to the PTSC counter period by executing CPUID
	 * Fn8000_0007:ECX
	 */
	data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);

	if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
		pr_err("Failed to read max compute unit power accumulator MSR\n");
		return -ENODEV;
	}

	data->max_cu_acc_power = tmp;

	/*
	 * Milliseconds are a reasonable interval for the measurement.
	 * But it shouldn't set too long here, because several seconds
	 * would cause the read function to hang. So set default
	 * interval as 10 ms.
	 */
	data->power_period = 10;

	return read_registers(data);
}

static int fam15h_power_probe(struct pci_dev *pdev,
			      const struct pci_device_id *id)
{
	struct fam15h_power_data *data;
	struct device *dev = &pdev->dev;
	struct device *hwmon_dev;
	int ret;

	/*
	 * though we ignore every other northbridge, we still have to
	 * do the tweaking on _each_ node in MCM processors as the counters
	 * are working hand-in-hand
	 */
	tweak_runavg_range(pdev);

	if (!should_load_on_this_node(pdev))
		return -ENODEV;

	data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	ret = fam15h_power_init_data(pdev, data);
	if (ret)
		return ret;

	data->pdev = pdev;

	data->groups[0] = &data->group;

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
							   data,
							   &data->groups[0]);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id fam15h_power_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
	{}
};
MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);

static struct pci_driver fam15h_power_driver = {
	.name = "fam15h_power",
	.id_table = fam15h_power_id_table,
	.probe = fam15h_power_probe,
	.resume = fam15h_power_resume,
};

module_pci_driver(fam15h_power_driver);
Commit	Line	Data
512d1027 AH	1	/*
	2	* fam15h_power.c - AMD Family 15h processor power monitoring
	3	*
a6e232f7	4	* Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
d034fbf0	5	* Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
512d1027 AH	6	*
	7	*
	8	* This driver is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This driver is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	15	* See the GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/err.h>
	22	#include <linux/hwmon.h>
	23	#include <linux/hwmon-sysfs.h>
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/bitops.h>
fa794344 HR	28	#include <linux/cpu.h>
fa794344 HR	29	#include <linux/cpumask.h>
11bf0d78 HR	30	#include <linux/time.h>
11bf0d78 HR	31	#include <linux/sched.h>
512d1027	32	#include <asm/processor.h>
3b5ea47d	33	#include <asm/msr.h>
512d1027 AH	34
512d1027 AH	35	MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
d034fbf0	36	MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
512d1027 AH	37	MODULE_LICENSE("GPL");
	38
	39	/* D18F3 */
	40	#define REG_NORTHBRIDGE_CAP 0xe8
	41
	42	/* D18F4 */
	43	#define REG_PROCESSOR_TDP 0x1b8
	44
	45	/* D18F5 */
	46	#define REG_TDP_RUNNING_AVERAGE 0xe0
	47	#define REG_TDP_LIMIT3 0xe8
	48
7deb14b1 HR	49	#define FAM15H_MIN_NUM_ATTRS 2
7deb14b1 HR	50	#define FAM15H_NUM_GROUPS 2
fa794344	51	#define MAX_CUS 8
7deb14b1	52
11bf0d78 HR	53	/* set maximum interval as 1 second */
	54	#define MAX_INTERVAL 1000
	55
fa794344	56	#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
3b5ea47d	57	#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
cdb9e110	58	#define MSR_F15H_PTSC 0xc0010280
3b5ea47d	59
eff2a945 HR	60	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
eff2a945 HR	61
512d1027	62	struct fam15h_power_data {
562dc973	63	struct pci_dev *pdev;
512d1027 AH	64	unsigned int tdp_to_watts;
	65	unsigned int base_tdp;
	66	unsigned int processor_pwr_watts;
1ed32160	67	unsigned int cpu_pwr_sample_ratio;
7deb14b1 HR	68	const struct attribute_group *groups[FAM15H_NUM_GROUPS];
7deb14b1 HR	69	struct attribute_group group;
3b5ea47d HR	70	/* maximum accumulated power of a compute unit */
3b5ea47d HR	71	u64 max_cu_acc_power;
fa794344 HR	72	/* accumulated power of the compute units */
fa794344 HR	73	u64 cu_acc_power[MAX_CUS];
cdb9e110 HR	74	/* performance timestamp counter */
cdb9e110 HR	75	u64 cpu_sw_pwr_ptsc[MAX_CUS];
11bf0d78 HR	76	/* online/offline status of current compute unit */
	77	int cu_on[MAX_CUS];
	78	unsigned long power_period;
512d1027 AH	79	};
512d1027 AH	80
1d28e016 HR	81	static bool is_carrizo_or_later(void)
	82	{
	83	return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
	84	}
	85
d013f7f5 JL	86	static ssize_t power1_input_show(struct device *dev,
d013f7f5 JL	87	struct device_attribute attr, char buf)
512d1027 AH	88	{
	89	u32 val, tdp_limit, running_avg_range;
	90	s32 running_avg_capture;
	91	u64 curr_pwr_watts;
512d1027	92	struct fam15h_power_data *data = dev_get_drvdata(dev);
562dc973	93	struct pci_dev *f4 = data->pdev;
512d1027 AH	94
	95	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	96	REG_TDP_RUNNING_AVERAGE, &val);
e9cd4d55 HR	97
	98	/*
	99	* On Carrizo and later platforms, TdpRunAvgAccCap bit field
	100	* is extended to 4:31 from 4:25.
	101	*/
1d28e016	102	if (is_carrizo_or_later()) {
e9cd4d55 HR	103	running_avg_capture = val >> 4;
	104	running_avg_capture = sign_extend32(running_avg_capture, 27);
	105	} else {
	106	running_avg_capture = (val >> 4) & 0x3fffff;
	107	running_avg_capture = sign_extend32(running_avg_capture, 21);
	108	}
	109
941a956b	110	running_avg_range = (val & 0xf) + 1;
512d1027 AH	111
	112	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	113	REG_TDP_LIMIT3, &val);
	114
60dee3ca GK	115	/*
	116	* On Carrizo and later platforms, ApmTdpLimit bit field
	117	* is extended to 16:31 from 16:28.
	118	*/
1d28e016	119	if (is_carrizo_or_later())
60dee3ca GK	120	tdp_limit = val >> 16;
	121	else
	122	tdp_limit = (val >> 16) & 0x1fff;
	123
62867d49 GR	124	curr_pwr_watts = ((u64)(tdp_limit +
62867d49 GR	125	data->base_tdp)) << running_avg_range;
941a956b	126	curr_pwr_watts -= running_avg_capture;
512d1027 AH	127	curr_pwr_watts *= data->tdp_to_watts;
	128
	129	/*
	130	* Convert to microWatt
	131	*
	132	* power is in Watt provided as fixed point integer with
	133	* scaling factor 1/(2^16). For conversion we use
	134	* (10^6)/(2^16) = 15625/(2^10)
	135	*/
941a956b	136	curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
512d1027 AH	137	return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
512d1027 AH	138	}
d013f7f5	139	static DEVICE_ATTR_RO(power1_input);
512d1027	140
d013f7f5 JL	141	static ssize_t power1_crit_show(struct device *dev,
d013f7f5 JL	142	struct device_attribute attr, char buf)
512d1027 AH	143	{
	144	struct fam15h_power_data *data = dev_get_drvdata(dev);
	145
	146	return sprintf(buf, "%u\n", data->processor_pwr_watts);
	147	}
d013f7f5	148	static DEVICE_ATTR_RO(power1_crit);
512d1027	149
fa794344 HR	150	static void do_read_registers_on_cu(void *_data)
	151	{
	152	struct fam15h_power_data *data = _data;
	153	int cpu, cu;
	154
	155	cpu = smp_processor_id();
	156
	157	/*
	158	* With the new x86 topology modelling, cpu core id actually
	159	* is compute unit id.
	160	*/
	161	cu = cpu_data(cpu).cpu_core_id;
	162
	163	rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
cdb9e110	164	rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
11bf0d78 HR	165
11bf0d78 HR	166	data->cu_on[cu] = 1;
fa794344 HR	167	}
	168
	169	/*
	170	* This function is only able to be called when CPUID
	171	* Fn8000_0007:EDX[12] is set.
	172	*/
	173	static int read_registers(struct fam15h_power_data *data)
	174	{
fa794344 HR	175	int core, this_core;
fa794344 HR	176	cpumask_var_t mask;
7be48818	177	int ret, cpu;
fa794344 HR	178
	179	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
	180	if (!ret)
	181	return -ENOMEM;
	182
11bf0d78 HR	183	memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
11bf0d78 HR	184
fa794344	185	get_online_cpus();
fa794344 HR	186
	187	/*
	188	* Choose the first online core of each compute unit, and then
	189	* read their MSR value of power and ptsc in a single IPI,
	190	* because the MSR value of CPU core represent the compute
	191	* unit's.
	192	*/
	193	core = -1;
	194
	195	for_each_online_cpu(cpu) {
	196	this_core = topology_core_id(cpu);
	197
	198	if (this_core == core)
	199	continue;
	200
	201	core = this_core;
	202
	203	/* get any CPU on this compute unit */
	204	cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
	205	}
	206
7be48818	207	on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
fa794344	208
fa794344	209	put_online_cpus();
fa794344 HR	210	free_cpumask_var(mask);
	211
	212	return 0;
	213	}
	214
d013f7f5 JL	215	static ssize_t power1_average_show(struct device *dev,
d013f7f5 JL	216	struct device_attribute attr, char buf)
11bf0d78 HR	217	{
	218	struct fam15h_power_data *data = dev_get_drvdata(dev);
	219	u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
	220	jdelta[MAX_CUS];
	221	u64 tdelta, avg_acc;
	222	int cu, cu_num, ret;
	223	signed long leftover;
	224
	225	/*
	226	* With the new x86 topology modelling, x86_max_cores is the
	227	* compute unit number.
	228	*/
	229	cu_num = boot_cpu_data.x86_max_cores;
	230
	231	ret = read_registers(data);
	232	if (ret)
	233	return 0;
	234
	235	for (cu = 0; cu < cu_num; cu++) {
	236	prev_cu_acc_power[cu] = data->cu_acc_power[cu];
	237	prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
	238	}
	239
	240	leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
	241	if (leftover)
	242	return 0;
	243
	244	ret = read_registers(data);
	245	if (ret)
	246	return 0;
	247
	248	for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
	249	/* check if current compute unit is online */
	250	if (data->cu_on[cu] == 0)
	251	continue;
	252
	253	if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
	254	jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
	255	jdelta[cu] -= prev_cu_acc_power[cu];
	256	} else {
	257	jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
	258	}
	259	tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
	260	jdelta[cu] = data->cpu_pwr_sample_ratio 1000;
	261	do_div(jdelta[cu], tdelta);
	262
	263	/* the unit is microWatt */
	264	avg_acc += jdelta[cu];
	265	}
	266
	267	return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
	268	}
d013f7f5	269	static DEVICE_ATTR_RO(power1_average);
11bf0d78	270
d013f7f5 JL	271	static ssize_t power1_average_interval_show(struct device *dev,
	272	struct device_attribute *attr,
	273	char *buf)
11bf0d78 HR	274	{
	275	struct fam15h_power_data *data = dev_get_drvdata(dev);
	276
	277	return sprintf(buf, "%lu\n", data->power_period);
	278	}
	279
d013f7f5 JL	280	static ssize_t power1_average_interval_store(struct device *dev,
	281	struct device_attribute *attr,
	282	const char *buf, size_t count)
11bf0d78 HR	283	{
	284	struct fam15h_power_data *data = dev_get_drvdata(dev);
	285	unsigned long temp;
	286	int ret;
	287
	288	ret = kstrtoul(buf, 10, &temp);
	289	if (ret)
	290	return ret;
	291
	292	if (temp > MAX_INTERVAL)
	293	return -EINVAL;
	294
	295	/* the interval value should be greater than 0 */
	296	if (temp <= 0)
	297	return -EINVAL;
	298
	299	data->power_period = temp;
	300
	301	return count;
	302	}
d013f7f5	303	static DEVICE_ATTR_RW(power1_average_interval);
11bf0d78	304
7deb14b1 HR	305	static int fam15h_power_init_attrs(struct pci_dev *pdev,
7deb14b1 HR	306	struct fam15h_power_data *data)
961a2378	307	{
7deb14b1 HR	308	int n = FAM15H_MIN_NUM_ATTRS;
7deb14b1 HR	309	struct attribute **fam15h_power_attrs;
46f29c2b	310	struct cpuinfo_x86 *c = &boot_cpu_data;
961a2378	311
46f29c2b HR	312	if (c->x86 == 0x15 &&
46f29c2b HR	313	(c->x86_model <= 0xf \|\|
eff2a945	314	(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
7deb14b1	315	n += 1;
961a2378	316
11bf0d78 HR	317	/* check if processor supports accumulated power */
	318	if (boot_cpu_has(X86_FEATURE_ACC_POWER))
	319	n += 2;
	320
7deb14b1 HR	321	fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
	322	sizeof(*fam15h_power_attrs),
	323	GFP_KERNEL);
512d1027	324
7deb14b1 HR	325	if (!fam15h_power_attrs)
	326	return -ENOMEM;
	327
	328	n = 0;
	329	fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
46f29c2b HR	330	if (c->x86 == 0x15 &&
46f29c2b HR	331	(c->x86_model <= 0xf \|\|
eff2a945	332	(c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
7deb14b1 HR	333	fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
7deb14b1 HR	334
11bf0d78 HR	335	if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
	336	fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
	337	fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
	338	}
	339
7deb14b1 HR	340	data->group.attrs = fam15h_power_attrs;
	341
	342	return 0;
	343	}
512d1027	344
d83e92b3	345	static bool should_load_on_this_node(struct pci_dev *f4)
512d1027 AH	346	{
	347	u32 val;
	348
	349	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
	350	REG_NORTHBRIDGE_CAP, &val);
	351	if ((val & BIT(29)) && ((val >> 30) & 3))
	352	return false;
	353
	354	return true;
	355	}
	356
00250ec9 AP	357	/*
	358	* Newer BKDG versions have an updated recommendation on how to properly
	359	* initialize the running average range (was: 0xE, now: 0x9). This avoids
	360	* counter saturations resulting in bogus power readings.
	361	* We correct this value ourselves to cope with older BIOSes.
	362	*/
5f0ecb90	363	static const struct pci_device_id affected_device[] = {
c3e40a99 GR	364	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	365	{ 0 }
	366	};
	367
5f0ecb90	368	static void tweak_runavg_range(struct pci_dev *pdev)
00250ec9 AP	369	{
00250ec9 AP	370	u32 val;
00250ec9 AP	371
	372	/*
	373	* let this quirk apply only to the current version of the
	374	* northbridge, since future versions may change the behavior
	375	*/
c3e40a99	376	if (!pci_match_id(affected_device, pdev))
00250ec9 AP	377	return;
	378
	379	pci_bus_read_config_dword(pdev->bus,
	380	PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
	381	REG_TDP_RUNNING_AVERAGE, &val);
	382	if ((val & 0xf) != 0xe)
	383	return;
	384
	385	val &= ~0xf;
	386	val \|= 0x9;
	387	pci_bus_write_config_dword(pdev->bus,
	388	PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
	389	REG_TDP_RUNNING_AVERAGE, val);
	390	}
	391
5f0ecb90 AH	392	#ifdef CONFIG_PM
	393	static int fam15h_power_resume(struct pci_dev *pdev)
	394	{
	395	tweak_runavg_range(pdev);
	396	return 0;
	397	}
	398	#else
	399	#define fam15h_power_resume NULL
	400	#endif
	401
7deb14b1 HR	402	static int fam15h_power_init_data(struct pci_dev *f4,
7deb14b1 HR	403	struct fam15h_power_data *data)
512d1027	404	{
11bf0d78	405	u32 val;
512d1027	406	u64 tmp;
7deb14b1	407	int ret;
512d1027 AH	408
	409	pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
	410	data->base_tdp = val >> 16;
	411	tmp = val & 0xffff;
	412
	413	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
	414	REG_TDP_LIMIT3, &val);
	415
	416	data->tdp_to_watts = ((val & 0x3ff) << 6) \| ((val >> 10) & 0x3f);
	417	tmp *= data->tdp_to_watts;
	418
	419	/* result not allowed to be >= 256W */
	420	if ((tmp >> 16) >= 256)
b55f3757 GR	421	dev_warn(&f4->dev,
b55f3757 GR	422	"Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
512d1027 AH	423	(unsigned int) (tmp >> 16));
	424
	425	/* convert to microWatt */
	426	data->processor_pwr_watts = (tmp * 15625) >> 10;
1ed32160	427
7deb14b1 HR	428	ret = fam15h_power_init_attrs(f4, data);
	429	if (ret)
	430	return ret;
	431
1ed32160 HR	432
1ed32160 HR	433	/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
11bf0d78	434	if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
7deb14b1	435	return 0;
1ed32160 HR	436
	437	/*
	438	* determine the ratio of the compute unit power accumulator
	439	* sample period to the PTSC counter period by executing CPUID
	440	* Fn8000_0007:ECX
	441	*/
11bf0d78	442	data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
7deb14b1	443
3b5ea47d HR	444	if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
	445	pr_err("Failed to read max compute unit power accumulator MSR\n");
	446	return -ENODEV;
	447	}
	448
	449	data->max_cu_acc_power = tmp;
	450
11bf0d78 HR	451	/*
	452	* Milliseconds are a reasonable interval for the measurement.
	453	* But it shouldn't set too long here, because several seconds
	454	* would cause the read function to hang. So set default
	455	* interval as 10 ms.
	456	*/
	457	data->power_period = 10;
	458
fa794344	459	return read_registers(data);
512d1027 AH	460	}
512d1027 AH	461
6c931ae1	462	static int fam15h_power_probe(struct pci_dev *pdev,
7deb14b1	463	const struct pci_device_id *id)
512d1027 AH	464	{
512d1027 AH	465	struct fam15h_power_data *data;
87432a2e	466	struct device *dev = &pdev->dev;
562dc973	467	struct device *hwmon_dev;
7deb14b1	468	int ret;
512d1027	469
00250ec9 AP	470	/*
	471	* though we ignore every other northbridge, we still have to
	472	* do the tweaking on _each_ node in MCM processors as the counters
	473	* are working hand-in-hand
	474	*/
	475	tweak_runavg_range(pdev);
	476
d83e92b3	477	if (!should_load_on_this_node(pdev))
87432a2e GR	478	return -ENODEV;
	479
	480	data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
	481	if (!data)
	482	return -ENOMEM;
512d1027	483
7deb14b1 HR	484	ret = fam15h_power_init_data(pdev, data);
	485	if (ret)
	486	return ret;
	487
562dc973	488	data->pdev = pdev;
512d1027	489
7deb14b1 HR	490	data->groups[0] = &data->group;
7deb14b1 HR	491
562dc973 AL	492	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
562dc973 AL	493	data,
7deb14b1	494	&data->groups[0]);
562dc973	495	return PTR_ERR_OR_ZERO(hwmon_dev);
512d1027 AH	496	}
512d1027 AH	497
cd9bb056	498	static const struct pci_device_id fam15h_power_id_table[] = {
512d1027	499	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
0a0039ad	500	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
5dc08725	501	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
eff2a945	502	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
22e32f4f	503	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
0bd52941	504	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
512d1027 AH	505	{}
	506	};
	507	MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
	508
	509	static struct pci_driver fam15h_power_driver = {
	510	.name = "fam15h_power",
	511	.id_table = fam15h_power_id_table,
	512	.probe = fam15h_power_probe,
5f0ecb90	513	.resume = fam15h_power_resume,
512d1027 AH	514	};
512d1027 AH	515
f71f5a55	516	module_pci_driver(fam15h_power_driver);