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512d1027 AH |
1 | /* |
2 | * fam15h_power.c - AMD Family 15h processor power monitoring | |
3 | * | |
4 | * Copyright (c) 2011 Advanced Micro Devices, Inc. | |
d034fbf0 | 5 | * Author: Andreas Herrmann <herrmann.der.user@googlemail.com> |
512d1027 AH |
6 | * |
7 | * | |
8 | * This driver is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This driver is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
15 | * See the GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this driver; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/err.h> | |
22 | #include <linux/hwmon.h> | |
23 | #include <linux/hwmon-sysfs.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/bitops.h> | |
fa794344 HR |
28 | #include <linux/cpu.h> |
29 | #include <linux/cpumask.h> | |
11bf0d78 HR |
30 | #include <linux/time.h> |
31 | #include <linux/sched.h> | |
512d1027 | 32 | #include <asm/processor.h> |
3b5ea47d | 33 | #include <asm/msr.h> |
512d1027 AH |
34 | |
35 | MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor"); | |
d034fbf0 | 36 | MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>"); |
512d1027 AH |
37 | MODULE_LICENSE("GPL"); |
38 | ||
39 | /* D18F3 */ | |
40 | #define REG_NORTHBRIDGE_CAP 0xe8 | |
41 | ||
42 | /* D18F4 */ | |
43 | #define REG_PROCESSOR_TDP 0x1b8 | |
44 | ||
45 | /* D18F5 */ | |
46 | #define REG_TDP_RUNNING_AVERAGE 0xe0 | |
47 | #define REG_TDP_LIMIT3 0xe8 | |
48 | ||
7deb14b1 HR |
49 | #define FAM15H_MIN_NUM_ATTRS 2 |
50 | #define FAM15H_NUM_GROUPS 2 | |
fa794344 | 51 | #define MAX_CUS 8 |
7deb14b1 | 52 | |
11bf0d78 HR |
53 | /* set maximum interval as 1 second */ |
54 | #define MAX_INTERVAL 1000 | |
55 | ||
fa794344 | 56 | #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a |
3b5ea47d | 57 | #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b |
cdb9e110 | 58 | #define MSR_F15H_PTSC 0xc0010280 |
3b5ea47d | 59 | |
eff2a945 HR |
60 | #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4 |
61 | ||
512d1027 | 62 | struct fam15h_power_data { |
562dc973 | 63 | struct pci_dev *pdev; |
512d1027 AH |
64 | unsigned int tdp_to_watts; |
65 | unsigned int base_tdp; | |
66 | unsigned int processor_pwr_watts; | |
1ed32160 | 67 | unsigned int cpu_pwr_sample_ratio; |
7deb14b1 HR |
68 | const struct attribute_group *groups[FAM15H_NUM_GROUPS]; |
69 | struct attribute_group group; | |
3b5ea47d HR |
70 | /* maximum accumulated power of a compute unit */ |
71 | u64 max_cu_acc_power; | |
fa794344 HR |
72 | /* accumulated power of the compute units */ |
73 | u64 cu_acc_power[MAX_CUS]; | |
cdb9e110 HR |
74 | /* performance timestamp counter */ |
75 | u64 cpu_sw_pwr_ptsc[MAX_CUS]; | |
11bf0d78 HR |
76 | /* online/offline status of current compute unit */ |
77 | int cu_on[MAX_CUS]; | |
78 | unsigned long power_period; | |
512d1027 AH |
79 | }; |
80 | ||
81 | static ssize_t show_power(struct device *dev, | |
82 | struct device_attribute *attr, char *buf) | |
83 | { | |
84 | u32 val, tdp_limit, running_avg_range; | |
85 | s32 running_avg_capture; | |
86 | u64 curr_pwr_watts; | |
512d1027 | 87 | struct fam15h_power_data *data = dev_get_drvdata(dev); |
562dc973 | 88 | struct pci_dev *f4 = data->pdev; |
512d1027 AH |
89 | |
90 | pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), | |
91 | REG_TDP_RUNNING_AVERAGE, &val); | |
e9cd4d55 HR |
92 | |
93 | /* | |
94 | * On Carrizo and later platforms, TdpRunAvgAccCap bit field | |
95 | * is extended to 4:31 from 4:25. | |
96 | */ | |
97 | if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60) { | |
98 | running_avg_capture = val >> 4; | |
99 | running_avg_capture = sign_extend32(running_avg_capture, 27); | |
100 | } else { | |
101 | running_avg_capture = (val >> 4) & 0x3fffff; | |
102 | running_avg_capture = sign_extend32(running_avg_capture, 21); | |
103 | } | |
104 | ||
941a956b | 105 | running_avg_range = (val & 0xf) + 1; |
512d1027 AH |
106 | |
107 | pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), | |
108 | REG_TDP_LIMIT3, &val); | |
109 | ||
60dee3ca GK |
110 | /* |
111 | * On Carrizo and later platforms, ApmTdpLimit bit field | |
112 | * is extended to 16:31 from 16:28. | |
113 | */ | |
114 | if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60) | |
115 | tdp_limit = val >> 16; | |
116 | else | |
117 | tdp_limit = (val >> 16) & 0x1fff; | |
118 | ||
62867d49 GR |
119 | curr_pwr_watts = ((u64)(tdp_limit + |
120 | data->base_tdp)) << running_avg_range; | |
941a956b | 121 | curr_pwr_watts -= running_avg_capture; |
512d1027 AH |
122 | curr_pwr_watts *= data->tdp_to_watts; |
123 | ||
124 | /* | |
125 | * Convert to microWatt | |
126 | * | |
127 | * power is in Watt provided as fixed point integer with | |
128 | * scaling factor 1/(2^16). For conversion we use | |
129 | * (10^6)/(2^16) = 15625/(2^10) | |
130 | */ | |
941a956b | 131 | curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range); |
512d1027 AH |
132 | return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts); |
133 | } | |
134 | static DEVICE_ATTR(power1_input, S_IRUGO, show_power, NULL); | |
135 | ||
136 | static ssize_t show_power_crit(struct device *dev, | |
137 | struct device_attribute *attr, char *buf) | |
138 | { | |
139 | struct fam15h_power_data *data = dev_get_drvdata(dev); | |
140 | ||
141 | return sprintf(buf, "%u\n", data->processor_pwr_watts); | |
142 | } | |
143 | static DEVICE_ATTR(power1_crit, S_IRUGO, show_power_crit, NULL); | |
144 | ||
fa794344 HR |
145 | static void do_read_registers_on_cu(void *_data) |
146 | { | |
147 | struct fam15h_power_data *data = _data; | |
148 | int cpu, cu; | |
149 | ||
150 | cpu = smp_processor_id(); | |
151 | ||
152 | /* | |
153 | * With the new x86 topology modelling, cpu core id actually | |
154 | * is compute unit id. | |
155 | */ | |
156 | cu = cpu_data(cpu).cpu_core_id; | |
157 | ||
158 | rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]); | |
cdb9e110 | 159 | rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]); |
11bf0d78 HR |
160 | |
161 | data->cu_on[cu] = 1; | |
fa794344 HR |
162 | } |
163 | ||
164 | /* | |
165 | * This function is only able to be called when CPUID | |
166 | * Fn8000_0007:EDX[12] is set. | |
167 | */ | |
168 | static int read_registers(struct fam15h_power_data *data) | |
169 | { | |
170 | int this_cpu, ret, cpu; | |
171 | int core, this_core; | |
172 | cpumask_var_t mask; | |
173 | ||
174 | ret = zalloc_cpumask_var(&mask, GFP_KERNEL); | |
175 | if (!ret) | |
176 | return -ENOMEM; | |
177 | ||
11bf0d78 HR |
178 | memset(data->cu_on, 0, sizeof(int) * MAX_CUS); |
179 | ||
fa794344 HR |
180 | get_online_cpus(); |
181 | this_cpu = smp_processor_id(); | |
182 | ||
183 | /* | |
184 | * Choose the first online core of each compute unit, and then | |
185 | * read their MSR value of power and ptsc in a single IPI, | |
186 | * because the MSR value of CPU core represent the compute | |
187 | * unit's. | |
188 | */ | |
189 | core = -1; | |
190 | ||
191 | for_each_online_cpu(cpu) { | |
192 | this_core = topology_core_id(cpu); | |
193 | ||
194 | if (this_core == core) | |
195 | continue; | |
196 | ||
197 | core = this_core; | |
198 | ||
199 | /* get any CPU on this compute unit */ | |
200 | cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask); | |
201 | } | |
202 | ||
203 | if (cpumask_test_cpu(this_cpu, mask)) | |
204 | do_read_registers_on_cu(data); | |
205 | ||
206 | smp_call_function_many(mask, do_read_registers_on_cu, data, true); | |
207 | put_online_cpus(); | |
208 | ||
209 | free_cpumask_var(mask); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
11bf0d78 HR |
214 | static ssize_t acc_show_power(struct device *dev, |
215 | struct device_attribute *attr, | |
216 | char *buf) | |
217 | { | |
218 | struct fam15h_power_data *data = dev_get_drvdata(dev); | |
219 | u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS], | |
220 | jdelta[MAX_CUS]; | |
221 | u64 tdelta, avg_acc; | |
222 | int cu, cu_num, ret; | |
223 | signed long leftover; | |
224 | ||
225 | /* | |
226 | * With the new x86 topology modelling, x86_max_cores is the | |
227 | * compute unit number. | |
228 | */ | |
229 | cu_num = boot_cpu_data.x86_max_cores; | |
230 | ||
231 | ret = read_registers(data); | |
232 | if (ret) | |
233 | return 0; | |
234 | ||
235 | for (cu = 0; cu < cu_num; cu++) { | |
236 | prev_cu_acc_power[cu] = data->cu_acc_power[cu]; | |
237 | prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu]; | |
238 | } | |
239 | ||
240 | leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period)); | |
241 | if (leftover) | |
242 | return 0; | |
243 | ||
244 | ret = read_registers(data); | |
245 | if (ret) | |
246 | return 0; | |
247 | ||
248 | for (cu = 0, avg_acc = 0; cu < cu_num; cu++) { | |
249 | /* check if current compute unit is online */ | |
250 | if (data->cu_on[cu] == 0) | |
251 | continue; | |
252 | ||
253 | if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) { | |
254 | jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu]; | |
255 | jdelta[cu] -= prev_cu_acc_power[cu]; | |
256 | } else { | |
257 | jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu]; | |
258 | } | |
259 | tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu]; | |
260 | jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000; | |
261 | do_div(jdelta[cu], tdelta); | |
262 | ||
263 | /* the unit is microWatt */ | |
264 | avg_acc += jdelta[cu]; | |
265 | } | |
266 | ||
267 | return sprintf(buf, "%llu\n", (unsigned long long)avg_acc); | |
268 | } | |
269 | static DEVICE_ATTR(power1_average, S_IRUGO, acc_show_power, NULL); | |
270 | ||
271 | static ssize_t acc_show_power_period(struct device *dev, | |
272 | struct device_attribute *attr, | |
273 | char *buf) | |
274 | { | |
275 | struct fam15h_power_data *data = dev_get_drvdata(dev); | |
276 | ||
277 | return sprintf(buf, "%lu\n", data->power_period); | |
278 | } | |
279 | ||
280 | static ssize_t acc_set_power_period(struct device *dev, | |
281 | struct device_attribute *attr, | |
282 | const char *buf, size_t count) | |
283 | { | |
284 | struct fam15h_power_data *data = dev_get_drvdata(dev); | |
285 | unsigned long temp; | |
286 | int ret; | |
287 | ||
288 | ret = kstrtoul(buf, 10, &temp); | |
289 | if (ret) | |
290 | return ret; | |
291 | ||
292 | if (temp > MAX_INTERVAL) | |
293 | return -EINVAL; | |
294 | ||
295 | /* the interval value should be greater than 0 */ | |
296 | if (temp <= 0) | |
297 | return -EINVAL; | |
298 | ||
299 | data->power_period = temp; | |
300 | ||
301 | return count; | |
302 | } | |
303 | static DEVICE_ATTR(power1_average_interval, S_IRUGO | S_IWUSR, | |
304 | acc_show_power_period, acc_set_power_period); | |
305 | ||
7deb14b1 HR |
306 | static int fam15h_power_init_attrs(struct pci_dev *pdev, |
307 | struct fam15h_power_data *data) | |
961a2378 | 308 | { |
7deb14b1 HR |
309 | int n = FAM15H_MIN_NUM_ATTRS; |
310 | struct attribute **fam15h_power_attrs; | |
46f29c2b | 311 | struct cpuinfo_x86 *c = &boot_cpu_data; |
961a2378 | 312 | |
46f29c2b HR |
313 | if (c->x86 == 0x15 && |
314 | (c->x86_model <= 0xf || | |
eff2a945 | 315 | (c->x86_model >= 0x60 && c->x86_model <= 0x7f))) |
7deb14b1 | 316 | n += 1; |
961a2378 | 317 | |
11bf0d78 HR |
318 | /* check if processor supports accumulated power */ |
319 | if (boot_cpu_has(X86_FEATURE_ACC_POWER)) | |
320 | n += 2; | |
321 | ||
7deb14b1 HR |
322 | fam15h_power_attrs = devm_kcalloc(&pdev->dev, n, |
323 | sizeof(*fam15h_power_attrs), | |
324 | GFP_KERNEL); | |
512d1027 | 325 | |
7deb14b1 HR |
326 | if (!fam15h_power_attrs) |
327 | return -ENOMEM; | |
328 | ||
329 | n = 0; | |
330 | fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr; | |
46f29c2b HR |
331 | if (c->x86 == 0x15 && |
332 | (c->x86_model <= 0xf || | |
eff2a945 | 333 | (c->x86_model >= 0x60 && c->x86_model <= 0x7f))) |
7deb14b1 HR |
334 | fam15h_power_attrs[n++] = &dev_attr_power1_input.attr; |
335 | ||
11bf0d78 HR |
336 | if (boot_cpu_has(X86_FEATURE_ACC_POWER)) { |
337 | fam15h_power_attrs[n++] = &dev_attr_power1_average.attr; | |
338 | fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr; | |
339 | } | |
340 | ||
7deb14b1 HR |
341 | data->group.attrs = fam15h_power_attrs; |
342 | ||
343 | return 0; | |
344 | } | |
512d1027 | 345 | |
d83e92b3 | 346 | static bool should_load_on_this_node(struct pci_dev *f4) |
512d1027 AH |
347 | { |
348 | u32 val; | |
349 | ||
350 | pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3), | |
351 | REG_NORTHBRIDGE_CAP, &val); | |
352 | if ((val & BIT(29)) && ((val >> 30) & 3)) | |
353 | return false; | |
354 | ||
355 | return true; | |
356 | } | |
357 | ||
00250ec9 AP |
358 | /* |
359 | * Newer BKDG versions have an updated recommendation on how to properly | |
360 | * initialize the running average range (was: 0xE, now: 0x9). This avoids | |
361 | * counter saturations resulting in bogus power readings. | |
362 | * We correct this value ourselves to cope with older BIOSes. | |
363 | */ | |
5f0ecb90 | 364 | static const struct pci_device_id affected_device[] = { |
c3e40a99 GR |
365 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, |
366 | { 0 } | |
367 | }; | |
368 | ||
5f0ecb90 | 369 | static void tweak_runavg_range(struct pci_dev *pdev) |
00250ec9 AP |
370 | { |
371 | u32 val; | |
00250ec9 AP |
372 | |
373 | /* | |
374 | * let this quirk apply only to the current version of the | |
375 | * northbridge, since future versions may change the behavior | |
376 | */ | |
c3e40a99 | 377 | if (!pci_match_id(affected_device, pdev)) |
00250ec9 AP |
378 | return; |
379 | ||
380 | pci_bus_read_config_dword(pdev->bus, | |
381 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), | |
382 | REG_TDP_RUNNING_AVERAGE, &val); | |
383 | if ((val & 0xf) != 0xe) | |
384 | return; | |
385 | ||
386 | val &= ~0xf; | |
387 | val |= 0x9; | |
388 | pci_bus_write_config_dword(pdev->bus, | |
389 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), | |
390 | REG_TDP_RUNNING_AVERAGE, val); | |
391 | } | |
392 | ||
5f0ecb90 AH |
393 | #ifdef CONFIG_PM |
394 | static int fam15h_power_resume(struct pci_dev *pdev) | |
395 | { | |
396 | tweak_runavg_range(pdev); | |
397 | return 0; | |
398 | } | |
399 | #else | |
400 | #define fam15h_power_resume NULL | |
401 | #endif | |
402 | ||
7deb14b1 HR |
403 | static int fam15h_power_init_data(struct pci_dev *f4, |
404 | struct fam15h_power_data *data) | |
512d1027 | 405 | { |
11bf0d78 | 406 | u32 val; |
512d1027 | 407 | u64 tmp; |
7deb14b1 | 408 | int ret; |
512d1027 AH |
409 | |
410 | pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val); | |
411 | data->base_tdp = val >> 16; | |
412 | tmp = val & 0xffff; | |
413 | ||
414 | pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), | |
415 | REG_TDP_LIMIT3, &val); | |
416 | ||
417 | data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f); | |
418 | tmp *= data->tdp_to_watts; | |
419 | ||
420 | /* result not allowed to be >= 256W */ | |
421 | if ((tmp >> 16) >= 256) | |
b55f3757 GR |
422 | dev_warn(&f4->dev, |
423 | "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n", | |
512d1027 AH |
424 | (unsigned int) (tmp >> 16)); |
425 | ||
426 | /* convert to microWatt */ | |
427 | data->processor_pwr_watts = (tmp * 15625) >> 10; | |
1ed32160 | 428 | |
7deb14b1 HR |
429 | ret = fam15h_power_init_attrs(f4, data); |
430 | if (ret) | |
431 | return ret; | |
432 | ||
1ed32160 HR |
433 | |
434 | /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */ | |
11bf0d78 | 435 | if (!boot_cpu_has(X86_FEATURE_ACC_POWER)) |
7deb14b1 | 436 | return 0; |
1ed32160 HR |
437 | |
438 | /* | |
439 | * determine the ratio of the compute unit power accumulator | |
440 | * sample period to the PTSC counter period by executing CPUID | |
441 | * Fn8000_0007:ECX | |
442 | */ | |
11bf0d78 | 443 | data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007); |
7deb14b1 | 444 | |
3b5ea47d HR |
445 | if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) { |
446 | pr_err("Failed to read max compute unit power accumulator MSR\n"); | |
447 | return -ENODEV; | |
448 | } | |
449 | ||
450 | data->max_cu_acc_power = tmp; | |
451 | ||
11bf0d78 HR |
452 | /* |
453 | * Milliseconds are a reasonable interval for the measurement. | |
454 | * But it shouldn't set too long here, because several seconds | |
455 | * would cause the read function to hang. So set default | |
456 | * interval as 10 ms. | |
457 | */ | |
458 | data->power_period = 10; | |
459 | ||
fa794344 | 460 | return read_registers(data); |
512d1027 AH |
461 | } |
462 | ||
6c931ae1 | 463 | static int fam15h_power_probe(struct pci_dev *pdev, |
7deb14b1 | 464 | const struct pci_device_id *id) |
512d1027 AH |
465 | { |
466 | struct fam15h_power_data *data; | |
87432a2e | 467 | struct device *dev = &pdev->dev; |
562dc973 | 468 | struct device *hwmon_dev; |
7deb14b1 | 469 | int ret; |
512d1027 | 470 | |
00250ec9 AP |
471 | /* |
472 | * though we ignore every other northbridge, we still have to | |
473 | * do the tweaking on _each_ node in MCM processors as the counters | |
474 | * are working hand-in-hand | |
475 | */ | |
476 | tweak_runavg_range(pdev); | |
477 | ||
d83e92b3 | 478 | if (!should_load_on_this_node(pdev)) |
87432a2e GR |
479 | return -ENODEV; |
480 | ||
481 | data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL); | |
482 | if (!data) | |
483 | return -ENOMEM; | |
512d1027 | 484 | |
7deb14b1 HR |
485 | ret = fam15h_power_init_data(pdev, data); |
486 | if (ret) | |
487 | return ret; | |
488 | ||
562dc973 | 489 | data->pdev = pdev; |
512d1027 | 490 | |
7deb14b1 HR |
491 | data->groups[0] = &data->group; |
492 | ||
562dc973 AL |
493 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power", |
494 | data, | |
7deb14b1 | 495 | &data->groups[0]); |
562dc973 | 496 | return PTR_ERR_OR_ZERO(hwmon_dev); |
512d1027 AH |
497 | } |
498 | ||
cd9bb056 | 499 | static const struct pci_device_id fam15h_power_id_table[] = { |
512d1027 | 500 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, |
0a0039ad | 501 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, |
5dc08725 | 502 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) }, |
eff2a945 | 503 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) }, |
22e32f4f | 504 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, |
0bd52941 | 505 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) }, |
512d1027 AH |
506 | {} |
507 | }; | |
508 | MODULE_DEVICE_TABLE(pci, fam15h_power_id_table); | |
509 | ||
510 | static struct pci_driver fam15h_power_driver = { | |
511 | .name = "fam15h_power", | |
512 | .id_table = fam15h_power_id_table, | |
513 | .probe = fam15h_power_probe, | |
5f0ecb90 | 514 | .resume = fam15h_power_resume, |
512d1027 AH |
515 | }; |
516 | ||
f71f5a55 | 517 | module_pci_driver(fam15h_power_driver); |