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1/*
2 * INA3221 Triple Current/Voltage Monitor
3 *
4 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
5 * Andrew F. Davis <afd@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17#include <linux/hwmon.h>
18#include <linux/hwmon-sysfs.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
87625b24 21#include <linux/mutex.h>
7cb6dcff 22#include <linux/of.h>
323aeb0e 23#include <linux/pm_runtime.h>
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24#include <linux/regmap.h>
25
26#define INA3221_DRIVER_NAME "ina3221"
27
28#define INA3221_CONFIG 0x00
29#define INA3221_SHUNT1 0x01
30#define INA3221_BUS1 0x02
31#define INA3221_SHUNT2 0x03
32#define INA3221_BUS2 0x04
33#define INA3221_SHUNT3 0x05
34#define INA3221_BUS3 0x06
35#define INA3221_CRIT1 0x07
36#define INA3221_WARN1 0x08
37#define INA3221_CRIT2 0x09
38#define INA3221_WARN2 0x0a
39#define INA3221_CRIT3 0x0b
40#define INA3221_WARN3 0x0c
41#define INA3221_MASK_ENABLE 0x0f
42
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43#define INA3221_CONFIG_MODE_MASK GENMASK(2, 0)
44#define INA3221_CONFIG_MODE_POWERDOWN 0
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45#define INA3221_CONFIG_MODE_SHUNT BIT(0)
46#define INA3221_CONFIG_MODE_BUS BIT(1)
47#define INA3221_CONFIG_MODE_CONTINUOUS BIT(2)
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48#define INA3221_CONFIG_VSH_CT_SHIFT 3
49#define INA3221_CONFIG_VSH_CT_MASK GENMASK(5, 3)
50#define INA3221_CONFIG_VSH_CT(x) (((x) & GENMASK(5, 3)) >> 3)
51#define INA3221_CONFIG_VBUS_CT_SHIFT 6
52#define INA3221_CONFIG_VBUS_CT_MASK GENMASK(8, 6)
53#define INA3221_CONFIG_VBUS_CT(x) (((x) & GENMASK(8, 6)) >> 6)
54#define INA3221_CONFIG_CHs_EN_MASK GENMASK(14, 12)
a9e9dd9c 55#define INA3221_CONFIG_CHx_EN(x) BIT(14 - (x))
7cb6dcff 56
323aeb0e 57#define INA3221_CONFIG_DEFAULT 0x7127
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58#define INA3221_RSHUNT_DEFAULT 10000
59
60enum ina3221_fields {
61 /* Configuration */
62 F_RST,
63
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64 /* Status Flags */
65 F_CVRF,
66
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67 /* Alert Flags */
68 F_WF3, F_WF2, F_WF1,
69 F_CF3, F_CF2, F_CF1,
70
71 /* sentinel */
72 F_MAX_FIELDS
73};
74
75static const struct reg_field ina3221_reg_fields[] = {
76 [F_RST] = REG_FIELD(INA3221_CONFIG, 15, 15),
77
4c0415a3 78 [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0),
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79 [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3),
80 [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4),
81 [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5),
82 [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7),
83 [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8),
84 [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9),
85};
86
87enum ina3221_channels {
88 INA3221_CHANNEL1,
89 INA3221_CHANNEL2,
90 INA3221_CHANNEL3,
91 INA3221_NUM_CHANNELS
92};
93
a9e9dd9c
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94/**
95 * struct ina3221_input - channel input source specific information
96 * @label: label of channel input source
97 * @shunt_resistor: shunt resistor value of channel input source
98 * @disconnected: connection status of channel input source
99 */
100struct ina3221_input {
101 const char *label;
102 int shunt_resistor;
103 bool disconnected;
104};
105
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106/**
107 * struct ina3221_data - device specific information
323aeb0e 108 * @pm_dev: Device pointer for pm runtime
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109 * @regmap: Register map of the device
110 * @fields: Register fields of the device
a9e9dd9c 111 * @inputs: Array of channel input source specific structures
87625b24 112 * @lock: mutex lock to serialize sysfs attribute accesses
59d608e1 113 * @reg_config: Register value of INA3221_CONFIG
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114 */
115struct ina3221_data {
323aeb0e 116 struct device *pm_dev;
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117 struct regmap *regmap;
118 struct regmap_field *fields[F_MAX_FIELDS];
a9e9dd9c 119 struct ina3221_input inputs[INA3221_NUM_CHANNELS];
87625b24 120 struct mutex lock;
59d608e1 121 u32 reg_config;
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122};
123
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124static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channel)
125{
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126 return pm_runtime_active(ina->pm_dev) &&
127 (ina->reg_config & INA3221_CONFIG_CHx_EN(channel));
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128}
129
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130/* Lookup table for Bus and Shunt conversion times in usec */
131static const u16 ina3221_conv_time[] = {
132 140, 204, 332, 588, 1100, 2116, 4156, 8244,
133};
134
135static inline int ina3221_wait_for_data(struct ina3221_data *ina)
136{
137 u32 channels = hweight16(ina->reg_config & INA3221_CONFIG_CHs_EN_MASK);
138 u32 vbus_ct_idx = INA3221_CONFIG_VBUS_CT(ina->reg_config);
139 u32 vsh_ct_idx = INA3221_CONFIG_VSH_CT(ina->reg_config);
140 u32 vbus_ct = ina3221_conv_time[vbus_ct_idx];
141 u32 vsh_ct = ina3221_conv_time[vsh_ct_idx];
142 u32 wait, cvrf;
143
144 /* Calculate total conversion time */
145 wait = channels * (vbus_ct + vsh_ct);
146
147 /* Polling the CVRF bit to make sure read data is ready */
148 return regmap_field_read_poll_timeout(ina->fields[F_CVRF],
149 cvrf, cvrf, wait, 100000);
150}
151
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152static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
153 int *val)
154{
155 unsigned int regval;
156 int ret;
157
158 ret = regmap_read(ina->regmap, reg, &regval);
159 if (ret)
160 return ret;
161
162 *val = sign_extend32(regval >> 3, 12);
163
164 return 0;
165}
166
167static const u8 ina3221_in_reg[] = {
168 INA3221_BUS1,
169 INA3221_BUS2,
170 INA3221_BUS3,
171 INA3221_SHUNT1,
172 INA3221_SHUNT2,
173 INA3221_SHUNT3,
174};
175
176static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val)
177{
178 const bool is_shunt = channel > INA3221_CHANNEL3;
179 struct ina3221_data *ina = dev_get_drvdata(dev);
180 u8 reg = ina3221_in_reg[channel];
181 int regval, ret;
182
183 /* Translate shunt channel index to sensor channel index */
184 channel %= INA3221_NUM_CHANNELS;
185
186 switch (attr) {
187 case hwmon_in_input:
188 if (!ina3221_is_enabled(ina, channel))
189 return -ENODATA;
190
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191 ret = ina3221_wait_for_data(ina);
192 if (ret)
193 return ret;
194
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195 ret = ina3221_read_value(ina, reg, &regval);
196 if (ret)
197 return ret;
198
199 /*
200 * Scale of shunt voltage (uV): LSB is 40uV
201 * Scale of bus voltage (mV): LSB is 8mV
202 */
203 *val = regval * (is_shunt ? 40 : 8);
204 return 0;
205 case hwmon_in_enable:
206 *val = ina3221_is_enabled(ina, channel);
207 return 0;
208 default:
209 return -EOPNOTSUPP;
210 }
211}
212
213static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNELS] = {
214 [hwmon_curr_input] = { INA3221_SHUNT1, INA3221_SHUNT2, INA3221_SHUNT3 },
215 [hwmon_curr_max] = { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3 },
216 [hwmon_curr_crit] = { INA3221_CRIT1, INA3221_CRIT2, INA3221_CRIT3 },
217 [hwmon_curr_max_alarm] = { F_WF1, F_WF2, F_WF3 },
218 [hwmon_curr_crit_alarm] = { F_CF1, F_CF2, F_CF3 },
219};
220
221static int ina3221_read_curr(struct device *dev, u32 attr,
222 int channel, long *val)
a9e9dd9c 223{
a9e9dd9c 224 struct ina3221_data *ina = dev_get_drvdata(dev);
a9e9dd9c 225 struct ina3221_input *input = &ina->inputs[channel];
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226 int resistance_uo = input->shunt_resistor;
227 u8 reg = ina3221_curr_reg[attr][channel];
228 int regval, voltage_nv, ret;
229
230 switch (attr) {
231 case hwmon_curr_input:
232 if (!ina3221_is_enabled(ina, channel))
233 return -ENODATA;
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234
235 ret = ina3221_wait_for_data(ina);
236 if (ret)
237 return ret;
238
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239 /* fall through */
240 case hwmon_curr_crit:
241 case hwmon_curr_max:
242 ret = ina3221_read_value(ina, reg, &regval);
243 if (ret)
244 return ret;
a9e9dd9c 245
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246 /* Scale of shunt voltage: LSB is 40uV (40000nV) */
247 voltage_nv = regval * 40000;
248 /* Return current in mA */
249 *val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo);
250 return 0;
251 case hwmon_curr_crit_alarm:
252 case hwmon_curr_max_alarm:
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253 /* No actual register read if channel is disabled */
254 if (!ina3221_is_enabled(ina, channel)) {
255 /* Return 0 for alert flags */
256 *val = 0;
257 return 0;
258 }
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259 ret = regmap_field_read(ina->fields[reg], &regval);
260 if (ret)
261 return ret;
262 *val = regval;
263 return 0;
264 default:
265 return -EOPNOTSUPP;
266 }
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267}
268
d4b0166d
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269static int ina3221_write_curr(struct device *dev, u32 attr,
270 int channel, long val)
a9e9dd9c 271{
a9e9dd9c 272 struct ina3221_data *ina = dev_get_drvdata(dev);
d4b0166d
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273 struct ina3221_input *input = &ina->inputs[channel];
274 int resistance_uo = input->shunt_resistor;
275 u8 reg = ina3221_curr_reg[attr][channel];
276 int regval, current_ma, voltage_uv;
277
278 /* clamp current */
279 current_ma = clamp_val(val,
280 INT_MIN / resistance_uo,
281 INT_MAX / resistance_uo);
282
283 voltage_uv = DIV_ROUND_CLOSEST(current_ma * resistance_uo, 1000);
284
285 /* clamp voltage */
286 voltage_uv = clamp_val(voltage_uv, -163800, 163800);
287
288 /* 1 / 40uV(scale) << 3(register shift) = 5 */
289 regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8;
a9e9dd9c 290
d4b0166d 291 return regmap_write(ina->regmap, reg, regval);
a9e9dd9c
NC
292}
293
d4b0166d 294static int ina3221_write_enable(struct device *dev, int channel, bool enable)
a9e9dd9c 295{
a9e9dd9c 296 struct ina3221_data *ina = dev_get_drvdata(dev);
a9e9dd9c 297 u16 config, mask = INA3221_CONFIG_CHx_EN(channel);
323aeb0e 298 u16 config_old = ina->reg_config & mask;
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299 int ret;
300
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301 config = enable ? mask : 0;
302
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303 /* Bypass if enable status is not being changed */
304 if (config_old == config)
305 return 0;
306
307 /* For enabling routine, increase refcount and resume() at first */
308 if (enable) {
309 ret = pm_runtime_get_sync(ina->pm_dev);
310 if (ret < 0) {
311 dev_err(dev, "Failed to get PM runtime\n");
312 return ret;
313 }
314 }
315
a9e9dd9c
NC
316 /* Enable or disable the channel */
317 ret = regmap_update_bits(ina->regmap, INA3221_CONFIG, mask, config);
318 if (ret)
323aeb0e 319 goto fail;
a9e9dd9c
NC
320
321 /* Cache the latest config register value */
322 ret = regmap_read(ina->regmap, INA3221_CONFIG, &ina->reg_config);
323 if (ret)
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NC
324 goto fail;
325
326 /* For disabling routine, decrease refcount or suspend() at last */
327 if (!enable)
328 pm_runtime_put_sync(ina->pm_dev);
a9e9dd9c 329
d4b0166d 330 return 0;
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331
332fail:
333 if (enable) {
334 dev_err(dev, "Failed to enable channel %d: error %d\n",
335 channel, ret);
336 pm_runtime_put_sync(ina->pm_dev);
337 }
338
339 return ret;
a9e9dd9c
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340}
341
d4b0166d
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342static int ina3221_read(struct device *dev, enum hwmon_sensor_types type,
343 u32 attr, int channel, long *val)
7cb6dcff 344{
87625b24
NC
345 struct ina3221_data *ina = dev_get_drvdata(dev);
346 int ret;
347
348 mutex_lock(&ina->lock);
349
d4b0166d
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350 switch (type) {
351 case hwmon_in:
352 /* 0-align channel ID */
87625b24
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353 ret = ina3221_read_in(dev, attr, channel - 1, val);
354 break;
d4b0166d 355 case hwmon_curr:
87625b24
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356 ret = ina3221_read_curr(dev, attr, channel, val);
357 break;
d4b0166d 358 default:
87625b24
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359 ret = -EOPNOTSUPP;
360 break;
d4b0166d 361 }
87625b24
NC
362
363 mutex_unlock(&ina->lock);
364
365 return ret;
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AD
366}
367
d4b0166d
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368static int ina3221_write(struct device *dev, enum hwmon_sensor_types type,
369 u32 attr, int channel, long val)
7cb6dcff 370{
87625b24
NC
371 struct ina3221_data *ina = dev_get_drvdata(dev);
372 int ret;
373
374 mutex_lock(&ina->lock);
375
d4b0166d
NC
376 switch (type) {
377 case hwmon_in:
378 /* 0-align channel ID */
87625b24
NC
379 ret = ina3221_write_enable(dev, channel - 1, val);
380 break;
d4b0166d 381 case hwmon_curr:
87625b24
NC
382 ret = ina3221_write_curr(dev, attr, channel, val);
383 break;
d4b0166d 384 default:
87625b24
NC
385 ret = -EOPNOTSUPP;
386 break;
d4b0166d 387 }
87625b24
NC
388
389 mutex_unlock(&ina->lock);
390
391 return ret;
7cb6dcff
AD
392}
393
d4b0166d
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394static int ina3221_read_string(struct device *dev, enum hwmon_sensor_types type,
395 u32 attr, int channel, const char **str)
7cb6dcff 396{
7cb6dcff 397 struct ina3221_data *ina = dev_get_drvdata(dev);
d4b0166d 398 int index = channel - 1;
7cb6dcff 399
d4b0166d 400 *str = ina->inputs[index].label;
a9e9dd9c 401
d4b0166d 402 return 0;
7cb6dcff
AD
403}
404
d4b0166d
NC
405static umode_t ina3221_is_visible(const void *drvdata,
406 enum hwmon_sensor_types type,
407 u32 attr, int channel)
7cb6dcff 408{
d4b0166d
NC
409 const struct ina3221_data *ina = drvdata;
410 const struct ina3221_input *input = NULL;
411
412 switch (type) {
413 case hwmon_in:
414 /* Ignore in0_ */
415 if (channel == 0)
416 return 0;
417
418 switch (attr) {
419 case hwmon_in_label:
420 if (channel - 1 <= INA3221_CHANNEL3)
421 input = &ina->inputs[channel - 1];
422 /* Hide label node if label is not provided */
423 return (input && input->label) ? 0444 : 0;
424 case hwmon_in_input:
425 return 0444;
426 case hwmon_in_enable:
427 return 0644;
428 default:
429 return 0;
430 }
431 case hwmon_curr:
432 switch (attr) {
433 case hwmon_curr_input:
434 case hwmon_curr_crit_alarm:
435 case hwmon_curr_max_alarm:
436 return 0444;
437 case hwmon_curr_crit:
438 case hwmon_curr_max:
439 return 0644;
440 default:
441 return 0;
442 }
443 default:
444 return 0;
445 }
7cb6dcff
AD
446}
447
d4b0166d
NC
448static const u32 ina3221_in_config[] = {
449 /* 0: dummy, skipped in is_visible */
450 HWMON_I_INPUT,
451 /* 1-3: input voltage Channels */
452 HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
453 HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
454 HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
455 /* 4-6: shunt voltage Channels */
456 HWMON_I_INPUT,
457 HWMON_I_INPUT,
458 HWMON_I_INPUT,
459 0
460};
7cb6dcff 461
d4b0166d
NC
462static const struct hwmon_channel_info ina3221_in = {
463 .type = hwmon_in,
464 .config = ina3221_in_config,
465};
7cb6dcff 466
d4b0166d
NC
467#define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \
468 HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \
469 HWMON_C_MAX | HWMON_C_MAX_ALARM)
7cb6dcff 470
d4b0166d
NC
471static const u32 ina3221_curr_config[] = {
472 INA3221_HWMON_CURR_CONFIG,
473 INA3221_HWMON_CURR_CONFIG,
474 INA3221_HWMON_CURR_CONFIG,
475 0
476};
7cb6dcff 477
d4b0166d
NC
478static const struct hwmon_channel_info ina3221_curr = {
479 .type = hwmon_curr,
480 .config = ina3221_curr_config,
481};
7cb6dcff 482
d4b0166d
NC
483static const struct hwmon_channel_info *ina3221_info[] = {
484 &ina3221_in,
485 &ina3221_curr,
486 NULL
487};
7cb6dcff 488
d4b0166d
NC
489static const struct hwmon_ops ina3221_hwmon_ops = {
490 .is_visible = ina3221_is_visible,
491 .read_string = ina3221_read_string,
492 .read = ina3221_read,
493 .write = ina3221_write,
494};
7cb6dcff 495
d4b0166d
NC
496static const struct hwmon_chip_info ina3221_chip_info = {
497 .ops = &ina3221_hwmon_ops,
498 .info = ina3221_info,
499};
7cb6dcff 500
d4b0166d 501/* Extra attribute groups */
a4ec92ed 502static ssize_t ina3221_shunt_show(struct device *dev,
7cb6dcff
AD
503 struct device_attribute *attr, char *buf)
504{
505 struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr);
506 struct ina3221_data *ina = dev_get_drvdata(dev);
507 unsigned int channel = sd_attr->index;
a9e9dd9c 508 struct ina3221_input *input = &ina->inputs[channel];
7cb6dcff 509
a9e9dd9c 510 return snprintf(buf, PAGE_SIZE, "%d\n", input->shunt_resistor);
7cb6dcff
AD
511}
512
a4ec92ed
GR
513static ssize_t ina3221_shunt_store(struct device *dev,
514 struct device_attribute *attr,
515 const char *buf, size_t count)
7cb6dcff
AD
516{
517 struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr);
518 struct ina3221_data *ina = dev_get_drvdata(dev);
519 unsigned int channel = sd_attr->index;
a9e9dd9c 520 struct ina3221_input *input = &ina->inputs[channel];
9ad0df1a 521 int val;
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522 int ret;
523
9ad0df1a 524 ret = kstrtoint(buf, 0, &val);
7cb6dcff
AD
525 if (ret)
526 return ret;
527
9ad0df1a 528 val = clamp_val(val, 1, INT_MAX);
7cb6dcff 529
a9e9dd9c 530 input->shunt_resistor = val;
7cb6dcff
AD
531
532 return count;
533}
534
7cb6dcff 535/* shunt resistance */
a4ec92ed
GR
536static SENSOR_DEVICE_ATTR_RW(shunt1_resistor, ina3221_shunt, INA3221_CHANNEL1);
537static SENSOR_DEVICE_ATTR_RW(shunt2_resistor, ina3221_shunt, INA3221_CHANNEL2);
538static SENSOR_DEVICE_ATTR_RW(shunt3_resistor, ina3221_shunt, INA3221_CHANNEL3);
7cb6dcff 539
7cb6dcff 540static struct attribute *ina3221_attrs[] = {
7cb6dcff 541 &sensor_dev_attr_shunt1_resistor.dev_attr.attr,
7cb6dcff 542 &sensor_dev_attr_shunt2_resistor.dev_attr.attr,
7cb6dcff 543 &sensor_dev_attr_shunt3_resistor.dev_attr.attr,
7cb6dcff
AD
544 NULL,
545};
d4b0166d 546ATTRIBUTE_GROUPS(ina3221);
7cb6dcff
AD
547
548static const struct regmap_range ina3221_yes_ranges[] = {
c20217b3 549 regmap_reg_range(INA3221_CONFIG, INA3221_BUS3),
7cb6dcff
AD
550 regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE),
551};
552
553static const struct regmap_access_table ina3221_volatile_table = {
554 .yes_ranges = ina3221_yes_ranges,
555 .n_yes_ranges = ARRAY_SIZE(ina3221_yes_ranges),
556};
557
558static const struct regmap_config ina3221_regmap_config = {
559 .reg_bits = 8,
560 .val_bits = 16,
561
562 .cache_type = REGCACHE_RBTREE,
563 .volatile_table = &ina3221_volatile_table,
564};
565
a9e9dd9c
NC
566static int ina3221_probe_child_from_dt(struct device *dev,
567 struct device_node *child,
568 struct ina3221_data *ina)
569{
570 struct ina3221_input *input;
571 u32 val;
572 int ret;
573
574 ret = of_property_read_u32(child, "reg", &val);
575 if (ret) {
1b1f4efa 576 dev_err(dev, "missing reg property of %pOFn\n", child);
a9e9dd9c
NC
577 return ret;
578 } else if (val > INA3221_CHANNEL3) {
1b1f4efa 579 dev_err(dev, "invalid reg %d of %pOFn\n", val, child);
a9e9dd9c
NC
580 return ret;
581 }
582
583 input = &ina->inputs[val];
584
585 /* Log the disconnected channel input */
586 if (!of_device_is_available(child)) {
587 input->disconnected = true;
588 return 0;
589 }
590
591 /* Save the connected input label if available */
592 of_property_read_string(child, "label", &input->label);
593
594 /* Overwrite default shunt resistor value optionally */
a6e43263
NC
595 if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) {
596 if (val < 1 || val > INT_MAX) {
1b1f4efa
RH
597 dev_err(dev, "invalid shunt resistor value %u of %pOFn\n",
598 val, child);
a6e43263
NC
599 return -EINVAL;
600 }
a9e9dd9c 601 input->shunt_resistor = val;
a6e43263 602 }
a9e9dd9c
NC
603
604 return 0;
605}
606
607static int ina3221_probe_from_dt(struct device *dev, struct ina3221_data *ina)
608{
609 const struct device_node *np = dev->of_node;
610 struct device_node *child;
611 int ret;
612
613 /* Compatible with non-DT platforms */
614 if (!np)
615 return 0;
616
617 for_each_child_of_node(np, child) {
618 ret = ina3221_probe_child_from_dt(dev, child, ina);
619 if (ret)
620 return ret;
621 }
622
623 return 0;
624}
625
7cb6dcff
AD
626static int ina3221_probe(struct i2c_client *client,
627 const struct i2c_device_id *id)
628{
629 struct device *dev = &client->dev;
630 struct ina3221_data *ina;
631 struct device *hwmon_dev;
632 int i, ret;
633
634 ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL);
635 if (!ina)
636 return -ENOMEM;
637
638 ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config);
639 if (IS_ERR(ina->regmap)) {
640 dev_err(dev, "Unable to allocate register map\n");
641 return PTR_ERR(ina->regmap);
642 }
643
644 for (i = 0; i < F_MAX_FIELDS; i++) {
645 ina->fields[i] = devm_regmap_field_alloc(dev,
646 ina->regmap,
647 ina3221_reg_fields[i]);
648 if (IS_ERR(ina->fields[i])) {
649 dev_err(dev, "Unable to allocate regmap fields\n");
650 return PTR_ERR(ina->fields[i]);
651 }
652 }
653
654 for (i = 0; i < INA3221_NUM_CHANNELS; i++)
a9e9dd9c
NC
655 ina->inputs[i].shunt_resistor = INA3221_RSHUNT_DEFAULT;
656
657 ret = ina3221_probe_from_dt(dev, ina);
658 if (ret) {
659 dev_err(dev, "Unable to probe from device tree\n");
660 return ret;
661 }
7cb6dcff 662
323aeb0e
NC
663 /* The driver will be reset, so use reset value */
664 ina->reg_config = INA3221_CONFIG_DEFAULT;
a9e9dd9c
NC
665
666 /* Disable channels if their inputs are disconnected */
667 for (i = 0; i < INA3221_NUM_CHANNELS; i++) {
668 if (ina->inputs[i].disconnected)
669 ina->reg_config &= ~INA3221_CONFIG_CHx_EN(i);
670 }
a9e9dd9c 671
323aeb0e 672 ina->pm_dev = dev;
87625b24 673 mutex_init(&ina->lock);
59d608e1
NC
674 dev_set_drvdata(dev, ina);
675
323aeb0e
NC
676 /* Enable PM runtime -- status is suspended by default */
677 pm_runtime_enable(ina->pm_dev);
678
679 /* Initialize (resume) the device */
680 for (i = 0; i < INA3221_NUM_CHANNELS; i++) {
681 if (ina->inputs[i].disconnected)
682 continue;
683 /* Match the refcount with number of enabled channels */
684 ret = pm_runtime_get_sync(ina->pm_dev);
685 if (ret < 0)
686 goto fail;
687 }
688
d4b0166d
NC
689 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, ina,
690 &ina3221_chip_info,
691 ina3221_groups);
7cb6dcff
AD
692 if (IS_ERR(hwmon_dev)) {
693 dev_err(dev, "Unable to register hwmon device\n");
323aeb0e
NC
694 ret = PTR_ERR(hwmon_dev);
695 goto fail;
7cb6dcff
AD
696 }
697
698 return 0;
323aeb0e
NC
699
700fail:
701 pm_runtime_disable(ina->pm_dev);
702 pm_runtime_set_suspended(ina->pm_dev);
703 /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */
704 for (i = 0; i < INA3221_NUM_CHANNELS; i++)
705 pm_runtime_put_noidle(ina->pm_dev);
706 mutex_destroy(&ina->lock);
707
708 return ret;
7cb6dcff
AD
709}
710
87625b24
NC
711static int ina3221_remove(struct i2c_client *client)
712{
713 struct ina3221_data *ina = dev_get_drvdata(&client->dev);
323aeb0e
NC
714 int i;
715
716 pm_runtime_disable(ina->pm_dev);
717 pm_runtime_set_suspended(ina->pm_dev);
718
719 /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */
720 for (i = 0; i < INA3221_NUM_CHANNELS; i++)
721 pm_runtime_put_noidle(ina->pm_dev);
87625b24
NC
722
723 mutex_destroy(&ina->lock);
724
725 return 0;
726}
727
ead21c77 728static int __maybe_unused ina3221_suspend(struct device *dev)
59d608e1
NC
729{
730 struct ina3221_data *ina = dev_get_drvdata(dev);
731 int ret;
732
733 /* Save config register value and enable cache-only */
734 ret = regmap_read(ina->regmap, INA3221_CONFIG, &ina->reg_config);
735 if (ret)
736 return ret;
737
738 /* Set to power-down mode for power saving */
739 ret = regmap_update_bits(ina->regmap, INA3221_CONFIG,
740 INA3221_CONFIG_MODE_MASK,
741 INA3221_CONFIG_MODE_POWERDOWN);
742 if (ret)
743 return ret;
744
745 regcache_cache_only(ina->regmap, true);
746 regcache_mark_dirty(ina->regmap);
747
748 return 0;
749}
750
ead21c77 751static int __maybe_unused ina3221_resume(struct device *dev)
59d608e1
NC
752{
753 struct ina3221_data *ina = dev_get_drvdata(dev);
754 int ret;
755
756 regcache_cache_only(ina->regmap, false);
757
758 /* Software reset the chip */
759 ret = regmap_field_write(ina->fields[F_RST], true);
760 if (ret) {
761 dev_err(dev, "Unable to reset device\n");
762 return ret;
763 }
764
765 /* Restore cached register values to hardware */
766 ret = regcache_sync(ina->regmap);
767 if (ret)
768 return ret;
769
770 /* Restore config register value to hardware */
771 ret = regmap_write(ina->regmap, INA3221_CONFIG, ina->reg_config);
772 if (ret)
773 return ret;
774
775 return 0;
776}
59d608e1
NC
777
778static const struct dev_pm_ops ina3221_pm = {
323aeb0e
NC
779 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
780 pm_runtime_force_resume)
781 SET_RUNTIME_PM_OPS(ina3221_suspend, ina3221_resume, NULL)
59d608e1
NC
782};
783
7cb6dcff
AD
784static const struct of_device_id ina3221_of_match_table[] = {
785 { .compatible = "ti,ina3221", },
786 { /* sentinel */ }
787};
788MODULE_DEVICE_TABLE(of, ina3221_of_match_table);
789
790static const struct i2c_device_id ina3221_ids[] = {
791 { "ina3221", 0 },
792 { /* sentinel */ }
793};
794MODULE_DEVICE_TABLE(i2c, ina3221_ids);
795
796static struct i2c_driver ina3221_i2c_driver = {
797 .probe = ina3221_probe,
87625b24 798 .remove = ina3221_remove,
7cb6dcff
AD
799 .driver = {
800 .name = INA3221_DRIVER_NAME,
801 .of_match_table = ina3221_of_match_table,
59d608e1 802 .pm = &ina3221_pm,
7cb6dcff
AD
803 },
804 .id_table = ina3221_ids,
805};
806module_i2c_driver(ina3221_i2c_driver);
807
808MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
809MODULE_DESCRIPTION("Texas Instruments INA3221 HWMon Driver");
810MODULE_LICENSE("GPL v2");