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Commit | Line | Data |
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1da177e4 | 1 | /* |
5f2dc798 JD |
2 | * it87.c - Part of lm_sensors, Linux kernel modules for hardware |
3 | * monitoring. | |
4 | * | |
5 | * The IT8705F is an LPC-based Super I/O part that contains UARTs, a | |
6 | * parallel port, an IR port, a MIDI port, a floppy controller, etc., in | |
7 | * addition to an Environment Controller (Enhanced Hardware Monitor and | |
8 | * Fan Controller) | |
9 | * | |
10 | * This driver supports only the Environment Controller in the IT8705F and | |
11 | * similar parts. The other devices are supported by different drivers. | |
12 | * | |
c145d5c6 | 13 | * Supports: IT8603E Super I/O chip w/LPC interface |
3ba9d977 | 14 | * IT8620E Super I/O chip w/LPC interface |
8af1abae | 15 | * IT8622E Super I/O chip w/LPC interface |
574e9bd8 | 16 | * IT8623E Super I/O chip w/LPC interface |
71a9c232 | 17 | * IT8628E Super I/O chip w/LPC interface |
c145d5c6 | 18 | * IT8705F Super I/O chip w/LPC interface |
5f2dc798 JD |
19 | * IT8712F Super I/O chip w/LPC interface |
20 | * IT8716F Super I/O chip w/LPC interface | |
21 | * IT8718F Super I/O chip w/LPC interface | |
22 | * IT8720F Super I/O chip w/LPC interface | |
44c1bcd4 | 23 | * IT8721F Super I/O chip w/LPC interface |
5f2dc798 | 24 | * IT8726F Super I/O chip w/LPC interface |
16b5dda2 | 25 | * IT8728F Super I/O chip w/LPC interface |
ead80803 | 26 | * IT8732F Super I/O chip w/LPC interface |
44c1bcd4 | 27 | * IT8758E Super I/O chip w/LPC interface |
b0636707 GR |
28 | * IT8771E Super I/O chip w/LPC interface |
29 | * IT8772E Super I/O chip w/LPC interface | |
7bc32d29 | 30 | * IT8781F Super I/O chip w/LPC interface |
0531d98b GR |
31 | * IT8782F Super I/O chip w/LPC interface |
32 | * IT8783E/F Super I/O chip w/LPC interface | |
a0c1424a | 33 | * IT8786E Super I/O chip w/LPC interface |
4ee07157 | 34 | * IT8790E Super I/O chip w/LPC interface |
e531ffc0 | 35 | * IT8792E Super I/O chip w/LPC interface |
5f2dc798 JD |
36 | * Sis950 A clone of the IT8705F |
37 | * | |
38 | * Copyright (C) 2001 Chris Gauthron | |
7c81c60f | 39 | * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> |
5f2dc798 JD |
40 | * |
41 | * This program is free software; you can redistribute it and/or modify | |
42 | * it under the terms of the GNU General Public License as published by | |
43 | * the Free Software Foundation; either version 2 of the License, or | |
44 | * (at your option) any later version. | |
45 | * | |
46 | * This program is distributed in the hope that it will be useful, | |
47 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
48 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
49 | * GNU General Public License for more details. | |
5f2dc798 | 50 | */ |
1da177e4 | 51 | |
a8ca1037 JP |
52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
53 | ||
48b2ae7f | 54 | #include <linux/bitops.h> |
1da177e4 LT |
55 | #include <linux/module.h> |
56 | #include <linux/init.h> | |
57 | #include <linux/slab.h> | |
58 | #include <linux/jiffies.h> | |
b74f3fdd | 59 | #include <linux/platform_device.h> |
943b0830 | 60 | #include <linux/hwmon.h> |
303760b4 JD |
61 | #include <linux/hwmon-sysfs.h> |
62 | #include <linux/hwmon-vid.h> | |
943b0830 | 63 | #include <linux/err.h> |
9a61bf63 | 64 | #include <linux/mutex.h> |
87808be4 | 65 | #include <linux/sysfs.h> |
98dd22c3 JD |
66 | #include <linux/string.h> |
67 | #include <linux/dmi.h> | |
b9acb64a | 68 | #include <linux/acpi.h> |
6055fae8 | 69 | #include <linux/io.h> |
1da177e4 | 70 | |
b74f3fdd | 71 | #define DRVNAME "it87" |
1da177e4 | 72 | |
ead80803 | 73 | enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, |
e531ffc0 GR |
74 | it8771, it8772, it8781, it8782, it8783, it8786, it8790, |
75 | it8792, it8603, it8620, it8622, it8628 }; | |
1da177e4 | 76 | |
67b671bc JD |
77 | static unsigned short force_id; |
78 | module_param(force_id, ushort, 0); | |
79 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
80 | ||
e84bd953 | 81 | static struct platform_device *it87_pdev[2]; |
b74f3fdd | 82 | |
3c2e3512 | 83 | #define REG_2E 0x2e /* The register to read/write */ |
e84bd953 | 84 | #define REG_4E 0x4e /* Secondary register to read/write */ |
3c2e3512 | 85 | |
1da177e4 | 86 | #define DEV 0x07 /* Register: Logical device select */ |
1da177e4 | 87 | #define PME 0x04 /* The device with the fan registers in it */ |
b4da93e4 JMS |
88 | |
89 | /* The device with the IT8718F/IT8720F VID value in it */ | |
90 | #define GPIO 0x07 | |
91 | ||
1da177e4 LT |
92 | #define DEVID 0x20 /* Register: Device ID */ |
93 | #define DEVREV 0x22 /* Register: Device Revision */ | |
94 | ||
3c2e3512 | 95 | static inline int superio_inb(int ioreg, int reg) |
1da177e4 | 96 | { |
3c2e3512 GR |
97 | outb(reg, ioreg); |
98 | return inb(ioreg + 1); | |
1da177e4 LT |
99 | } |
100 | ||
3c2e3512 | 101 | static inline void superio_outb(int ioreg, int reg, int val) |
436cad2a | 102 | { |
3c2e3512 GR |
103 | outb(reg, ioreg); |
104 | outb(val, ioreg + 1); | |
436cad2a JD |
105 | } |
106 | ||
3c2e3512 | 107 | static int superio_inw(int ioreg, int reg) |
1da177e4 LT |
108 | { |
109 | int val; | |
c962024e | 110 | |
3c2e3512 GR |
111 | outb(reg++, ioreg); |
112 | val = inb(ioreg + 1) << 8; | |
113 | outb(reg, ioreg); | |
114 | val |= inb(ioreg + 1); | |
1da177e4 LT |
115 | return val; |
116 | } | |
117 | ||
3c2e3512 | 118 | static inline void superio_select(int ioreg, int ldn) |
1da177e4 | 119 | { |
3c2e3512 GR |
120 | outb(DEV, ioreg); |
121 | outb(ldn, ioreg + 1); | |
1da177e4 LT |
122 | } |
123 | ||
3c2e3512 | 124 | static inline int superio_enter(int ioreg) |
1da177e4 | 125 | { |
5b0380c9 | 126 | /* |
3c2e3512 | 127 | * Try to reserve ioreg and ioreg + 1 for exclusive access. |
5b0380c9 | 128 | */ |
3c2e3512 | 129 | if (!request_muxed_region(ioreg, 2, DRVNAME)) |
5b0380c9 NG |
130 | return -EBUSY; |
131 | ||
3c2e3512 GR |
132 | outb(0x87, ioreg); |
133 | outb(0x01, ioreg); | |
134 | outb(0x55, ioreg); | |
e84bd953 | 135 | outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); |
5b0380c9 | 136 | return 0; |
1da177e4 LT |
137 | } |
138 | ||
3c2e3512 | 139 | static inline void superio_exit(int ioreg) |
1da177e4 | 140 | { |
3c2e3512 GR |
141 | outb(0x02, ioreg); |
142 | outb(0x02, ioreg + 1); | |
143 | release_region(ioreg, 2); | |
1da177e4 LT |
144 | } |
145 | ||
87673dd7 | 146 | /* Logical device 4 registers */ |
1da177e4 LT |
147 | #define IT8712F_DEVID 0x8712 |
148 | #define IT8705F_DEVID 0x8705 | |
17d648bf | 149 | #define IT8716F_DEVID 0x8716 |
87673dd7 | 150 | #define IT8718F_DEVID 0x8718 |
b4da93e4 | 151 | #define IT8720F_DEVID 0x8720 |
44c1bcd4 | 152 | #define IT8721F_DEVID 0x8721 |
08a8f6e9 | 153 | #define IT8726F_DEVID 0x8726 |
16b5dda2 | 154 | #define IT8728F_DEVID 0x8728 |
ead80803 | 155 | #define IT8732F_DEVID 0x8732 |
e531ffc0 | 156 | #define IT8792E_DEVID 0x8733 |
b0636707 GR |
157 | #define IT8771E_DEVID 0x8771 |
158 | #define IT8772E_DEVID 0x8772 | |
7bc32d29 | 159 | #define IT8781F_DEVID 0x8781 |
0531d98b GR |
160 | #define IT8782F_DEVID 0x8782 |
161 | #define IT8783E_DEVID 0x8783 | |
a0c1424a | 162 | #define IT8786E_DEVID 0x8786 |
4ee07157 | 163 | #define IT8790E_DEVID 0x8790 |
7183ae8c | 164 | #define IT8603E_DEVID 0x8603 |
3ba9d977 | 165 | #define IT8620E_DEVID 0x8620 |
8af1abae | 166 | #define IT8622E_DEVID 0x8622 |
574e9bd8 | 167 | #define IT8623E_DEVID 0x8623 |
71a9c232 | 168 | #define IT8628E_DEVID 0x8628 |
1da177e4 LT |
169 | #define IT87_ACT_REG 0x30 |
170 | #define IT87_BASE_REG 0x60 | |
171 | ||
87673dd7 | 172 | /* Logical device 7 registers (IT8712F and later) */ |
0531d98b | 173 | #define IT87_SIO_GPIO1_REG 0x25 |
3ba9d977 | 174 | #define IT87_SIO_GPIO2_REG 0x26 |
895ff267 | 175 | #define IT87_SIO_GPIO3_REG 0x27 |
36c4d98a | 176 | #define IT87_SIO_GPIO4_REG 0x28 |
591ec650 | 177 | #define IT87_SIO_GPIO5_REG 0x29 |
0531d98b | 178 | #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ |
87673dd7 | 179 | #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ |
0531d98b | 180 | #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ |
87673dd7 | 181 | #define IT87_SIO_VID_REG 0xfc /* VID value */ |
d9b327c3 | 182 | #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ |
87673dd7 | 183 | |
1da177e4 | 184 | /* Update battery voltage after every reading if true */ |
90ab5ee9 | 185 | static bool update_vbat; |
1da177e4 LT |
186 | |
187 | /* Not all BIOSes properly configure the PWM registers */ | |
90ab5ee9 | 188 | static bool fix_pwm_polarity; |
1da177e4 | 189 | |
1da177e4 LT |
190 | /* Many IT87 constants specified below */ |
191 | ||
192 | /* Length of ISA address segment */ | |
193 | #define IT87_EXTENT 8 | |
194 | ||
87b4b663 BH |
195 | /* Length of ISA address segment for Environmental Controller */ |
196 | #define IT87_EC_EXTENT 2 | |
197 | ||
198 | /* Offset of EC registers from ISA base address */ | |
199 | #define IT87_EC_OFFSET 5 | |
200 | ||
201 | /* Where are the ISA address/data registers relative to the EC base address */ | |
202 | #define IT87_ADDR_REG_OFFSET 0 | |
203 | #define IT87_DATA_REG_OFFSET 1 | |
1da177e4 LT |
204 | |
205 | /*----- The IT87 registers -----*/ | |
206 | ||
207 | #define IT87_REG_CONFIG 0x00 | |
208 | ||
209 | #define IT87_REG_ALARM1 0x01 | |
210 | #define IT87_REG_ALARM2 0x02 | |
211 | #define IT87_REG_ALARM3 0x03 | |
212 | ||
4a0d71cf GR |
213 | /* |
214 | * The IT8718F and IT8720F have the VID value in a different register, in | |
215 | * Super-I/O configuration space. | |
216 | */ | |
1da177e4 | 217 | #define IT87_REG_VID 0x0a |
4a0d71cf GR |
218 | /* |
219 | * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b | |
220 | * for fan divisors. Later IT8712F revisions must use 16-bit tachometer | |
221 | * mode. | |
222 | */ | |
1da177e4 | 223 | #define IT87_REG_FAN_DIV 0x0b |
17d648bf | 224 | #define IT87_REG_FAN_16BIT 0x0c |
1da177e4 | 225 | |
f838aa26 GR |
226 | /* |
227 | * Monitors: | |
228 | * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) | |
229 | * - up to 6 temp (1 to 6) | |
230 | * - up to 6 fan (1 to 6) | |
231 | */ | |
1da177e4 | 232 | |
fa3f70d6 GR |
233 | static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; |
234 | static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; | |
235 | static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; | |
236 | static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; | |
237 | static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; | |
161d898a | 238 | |
1da177e4 LT |
239 | #define IT87_REG_FAN_MAIN_CTRL 0x13 |
240 | #define IT87_REG_FAN_CTL 0x14 | |
36c4d98a GR |
241 | static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; |
242 | static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; | |
1da177e4 | 243 | |
559313c4 | 244 | static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, |
f838aa26 | 245 | 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; |
1da177e4 | 246 | |
559313c4 | 247 | #define IT87_REG_TEMP(nr) (0x29 + (nr)) |
73055405 | 248 | |
1da177e4 LT |
249 | #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) |
250 | #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) | |
251 | #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) | |
252 | #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) | |
253 | ||
1da177e4 LT |
254 | #define IT87_REG_VIN_ENABLE 0x50 |
255 | #define IT87_REG_TEMP_ENABLE 0x51 | |
4573acbc | 256 | #define IT87_REG_TEMP_EXTRA 0x55 |
d9b327c3 | 257 | #define IT87_REG_BEEP_ENABLE 0x5c |
1da177e4 LT |
258 | |
259 | #define IT87_REG_CHIPID 0x58 | |
260 | ||
2cbb9c37 GR |
261 | static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; |
262 | ||
263 | #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) | |
264 | #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) | |
4f3f51bc | 265 | |
cc18da79 GR |
266 | #define IT87_REG_TEMP456_ENABLE 0x77 |
267 | ||
2310048d GR |
268 | #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) |
269 | #define NUM_VIN_LIMIT 8 | |
270 | #define NUM_TEMP 6 | |
271 | #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) | |
272 | #define NUM_TEMP_LIMIT 3 | |
273 | #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) | |
274 | #define NUM_FAN_DIV 3 | |
275 | #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) | |
276 | #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) | |
277 | ||
483db43e GR |
278 | struct it87_devices { |
279 | const char *name; | |
faf392fb | 280 | const char * const suffix; |
cc18da79 | 281 | u32 features; |
19529784 GR |
282 | u8 peci_mask; |
283 | u8 old_peci_mask; | |
483db43e GR |
284 | }; |
285 | ||
48b2ae7f GR |
286 | #define FEAT_12MV_ADC BIT(0) |
287 | #define FEAT_NEWER_AUTOPWM BIT(1) | |
288 | #define FEAT_OLD_AUTOPWM BIT(2) | |
289 | #define FEAT_16BIT_FANS BIT(3) | |
290 | #define FEAT_TEMP_OFFSET BIT(4) | |
291 | #define FEAT_TEMP_PECI BIT(5) | |
292 | #define FEAT_TEMP_OLD_PECI BIT(6) | |
293 | #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ | |
294 | #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ | |
295 | #define FEAT_VID BIT(9) /* Set if chip supports VID */ | |
296 | #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ | |
297 | #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ | |
298 | #define FEAT_10_9MV_ADC BIT(12) | |
299 | #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ | |
638c1c07 GR |
300 | #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ |
301 | #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ | |
302 | #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ | |
303 | #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ | |
304 | #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ | |
483db43e GR |
305 | |
306 | static const struct it87_devices it87_devices[] = { | |
307 | [it87] = { | |
308 | .name = "it87", | |
faf392fb | 309 | .suffix = "F", |
483db43e GR |
310 | .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */ |
311 | }, | |
312 | [it8712] = { | |
313 | .name = "it8712", | |
faf392fb | 314 | .suffix = "F", |
32dd7c40 GR |
315 | .features = FEAT_OLD_AUTOPWM | FEAT_VID, |
316 | /* may need to overwrite */ | |
483db43e GR |
317 | }, |
318 | [it8716] = { | |
319 | .name = "it8716", | |
faf392fb | 320 | .suffix = "F", |
32dd7c40 | 321 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf | 322 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2, |
483db43e GR |
323 | }, |
324 | [it8718] = { | |
325 | .name = "it8718", | |
faf392fb | 326 | .suffix = "F", |
32dd7c40 | 327 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
328 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
329 | | FEAT_PWM_FREQ2, | |
19529784 | 330 | .old_peci_mask = 0x4, |
483db43e GR |
331 | }, |
332 | [it8720] = { | |
333 | .name = "it8720", | |
faf392fb | 334 | .suffix = "F", |
32dd7c40 | 335 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
336 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
337 | | FEAT_PWM_FREQ2, | |
19529784 | 338 | .old_peci_mask = 0x4, |
483db43e GR |
339 | }, |
340 | [it8721] = { | |
341 | .name = "it8721", | |
faf392fb | 342 | .suffix = "F", |
483db43e | 343 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
9faf28ca | 344 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI |
60878bcf GR |
345 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL |
346 | | FEAT_PWM_FREQ2, | |
5d8d2f2b | 347 | .peci_mask = 0x05, |
19529784 | 348 | .old_peci_mask = 0x02, /* Actually reports PCH */ |
483db43e GR |
349 | }, |
350 | [it8728] = { | |
351 | .name = "it8728", | |
faf392fb | 352 | .suffix = "F", |
483db43e | 353 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
7f5726c3 | 354 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS |
60878bcf | 355 | | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2, |
5d8d2f2b | 356 | .peci_mask = 0x07, |
483db43e | 357 | }, |
ead80803 JM |
358 | [it8732] = { |
359 | .name = "it8732", | |
360 | .suffix = "F", | |
361 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS | |
362 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
363 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, | |
364 | .peci_mask = 0x07, | |
365 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
366 | }, | |
b0636707 GR |
367 | [it8771] = { |
368 | .name = "it8771", | |
faf392fb | 369 | .suffix = "E", |
b0636707 | 370 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
371 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
372 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
373 | /* PECI: guesswork */ |
374 | /* 12mV ADC (OHM) */ | |
375 | /* 16 bit fans (OHM) */ | |
376 | /* three fans, always 16 bit (guesswork) */ | |
b0636707 GR |
377 | .peci_mask = 0x07, |
378 | }, | |
379 | [it8772] = { | |
380 | .name = "it8772", | |
faf392fb | 381 | .suffix = "E", |
b0636707 | 382 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
383 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
384 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
385 | /* PECI (coreboot) */ |
386 | /* 12mV ADC (HWSensors4, OHM) */ | |
387 | /* 16 bit fans (HWSensors4, OHM) */ | |
388 | /* three fans, always 16 bit (datasheet) */ | |
b0636707 GR |
389 | .peci_mask = 0x07, |
390 | }, | |
7bc32d29 GR |
391 | [it8781] = { |
392 | .name = "it8781", | |
faf392fb | 393 | .suffix = "F", |
7bc32d29 | 394 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 395 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
7bc32d29 GR |
396 | .old_peci_mask = 0x4, |
397 | }, | |
483db43e GR |
398 | [it8782] = { |
399 | .name = "it8782", | |
faf392fb | 400 | .suffix = "F", |
19529784 | 401 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 402 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 403 | .old_peci_mask = 0x4, |
483db43e GR |
404 | }, |
405 | [it8783] = { | |
406 | .name = "it8783", | |
faf392fb | 407 | .suffix = "E/F", |
19529784 | 408 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 409 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 410 | .old_peci_mask = 0x4, |
483db43e | 411 | }, |
a0c1424a TL |
412 | [it8786] = { |
413 | .name = "it8786", | |
faf392fb | 414 | .suffix = "E", |
a0c1424a | 415 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
416 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
417 | | FEAT_PWM_FREQ2, | |
a0c1424a TL |
418 | .peci_mask = 0x07, |
419 | }, | |
4ee07157 GR |
420 | [it8790] = { |
421 | .name = "it8790", | |
422 | .suffix = "E", | |
423 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
60878bcf GR |
424 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
425 | | FEAT_PWM_FREQ2, | |
4ee07157 GR |
426 | .peci_mask = 0x07, |
427 | }, | |
e531ffc0 GR |
428 | [it8792] = { |
429 | .name = "it8792", | |
430 | .suffix = "E", | |
431 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS | |
432 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
433 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, | |
434 | .peci_mask = 0x07, | |
435 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
436 | }, | |
c145d5c6 RM |
437 | [it8603] = { |
438 | .name = "it8603", | |
faf392fb | 439 | .suffix = "E", |
c145d5c6 | 440 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
73055405 | 441 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
60878bcf | 442 | | FEAT_AVCC3 | FEAT_PWM_FREQ2, |
c145d5c6 RM |
443 | .peci_mask = 0x07, |
444 | }, | |
3ba9d977 GR |
445 | [it8620] = { |
446 | .name = "it8620", | |
447 | .suffix = "E", | |
448 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
fa3f70d6 | 449 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS |
cc18da79 | 450 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 |
a9eebd4f | 451 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
3ba9d977 GR |
452 | .peci_mask = 0x07, |
453 | }, | |
8af1abae GR |
454 | [it8622] = { |
455 | .name = "it8622", | |
456 | .suffix = "E", | |
457 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
458 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS | |
638c1c07 GR |
459 | | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 |
460 | | FEAT_AVCC3 | FEAT_VIN3_5V, | |
8af1abae GR |
461 | .peci_mask = 0x07, |
462 | }, | |
71a9c232 GR |
463 | [it8628] = { |
464 | .name = "it8628", | |
465 | .suffix = "E", | |
466 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
467 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS | |
468 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | |
a9eebd4f | 469 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
71a9c232 GR |
470 | .peci_mask = 0x07, |
471 | }, | |
483db43e GR |
472 | }; |
473 | ||
474 | #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) | |
475 | #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) | |
ead80803 | 476 | #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) |
483db43e GR |
477 | #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) |
478 | #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) | |
479 | #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) | |
5d8d2f2b | 480 | #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ |
48b2ae7f | 481 | ((data)->peci_mask & BIT(nr))) |
19529784 GR |
482 | #define has_temp_old_peci(data, nr) \ |
483 | (((data)->features & FEAT_TEMP_OLD_PECI) && \ | |
48b2ae7f | 484 | ((data)->old_peci_mask & BIT(nr))) |
9faf28ca | 485 | #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) |
fa3f70d6 GR |
486 | #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ |
487 | FEAT_SIX_FANS)) | |
32dd7c40 | 488 | #define has_vid(data) ((data)->features & FEAT_VID) |
7f5726c3 | 489 | #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) |
fa3f70d6 | 490 | #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) |
73055405 | 491 | #define has_avcc3(data) ((data)->features & FEAT_AVCC3) |
638c1c07 GR |
492 | #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \ |
493 | | FEAT_SIX_PWM)) | |
36c4d98a | 494 | #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) |
60878bcf | 495 | #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) |
cc18da79 | 496 | #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) |
a9eebd4f | 497 | #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) |
1da177e4 | 498 | |
b74f3fdd | 499 | struct it87_sio_data { |
500 | enum chips type; | |
501 | /* Values read from Super-I/O config space */ | |
0475169c | 502 | u8 revision; |
b74f3fdd | 503 | u8 vid_value; |
d9b327c3 | 504 | u8 beep_pin; |
738e5e05 | 505 | u8 internal; /* Internal sensors can be labeled */ |
591ec650 | 506 | /* Features skipped based on config or DMI */ |
9172b5d1 | 507 | u16 skip_in; |
895ff267 | 508 | u8 skip_vid; |
591ec650 | 509 | u8 skip_fan; |
98dd22c3 | 510 | u8 skip_pwm; |
4573acbc | 511 | u8 skip_temp; |
b74f3fdd | 512 | }; |
513 | ||
4a0d71cf GR |
514 | /* |
515 | * For each registered chip, we need to keep some data in memory. | |
516 | * The structure is dynamically allocated. | |
517 | */ | |
1da177e4 | 518 | struct it87_data { |
8638d0af | 519 | const struct attribute_group *groups[7]; |
1da177e4 | 520 | enum chips type; |
aa8b187e | 521 | u32 features; |
19529784 GR |
522 | u8 peci_mask; |
523 | u8 old_peci_mask; | |
1da177e4 | 524 | |
b74f3fdd | 525 | unsigned short addr; |
526 | const char *name; | |
9a61bf63 | 527 | struct mutex update_lock; |
1da177e4 LT |
528 | char valid; /* !=0 if following fields are valid */ |
529 | unsigned long last_updated; /* In jiffies */ | |
530 | ||
44c1bcd4 | 531 | u16 in_scaled; /* Internal voltage sensors are scaled */ |
d3766848 | 532 | u16 in_internal; /* Bitfield, internal sensors (for labels) */ |
52929715 | 533 | u16 has_in; /* Bitfield, voltage sensors enabled */ |
2310048d | 534 | u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ |
9060f8bd | 535 | u8 has_fan; /* Bitfield, fans enabled */ |
2310048d | 536 | u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ |
4573acbc | 537 | u8 has_temp; /* Bitfield, temp sensors enabled */ |
2310048d | 538 | s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ |
19529784 GR |
539 | u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ |
540 | u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ | |
2310048d | 541 | u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ |
d3766848 | 542 | bool has_vid; /* True if VID supported */ |
1da177e4 | 543 | u8 vid; /* Register encoding, combined */ |
a7be58a1 | 544 | u8 vrm; |
1da177e4 | 545 | u32 alarms; /* Register encoding, combined */ |
52929715 | 546 | bool has_beep; /* true if beep supported */ |
d9b327c3 | 547 | u8 beeps; /* Register encoding */ |
1da177e4 | 548 | u8 fan_main_ctrl; /* Register value */ |
f8d0c19a | 549 | u8 fan_ctl; /* Register value */ |
b99883dc | 550 | |
4a0d71cf GR |
551 | /* |
552 | * The following 3 arrays correspond to the same registers up to | |
6229cdb2 JD |
553 | * the IT8720F. The meaning of bits 6-0 depends on the value of bit |
554 | * 7, and we want to preserve settings on mode changes, so we have | |
555 | * to track all values separately. | |
556 | * Starting with the IT8721F, the manual PWM duty cycles are stored | |
557 | * in separate registers (8-bit values), so the separate tracking | |
558 | * is no longer needed, but it is still done to keep the driver | |
4a0d71cf GR |
559 | * simple. |
560 | */ | |
5c391261 | 561 | u8 has_pwm; /* Bitfield, pwm control enabled */ |
2310048d GR |
562 | u8 pwm_ctrl[NUM_PWM]; /* Register value */ |
563 | u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ | |
564 | u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ | |
4f3f51bc JD |
565 | |
566 | /* Automatic fan speed control registers */ | |
2310048d GR |
567 | u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ |
568 | s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ | |
1da177e4 | 569 | }; |
0df6454d | 570 | |
0531d98b | 571 | static int adc_lsb(const struct it87_data *data, int nr) |
44c1bcd4 | 572 | { |
ead80803 JM |
573 | int lsb; |
574 | ||
575 | if (has_12mv_adc(data)) | |
576 | lsb = 120; | |
577 | else if (has_10_9mv_adc(data)) | |
578 | lsb = 109; | |
579 | else | |
580 | lsb = 160; | |
48b2ae7f | 581 | if (data->in_scaled & BIT(nr)) |
0531d98b GR |
582 | lsb <<= 1; |
583 | return lsb; | |
584 | } | |
44c1bcd4 | 585 | |
0531d98b GR |
586 | static u8 in_to_reg(const struct it87_data *data, int nr, long val) |
587 | { | |
ead80803 | 588 | val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); |
2a844c14 | 589 | return clamp_val(val, 0, 255); |
44c1bcd4 JD |
590 | } |
591 | ||
592 | static int in_from_reg(const struct it87_data *data, int nr, int val) | |
593 | { | |
ead80803 | 594 | return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); |
44c1bcd4 | 595 | } |
0df6454d JD |
596 | |
597 | static inline u8 FAN_TO_REG(long rpm, int div) | |
598 | { | |
599 | if (rpm == 0) | |
600 | return 255; | |
2a844c14 GR |
601 | rpm = clamp_val(rpm, 1, 1000000); |
602 | return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); | |
0df6454d JD |
603 | } |
604 | ||
605 | static inline u16 FAN16_TO_REG(long rpm) | |
606 | { | |
607 | if (rpm == 0) | |
608 | return 0xffff; | |
2a844c14 | 609 | return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); |
0df6454d JD |
610 | } |
611 | ||
612 | #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ | |
613 | 1350000 / ((val) * (div))) | |
614 | /* The divider is fixed to 2 in 16-bit mode */ | |
615 | #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ | |
616 | 1350000 / ((val) * 2)) | |
617 | ||
2a844c14 GR |
618 | #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ |
619 | ((val) + 500) / 1000), -128, 127)) | |
0df6454d JD |
620 | #define TEMP_FROM_REG(val) ((val) * 1000) |
621 | ||
44c1bcd4 JD |
622 | static u8 pwm_to_reg(const struct it87_data *data, long val) |
623 | { | |
16b5dda2 | 624 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
625 | return val; |
626 | else | |
627 | return val >> 1; | |
628 | } | |
629 | ||
630 | static int pwm_from_reg(const struct it87_data *data, u8 reg) | |
631 | { | |
16b5dda2 | 632 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
633 | return reg; |
634 | else | |
635 | return (reg & 0x7f) << 1; | |
636 | } | |
637 | ||
0df6454d JD |
638 | static int DIV_TO_REG(int val) |
639 | { | |
640 | int answer = 0; | |
c962024e | 641 | |
0df6454d JD |
642 | while (answer < 7 && (val >>= 1)) |
643 | answer++; | |
644 | return answer; | |
645 | } | |
48b2ae7f GR |
646 | |
647 | #define DIV_FROM_REG(val) BIT(val) | |
0df6454d | 648 | |
f56c9c0a GR |
649 | /* |
650 | * PWM base frequencies. The frequency has to be divided by either 128 or 256, | |
651 | * depending on the chip type, to calculate the actual PWM frequency. | |
652 | * | |
653 | * Some of the chip datasheets suggest a base frequency of 51 kHz instead | |
654 | * of 750 kHz for the slowest base frequency, resulting in a PWM frequency | |
655 | * of 200 Hz. Sometimes both PWM frequency select registers are affected, | |
656 | * sometimes just one. It is unknown if this is a datasheet error or real, | |
657 | * so this is ignored for now. | |
658 | */ | |
0df6454d | 659 | static const unsigned int pwm_freq[8] = { |
f56c9c0a GR |
660 | 48000000, |
661 | 24000000, | |
662 | 12000000, | |
663 | 8000000, | |
664 | 6000000, | |
665 | 3000000, | |
666 | 1500000, | |
667 | 750000, | |
0df6454d | 668 | }; |
1da177e4 | 669 | |
c1e7a4ca GR |
670 | /* |
671 | * Must be called with data->update_lock held, except during initialization. | |
672 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
673 | * would slow down the IT87 access and should not be necessary. | |
674 | */ | |
675 | static int it87_read_value(struct it87_data *data, u8 reg) | |
676 | { | |
677 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
678 | return inb_p(data->addr + IT87_DATA_REG_OFFSET); | |
679 | } | |
680 | ||
681 | /* | |
682 | * Must be called with data->update_lock held, except during initialization. | |
683 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
684 | * would slow down the IT87 access and should not be necessary. | |
685 | */ | |
686 | static void it87_write_value(struct it87_data *data, u8 reg, u8 value) | |
687 | { | |
688 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
689 | outb_p(value, data->addr + IT87_DATA_REG_OFFSET); | |
690 | } | |
691 | ||
692 | static void it87_update_pwm_ctrl(struct it87_data *data, int nr) | |
693 | { | |
694 | data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); | |
695 | if (has_newer_autopwm(data)) { | |
0624d861 | 696 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; |
c1e7a4ca GR |
697 | data->pwm_duty[nr] = it87_read_value(data, |
698 | IT87_REG_PWM_DUTY[nr]); | |
699 | } else { | |
700 | if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ | |
701 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; | |
702 | else /* Manual mode */ | |
703 | data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; | |
704 | } | |
1da177e4 | 705 | |
c1e7a4ca GR |
706 | if (has_old_autopwm(data)) { |
707 | int i; | |
1da177e4 | 708 | |
c1e7a4ca GR |
709 | for (i = 0; i < 5 ; i++) |
710 | data->auto_temp[nr][i] = it87_read_value(data, | |
711 | IT87_REG_AUTO_TEMP(nr, i)); | |
712 | for (i = 0; i < 3 ; i++) | |
713 | data->auto_pwm[nr][i] = it87_read_value(data, | |
714 | IT87_REG_AUTO_PWM(nr, i)); | |
2cbb9c37 GR |
715 | } else if (has_newer_autopwm(data)) { |
716 | int i; | |
717 | ||
718 | /* | |
719 | * 0: temperature hysteresis (base + 5) | |
720 | * 1: fan off temperature (base + 0) | |
721 | * 2: fan start temperature (base + 1) | |
722 | * 3: fan max temperature (base + 2) | |
723 | */ | |
724 | data->auto_temp[nr][0] = | |
725 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); | |
726 | ||
727 | for (i = 0; i < 3 ; i++) | |
728 | data->auto_temp[nr][i + 1] = | |
729 | it87_read_value(data, | |
730 | IT87_REG_AUTO_TEMP(nr, i)); | |
731 | /* | |
732 | * 0: start pwm value (base + 3) | |
733 | * 1: pwm slope (base + 4, 1/8th pwm) | |
734 | */ | |
735 | data->auto_pwm[nr][0] = | |
736 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); | |
737 | data->auto_pwm[nr][1] = | |
738 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); | |
c1e7a4ca GR |
739 | } |
740 | } | |
1da177e4 | 741 | |
c1e7a4ca GR |
742 | static struct it87_data *it87_update_device(struct device *dev) |
743 | { | |
744 | struct it87_data *data = dev_get_drvdata(dev); | |
745 | int i; | |
746 | ||
747 | mutex_lock(&data->update_lock); | |
748 | ||
c962024e GR |
749 | if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || |
750 | !data->valid) { | |
c1e7a4ca GR |
751 | if (update_vbat) { |
752 | /* | |
753 | * Cleared after each update, so reenable. Value | |
754 | * returned by this read will be previous value | |
755 | */ | |
756 | it87_write_value(data, IT87_REG_CONFIG, | |
757 | it87_read_value(data, IT87_REG_CONFIG) | 0x40); | |
758 | } | |
2310048d | 759 | for (i = 0; i < NUM_VIN; i++) { |
48b2ae7f | 760 | if (!(data->has_in & BIT(i))) |
559313c4 GR |
761 | continue; |
762 | ||
c1e7a4ca | 763 | data->in[i][0] = |
559313c4 GR |
764 | it87_read_value(data, IT87_REG_VIN[i]); |
765 | ||
766 | /* VBAT and AVCC don't have limit registers */ | |
2310048d | 767 | if (i >= NUM_VIN_LIMIT) |
559313c4 GR |
768 | continue; |
769 | ||
c1e7a4ca GR |
770 | data->in[i][1] = |
771 | it87_read_value(data, IT87_REG_VIN_MIN(i)); | |
772 | data->in[i][2] = | |
773 | it87_read_value(data, IT87_REG_VIN_MAX(i)); | |
774 | } | |
c1e7a4ca | 775 | |
2310048d | 776 | for (i = 0; i < NUM_FAN; i++) { |
c1e7a4ca | 777 | /* Skip disabled fans */ |
48b2ae7f | 778 | if (!(data->has_fan & BIT(i))) |
c1e7a4ca GR |
779 | continue; |
780 | ||
781 | data->fan[i][1] = | |
782 | it87_read_value(data, IT87_REG_FAN_MIN[i]); | |
783 | data->fan[i][0] = it87_read_value(data, | |
784 | IT87_REG_FAN[i]); | |
785 | /* Add high byte if in 16-bit mode */ | |
786 | if (has_16bit_fans(data)) { | |
787 | data->fan[i][0] |= it87_read_value(data, | |
788 | IT87_REG_FANX[i]) << 8; | |
789 | data->fan[i][1] |= it87_read_value(data, | |
790 | IT87_REG_FANX_MIN[i]) << 8; | |
791 | } | |
792 | } | |
2310048d | 793 | for (i = 0; i < NUM_TEMP; i++) { |
48b2ae7f | 794 | if (!(data->has_temp & BIT(i))) |
c1e7a4ca GR |
795 | continue; |
796 | data->temp[i][0] = | |
797 | it87_read_value(data, IT87_REG_TEMP(i)); | |
cc18da79 | 798 | |
2310048d GR |
799 | if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) |
800 | data->temp[i][3] = | |
801 | it87_read_value(data, | |
802 | IT87_REG_TEMP_OFFSET[i]); | |
803 | ||
804 | if (i >= NUM_TEMP_LIMIT) | |
cc18da79 GR |
805 | continue; |
806 | ||
c1e7a4ca GR |
807 | data->temp[i][1] = |
808 | it87_read_value(data, IT87_REG_TEMP_LOW(i)); | |
809 | data->temp[i][2] = | |
810 | it87_read_value(data, IT87_REG_TEMP_HIGH(i)); | |
c1e7a4ca GR |
811 | } |
812 | ||
813 | /* Newer chips don't have clock dividers */ | |
814 | if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { | |
815 | i = it87_read_value(data, IT87_REG_FAN_DIV); | |
816 | data->fan_div[0] = i & 0x07; | |
817 | data->fan_div[1] = (i >> 3) & 0x07; | |
818 | data->fan_div[2] = (i & 0x40) ? 3 : 1; | |
819 | } | |
820 | ||
821 | data->alarms = | |
822 | it87_read_value(data, IT87_REG_ALARM1) | | |
823 | (it87_read_value(data, IT87_REG_ALARM2) << 8) | | |
824 | (it87_read_value(data, IT87_REG_ALARM3) << 16); | |
825 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
826 | ||
827 | data->fan_main_ctrl = it87_read_value(data, | |
828 | IT87_REG_FAN_MAIN_CTRL); | |
829 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); | |
0624d861 GR |
830 | for (i = 0; i < NUM_PWM; i++) { |
831 | if (!(data->has_pwm & BIT(i))) | |
832 | continue; | |
c1e7a4ca | 833 | it87_update_pwm_ctrl(data, i); |
0624d861 | 834 | } |
c1e7a4ca GR |
835 | |
836 | data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); | |
837 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); | |
838 | /* | |
839 | * The IT8705F does not have VID capability. | |
840 | * The IT8718F and later don't use IT87_REG_VID for the | |
841 | * same purpose. | |
842 | */ | |
843 | if (data->type == it8712 || data->type == it8716) { | |
844 | data->vid = it87_read_value(data, IT87_REG_VID); | |
845 | /* | |
846 | * The older IT8712F revisions had only 5 VID pins, | |
847 | * but we assume it is always safe to read 6 bits. | |
848 | */ | |
849 | data->vid &= 0x3f; | |
850 | } | |
851 | data->last_updated = jiffies; | |
852 | data->valid = 1; | |
853 | } | |
854 | ||
855 | mutex_unlock(&data->update_lock); | |
856 | ||
857 | return data; | |
858 | } | |
fde09509 | 859 | |
20ad93d4 | 860 | static ssize_t show_in(struct device *dev, struct device_attribute *attr, |
929c6a56 | 861 | char *buf) |
1da177e4 | 862 | { |
929c6a56 | 863 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
c962024e | 864 | struct it87_data *data = it87_update_device(dev); |
929c6a56 | 865 | int index = sattr->index; |
c962024e | 866 | int nr = sattr->nr; |
20ad93d4 | 867 | |
929c6a56 | 868 | return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); |
1da177e4 LT |
869 | } |
870 | ||
929c6a56 GR |
871 | static ssize_t set_in(struct device *dev, struct device_attribute *attr, |
872 | const char *buf, size_t count) | |
1da177e4 | 873 | { |
929c6a56 | 874 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
b74f3fdd | 875 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e GR |
876 | int index = sattr->index; |
877 | int nr = sattr->nr; | |
f5f64501 JD |
878 | unsigned long val; |
879 | ||
179c4fdb | 880 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 881 | return -EINVAL; |
1da177e4 | 882 | |
9a61bf63 | 883 | mutex_lock(&data->update_lock); |
929c6a56 GR |
884 | data->in[nr][index] = in_to_reg(data, nr, val); |
885 | it87_write_value(data, | |
886 | index == 1 ? IT87_REG_VIN_MIN(nr) | |
887 | : IT87_REG_VIN_MAX(nr), | |
888 | data->in[nr][index]); | |
9a61bf63 | 889 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
890 | return count; |
891 | } | |
20ad93d4 | 892 | |
929c6a56 GR |
893 | static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); |
894 | static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
895 | 0, 1); | |
896 | static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
897 | 0, 2); | |
f5f64501 | 898 | |
929c6a56 GR |
899 | static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); |
900 | static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
901 | 1, 1); | |
902 | static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
903 | 1, 2); | |
1da177e4 | 904 | |
929c6a56 GR |
905 | static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); |
906 | static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
907 | 2, 1); | |
908 | static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
909 | 2, 2); | |
1da177e4 | 910 | |
929c6a56 GR |
911 | static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); |
912 | static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
913 | 3, 1); | |
914 | static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
915 | 3, 2); | |
916 | ||
917 | static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); | |
918 | static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
919 | 4, 1); | |
920 | static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
921 | 4, 2); | |
922 | ||
923 | static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); | |
924 | static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
925 | 5, 1); | |
926 | static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
927 | 5, 2); | |
928 | ||
929 | static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); | |
930 | static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
931 | 6, 1); | |
932 | static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
933 | 6, 2); | |
934 | ||
935 | static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); | |
936 | static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
937 | 7, 1); | |
938 | static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
939 | 7, 2); | |
940 | ||
941 | static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); | |
c145d5c6 | 942 | static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); |
f838aa26 GR |
943 | static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); |
944 | static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); | |
945 | static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); | |
1da177e4 | 946 | |
cc18da79 | 947 | /* Up to 6 temperatures */ |
20ad93d4 | 948 | static ssize_t show_temp(struct device *dev, struct device_attribute *attr, |
60ca385a | 949 | char *buf) |
1da177e4 | 950 | { |
60ca385a GR |
951 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
952 | int nr = sattr->nr; | |
953 | int index = sattr->index; | |
1da177e4 | 954 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 955 | |
60ca385a | 956 | return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); |
1da177e4 | 957 | } |
20ad93d4 | 958 | |
60ca385a GR |
959 | static ssize_t set_temp(struct device *dev, struct device_attribute *attr, |
960 | const char *buf, size_t count) | |
1da177e4 | 961 | { |
60ca385a GR |
962 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
963 | int nr = sattr->nr; | |
964 | int index = sattr->index; | |
b74f3fdd | 965 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 966 | long val; |
161d898a | 967 | u8 reg, regval; |
f5f64501 | 968 | |
179c4fdb | 969 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 970 | return -EINVAL; |
1da177e4 | 971 | |
9a61bf63 | 972 | mutex_lock(&data->update_lock); |
161d898a GR |
973 | |
974 | switch (index) { | |
975 | default: | |
976 | case 1: | |
977 | reg = IT87_REG_TEMP_LOW(nr); | |
978 | break; | |
979 | case 2: | |
980 | reg = IT87_REG_TEMP_HIGH(nr); | |
981 | break; | |
982 | case 3: | |
983 | regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
984 | if (!(regval & 0x80)) { | |
985 | regval |= 0x80; | |
986 | it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); | |
987 | } | |
988 | data->valid = 0; | |
989 | reg = IT87_REG_TEMP_OFFSET[nr]; | |
990 | break; | |
991 | } | |
992 | ||
60ca385a | 993 | data->temp[nr][index] = TEMP_TO_REG(val); |
161d898a | 994 | it87_write_value(data, reg, data->temp[nr][index]); |
9a61bf63 | 995 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
996 | return count; |
997 | } | |
1da177e4 | 998 | |
60ca385a GR |
999 | static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); |
1000 | static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1001 | 0, 1); | |
1002 | static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1003 | 0, 2); | |
161d898a GR |
1004 | static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, |
1005 | set_temp, 0, 3); | |
60ca385a GR |
1006 | static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); |
1007 | static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1008 | 1, 1); | |
1009 | static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1010 | 1, 2); | |
161d898a GR |
1011 | static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, |
1012 | set_temp, 1, 3); | |
60ca385a GR |
1013 | static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); |
1014 | static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1015 | 2, 1); | |
1016 | static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1017 | 2, 2); | |
161d898a GR |
1018 | static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, |
1019 | set_temp, 2, 3); | |
cc18da79 GR |
1020 | static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); |
1021 | static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); | |
1022 | static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); | |
1da177e4 | 1023 | |
2cece01f GR |
1024 | static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, |
1025 | char *buf) | |
1da177e4 | 1026 | { |
20ad93d4 JD |
1027 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1028 | int nr = sensor_attr->index; | |
1da177e4 | 1029 | struct it87_data *data = it87_update_device(dev); |
4a0d71cf | 1030 | u8 reg = data->sensor; /* In case value is updated while used */ |
19529784 | 1031 | u8 extra = data->extra; |
5f2dc798 | 1032 | |
c962024e GR |
1033 | if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || |
1034 | (has_temp_old_peci(data, nr) && (extra & 0x80))) | |
5d8d2f2b | 1035 | return sprintf(buf, "6\n"); /* Intel PECI */ |
1da177e4 LT |
1036 | if (reg & (1 << nr)) |
1037 | return sprintf(buf, "3\n"); /* thermal diode */ | |
1038 | if (reg & (8 << nr)) | |
4ed10779 | 1039 | return sprintf(buf, "4\n"); /* thermistor */ |
1da177e4 LT |
1040 | return sprintf(buf, "0\n"); /* disabled */ |
1041 | } | |
2cece01f GR |
1042 | |
1043 | static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, | |
1044 | const char *buf, size_t count) | |
1da177e4 | 1045 | { |
20ad93d4 JD |
1046 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1047 | int nr = sensor_attr->index; | |
1048 | ||
b74f3fdd | 1049 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1050 | long val; |
19529784 | 1051 | u8 reg, extra; |
f5f64501 | 1052 | |
179c4fdb | 1053 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 1054 | return -EINVAL; |
1da177e4 | 1055 | |
8acf07c5 JD |
1056 | reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); |
1057 | reg &= ~(1 << nr); | |
1058 | reg &= ~(8 << nr); | |
5d8d2f2b GR |
1059 | if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) |
1060 | reg &= 0x3f; | |
19529784 GR |
1061 | extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); |
1062 | if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) | |
1063 | extra &= 0x7f; | |
4ed10779 | 1064 | if (val == 2) { /* backwards compatibility */ |
1d9bcf6a GR |
1065 | dev_warn(dev, |
1066 | "Sensor type 2 is deprecated, please use 4 instead\n"); | |
4ed10779 JD |
1067 | val = 4; |
1068 | } | |
5d8d2f2b | 1069 | /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ |
1da177e4 | 1070 | if (val == 3) |
8acf07c5 | 1071 | reg |= 1 << nr; |
4ed10779 | 1072 | else if (val == 4) |
8acf07c5 | 1073 | reg |= 8 << nr; |
5d8d2f2b GR |
1074 | else if (has_temp_peci(data, nr) && val == 6) |
1075 | reg |= (nr + 1) << 6; | |
19529784 GR |
1076 | else if (has_temp_old_peci(data, nr) && val == 6) |
1077 | extra |= 0x80; | |
8acf07c5 | 1078 | else if (val != 0) |
1da177e4 | 1079 | return -EINVAL; |
8acf07c5 JD |
1080 | |
1081 | mutex_lock(&data->update_lock); | |
1082 | data->sensor = reg; | |
19529784 | 1083 | data->extra = extra; |
b74f3fdd | 1084 | it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); |
19529784 GR |
1085 | if (has_temp_old_peci(data, nr)) |
1086 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
2b3d1d87 | 1087 | data->valid = 0; /* Force cache refresh */ |
9a61bf63 | 1088 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1089 | return count; |
1090 | } | |
1da177e4 | 1091 | |
2cece01f GR |
1092 | static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, |
1093 | set_temp_type, 0); | |
1094 | static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1095 | set_temp_type, 1); | |
1096 | static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1097 | set_temp_type, 2); | |
1da177e4 | 1098 | |
f1bbe618 | 1099 | /* 6 Fans */ |
b99883dc JD |
1100 | |
1101 | static int pwm_mode(const struct it87_data *data, int nr) | |
1102 | { | |
f1bbe618 GR |
1103 | if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) |
1104 | return 0; /* Full speed */ | |
1105 | if (data->pwm_ctrl[nr] & 0x80) | |
1106 | return 2; /* Automatic mode */ | |
1107 | if ((data->type == it8603 || nr >= 3) && | |
1108 | data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) | |
1109 | return 0; /* Full speed */ | |
1110 | ||
1111 | return 1; /* Manual mode */ | |
b99883dc JD |
1112 | } |
1113 | ||
20ad93d4 | 1114 | static ssize_t show_fan(struct device *dev, struct device_attribute *attr, |
e1169ba0 | 1115 | char *buf) |
1da177e4 | 1116 | { |
e1169ba0 GR |
1117 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1118 | int nr = sattr->nr; | |
1119 | int index = sattr->index; | |
1120 | int speed; | |
1da177e4 | 1121 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 1122 | |
e1169ba0 GR |
1123 | speed = has_16bit_fans(data) ? |
1124 | FAN16_FROM_REG(data->fan[nr][index]) : | |
1125 | FAN_FROM_REG(data->fan[nr][index], | |
1126 | DIV_FROM_REG(data->fan_div[nr])); | |
1127 | return sprintf(buf, "%d\n", speed); | |
1da177e4 | 1128 | } |
e1169ba0 | 1129 | |
20ad93d4 | 1130 | static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1131 | char *buf) |
1da177e4 | 1132 | { |
20ad93d4 | 1133 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1134 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1135 | int nr = sensor_attr->index; |
1136 | ||
48b2ae7f | 1137 | return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 | 1138 | } |
c962024e | 1139 | |
5f2dc798 | 1140 | static ssize_t show_pwm_enable(struct device *dev, |
c962024e | 1141 | struct device_attribute *attr, char *buf) |
1da177e4 | 1142 | { |
20ad93d4 | 1143 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1144 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1145 | int nr = sensor_attr->index; |
1146 | ||
b99883dc | 1147 | return sprintf(buf, "%d\n", pwm_mode(data, nr)); |
1da177e4 | 1148 | } |
c962024e | 1149 | |
20ad93d4 | 1150 | static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1151 | char *buf) |
1da177e4 | 1152 | { |
20ad93d4 | 1153 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1154 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1155 | int nr = sensor_attr->index; |
1156 | ||
44c1bcd4 JD |
1157 | return sprintf(buf, "%d\n", |
1158 | pwm_from_reg(data, data->pwm_duty[nr])); | |
1da177e4 | 1159 | } |
c962024e | 1160 | |
f8d0c19a | 1161 | static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, |
c962024e | 1162 | char *buf) |
f8d0c19a | 1163 | { |
60878bcf | 1164 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
f8d0c19a | 1165 | struct it87_data *data = it87_update_device(dev); |
60878bcf | 1166 | int nr = sensor_attr->index; |
f56c9c0a | 1167 | unsigned int freq; |
60878bcf GR |
1168 | int index; |
1169 | ||
1170 | if (has_pwm_freq2(data) && nr == 1) | |
1171 | index = (data->extra >> 4) & 0x07; | |
1172 | else | |
1173 | index = (data->fan_ctl >> 4) & 0x07; | |
f8d0c19a | 1174 | |
f56c9c0a GR |
1175 | freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); |
1176 | ||
1177 | return sprintf(buf, "%u\n", freq); | |
f8d0c19a | 1178 | } |
e1169ba0 GR |
1179 | |
1180 | static ssize_t set_fan(struct device *dev, struct device_attribute *attr, | |
1181 | const char *buf, size_t count) | |
1da177e4 | 1182 | { |
e1169ba0 GR |
1183 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1184 | int nr = sattr->nr; | |
1185 | int index = sattr->index; | |
20ad93d4 | 1186 | |
b74f3fdd | 1187 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1188 | long val; |
7f999aa7 | 1189 | u8 reg; |
1da177e4 | 1190 | |
179c4fdb | 1191 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 JD |
1192 | return -EINVAL; |
1193 | ||
9a61bf63 | 1194 | mutex_lock(&data->update_lock); |
e1169ba0 GR |
1195 | |
1196 | if (has_16bit_fans(data)) { | |
1197 | data->fan[nr][index] = FAN16_TO_REG(val); | |
1198 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1199 | data->fan[nr][index] & 0xff); | |
1200 | it87_write_value(data, IT87_REG_FANX_MIN[nr], | |
1201 | data->fan[nr][index] >> 8); | |
1202 | } else { | |
1203 | reg = it87_read_value(data, IT87_REG_FAN_DIV); | |
1204 | switch (nr) { | |
1205 | case 0: | |
1206 | data->fan_div[nr] = reg & 0x07; | |
1207 | break; | |
1208 | case 1: | |
1209 | data->fan_div[nr] = (reg >> 3) & 0x07; | |
1210 | break; | |
1211 | case 2: | |
1212 | data->fan_div[nr] = (reg & 0x40) ? 3 : 1; | |
1213 | break; | |
1214 | } | |
1215 | data->fan[nr][index] = | |
1216 | FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); | |
1217 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1218 | data->fan[nr][index]); | |
07eab46d JD |
1219 | } |
1220 | ||
9a61bf63 | 1221 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1222 | return count; |
1223 | } | |
e1169ba0 | 1224 | |
20ad93d4 | 1225 | static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1226 | const char *buf, size_t count) |
1da177e4 | 1227 | { |
20ad93d4 | 1228 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1229 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1230 | int nr = sensor_attr->index; |
f5f64501 | 1231 | unsigned long val; |
8ab4ec3e | 1232 | int min; |
1da177e4 LT |
1233 | u8 old; |
1234 | ||
179c4fdb | 1235 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 JD |
1236 | return -EINVAL; |
1237 | ||
9a61bf63 | 1238 | mutex_lock(&data->update_lock); |
b74f3fdd | 1239 | old = it87_read_value(data, IT87_REG_FAN_DIV); |
1da177e4 | 1240 | |
8ab4ec3e | 1241 | /* Save fan min limit */ |
e1169ba0 | 1242 | min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 LT |
1243 | |
1244 | switch (nr) { | |
1245 | case 0: | |
1246 | case 1: | |
1247 | data->fan_div[nr] = DIV_TO_REG(val); | |
1248 | break; | |
1249 | case 2: | |
1250 | if (val < 8) | |
1251 | data->fan_div[nr] = 1; | |
1252 | else | |
1253 | data->fan_div[nr] = 3; | |
1254 | } | |
1255 | val = old & 0x80; | |
1256 | val |= (data->fan_div[0] & 0x07); | |
1257 | val |= (data->fan_div[1] & 0x07) << 3; | |
1258 | if (data->fan_div[2] == 3) | |
1259 | val |= 0x1 << 6; | |
b74f3fdd | 1260 | it87_write_value(data, IT87_REG_FAN_DIV, val); |
1da177e4 | 1261 | |
8ab4ec3e | 1262 | /* Restore fan min limit */ |
e1169ba0 GR |
1263 | data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); |
1264 | it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); | |
8ab4ec3e | 1265 | |
9a61bf63 | 1266 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1267 | return count; |
1268 | } | |
cccfc9c4 JD |
1269 | |
1270 | /* Returns 0 if OK, -EINVAL otherwise */ | |
1271 | static int check_trip_points(struct device *dev, int nr) | |
1272 | { | |
1273 | const struct it87_data *data = dev_get_drvdata(dev); | |
1274 | int i, err = 0; | |
1275 | ||
1276 | if (has_old_autopwm(data)) { | |
1277 | for (i = 0; i < 3; i++) { | |
1278 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1279 | err = -EINVAL; | |
1280 | } | |
1281 | for (i = 0; i < 2; i++) { | |
1282 | if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) | |
1283 | err = -EINVAL; | |
1284 | } | |
2cbb9c37 GR |
1285 | } else if (has_newer_autopwm(data)) { |
1286 | for (i = 1; i < 3; i++) { | |
1287 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1288 | err = -EINVAL; | |
1289 | } | |
cccfc9c4 JD |
1290 | } |
1291 | ||
1292 | if (err) { | |
1d9bcf6a GR |
1293 | dev_err(dev, |
1294 | "Inconsistent trip points, not switching to automatic mode\n"); | |
cccfc9c4 JD |
1295 | dev_err(dev, "Adjust the trip points and try again\n"); |
1296 | } | |
1297 | return err; | |
1298 | } | |
1299 | ||
c962024e GR |
1300 | static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, |
1301 | const char *buf, size_t count) | |
1da177e4 | 1302 | { |
20ad93d4 | 1303 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1304 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1305 | int nr = sensor_attr->index; |
f5f64501 | 1306 | long val; |
1da177e4 | 1307 | |
179c4fdb | 1308 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) |
b99883dc JD |
1309 | return -EINVAL; |
1310 | ||
cccfc9c4 JD |
1311 | /* Check trip points before switching to automatic mode */ |
1312 | if (val == 2) { | |
1313 | if (check_trip_points(dev, nr) < 0) | |
1314 | return -EINVAL; | |
1315 | } | |
1316 | ||
9a61bf63 | 1317 | mutex_lock(&data->update_lock); |
1da177e4 LT |
1318 | |
1319 | if (val == 0) { | |
f1bbe618 GR |
1320 | if (nr < 3 && data->type != it8603) { |
1321 | int tmp; | |
1322 | /* make sure the fan is on when in on/off mode */ | |
1323 | tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
1324 | it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); | |
1325 | /* set on/off mode */ | |
1326 | data->fan_main_ctrl &= ~BIT(nr); | |
1327 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
1328 | data->fan_main_ctrl); | |
1329 | } else { | |
4c7b8ca1 GR |
1330 | u8 ctrl; |
1331 | ||
f1bbe618 GR |
1332 | /* No on/off mode, set maximum pwm value */ |
1333 | data->pwm_duty[nr] = pwm_to_reg(data, 0xff); | |
1334 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], | |
1335 | data->pwm_duty[nr]); | |
1336 | /* and set manual mode */ | |
4c7b8ca1 GR |
1337 | if (has_newer_autopwm(data)) { |
1338 | ctrl = (data->pwm_ctrl[nr] & 0x7c) | | |
1339 | data->pwm_temp_map[nr]; | |
1340 | } else { | |
1341 | ctrl = data->pwm_duty[nr]; | |
1342 | } | |
1343 | data->pwm_ctrl[nr] = ctrl; | |
1344 | it87_write_value(data, IT87_REG_PWM[nr], ctrl); | |
f1bbe618 | 1345 | } |
b99883dc | 1346 | } else { |
4c7b8ca1 GR |
1347 | u8 ctrl; |
1348 | ||
1349 | if (has_newer_autopwm(data)) { | |
1350 | ctrl = (data->pwm_ctrl[nr] & 0x7c) | | |
1351 | data->pwm_temp_map[nr]; | |
1352 | if (val != 1) | |
1353 | ctrl |= 0x80; | |
1354 | } else { | |
1355 | ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); | |
1356 | } | |
1357 | data->pwm_ctrl[nr] = ctrl; | |
1358 | it87_write_value(data, IT87_REG_PWM[nr], ctrl); | |
c145d5c6 | 1359 | |
f1bbe618 | 1360 | if (data->type != it8603 && nr < 3) { |
c145d5c6 | 1361 | /* set SmartGuardian mode */ |
48b2ae7f | 1362 | data->fan_main_ctrl |= BIT(nr); |
c145d5c6 RM |
1363 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, |
1364 | data->fan_main_ctrl); | |
1365 | } | |
1da177e4 LT |
1366 | } |
1367 | ||
9a61bf63 | 1368 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1369 | return count; |
1370 | } | |
c962024e | 1371 | |
20ad93d4 | 1372 | static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1373 | const char *buf, size_t count) |
1da177e4 | 1374 | { |
20ad93d4 | 1375 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1376 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1377 | int nr = sensor_attr->index; |
f5f64501 | 1378 | long val; |
1da177e4 | 1379 | |
179c4fdb | 1380 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
1da177e4 LT |
1381 | return -EINVAL; |
1382 | ||
9a61bf63 | 1383 | mutex_lock(&data->update_lock); |
82dbe987 | 1384 | it87_update_pwm_ctrl(data, nr); |
16b5dda2 | 1385 | if (has_newer_autopwm(data)) { |
4a0d71cf GR |
1386 | /* |
1387 | * If we are in automatic mode, the PWM duty cycle register | |
1388 | * is read-only so we can't write the value. | |
1389 | */ | |
6229cdb2 JD |
1390 | if (data->pwm_ctrl[nr] & 0x80) { |
1391 | mutex_unlock(&data->update_lock); | |
1392 | return -EBUSY; | |
1393 | } | |
1394 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
36c4d98a | 1395 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], |
6229cdb2 JD |
1396 | data->pwm_duty[nr]); |
1397 | } else { | |
1398 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
4a0d71cf GR |
1399 | /* |
1400 | * If we are in manual mode, write the duty cycle immediately; | |
1401 | * otherwise, just store it for later use. | |
1402 | */ | |
6229cdb2 JD |
1403 | if (!(data->pwm_ctrl[nr] & 0x80)) { |
1404 | data->pwm_ctrl[nr] = data->pwm_duty[nr]; | |
36c4d98a | 1405 | it87_write_value(data, IT87_REG_PWM[nr], |
6229cdb2 JD |
1406 | data->pwm_ctrl[nr]); |
1407 | } | |
b99883dc | 1408 | } |
9a61bf63 | 1409 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1410 | return count; |
1411 | } | |
c962024e GR |
1412 | |
1413 | static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, | |
1414 | const char *buf, size_t count) | |
f8d0c19a | 1415 | { |
60878bcf | 1416 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1417 | struct it87_data *data = dev_get_drvdata(dev); |
60878bcf | 1418 | int nr = sensor_attr->index; |
f5f64501 | 1419 | unsigned long val; |
f8d0c19a JD |
1420 | int i; |
1421 | ||
179c4fdb | 1422 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1423 | return -EINVAL; |
f56c9c0a GR |
1424 | |
1425 | val = clamp_val(val, 0, 1000000); | |
1426 | val *= has_newer_autopwm(data) ? 256 : 128; | |
f5f64501 | 1427 | |
f8d0c19a JD |
1428 | /* Search for the nearest available frequency */ |
1429 | for (i = 0; i < 7; i++) { | |
c962024e | 1430 | if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) |
f8d0c19a JD |
1431 | break; |
1432 | } | |
1433 | ||
1434 | mutex_lock(&data->update_lock); | |
60878bcf GR |
1435 | if (nr == 0) { |
1436 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; | |
1437 | data->fan_ctl |= i << 4; | |
1438 | it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); | |
1439 | } else { | |
1440 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; | |
1441 | data->extra |= i << 4; | |
1442 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
1443 | } | |
f8d0c19a JD |
1444 | mutex_unlock(&data->update_lock); |
1445 | ||
1446 | return count; | |
1447 | } | |
c962024e | 1448 | |
94ac7ee6 | 1449 | static ssize_t show_pwm_temp_map(struct device *dev, |
c962024e | 1450 | struct device_attribute *attr, char *buf) |
94ac7ee6 JD |
1451 | { |
1452 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1453 | struct it87_data *data = it87_update_device(dev); |
c962024e | 1454 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1455 | int map; |
1456 | ||
0624d861 GR |
1457 | map = data->pwm_temp_map[nr]; |
1458 | if (map >= 3) | |
1459 | map = 0; /* Should never happen */ | |
1460 | if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ | |
1461 | map += 3; | |
1462 | ||
1463 | return sprintf(buf, "%d\n", (int)BIT(map)); | |
94ac7ee6 | 1464 | } |
c962024e | 1465 | |
94ac7ee6 | 1466 | static ssize_t set_pwm_temp_map(struct device *dev, |
c962024e GR |
1467 | struct device_attribute *attr, const char *buf, |
1468 | size_t count) | |
94ac7ee6 JD |
1469 | { |
1470 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1471 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1472 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1473 | long val; |
1474 | u8 reg; | |
1475 | ||
179c4fdb | 1476 | if (kstrtol(buf, 10, &val) < 0) |
94ac7ee6 JD |
1477 | return -EINVAL; |
1478 | ||
0624d861 GR |
1479 | if (nr >= 3) |
1480 | val -= 3; | |
1481 | ||
94ac7ee6 | 1482 | switch (val) { |
48b2ae7f | 1483 | case BIT(0): |
94ac7ee6 JD |
1484 | reg = 0x00; |
1485 | break; | |
48b2ae7f | 1486 | case BIT(1): |
94ac7ee6 JD |
1487 | reg = 0x01; |
1488 | break; | |
48b2ae7f | 1489 | case BIT(2): |
94ac7ee6 JD |
1490 | reg = 0x02; |
1491 | break; | |
1492 | default: | |
1493 | return -EINVAL; | |
1494 | } | |
1495 | ||
1496 | mutex_lock(&data->update_lock); | |
82dbe987 | 1497 | it87_update_pwm_ctrl(data, nr); |
94ac7ee6 | 1498 | data->pwm_temp_map[nr] = reg; |
4a0d71cf GR |
1499 | /* |
1500 | * If we are in automatic mode, write the temp mapping immediately; | |
1501 | * otherwise, just store it for later use. | |
1502 | */ | |
94ac7ee6 | 1503 | if (data->pwm_ctrl[nr] & 0x80) { |
4c7b8ca1 GR |
1504 | data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | |
1505 | data->pwm_temp_map[nr]; | |
36c4d98a | 1506 | it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); |
94ac7ee6 JD |
1507 | } |
1508 | mutex_unlock(&data->update_lock); | |
1509 | return count; | |
1510 | } | |
1da177e4 | 1511 | |
c962024e GR |
1512 | static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, |
1513 | char *buf) | |
4f3f51bc JD |
1514 | { |
1515 | struct it87_data *data = it87_update_device(dev); | |
1516 | struct sensor_device_attribute_2 *sensor_attr = | |
1517 | to_sensor_dev_attr_2(attr); | |
1518 | int nr = sensor_attr->nr; | |
1519 | int point = sensor_attr->index; | |
1520 | ||
44c1bcd4 JD |
1521 | return sprintf(buf, "%d\n", |
1522 | pwm_from_reg(data, data->auto_pwm[nr][point])); | |
4f3f51bc JD |
1523 | } |
1524 | ||
c962024e GR |
1525 | static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, |
1526 | const char *buf, size_t count) | |
4f3f51bc JD |
1527 | { |
1528 | struct it87_data *data = dev_get_drvdata(dev); | |
1529 | struct sensor_device_attribute_2 *sensor_attr = | |
1530 | to_sensor_dev_attr_2(attr); | |
1531 | int nr = sensor_attr->nr; | |
1532 | int point = sensor_attr->index; | |
2cbb9c37 | 1533 | int regaddr; |
4f3f51bc JD |
1534 | long val; |
1535 | ||
179c4fdb | 1536 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
4f3f51bc JD |
1537 | return -EINVAL; |
1538 | ||
1539 | mutex_lock(&data->update_lock); | |
44c1bcd4 | 1540 | data->auto_pwm[nr][point] = pwm_to_reg(data, val); |
2cbb9c37 GR |
1541 | if (has_newer_autopwm(data)) |
1542 | regaddr = IT87_REG_AUTO_TEMP(nr, 3); | |
1543 | else | |
1544 | regaddr = IT87_REG_AUTO_PWM(nr, point); | |
1545 | it87_write_value(data, regaddr, data->auto_pwm[nr][point]); | |
1546 | mutex_unlock(&data->update_lock); | |
1547 | return count; | |
1548 | } | |
1549 | ||
1550 | static ssize_t show_auto_pwm_slope(struct device *dev, | |
1551 | struct device_attribute *attr, char *buf) | |
1552 | { | |
1553 | struct it87_data *data = it87_update_device(dev); | |
1554 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1555 | int nr = sensor_attr->index; | |
1556 | ||
1557 | return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); | |
1558 | } | |
1559 | ||
1560 | static ssize_t set_auto_pwm_slope(struct device *dev, | |
1561 | struct device_attribute *attr, | |
1562 | const char *buf, size_t count) | |
1563 | { | |
1564 | struct it87_data *data = dev_get_drvdata(dev); | |
1565 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1566 | int nr = sensor_attr->index; | |
1567 | unsigned long val; | |
1568 | ||
1569 | if (kstrtoul(buf, 10, &val) < 0 || val > 127) | |
1570 | return -EINVAL; | |
1571 | ||
1572 | mutex_lock(&data->update_lock); | |
1573 | data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; | |
1574 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), | |
1575 | data->auto_pwm[nr][1]); | |
4f3f51bc JD |
1576 | mutex_unlock(&data->update_lock); |
1577 | return count; | |
1578 | } | |
1579 | ||
c962024e GR |
1580 | static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, |
1581 | char *buf) | |
4f3f51bc JD |
1582 | { |
1583 | struct it87_data *data = it87_update_device(dev); | |
1584 | struct sensor_device_attribute_2 *sensor_attr = | |
1585 | to_sensor_dev_attr_2(attr); | |
1586 | int nr = sensor_attr->nr; | |
1587 | int point = sensor_attr->index; | |
2cbb9c37 GR |
1588 | int reg; |
1589 | ||
1590 | if (has_old_autopwm(data) || point) | |
1591 | reg = data->auto_temp[nr][point]; | |
1592 | else | |
1593 | reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); | |
4f3f51bc | 1594 | |
2cbb9c37 | 1595 | return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); |
4f3f51bc JD |
1596 | } |
1597 | ||
c962024e GR |
1598 | static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, |
1599 | const char *buf, size_t count) | |
4f3f51bc JD |
1600 | { |
1601 | struct it87_data *data = dev_get_drvdata(dev); | |
1602 | struct sensor_device_attribute_2 *sensor_attr = | |
1603 | to_sensor_dev_attr_2(attr); | |
1604 | int nr = sensor_attr->nr; | |
1605 | int point = sensor_attr->index; | |
1606 | long val; | |
2cbb9c37 | 1607 | int reg; |
4f3f51bc | 1608 | |
179c4fdb | 1609 | if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) |
4f3f51bc JD |
1610 | return -EINVAL; |
1611 | ||
1612 | mutex_lock(&data->update_lock); | |
2cbb9c37 GR |
1613 | if (has_newer_autopwm(data) && !point) { |
1614 | reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); | |
1615 | reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); | |
1616 | data->auto_temp[nr][0] = reg; | |
1617 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); | |
1618 | } else { | |
1619 | reg = TEMP_TO_REG(val); | |
1620 | data->auto_temp[nr][point] = reg; | |
1621 | if (has_newer_autopwm(data)) | |
1622 | point--; | |
1623 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); | |
1624 | } | |
4f3f51bc JD |
1625 | mutex_unlock(&data->update_lock); |
1626 | return count; | |
1627 | } | |
1628 | ||
e1169ba0 GR |
1629 | static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); |
1630 | static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1631 | 0, 1); | |
1632 | static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1633 | set_fan_div, 0); | |
1634 | ||
1635 | static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); | |
1636 | static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1637 | 1, 1); | |
1638 | static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1639 | set_fan_div, 1); | |
1640 | ||
1641 | static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); | |
1642 | static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1643 | 2, 1); | |
1644 | static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1645 | set_fan_div, 2); | |
1646 | ||
1647 | static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); | |
1648 | static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1649 | 3, 1); | |
1da177e4 | 1650 | |
e1169ba0 GR |
1651 | static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); |
1652 | static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1653 | 4, 1); | |
1da177e4 | 1654 | |
fa3f70d6 GR |
1655 | static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); |
1656 | static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1657 | 5, 1); | |
1658 | ||
c4458db3 GR |
1659 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, |
1660 | show_pwm_enable, set_pwm_enable, 0); | |
1661 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); | |
60878bcf GR |
1662 | static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, |
1663 | set_pwm_freq, 0); | |
5c391261 | 1664 | static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1665 | show_pwm_temp_map, set_pwm_temp_map, 0); |
1666 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1667 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1668 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1669 | show_auto_pwm, set_auto_pwm, 0, 1); | |
1670 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1671 | show_auto_pwm, set_auto_pwm, 0, 2); | |
1672 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, | |
1673 | show_auto_pwm, NULL, 0, 3); | |
1674 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1675 | show_auto_temp, set_auto_temp, 0, 1); | |
1676 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1677 | show_auto_temp, set_auto_temp, 0, 0); | |
1678 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1679 | show_auto_temp, set_auto_temp, 0, 2); | |
1680 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1681 | show_auto_temp, set_auto_temp, 0, 3); | |
1682 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1683 | show_auto_temp, set_auto_temp, 0, 4); | |
2cbb9c37 GR |
1684 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, |
1685 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1686 | static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, | |
1687 | show_auto_pwm_slope, set_auto_pwm_slope, 0); | |
c4458db3 GR |
1688 | |
1689 | static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, | |
1690 | show_pwm_enable, set_pwm_enable, 1); | |
1691 | static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); | |
60878bcf | 1692 | static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); |
5c391261 | 1693 | static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1694 | show_pwm_temp_map, set_pwm_temp_map, 1); |
1695 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1696 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1697 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1698 | show_auto_pwm, set_auto_pwm, 1, 1); | |
1699 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1700 | show_auto_pwm, set_auto_pwm, 1, 2); | |
1701 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, | |
1702 | show_auto_pwm, NULL, 1, 3); | |
1703 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1704 | show_auto_temp, set_auto_temp, 1, 1); | |
1705 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1706 | show_auto_temp, set_auto_temp, 1, 0); | |
1707 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1708 | show_auto_temp, set_auto_temp, 1, 2); | |
1709 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1710 | show_auto_temp, set_auto_temp, 1, 3); | |
1711 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1712 | show_auto_temp, set_auto_temp, 1, 4); | |
2cbb9c37 GR |
1713 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, |
1714 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1715 | static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, | |
1716 | show_auto_pwm_slope, set_auto_pwm_slope, 1); | |
c4458db3 GR |
1717 | |
1718 | static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, | |
1719 | show_pwm_enable, set_pwm_enable, 2); | |
1720 | static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); | |
60878bcf | 1721 | static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); |
5c391261 | 1722 | static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1723 | show_pwm_temp_map, set_pwm_temp_map, 2); |
1724 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1725 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1726 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1727 | show_auto_pwm, set_auto_pwm, 2, 1); | |
1728 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1729 | show_auto_pwm, set_auto_pwm, 2, 2); | |
1730 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, | |
1731 | show_auto_pwm, NULL, 2, 3); | |
1732 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1733 | show_auto_temp, set_auto_temp, 2, 1); | |
1734 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1735 | show_auto_temp, set_auto_temp, 2, 0); | |
1736 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1737 | show_auto_temp, set_auto_temp, 2, 2); | |
1738 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1739 | show_auto_temp, set_auto_temp, 2, 3); | |
1740 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1741 | show_auto_temp, set_auto_temp, 2, 4); | |
2cbb9c37 GR |
1742 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, |
1743 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1744 | static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, | |
1745 | show_auto_pwm_slope, set_auto_pwm_slope, 2); | |
1da177e4 | 1746 | |
36c4d98a GR |
1747 | static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, |
1748 | show_pwm_enable, set_pwm_enable, 3); | |
1749 | static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); | |
60878bcf | 1750 | static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); |
5c391261 | 1751 | static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, |
36c4d98a | 1752 | show_pwm_temp_map, set_pwm_temp_map, 3); |
2cbb9c37 GR |
1753 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, |
1754 | show_auto_temp, set_auto_temp, 2, 1); | |
1755 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1756 | show_auto_temp, set_auto_temp, 2, 0); | |
1757 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1758 | show_auto_temp, set_auto_temp, 2, 2); | |
1759 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1760 | show_auto_temp, set_auto_temp, 2, 3); | |
1761 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, | |
1762 | show_auto_pwm, set_auto_pwm, 3, 0); | |
1763 | static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, | |
1764 | show_auto_pwm_slope, set_auto_pwm_slope, 3); | |
36c4d98a GR |
1765 | |
1766 | static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, | |
1767 | show_pwm_enable, set_pwm_enable, 4); | |
1768 | static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); | |
60878bcf | 1769 | static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); |
5c391261 | 1770 | static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, |
36c4d98a | 1771 | show_pwm_temp_map, set_pwm_temp_map, 4); |
2cbb9c37 GR |
1772 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, |
1773 | show_auto_temp, set_auto_temp, 2, 1); | |
1774 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1775 | show_auto_temp, set_auto_temp, 2, 0); | |
1776 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1777 | show_auto_temp, set_auto_temp, 2, 2); | |
1778 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1779 | show_auto_temp, set_auto_temp, 2, 3); | |
1780 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, | |
1781 | show_auto_pwm, set_auto_pwm, 4, 0); | |
1782 | static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, | |
1783 | show_auto_pwm_slope, set_auto_pwm_slope, 4); | |
36c4d98a GR |
1784 | |
1785 | static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, | |
1786 | show_pwm_enable, set_pwm_enable, 5); | |
1787 | static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); | |
60878bcf | 1788 | static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); |
5c391261 | 1789 | static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, |
36c4d98a | 1790 | show_pwm_temp_map, set_pwm_temp_map, 5); |
2cbb9c37 GR |
1791 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, |
1792 | show_auto_temp, set_auto_temp, 2, 1); | |
1793 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1794 | show_auto_temp, set_auto_temp, 2, 0); | |
1795 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1796 | show_auto_temp, set_auto_temp, 2, 2); | |
1797 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1798 | show_auto_temp, set_auto_temp, 2, 3); | |
1799 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, | |
1800 | show_auto_pwm, set_auto_pwm, 5, 0); | |
1801 | static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, | |
1802 | show_auto_pwm_slope, set_auto_pwm_slope, 5); | |
36c4d98a | 1803 | |
1da177e4 | 1804 | /* Alarms */ |
ddc64ae8 | 1805 | static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, |
c962024e | 1806 | char *buf) |
1da177e4 LT |
1807 | { |
1808 | struct it87_data *data = it87_update_device(dev); | |
c962024e | 1809 | |
68188ba7 | 1810 | return sprintf(buf, "%u\n", data->alarms); |
1da177e4 | 1811 | } |
ddc64ae8 | 1812 | static DEVICE_ATTR_RO(alarms); |
1da177e4 | 1813 | |
0124dd78 | 1814 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
c962024e | 1815 | char *buf) |
0124dd78 | 1816 | { |
0124dd78 | 1817 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1818 | int bitnr = to_sensor_dev_attr(attr)->index; |
1819 | ||
0124dd78 JD |
1820 | return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); |
1821 | } | |
3d30f9e6 | 1822 | |
c962024e GR |
1823 | static ssize_t clear_intrusion(struct device *dev, |
1824 | struct device_attribute *attr, const char *buf, | |
1825 | size_t count) | |
3d30f9e6 JD |
1826 | { |
1827 | struct it87_data *data = dev_get_drvdata(dev); | |
3d30f9e6 | 1828 | int config; |
c962024e | 1829 | long val; |
3d30f9e6 | 1830 | |
179c4fdb | 1831 | if (kstrtol(buf, 10, &val) < 0 || val != 0) |
3d30f9e6 JD |
1832 | return -EINVAL; |
1833 | ||
1834 | mutex_lock(&data->update_lock); | |
1835 | config = it87_read_value(data, IT87_REG_CONFIG); | |
1836 | if (config < 0) { | |
1837 | count = config; | |
1838 | } else { | |
48b2ae7f | 1839 | config |= BIT(5); |
3d30f9e6 JD |
1840 | it87_write_value(data, IT87_REG_CONFIG, config); |
1841 | /* Invalidate cache to force re-read */ | |
1842 | data->valid = 0; | |
1843 | } | |
1844 | mutex_unlock(&data->update_lock); | |
1845 | ||
1846 | return count; | |
1847 | } | |
1848 | ||
0124dd78 JD |
1849 | static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); |
1850 | static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); | |
1851 | static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); | |
1852 | static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); | |
1853 | static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); | |
1854 | static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); | |
1855 | static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); | |
1856 | static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); | |
1857 | static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); | |
1858 | static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); | |
1859 | static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); | |
1860 | static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); | |
1861 | static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); | |
fa3f70d6 | 1862 | static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); |
0124dd78 JD |
1863 | static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); |
1864 | static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); | |
1865 | static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); | |
3d30f9e6 JD |
1866 | static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, |
1867 | show_alarm, clear_intrusion, 4); | |
0124dd78 | 1868 | |
d9b327c3 | 1869 | static ssize_t show_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1870 | char *buf) |
d9b327c3 | 1871 | { |
d9b327c3 | 1872 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1873 | int bitnr = to_sensor_dev_attr(attr)->index; |
1874 | ||
d9b327c3 JD |
1875 | return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); |
1876 | } | |
c962024e | 1877 | |
d9b327c3 | 1878 | static ssize_t set_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1879 | const char *buf, size_t count) |
d9b327c3 JD |
1880 | { |
1881 | int bitnr = to_sensor_dev_attr(attr)->index; | |
1882 | struct it87_data *data = dev_get_drvdata(dev); | |
1883 | long val; | |
1884 | ||
c962024e | 1885 | if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) |
d9b327c3 JD |
1886 | return -EINVAL; |
1887 | ||
1888 | mutex_lock(&data->update_lock); | |
1889 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
1890 | if (val) | |
48b2ae7f | 1891 | data->beeps |= BIT(bitnr); |
d9b327c3 | 1892 | else |
48b2ae7f | 1893 | data->beeps &= ~BIT(bitnr); |
d9b327c3 JD |
1894 | it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); |
1895 | mutex_unlock(&data->update_lock); | |
1896 | return count; | |
1897 | } | |
1898 | ||
1899 | static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, | |
1900 | show_beep, set_beep, 1); | |
1901 | static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); | |
1902 | static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); | |
1903 | static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); | |
1904 | static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); | |
1905 | static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); | |
1906 | static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); | |
1907 | static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); | |
1908 | /* fanX_beep writability is set later */ | |
1909 | static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); | |
1910 | static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); | |
1911 | static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); | |
1912 | static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); | |
1913 | static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); | |
fa3f70d6 | 1914 | static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); |
d9b327c3 JD |
1915 | static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, |
1916 | show_beep, set_beep, 2); | |
1917 | static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); | |
1918 | static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); | |
1919 | ||
ddc64ae8 JL |
1920 | static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, |
1921 | char *buf) | |
1da177e4 | 1922 | { |
90d6619a | 1923 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1924 | |
a7be58a1 | 1925 | return sprintf(buf, "%u\n", data->vrm); |
1da177e4 | 1926 | } |
c962024e | 1927 | |
ddc64ae8 JL |
1928 | static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, |
1929 | const char *buf, size_t count) | |
1da177e4 | 1930 | { |
b74f3fdd | 1931 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 JD |
1932 | unsigned long val; |
1933 | ||
179c4fdb | 1934 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1935 | return -EINVAL; |
1da177e4 | 1936 | |
1da177e4 LT |
1937 | data->vrm = val; |
1938 | ||
1939 | return count; | |
1940 | } | |
ddc64ae8 | 1941 | static DEVICE_ATTR_RW(vrm); |
1da177e4 | 1942 | |
ddc64ae8 JL |
1943 | static ssize_t cpu0_vid_show(struct device *dev, |
1944 | struct device_attribute *attr, char *buf) | |
1da177e4 LT |
1945 | { |
1946 | struct it87_data *data = it87_update_device(dev); | |
c962024e GR |
1947 | |
1948 | return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); | |
1da177e4 | 1949 | } |
ddc64ae8 | 1950 | static DEVICE_ATTR_RO(cpu0_vid); |
87808be4 | 1951 | |
738e5e05 | 1952 | static ssize_t show_label(struct device *dev, struct device_attribute *attr, |
c962024e | 1953 | char *buf) |
738e5e05 | 1954 | { |
3c4c4971 | 1955 | static const char * const labels[] = { |
738e5e05 JD |
1956 | "+5V", |
1957 | "5VSB", | |
1958 | "Vbat", | |
638c1c07 | 1959 | "AVCC", |
738e5e05 | 1960 | }; |
3c4c4971 | 1961 | static const char * const labels_it8721[] = { |
44c1bcd4 JD |
1962 | "+3.3V", |
1963 | "3VSB", | |
1964 | "Vbat", | |
638c1c07 | 1965 | "+3.3V", |
44c1bcd4 JD |
1966 | }; |
1967 | struct it87_data *data = dev_get_drvdata(dev); | |
738e5e05 | 1968 | int nr = to_sensor_dev_attr(attr)->index; |
ead80803 | 1969 | const char *label; |
738e5e05 | 1970 | |
a9eebd4f GR |
1971 | if (has_vin3_5v(data) && nr == 0) |
1972 | label = labels[0]; | |
1973 | else if (has_12mv_adc(data) || has_10_9mv_adc(data)) | |
ead80803 JM |
1974 | label = labels_it8721[nr]; |
1975 | else | |
1976 | label = labels[nr]; | |
1977 | ||
1978 | return sprintf(buf, "%s\n", label); | |
738e5e05 JD |
1979 | } |
1980 | static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); | |
1981 | static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); | |
1982 | static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); | |
73055405 | 1983 | /* AVCC3 */ |
638c1c07 | 1984 | static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); |
738e5e05 | 1985 | |
52929715 GR |
1986 | static umode_t it87_in_is_visible(struct kobject *kobj, |
1987 | struct attribute *attr, int index) | |
9172b5d1 | 1988 | { |
52929715 GR |
1989 | struct device *dev = container_of(kobj, struct device, kobj); |
1990 | struct it87_data *data = dev_get_drvdata(dev); | |
1991 | int i = index / 5; /* voltage index */ | |
1992 | int a = index % 5; /* attribute index */ | |
1993 | ||
f838aa26 | 1994 | if (index >= 40) { /* in8 and higher only have input attributes */ |
52929715 GR |
1995 | i = index - 40 + 8; |
1996 | a = 0; | |
1997 | } | |
1998 | ||
48b2ae7f | 1999 | if (!(data->has_in & BIT(i))) |
52929715 GR |
2000 | return 0; |
2001 | ||
2002 | if (a == 4 && !data->has_beep) | |
2003 | return 0; | |
2004 | ||
2005 | return attr->mode; | |
2006 | } | |
2007 | ||
2008 | static struct attribute *it87_attributes_in[] = { | |
87808be4 | 2009 | &sensor_dev_attr_in0_input.dev_attr.attr, |
87808be4 | 2010 | &sensor_dev_attr_in0_min.dev_attr.attr, |
87808be4 | 2011 | &sensor_dev_attr_in0_max.dev_attr.attr, |
0124dd78 | 2012 | &sensor_dev_attr_in0_alarm.dev_attr.attr, |
52929715 GR |
2013 | &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ |
2014 | ||
9172b5d1 GR |
2015 | &sensor_dev_attr_in1_input.dev_attr.attr, |
2016 | &sensor_dev_attr_in1_min.dev_attr.attr, | |
2017 | &sensor_dev_attr_in1_max.dev_attr.attr, | |
0124dd78 | 2018 | &sensor_dev_attr_in1_alarm.dev_attr.attr, |
52929715 GR |
2019 | &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ |
2020 | ||
9172b5d1 GR |
2021 | &sensor_dev_attr_in2_input.dev_attr.attr, |
2022 | &sensor_dev_attr_in2_min.dev_attr.attr, | |
2023 | &sensor_dev_attr_in2_max.dev_attr.attr, | |
0124dd78 | 2024 | &sensor_dev_attr_in2_alarm.dev_attr.attr, |
52929715 GR |
2025 | &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ |
2026 | ||
9172b5d1 GR |
2027 | &sensor_dev_attr_in3_input.dev_attr.attr, |
2028 | &sensor_dev_attr_in3_min.dev_attr.attr, | |
2029 | &sensor_dev_attr_in3_max.dev_attr.attr, | |
0124dd78 | 2030 | &sensor_dev_attr_in3_alarm.dev_attr.attr, |
52929715 GR |
2031 | &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ |
2032 | ||
9172b5d1 GR |
2033 | &sensor_dev_attr_in4_input.dev_attr.attr, |
2034 | &sensor_dev_attr_in4_min.dev_attr.attr, | |
2035 | &sensor_dev_attr_in4_max.dev_attr.attr, | |
0124dd78 | 2036 | &sensor_dev_attr_in4_alarm.dev_attr.attr, |
52929715 GR |
2037 | &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ |
2038 | ||
9172b5d1 GR |
2039 | &sensor_dev_attr_in5_input.dev_attr.attr, |
2040 | &sensor_dev_attr_in5_min.dev_attr.attr, | |
2041 | &sensor_dev_attr_in5_max.dev_attr.attr, | |
0124dd78 | 2042 | &sensor_dev_attr_in5_alarm.dev_attr.attr, |
52929715 GR |
2043 | &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ |
2044 | ||
9172b5d1 GR |
2045 | &sensor_dev_attr_in6_input.dev_attr.attr, |
2046 | &sensor_dev_attr_in6_min.dev_attr.attr, | |
2047 | &sensor_dev_attr_in6_max.dev_attr.attr, | |
0124dd78 | 2048 | &sensor_dev_attr_in6_alarm.dev_attr.attr, |
52929715 GR |
2049 | &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ |
2050 | ||
9172b5d1 GR |
2051 | &sensor_dev_attr_in7_input.dev_attr.attr, |
2052 | &sensor_dev_attr_in7_min.dev_attr.attr, | |
2053 | &sensor_dev_attr_in7_max.dev_attr.attr, | |
0124dd78 | 2054 | &sensor_dev_attr_in7_alarm.dev_attr.attr, |
52929715 GR |
2055 | &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ |
2056 | ||
2057 | &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ | |
d5f3f6c8 JD |
2058 | &sensor_dev_attr_in9_input.dev_attr.attr, |
2059 | &sensor_dev_attr_in10_input.dev_attr.attr, | |
2060 | &sensor_dev_attr_in11_input.dev_attr.attr, | |
2061 | &sensor_dev_attr_in12_input.dev_attr.attr, | |
3c329263 | 2062 | NULL |
52929715 GR |
2063 | }; |
2064 | ||
2065 | static const struct attribute_group it87_group_in = { | |
2066 | .attrs = it87_attributes_in, | |
2067 | .is_visible = it87_in_is_visible, | |
9172b5d1 GR |
2068 | }; |
2069 | ||
87533770 GR |
2070 | static umode_t it87_temp_is_visible(struct kobject *kobj, |
2071 | struct attribute *attr, int index) | |
4573acbc | 2072 | { |
87533770 GR |
2073 | struct device *dev = container_of(kobj, struct device, kobj); |
2074 | struct it87_data *data = dev_get_drvdata(dev); | |
2075 | int i = index / 7; /* temperature index */ | |
2076 | int a = index % 7; /* attribute index */ | |
2077 | ||
cc18da79 GR |
2078 | if (index >= 21) { |
2079 | i = index - 21 + 3; | |
2080 | a = 0; | |
2081 | } | |
2082 | ||
48b2ae7f | 2083 | if (!(data->has_temp & BIT(i))) |
87533770 GR |
2084 | return 0; |
2085 | ||
2086 | if (a == 5 && !has_temp_offset(data)) | |
2087 | return 0; | |
2088 | ||
2089 | if (a == 6 && !data->has_beep) | |
2090 | return 0; | |
2091 | ||
2092 | return attr->mode; | |
2093 | } | |
2094 | ||
2095 | static struct attribute *it87_attributes_temp[] = { | |
87808be4 | 2096 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
87808be4 | 2097 | &sensor_dev_attr_temp1_max.dev_attr.attr, |
87808be4 | 2098 | &sensor_dev_attr_temp1_min.dev_attr.attr, |
87808be4 | 2099 | &sensor_dev_attr_temp1_type.dev_attr.attr, |
0124dd78 | 2100 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, |
87533770 GR |
2101 | &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ |
2102 | &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ | |
2103 | ||
cc18da79 | 2104 | &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ |
4573acbc GR |
2105 | &sensor_dev_attr_temp2_max.dev_attr.attr, |
2106 | &sensor_dev_attr_temp2_min.dev_attr.attr, | |
2107 | &sensor_dev_attr_temp2_type.dev_attr.attr, | |
0124dd78 | 2108 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, |
87533770 GR |
2109 | &sensor_dev_attr_temp2_offset.dev_attr.attr, |
2110 | &sensor_dev_attr_temp2_beep.dev_attr.attr, | |
2111 | ||
cc18da79 | 2112 | &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ |
4573acbc GR |
2113 | &sensor_dev_attr_temp3_max.dev_attr.attr, |
2114 | &sensor_dev_attr_temp3_min.dev_attr.attr, | |
2115 | &sensor_dev_attr_temp3_type.dev_attr.attr, | |
0124dd78 | 2116 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, |
87533770 GR |
2117 | &sensor_dev_attr_temp3_offset.dev_attr.attr, |
2118 | &sensor_dev_attr_temp3_beep.dev_attr.attr, | |
4573acbc | 2119 | |
cc18da79 GR |
2120 | &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ |
2121 | &sensor_dev_attr_temp5_input.dev_attr.attr, | |
2122 | &sensor_dev_attr_temp6_input.dev_attr.attr, | |
87533770 | 2123 | NULL |
4573acbc | 2124 | }; |
87808be4 | 2125 | |
87533770 GR |
2126 | static const struct attribute_group it87_group_temp = { |
2127 | .attrs = it87_attributes_temp, | |
2128 | .is_visible = it87_temp_is_visible, | |
161d898a GR |
2129 | }; |
2130 | ||
d3766848 GR |
2131 | static umode_t it87_is_visible(struct kobject *kobj, |
2132 | struct attribute *attr, int index) | |
2133 | { | |
2134 | struct device *dev = container_of(kobj, struct device, kobj); | |
2135 | struct it87_data *data = dev_get_drvdata(dev); | |
2136 | ||
8638d0af | 2137 | if ((index == 2 || index == 3) && !data->has_vid) |
d3766848 GR |
2138 | return 0; |
2139 | ||
48b2ae7f | 2140 | if (index > 3 && !(data->in_internal & BIT(index - 4))) |
d3766848 GR |
2141 | return 0; |
2142 | ||
2143 | return attr->mode; | |
2144 | } | |
2145 | ||
4573acbc | 2146 | static struct attribute *it87_attributes[] = { |
87808be4 | 2147 | &dev_attr_alarms.attr, |
3d30f9e6 | 2148 | &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, |
8638d0af GR |
2149 | &dev_attr_vrm.attr, /* 2 */ |
2150 | &dev_attr_cpu0_vid.attr, /* 3 */ | |
2151 | &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ | |
d3766848 GR |
2152 | &sensor_dev_attr_in7_label.dev_attr.attr, |
2153 | &sensor_dev_attr_in8_label.dev_attr.attr, | |
2154 | &sensor_dev_attr_in9_label.dev_attr.attr, | |
87808be4 JD |
2155 | NULL |
2156 | }; | |
2157 | ||
2158 | static const struct attribute_group it87_group = { | |
2159 | .attrs = it87_attributes, | |
d3766848 | 2160 | .is_visible = it87_is_visible, |
87808be4 JD |
2161 | }; |
2162 | ||
9a70ee81 GR |
2163 | static umode_t it87_fan_is_visible(struct kobject *kobj, |
2164 | struct attribute *attr, int index) | |
2165 | { | |
2166 | struct device *dev = container_of(kobj, struct device, kobj); | |
2167 | struct it87_data *data = dev_get_drvdata(dev); | |
2168 | int i = index / 5; /* fan index */ | |
2169 | int a = index % 5; /* attribute index */ | |
2170 | ||
2171 | if (index >= 15) { /* fan 4..6 don't have divisor attributes */ | |
2172 | i = (index - 15) / 4 + 3; | |
2173 | a = (index - 15) % 4; | |
2174 | } | |
2175 | ||
48b2ae7f | 2176 | if (!(data->has_fan & BIT(i))) |
9a70ee81 GR |
2177 | return 0; |
2178 | ||
2179 | if (a == 3) { /* beep */ | |
2180 | if (!data->has_beep) | |
2181 | return 0; | |
2182 | /* first fan beep attribute is writable */ | |
2183 | if (i == __ffs(data->has_fan)) | |
2184 | return attr->mode | S_IWUSR; | |
2185 | } | |
2186 | ||
2187 | if (a == 4 && has_16bit_fans(data)) /* divisor */ | |
2188 | return 0; | |
2189 | ||
2190 | return attr->mode; | |
2191 | } | |
2192 | ||
2193 | static struct attribute *it87_attributes_fan[] = { | |
e1169ba0 GR |
2194 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
2195 | &sensor_dev_attr_fan1_min.dev_attr.attr, | |
723a0aa0 | 2196 | &sensor_dev_attr_fan1_alarm.dev_attr.attr, |
9a70ee81 GR |
2197 | &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ |
2198 | &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ | |
2199 | ||
e1169ba0 GR |
2200 | &sensor_dev_attr_fan2_input.dev_attr.attr, |
2201 | &sensor_dev_attr_fan2_min.dev_attr.attr, | |
723a0aa0 | 2202 | &sensor_dev_attr_fan2_alarm.dev_attr.attr, |
9a70ee81 GR |
2203 | &sensor_dev_attr_fan2_beep.dev_attr.attr, |
2204 | &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ | |
2205 | ||
e1169ba0 GR |
2206 | &sensor_dev_attr_fan3_input.dev_attr.attr, |
2207 | &sensor_dev_attr_fan3_min.dev_attr.attr, | |
723a0aa0 | 2208 | &sensor_dev_attr_fan3_alarm.dev_attr.attr, |
9a70ee81 GR |
2209 | &sensor_dev_attr_fan3_beep.dev_attr.attr, |
2210 | &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ | |
2211 | ||
2212 | &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ | |
e1169ba0 | 2213 | &sensor_dev_attr_fan4_min.dev_attr.attr, |
723a0aa0 | 2214 | &sensor_dev_attr_fan4_alarm.dev_attr.attr, |
9a70ee81 GR |
2215 | &sensor_dev_attr_fan4_beep.dev_attr.attr, |
2216 | ||
2217 | &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ | |
e1169ba0 | 2218 | &sensor_dev_attr_fan5_min.dev_attr.attr, |
723a0aa0 | 2219 | &sensor_dev_attr_fan5_alarm.dev_attr.attr, |
9a70ee81 GR |
2220 | &sensor_dev_attr_fan5_beep.dev_attr.attr, |
2221 | ||
2222 | &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ | |
fa3f70d6 GR |
2223 | &sensor_dev_attr_fan6_min.dev_attr.attr, |
2224 | &sensor_dev_attr_fan6_alarm.dev_attr.attr, | |
9a70ee81 | 2225 | &sensor_dev_attr_fan6_beep.dev_attr.attr, |
fa3f70d6 | 2226 | NULL |
723a0aa0 | 2227 | }; |
87808be4 | 2228 | |
9a70ee81 GR |
2229 | static const struct attribute_group it87_group_fan = { |
2230 | .attrs = it87_attributes_fan, | |
2231 | .is_visible = it87_fan_is_visible, | |
723a0aa0 JD |
2232 | }; |
2233 | ||
5c391261 GR |
2234 | static umode_t it87_pwm_is_visible(struct kobject *kobj, |
2235 | struct attribute *attr, int index) | |
2236 | { | |
2237 | struct device *dev = container_of(kobj, struct device, kobj); | |
2238 | struct it87_data *data = dev_get_drvdata(dev); | |
2239 | int i = index / 4; /* pwm index */ | |
2240 | int a = index % 4; /* attribute index */ | |
2241 | ||
48b2ae7f | 2242 | if (!(data->has_pwm & BIT(i))) |
5c391261 GR |
2243 | return 0; |
2244 | ||
2cbb9c37 GR |
2245 | /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ |
2246 | if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) | |
5c391261 GR |
2247 | return attr->mode | S_IWUSR; |
2248 | ||
2249 | /* pwm2_freq is writable if there are two pwm frequency selects */ | |
2250 | if (has_pwm_freq2(data) && i == 1 && a == 2) | |
2251 | return attr->mode | S_IWUSR; | |
2252 | ||
2253 | return attr->mode; | |
2254 | } | |
2255 | ||
2256 | static struct attribute *it87_attributes_pwm[] = { | |
87808be4 | 2257 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
87808be4 | 2258 | &sensor_dev_attr_pwm1.dev_attr.attr, |
60878bcf | 2259 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
94ac7ee6 | 2260 | &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, |
5c391261 | 2261 | |
723a0aa0 JD |
2262 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, |
2263 | &sensor_dev_attr_pwm2.dev_attr.attr, | |
60878bcf | 2264 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
94ac7ee6 | 2265 | &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, |
5c391261 | 2266 | |
723a0aa0 JD |
2267 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, |
2268 | &sensor_dev_attr_pwm3.dev_attr.attr, | |
60878bcf | 2269 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
94ac7ee6 | 2270 | &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, |
5c391261 | 2271 | |
36c4d98a GR |
2272 | &sensor_dev_attr_pwm4_enable.dev_attr.attr, |
2273 | &sensor_dev_attr_pwm4.dev_attr.attr, | |
60878bcf | 2274 | &sensor_dev_attr_pwm4_freq.dev_attr.attr, |
36c4d98a | 2275 | &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, |
5c391261 | 2276 | |
36c4d98a GR |
2277 | &sensor_dev_attr_pwm5_enable.dev_attr.attr, |
2278 | &sensor_dev_attr_pwm5.dev_attr.attr, | |
60878bcf | 2279 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, |
36c4d98a | 2280 | &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, |
5c391261 | 2281 | |
36c4d98a GR |
2282 | &sensor_dev_attr_pwm6_enable.dev_attr.attr, |
2283 | &sensor_dev_attr_pwm6.dev_attr.attr, | |
60878bcf | 2284 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, |
36c4d98a | 2285 | &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, |
5c391261 | 2286 | |
36c4d98a | 2287 | NULL |
5c391261 | 2288 | }; |
87808be4 | 2289 | |
5c391261 GR |
2290 | static const struct attribute_group it87_group_pwm = { |
2291 | .attrs = it87_attributes_pwm, | |
2292 | .is_visible = it87_pwm_is_visible, | |
2293 | }; | |
2294 | ||
2295 | static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, | |
2296 | struct attribute *attr, int index) | |
60878bcf GR |
2297 | { |
2298 | struct device *dev = container_of(kobj, struct device, kobj); | |
2299 | struct it87_data *data = dev_get_drvdata(dev); | |
2cbb9c37 GR |
2300 | int i = index / 11; /* pwm index */ |
2301 | int a = index % 11; /* attribute index */ | |
2302 | ||
2303 | if (index >= 33) { /* pwm 4..6 */ | |
2304 | i = (index - 33) / 6 + 3; | |
2305 | a = (index - 33) % 6 + 4; | |
2306 | } | |
60878bcf | 2307 | |
48b2ae7f | 2308 | if (!(data->has_pwm & BIT(i))) |
5c391261 | 2309 | return 0; |
60878bcf | 2310 | |
2cbb9c37 GR |
2311 | if (has_newer_autopwm(data)) { |
2312 | if (a < 4) /* no auto point pwm */ | |
2313 | return 0; | |
2314 | if (a == 8) /* no auto_point4 */ | |
2315 | return 0; | |
2316 | } | |
2317 | if (has_old_autopwm(data)) { | |
2318 | if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ | |
2319 | return 0; | |
2320 | } | |
2321 | ||
60878bcf GR |
2322 | return attr->mode; |
2323 | } | |
2324 | ||
5c391261 | 2325 | static struct attribute *it87_attributes_auto_pwm[] = { |
4f3f51bc JD |
2326 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, |
2327 | &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, | |
2328 | &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, | |
2329 | &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, | |
2330 | &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, | |
2331 | &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, | |
2332 | &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, | |
2333 | &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, | |
2334 | &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2335 | &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, |
2336 | &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, | |
5c391261 | 2337 | |
2cbb9c37 | 2338 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ |
4f3f51bc JD |
2339 | &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, |
2340 | &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, | |
2341 | &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, | |
2342 | &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, | |
2343 | &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, | |
2344 | &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, | |
2345 | &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, | |
2346 | &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2347 | &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, |
2348 | &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, | |
5c391261 | 2349 | |
2cbb9c37 | 2350 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ |
4f3f51bc JD |
2351 | &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, |
2352 | &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, | |
2353 | &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, | |
2354 | &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, | |
2355 | &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, | |
2356 | &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, | |
2357 | &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, | |
2358 | &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2359 | &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, |
2360 | &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, | |
2361 | ||
2362 | &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ | |
2363 | &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, | |
2364 | &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, | |
2365 | &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, | |
2366 | &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, | |
2367 | &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, | |
2368 | ||
2369 | &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, | |
2370 | &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, | |
2371 | &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, | |
2372 | &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, | |
2373 | &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, | |
2374 | &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, | |
2375 | ||
2376 | &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, | |
2377 | &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, | |
2378 | &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, | |
2379 | &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, | |
2380 | &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, | |
2381 | &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, | |
4f3f51bc | 2382 | |
5c391261 GR |
2383 | NULL, |
2384 | }; | |
2385 | ||
2386 | static const struct attribute_group it87_group_auto_pwm = { | |
2387 | .attrs = it87_attributes_auto_pwm, | |
2388 | .is_visible = it87_auto_pwm_is_visible, | |
4f3f51bc JD |
2389 | }; |
2390 | ||
2d8672c5 | 2391 | /* SuperIO detection - will change isa_address if a chip is found */ |
3c2e3512 GR |
2392 | static int __init it87_find(int sioaddr, unsigned short *address, |
2393 | struct it87_sio_data *sio_data) | |
1da177e4 | 2394 | { |
5b0380c9 | 2395 | int err; |
b74f3fdd | 2396 | u16 chip_type; |
98dd22c3 | 2397 | const char *board_vendor, *board_name; |
f83a9cb6 | 2398 | const struct it87_devices *config; |
1da177e4 | 2399 | |
3c2e3512 | 2400 | err = superio_enter(sioaddr); |
5b0380c9 NG |
2401 | if (err) |
2402 | return err; | |
2403 | ||
2404 | err = -ENODEV; | |
3c2e3512 | 2405 | chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID); |
b74f3fdd | 2406 | |
2407 | switch (chip_type) { | |
2408 | case IT8705F_DEVID: | |
2409 | sio_data->type = it87; | |
2410 | break; | |
2411 | case IT8712F_DEVID: | |
2412 | sio_data->type = it8712; | |
2413 | break; | |
2414 | case IT8716F_DEVID: | |
2415 | case IT8726F_DEVID: | |
2416 | sio_data->type = it8716; | |
2417 | break; | |
2418 | case IT8718F_DEVID: | |
2419 | sio_data->type = it8718; | |
2420 | break; | |
b4da93e4 JMS |
2421 | case IT8720F_DEVID: |
2422 | sio_data->type = it8720; | |
2423 | break; | |
44c1bcd4 JD |
2424 | case IT8721F_DEVID: |
2425 | sio_data->type = it8721; | |
2426 | break; | |
16b5dda2 JD |
2427 | case IT8728F_DEVID: |
2428 | sio_data->type = it8728; | |
2429 | break; | |
ead80803 JM |
2430 | case IT8732F_DEVID: |
2431 | sio_data->type = it8732; | |
2432 | break; | |
e531ffc0 GR |
2433 | case IT8792E_DEVID: |
2434 | sio_data->type = it8792; | |
2435 | break; | |
b0636707 GR |
2436 | case IT8771E_DEVID: |
2437 | sio_data->type = it8771; | |
2438 | break; | |
2439 | case IT8772E_DEVID: | |
2440 | sio_data->type = it8772; | |
2441 | break; | |
7bc32d29 GR |
2442 | case IT8781F_DEVID: |
2443 | sio_data->type = it8781; | |
2444 | break; | |
0531d98b GR |
2445 | case IT8782F_DEVID: |
2446 | sio_data->type = it8782; | |
2447 | break; | |
2448 | case IT8783E_DEVID: | |
2449 | sio_data->type = it8783; | |
2450 | break; | |
a0c1424a TL |
2451 | case IT8786E_DEVID: |
2452 | sio_data->type = it8786; | |
2453 | break; | |
4ee07157 GR |
2454 | case IT8790E_DEVID: |
2455 | sio_data->type = it8790; | |
2456 | break; | |
7183ae8c | 2457 | case IT8603E_DEVID: |
574e9bd8 | 2458 | case IT8623E_DEVID: |
c145d5c6 RM |
2459 | sio_data->type = it8603; |
2460 | break; | |
3ba9d977 GR |
2461 | case IT8620E_DEVID: |
2462 | sio_data->type = it8620; | |
2463 | break; | |
8af1abae GR |
2464 | case IT8622E_DEVID: |
2465 | sio_data->type = it8622; | |
2466 | break; | |
71a9c232 GR |
2467 | case IT8628E_DEVID: |
2468 | sio_data->type = it8628; | |
2469 | break; | |
b74f3fdd | 2470 | case 0xffff: /* No device at all */ |
2471 | goto exit; | |
2472 | default: | |
a8ca1037 | 2473 | pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); |
b74f3fdd | 2474 | goto exit; |
2475 | } | |
1da177e4 | 2476 | |
3c2e3512 GR |
2477 | superio_select(sioaddr, PME); |
2478 | if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { | |
a8ca1037 | 2479 | pr_info("Device not activated, skipping\n"); |
1da177e4 LT |
2480 | goto exit; |
2481 | } | |
2482 | ||
3c2e3512 | 2483 | *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); |
1da177e4 | 2484 | if (*address == 0) { |
a8ca1037 | 2485 | pr_info("Base address not set, skipping\n"); |
1da177e4 LT |
2486 | goto exit; |
2487 | } | |
2488 | ||
2489 | err = 0; | |
3c2e3512 | 2490 | sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; |
faf392fb GR |
2491 | pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type, |
2492 | it87_devices[sio_data->type].suffix, | |
a0c1424a | 2493 | *address, sio_data->revision); |
1da177e4 | 2494 | |
f83a9cb6 GR |
2495 | config = &it87_devices[sio_data->type]; |
2496 | ||
7f5726c3 | 2497 | /* in7 (VSB or VCCH5V) is always internal on some chips */ |
f83a9cb6 | 2498 | if (has_in7_internal(config)) |
48b2ae7f | 2499 | sio_data->internal |= BIT(1); |
7f5726c3 | 2500 | |
738e5e05 | 2501 | /* in8 (Vbat) is always internal */ |
48b2ae7f | 2502 | sio_data->internal |= BIT(2); |
7f5726c3 | 2503 | |
73055405 GR |
2504 | /* in9 (AVCC3), always internal if supported */ |
2505 | if (has_avcc3(config)) | |
48b2ae7f | 2506 | sio_data->internal |= BIT(3); /* in9 is AVCC */ |
73055405 | 2507 | else |
48b2ae7f | 2508 | sio_data->skip_in |= BIT(9); |
738e5e05 | 2509 | |
638c1c07 | 2510 | if (!has_five_pwm(config)) |
48b2ae7f | 2511 | sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); |
638c1c07 GR |
2512 | else if (!has_six_pwm(config)) |
2513 | sio_data->skip_pwm |= BIT(5); | |
36c4d98a | 2514 | |
f83a9cb6 | 2515 | if (!has_vid(config)) |
895ff267 | 2516 | sio_data->skip_vid = 1; |
d9b327c3 | 2517 | |
32dd7c40 GR |
2518 | /* Read GPIO config and VID value from LDN 7 (GPIO) */ |
2519 | if (sio_data->type == it87) { | |
d9b327c3 | 2520 | /* The IT8705F has a different LD number for GPIO */ |
3c2e3512 GR |
2521 | superio_select(sioaddr, 5); |
2522 | sio_data->beep_pin = superio_inb(sioaddr, | |
2523 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
0531d98b | 2524 | } else if (sio_data->type == it8783) { |
088ce2ac | 2525 | int reg25, reg27, reg2a, reg2c, regef; |
0531d98b | 2526 | |
3c2e3512 | 2527 | superio_select(sioaddr, GPIO); |
0531d98b | 2528 | |
3c2e3512 GR |
2529 | reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
2530 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2531 | reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); | |
2532 | reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2533 | regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); | |
0531d98b | 2534 | |
0531d98b | 2535 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2536 | if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) |
2537 | sio_data->skip_fan |= BIT(2); | |
c962024e GR |
2538 | if ((reg25 & BIT(4)) || |
2539 | (!(reg2a & BIT(1)) && (regef & BIT(0)))) | |
48b2ae7f | 2540 | sio_data->skip_pwm |= BIT(2); |
0531d98b GR |
2541 | |
2542 | /* Check if fan2 is there or not */ | |
48b2ae7f GR |
2543 | if (reg27 & BIT(7)) |
2544 | sio_data->skip_fan |= BIT(1); | |
2545 | if (reg27 & BIT(3)) | |
2546 | sio_data->skip_pwm |= BIT(1); | |
0531d98b GR |
2547 | |
2548 | /* VIN5 */ | |
48b2ae7f GR |
2549 | if ((reg27 & BIT(0)) || (reg2c & BIT(2))) |
2550 | sio_data->skip_in |= BIT(5); /* No VIN5 */ | |
0531d98b GR |
2551 | |
2552 | /* VIN6 */ | |
48b2ae7f GR |
2553 | if (reg27 & BIT(1)) |
2554 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
0531d98b GR |
2555 | |
2556 | /* | |
2557 | * VIN7 | |
2558 | * Does not depend on bit 2 of Reg2C, contrary to datasheet. | |
2559 | */ | |
48b2ae7f | 2560 | if (reg27 & BIT(2)) { |
9172b5d1 GR |
2561 | /* |
2562 | * The data sheet is a bit unclear regarding the | |
2563 | * internal voltage divider for VCCH5V. It says | |
2564 | * "This bit enables and switches VIN7 (pin 91) to the | |
2565 | * internal voltage divider for VCCH5V". | |
2566 | * This is different to other chips, where the internal | |
2567 | * voltage divider would connect VIN7 to an internal | |
2568 | * voltage source. Maybe that is the case here as well. | |
2569 | * | |
2570 | * Since we don't know for sure, re-route it if that is | |
2571 | * not the case, and ask the user to report if the | |
2572 | * resulting voltage is sane. | |
2573 | */ | |
48b2ae7f GR |
2574 | if (!(reg2c & BIT(1))) { |
2575 | reg2c |= BIT(1); | |
3c2e3512 GR |
2576 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, |
2577 | reg2c); | |
9172b5d1 GR |
2578 | pr_notice("Routing internal VCCH5V to in7.\n"); |
2579 | } | |
2580 | pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); | |
2581 | pr_notice("Please report if it displays a reasonable voltage.\n"); | |
2582 | } | |
0531d98b | 2583 | |
48b2ae7f GR |
2584 | if (reg2c & BIT(0)) |
2585 | sio_data->internal |= BIT(0); | |
2586 | if (reg2c & BIT(1)) | |
2587 | sio_data->internal |= BIT(1); | |
0531d98b | 2588 | |
3c2e3512 GR |
2589 | sio_data->beep_pin = superio_inb(sioaddr, |
2590 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
c145d5c6 RM |
2591 | } else if (sio_data->type == it8603) { |
2592 | int reg27, reg29; | |
2593 | ||
3c2e3512 | 2594 | superio_select(sioaddr, GPIO); |
0531d98b | 2595 | |
3c2e3512 | 2596 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
c145d5c6 RM |
2597 | |
2598 | /* Check if fan3 is there or not */ | |
48b2ae7f GR |
2599 | if (reg27 & BIT(6)) |
2600 | sio_data->skip_pwm |= BIT(2); | |
2601 | if (reg27 & BIT(7)) | |
2602 | sio_data->skip_fan |= BIT(2); | |
c145d5c6 RM |
2603 | |
2604 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2605 | reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2606 | if (reg29 & BIT(1)) |
2607 | sio_data->skip_pwm |= BIT(1); | |
2608 | if (reg29 & BIT(2)) | |
2609 | sio_data->skip_fan |= BIT(1); | |
c145d5c6 | 2610 | |
48b2ae7f GR |
2611 | sio_data->skip_in |= BIT(5); /* No VIN5 */ |
2612 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
c145d5c6 | 2613 | |
3c2e3512 GR |
2614 | sio_data->beep_pin = superio_inb(sioaddr, |
2615 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
71a9c232 | 2616 | } else if (sio_data->type == it8620 || sio_data->type == it8628) { |
3ba9d977 GR |
2617 | int reg; |
2618 | ||
3c2e3512 | 2619 | superio_select(sioaddr, GPIO); |
3ba9d977 | 2620 | |
36c4d98a | 2621 | /* Check for pwm5 */ |
3c2e3512 | 2622 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
48b2ae7f GR |
2623 | if (reg & BIT(6)) |
2624 | sio_data->skip_pwm |= BIT(4); | |
36c4d98a | 2625 | |
3ba9d977 | 2626 | /* Check for fan4, fan5 */ |
3c2e3512 | 2627 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); |
48b2ae7f GR |
2628 | if (!(reg & BIT(5))) |
2629 | sio_data->skip_fan |= BIT(3); | |
2630 | if (!(reg & BIT(4))) | |
2631 | sio_data->skip_fan |= BIT(4); | |
3ba9d977 GR |
2632 | |
2633 | /* Check for pwm3, fan3 */ | |
3c2e3512 | 2634 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
48b2ae7f GR |
2635 | if (reg & BIT(6)) |
2636 | sio_data->skip_pwm |= BIT(2); | |
2637 | if (reg & BIT(7)) | |
2638 | sio_data->skip_fan |= BIT(2); | |
3ba9d977 | 2639 | |
36c4d98a | 2640 | /* Check for pwm4 */ |
3c2e3512 | 2641 | reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); |
d66777ca | 2642 | if (reg & BIT(2)) |
48b2ae7f | 2643 | sio_data->skip_pwm |= BIT(3); |
36c4d98a | 2644 | |
3ba9d977 | 2645 | /* Check for pwm2, fan2 */ |
3c2e3512 | 2646 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2647 | if (reg & BIT(1)) |
2648 | sio_data->skip_pwm |= BIT(1); | |
2649 | if (reg & BIT(2)) | |
2650 | sio_data->skip_fan |= BIT(1); | |
36c4d98a | 2651 | /* Check for pwm6, fan6 */ |
48b2ae7f GR |
2652 | if (!(reg & BIT(7))) { |
2653 | sio_data->skip_pwm |= BIT(5); | |
2654 | sio_data->skip_fan |= BIT(5); | |
36c4d98a | 2655 | } |
3ba9d977 | 2656 | |
638c1c07 GR |
2657 | /* Check if AVCC is on VIN3 */ |
2658 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2659 | if (reg & BIT(0)) | |
2660 | sio_data->internal |= BIT(0); | |
2661 | else | |
2662 | sio_data->skip_in |= BIT(9); | |
2663 | ||
2664 | sio_data->beep_pin = superio_inb(sioaddr, | |
2665 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
2666 | } else if (sio_data->type == it8622) { | |
2667 | int reg; | |
2668 | ||
2669 | superio_select(sioaddr, GPIO); | |
2670 | ||
2671 | /* Check for pwm4, fan4 */ | |
2672 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); | |
2673 | if (reg & BIT(6)) | |
2674 | sio_data->skip_fan |= BIT(3); | |
2675 | if (reg & BIT(5)) | |
2676 | sio_data->skip_pwm |= BIT(3); | |
2677 | ||
2678 | /* Check for pwm3, fan3, pwm5, fan5 */ | |
2679 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2680 | if (reg & BIT(6)) | |
2681 | sio_data->skip_pwm |= BIT(2); | |
2682 | if (reg & BIT(7)) | |
2683 | sio_data->skip_fan |= BIT(2); | |
2684 | if (reg & BIT(3)) | |
2685 | sio_data->skip_pwm |= BIT(4); | |
2686 | if (reg & BIT(1)) | |
2687 | sio_data->skip_fan |= BIT(4); | |
2688 | ||
2689 | /* Check for pwm2, fan2 */ | |
2690 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); | |
2691 | if (reg & BIT(1)) | |
2692 | sio_data->skip_pwm |= BIT(1); | |
2693 | if (reg & BIT(2)) | |
2694 | sio_data->skip_fan |= BIT(1); | |
2695 | ||
2696 | /* Check for AVCC */ | |
2697 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2698 | if (!(reg & BIT(0))) | |
2699 | sio_data->skip_in |= BIT(9); | |
2700 | ||
3c2e3512 GR |
2701 | sio_data->beep_pin = superio_inb(sioaddr, |
2702 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
895ff267 | 2703 | } else { |
87673dd7 | 2704 | int reg; |
9172b5d1 | 2705 | bool uart6; |
87673dd7 | 2706 | |
3c2e3512 | 2707 | superio_select(sioaddr, GPIO); |
44c1bcd4 | 2708 | |
a0df926d GR |
2709 | /* Check for fan4, fan5 */ |
2710 | if (has_five_fans(config)) { | |
2711 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); | |
2712 | switch (sio_data->type) { | |
2713 | case it8718: | |
2714 | if (reg & BIT(5)) | |
2715 | sio_data->skip_fan |= BIT(3); | |
2716 | if (reg & BIT(4)) | |
2717 | sio_data->skip_fan |= BIT(4); | |
2718 | break; | |
2719 | case it8720: | |
2720 | case it8721: | |
2721 | case it8728: | |
2722 | if (!(reg & BIT(5))) | |
2723 | sio_data->skip_fan |= BIT(3); | |
2724 | if (!(reg & BIT(4))) | |
2725 | sio_data->skip_fan |= BIT(4); | |
2726 | break; | |
2727 | default: | |
2728 | break; | |
2729 | } | |
2730 | } | |
2731 | ||
3c2e3512 | 2732 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
32dd7c40 | 2733 | if (!sio_data->skip_vid) { |
44c1bcd4 JD |
2734 | /* We need at least 4 VID pins */ |
2735 | if (reg & 0x0f) { | |
a8ca1037 | 2736 | pr_info("VID is disabled (pins used for GPIO)\n"); |
44c1bcd4 JD |
2737 | sio_data->skip_vid = 1; |
2738 | } | |
895ff267 JD |
2739 | } |
2740 | ||
591ec650 | 2741 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2742 | if (reg & BIT(6)) |
2743 | sio_data->skip_pwm |= BIT(2); | |
2744 | if (reg & BIT(7)) | |
2745 | sio_data->skip_fan |= BIT(2); | |
591ec650 JD |
2746 | |
2747 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2748 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2749 | if (reg & BIT(1)) |
2750 | sio_data->skip_pwm |= BIT(1); | |
2751 | if (reg & BIT(2)) | |
2752 | sio_data->skip_fan |= BIT(1); | |
591ec650 | 2753 | |
c962024e GR |
2754 | if ((sio_data->type == it8718 || sio_data->type == it8720) && |
2755 | !(sio_data->skip_vid)) | |
3c2e3512 GR |
2756 | sio_data->vid_value = superio_inb(sioaddr, |
2757 | IT87_SIO_VID_REG); | |
87673dd7 | 2758 | |
3c2e3512 | 2759 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); |
9172b5d1 | 2760 | |
48b2ae7f | 2761 | uart6 = sio_data->type == it8782 && (reg & BIT(2)); |
9172b5d1 | 2762 | |
436cad2a JD |
2763 | /* |
2764 | * The IT8720F has no VIN7 pin, so VCCH should always be | |
2765 | * routed internally to VIN7 with an internal divider. | |
2766 | * Curiously, there still is a configuration bit to control | |
2767 | * this, which means it can be set incorrectly. And even | |
2768 | * more curiously, many boards out there are improperly | |
2769 | * configured, even though the IT8720F datasheet claims | |
2770 | * that the internal routing of VCCH to VIN7 is the default | |
2771 | * setting. So we force the internal routing in this case. | |
0531d98b GR |
2772 | * |
2773 | * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. | |
9172b5d1 GR |
2774 | * If UART6 is enabled, re-route VIN7 to the internal divider |
2775 | * if that is not already the case. | |
436cad2a | 2776 | */ |
48b2ae7f GR |
2777 | if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { |
2778 | reg |= BIT(1); | |
3c2e3512 | 2779 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); |
a8ca1037 | 2780 | pr_notice("Routing internal VCCH to in7\n"); |
436cad2a | 2781 | } |
48b2ae7f GR |
2782 | if (reg & BIT(0)) |
2783 | sio_data->internal |= BIT(0); | |
2784 | if (reg & BIT(1)) | |
2785 | sio_data->internal |= BIT(1); | |
d9b327c3 | 2786 | |
9172b5d1 GR |
2787 | /* |
2788 | * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. | |
2789 | * While VIN7 can be routed to the internal voltage divider, | |
2790 | * VIN5 and VIN6 are not available if UART6 is enabled. | |
4573acbc GR |
2791 | * |
2792 | * Also, temp3 is not available if UART6 is enabled and TEMPIN3 | |
2793 | * is the temperature source. Since we can not read the | |
2794 | * temperature source here, skip_temp is preliminary. | |
9172b5d1 | 2795 | */ |
4573acbc | 2796 | if (uart6) { |
48b2ae7f GR |
2797 | sio_data->skip_in |= BIT(5) | BIT(6); |
2798 | sio_data->skip_temp |= BIT(2); | |
4573acbc | 2799 | } |
9172b5d1 | 2800 | |
3c2e3512 GR |
2801 | sio_data->beep_pin = superio_inb(sioaddr, |
2802 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
87673dd7 | 2803 | } |
d9b327c3 | 2804 | if (sio_data->beep_pin) |
a8ca1037 | 2805 | pr_info("Beeping is supported\n"); |
87673dd7 | 2806 | |
98dd22c3 JD |
2807 | /* Disable specific features based on DMI strings */ |
2808 | board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); | |
2809 | board_name = dmi_get_system_info(DMI_BOARD_NAME); | |
2810 | if (board_vendor && board_name) { | |
c962024e GR |
2811 | if (strcmp(board_vendor, "nVIDIA") == 0 && |
2812 | strcmp(board_name, "FN68PT") == 0) { | |
4a0d71cf GR |
2813 | /* |
2814 | * On the Shuttle SN68PT, FAN_CTL2 is apparently not | |
2815 | * connected to a fan, but to something else. One user | |
2816 | * has reported instant system power-off when changing | |
2817 | * the PWM2 duty cycle, so we disable it. | |
2818 | * I use the board name string as the trigger in case | |
2819 | * the same board is ever used in other systems. | |
2820 | */ | |
a8ca1037 | 2821 | pr_info("Disabling pwm2 due to hardware constraints\n"); |
48b2ae7f | 2822 | sio_data->skip_pwm = BIT(1); |
98dd22c3 JD |
2823 | } |
2824 | } | |
2825 | ||
1da177e4 | 2826 | exit: |
3c2e3512 | 2827 | superio_exit(sioaddr); |
1da177e4 LT |
2828 | return err; |
2829 | } | |
2830 | ||
c1e7a4ca GR |
2831 | /* Called when we have found a new IT87. */ |
2832 | static void it87_init_device(struct platform_device *pdev) | |
1da177e4 | 2833 | { |
c1e7a4ca GR |
2834 | struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); |
2835 | struct it87_data *data = platform_get_drvdata(pdev); | |
2836 | int tmp, i; | |
2837 | u8 mask; | |
b74f3fdd | 2838 | |
c1e7a4ca GR |
2839 | /* |
2840 | * For each PWM channel: | |
2841 | * - If it is in automatic mode, setting to manual mode should set | |
2842 | * the fan to full speed by default. | |
2843 | * - If it is in manual mode, we need a mapping to temperature | |
2844 | * channels to use when later setting to automatic mode later. | |
2845 | * Use a 1:1 mapping by default (we are clueless.) | |
2846 | * In both cases, the value can (and should) be changed by the user | |
2847 | * prior to switching to a different mode. | |
2848 | * Note that this is no longer needed for the IT8721F and later, as | |
2849 | * these have separate registers for the temperature mapping and the | |
2850 | * manual duty cycle. | |
2851 | */ | |
2310048d | 2852 | for (i = 0; i < NUM_AUTO_PWM; i++) { |
c1e7a4ca GR |
2853 | data->pwm_temp_map[i] = i; |
2854 | data->pwm_duty[i] = 0x7f; /* Full speed */ | |
2855 | data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ | |
8e9afcbb | 2856 | } |
1da177e4 | 2857 | |
483db43e | 2858 | /* |
c1e7a4ca GR |
2859 | * Some chips seem to have default value 0xff for all limit |
2860 | * registers. For low voltage limits it makes no sense and triggers | |
2861 | * alarms, so change to 0 instead. For high temperature limits, it | |
2862 | * means -1 degree C, which surprisingly doesn't trigger an alarm, | |
2863 | * but is still confusing, so change to 127 degrees C. | |
483db43e | 2864 | */ |
2310048d | 2865 | for (i = 0; i < NUM_VIN_LIMIT; i++) { |
c1e7a4ca GR |
2866 | tmp = it87_read_value(data, IT87_REG_VIN_MIN(i)); |
2867 | if (tmp == 0xff) | |
2868 | it87_write_value(data, IT87_REG_VIN_MIN(i), 0); | |
2869 | } | |
2310048d | 2870 | for (i = 0; i < NUM_TEMP_LIMIT; i++) { |
c1e7a4ca GR |
2871 | tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); |
2872 | if (tmp == 0xff) | |
2873 | it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); | |
483db43e | 2874 | } |
1da177e4 | 2875 | |
c1e7a4ca GR |
2876 | /* |
2877 | * Temperature channels are not forcibly enabled, as they can be | |
2878 | * set to two different sensor types and we can't guess which one | |
2879 | * is correct for a given system. These channels can be enabled at | |
2880 | * run-time through the temp{1-3}_type sysfs accessors if needed. | |
2881 | */ | |
1da177e4 | 2882 | |
c1e7a4ca GR |
2883 | /* Check if voltage monitors are reset manually or by some reason */ |
2884 | tmp = it87_read_value(data, IT87_REG_VIN_ENABLE); | |
2885 | if ((tmp & 0xff) == 0) { | |
2886 | /* Enable all voltage monitors */ | |
2887 | it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); | |
2888 | } | |
2889 | ||
2890 | /* Check if tachometers are reset manually or by some reason */ | |
2891 | mask = 0x70 & ~(sio_data->skip_fan << 4); | |
2892 | data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); | |
2893 | if ((data->fan_main_ctrl & mask) == 0) { | |
2894 | /* Enable all fan tachometers */ | |
2895 | data->fan_main_ctrl |= mask; | |
2896 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
2897 | data->fan_main_ctrl); | |
2898 | } | |
2899 | data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; | |
2900 | ||
2901 | tmp = it87_read_value(data, IT87_REG_FAN_16BIT); | |
2902 | ||
2903 | /* Set tachometers to 16-bit mode if needed */ | |
2904 | if (has_fan16_config(data)) { | |
2905 | if (~tmp & 0x07 & data->has_fan) { | |
2906 | dev_dbg(&pdev->dev, | |
2907 | "Setting fan1-3 to 16-bit mode\n"); | |
2908 | it87_write_value(data, IT87_REG_FAN_16BIT, | |
2909 | tmp | 0x07); | |
2910 | } | |
2911 | } | |
2912 | ||
2913 | /* Check for additional fans */ | |
2914 | if (has_five_fans(data)) { | |
48b2ae7f GR |
2915 | if (tmp & BIT(4)) |
2916 | data->has_fan |= BIT(3); /* fan4 enabled */ | |
2917 | if (tmp & BIT(5)) | |
2918 | data->has_fan |= BIT(4); /* fan5 enabled */ | |
2919 | if (has_six_fans(data) && (tmp & BIT(2))) | |
2920 | data->has_fan |= BIT(5); /* fan6 enabled */ | |
c1e7a4ca GR |
2921 | } |
2922 | ||
2923 | /* Fan input pins may be used for alternative functions */ | |
2924 | data->has_fan &= ~sio_data->skip_fan; | |
2925 | ||
2926 | /* Check if pwm5, pwm6 are enabled */ | |
2927 | if (has_six_pwm(data)) { | |
2928 | /* The following code may be IT8620E specific */ | |
2929 | tmp = it87_read_value(data, IT87_REG_FAN_DIV); | |
2930 | if ((tmp & 0xc0) == 0xc0) | |
48b2ae7f GR |
2931 | sio_data->skip_pwm |= BIT(4); |
2932 | if (!(tmp & BIT(3))) | |
2933 | sio_data->skip_pwm |= BIT(5); | |
c1e7a4ca GR |
2934 | } |
2935 | ||
2936 | /* Start monitoring */ | |
2937 | it87_write_value(data, IT87_REG_CONFIG, | |
2938 | (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) | |
2939 | | (update_vbat ? 0x41 : 0x01)); | |
2940 | } | |
2941 | ||
2942 | /* Return 1 if and only if the PWM interface is safe to use */ | |
2943 | static int it87_check_pwm(struct device *dev) | |
2944 | { | |
2945 | struct it87_data *data = dev_get_drvdata(dev); | |
2946 | /* | |
2947 | * Some BIOSes fail to correctly configure the IT87 fans. All fans off | |
2948 | * and polarity set to active low is sign that this is the case so we | |
2949 | * disable pwm control to protect the user. | |
2950 | */ | |
2951 | int tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
2952 | ||
2953 | if ((tmp & 0x87) == 0) { | |
2954 | if (fix_pwm_polarity) { | |
2955 | /* | |
2956 | * The user asks us to attempt a chip reconfiguration. | |
2957 | * This means switching to active high polarity and | |
2958 | * inverting all fan speed values. | |
2959 | */ | |
2960 | int i; | |
2961 | u8 pwm[3]; | |
2962 | ||
2310048d | 2963 | for (i = 0; i < ARRAY_SIZE(pwm); i++) |
c1e7a4ca GR |
2964 | pwm[i] = it87_read_value(data, |
2965 | IT87_REG_PWM[i]); | |
2966 | ||
2967 | /* | |
2968 | * If any fan is in automatic pwm mode, the polarity | |
2969 | * might be correct, as suspicious as it seems, so we | |
2970 | * better don't change anything (but still disable the | |
2971 | * PWM interface). | |
2972 | */ | |
2973 | if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { | |
2974 | dev_info(dev, | |
2975 | "Reconfiguring PWM to active high polarity\n"); | |
2976 | it87_write_value(data, IT87_REG_FAN_CTL, | |
2977 | tmp | 0x87); | |
2978 | for (i = 0; i < 3; i++) | |
2979 | it87_write_value(data, | |
2980 | IT87_REG_PWM[i], | |
2981 | 0x7f & ~pwm[i]); | |
2982 | return 1; | |
2983 | } | |
2984 | ||
2985 | dev_info(dev, | |
2986 | "PWM configuration is too broken to be fixed\n"); | |
2987 | } | |
2988 | ||
2989 | dev_info(dev, | |
2990 | "Detected broken BIOS defaults, disabling PWM interface\n"); | |
2991 | return 0; | |
2992 | } else if (fix_pwm_polarity) { | |
2993 | dev_info(dev, | |
2994 | "PWM configuration looks sane, won't touch\n"); | |
2995 | } | |
2996 | ||
2997 | return 1; | |
2998 | } | |
2999 | ||
3000 | static int it87_probe(struct platform_device *pdev) | |
3001 | { | |
3002 | struct it87_data *data; | |
3003 | struct resource *res; | |
3004 | struct device *dev = &pdev->dev; | |
3005 | struct it87_sio_data *sio_data = dev_get_platdata(dev); | |
c1e7a4ca | 3006 | int enable_pwm_interface; |
8638d0af | 3007 | struct device *hwmon_dev; |
c1e7a4ca GR |
3008 | |
3009 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
3010 | if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, | |
3011 | DRVNAME)) { | |
3012 | dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", | |
3013 | (unsigned long)res->start, | |
3014 | (unsigned long)(res->start + IT87_EC_EXTENT - 1)); | |
3015 | return -EBUSY; | |
3016 | } | |
3017 | ||
3018 | data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); | |
3019 | if (!data) | |
3020 | return -ENOMEM; | |
3021 | ||
3022 | data->addr = res->start; | |
3023 | data->type = sio_data->type; | |
3024 | data->features = it87_devices[sio_data->type].features; | |
3025 | data->peci_mask = it87_devices[sio_data->type].peci_mask; | |
3026 | data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; | |
c1e7a4ca GR |
3027 | /* |
3028 | * IT8705F Datasheet 0.4.1, 3h == Version G. | |
3029 | * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. | |
3030 | * These are the first revisions with 16-bit tachometer support. | |
3031 | */ | |
3032 | switch (data->type) { | |
3033 | case it87: | |
3034 | if (sio_data->revision >= 0x03) { | |
3035 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3036 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; | |
3037 | } | |
3038 | break; | |
3039 | case it8712: | |
3040 | if (sio_data->revision >= 0x08) { | |
3041 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3042 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | | |
3043 | FEAT_FIVE_FANS; | |
3044 | } | |
3045 | break; | |
3046 | default: | |
3047 | break; | |
3048 | } | |
3049 | ||
3050 | /* Now, we do the remaining detection. */ | |
c962024e GR |
3051 | if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || |
3052 | it87_read_value(data, IT87_REG_CHIPID) != 0x90) | |
c1e7a4ca GR |
3053 | return -ENODEV; |
3054 | ||
3055 | platform_set_drvdata(pdev, data); | |
1da177e4 | 3056 | |
9a61bf63 | 3057 | mutex_init(&data->update_lock); |
1da177e4 | 3058 | |
1da177e4 | 3059 | /* Check PWM configuration */ |
b74f3fdd | 3060 | enable_pwm_interface = it87_check_pwm(dev); |
1da177e4 | 3061 | |
44c1bcd4 | 3062 | /* Starting with IT8721F, we handle scaling of internal voltages */ |
16b5dda2 | 3063 | if (has_12mv_adc(data)) { |
48b2ae7f GR |
3064 | if (sio_data->internal & BIT(0)) |
3065 | data->in_scaled |= BIT(3); /* in3 is AVCC */ | |
3066 | if (sio_data->internal & BIT(1)) | |
3067 | data->in_scaled |= BIT(7); /* in7 is VSB */ | |
3068 | if (sio_data->internal & BIT(2)) | |
3069 | data->in_scaled |= BIT(8); /* in8 is Vbat */ | |
3070 | if (sio_data->internal & BIT(3)) | |
3071 | data->in_scaled |= BIT(9); /* in9 is AVCC */ | |
7bc32d29 GR |
3072 | } else if (sio_data->type == it8781 || sio_data->type == it8782 || |
3073 | sio_data->type == it8783) { | |
48b2ae7f GR |
3074 | if (sio_data->internal & BIT(0)) |
3075 | data->in_scaled |= BIT(3); /* in3 is VCC5V */ | |
3076 | if (sio_data->internal & BIT(1)) | |
3077 | data->in_scaled |= BIT(7); /* in7 is VCCH5V */ | |
44c1bcd4 JD |
3078 | } |
3079 | ||
4573acbc | 3080 | data->has_temp = 0x07; |
48b2ae7f | 3081 | if (sio_data->skip_temp & BIT(2)) { |
c962024e GR |
3082 | if (sio_data->type == it8782 && |
3083 | !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) | |
48b2ae7f | 3084 | data->has_temp &= ~BIT(2); |
4573acbc GR |
3085 | } |
3086 | ||
d3766848 | 3087 | data->in_internal = sio_data->internal; |
52929715 GR |
3088 | data->has_in = 0x3ff & ~sio_data->skip_in; |
3089 | ||
cc18da79 GR |
3090 | if (has_six_temp(data)) { |
3091 | u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); | |
3092 | ||
f838aa26 | 3093 | /* Check for additional temperature sensors */ |
cc18da79 | 3094 | if ((reg & 0x03) >= 0x02) |
48b2ae7f | 3095 | data->has_temp |= BIT(3); |
cc18da79 | 3096 | if (((reg >> 2) & 0x03) >= 0x02) |
48b2ae7f | 3097 | data->has_temp |= BIT(4); |
cc18da79 | 3098 | if (((reg >> 4) & 0x03) >= 0x02) |
48b2ae7f | 3099 | data->has_temp |= BIT(5); |
f838aa26 GR |
3100 | |
3101 | /* Check for additional voltage sensors */ | |
3102 | if ((reg & 0x03) == 0x01) | |
48b2ae7f | 3103 | data->has_in |= BIT(10); |
f838aa26 | 3104 | if (((reg >> 2) & 0x03) == 0x01) |
48b2ae7f | 3105 | data->has_in |= BIT(11); |
f838aa26 | 3106 | if (((reg >> 4) & 0x03) == 0x01) |
48b2ae7f | 3107 | data->has_in |= BIT(12); |
cc18da79 GR |
3108 | } |
3109 | ||
52929715 GR |
3110 | data->has_beep = !!sio_data->beep_pin; |
3111 | ||
1da177e4 | 3112 | /* Initialize the IT87 chip */ |
b74f3fdd | 3113 | it87_init_device(pdev); |
1da177e4 | 3114 | |
d3766848 GR |
3115 | if (!sio_data->skip_vid) { |
3116 | data->has_vid = true; | |
3117 | data->vrm = vid_which_vrm(); | |
3118 | /* VID reading from Super-I/O config space if available */ | |
3119 | data->vid = sio_data->vid_value; | |
3120 | } | |
3121 | ||
8638d0af GR |
3122 | /* Prepare for sysfs hooks */ |
3123 | data->groups[0] = &it87_group; | |
3124 | data->groups[1] = &it87_group_in; | |
3125 | data->groups[2] = &it87_group_temp; | |
3126 | data->groups[3] = &it87_group_fan; | |
17d648bf | 3127 | |
1da177e4 | 3128 | if (enable_pwm_interface) { |
48b2ae7f | 3129 | data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; |
5c391261 | 3130 | data->has_pwm &= ~sio_data->skip_pwm; |
4f3f51bc | 3131 | |
8638d0af | 3132 | data->groups[4] = &it87_group_pwm; |
2cbb9c37 | 3133 | if (has_old_autopwm(data) || has_newer_autopwm(data)) |
8638d0af | 3134 | data->groups[5] = &it87_group_auto_pwm; |
1da177e4 LT |
3135 | } |
3136 | ||
8638d0af GR |
3137 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, |
3138 | it87_devices[sio_data->type].name, | |
3139 | data, data->groups); | |
3140 | return PTR_ERR_OR_ZERO(hwmon_dev); | |
1da177e4 LT |
3141 | } |
3142 | ||
c1e7a4ca GR |
3143 | static struct platform_driver it87_driver = { |
3144 | .driver = { | |
3145 | .name = DRVNAME, | |
3146 | }, | |
3147 | .probe = it87_probe, | |
c1e7a4ca | 3148 | }; |
1da177e4 | 3149 | |
e84bd953 | 3150 | static int __init it87_device_add(int index, unsigned short address, |
b74f3fdd | 3151 | const struct it87_sio_data *sio_data) |
3152 | { | |
8e50e3c3 | 3153 | struct platform_device *pdev; |
b74f3fdd | 3154 | struct resource res = { |
87b4b663 BH |
3155 | .start = address + IT87_EC_OFFSET, |
3156 | .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, | |
b74f3fdd | 3157 | .name = DRVNAME, |
3158 | .flags = IORESOURCE_IO, | |
3159 | }; | |
3160 | int err; | |
3161 | ||
b9acb64a JD |
3162 | err = acpi_check_resource_conflict(&res); |
3163 | if (err) | |
5cae84a5 | 3164 | return err; |
b9acb64a | 3165 | |
b74f3fdd | 3166 | pdev = platform_device_alloc(DRVNAME, address); |
5cae84a5 GR |
3167 | if (!pdev) |
3168 | return -ENOMEM; | |
b74f3fdd | 3169 | |
3170 | err = platform_device_add_resources(pdev, &res, 1); | |
3171 | if (err) { | |
a8ca1037 | 3172 | pr_err("Device resource addition failed (%d)\n", err); |
b74f3fdd | 3173 | goto exit_device_put; |
3174 | } | |
3175 | ||
3176 | err = platform_device_add_data(pdev, sio_data, | |
3177 | sizeof(struct it87_sio_data)); | |
3178 | if (err) { | |
a8ca1037 | 3179 | pr_err("Platform data allocation failed\n"); |
b74f3fdd | 3180 | goto exit_device_put; |
3181 | } | |
3182 | ||
3183 | err = platform_device_add(pdev); | |
3184 | if (err) { | |
a8ca1037 | 3185 | pr_err("Device addition failed (%d)\n", err); |
b74f3fdd | 3186 | goto exit_device_put; |
3187 | } | |
3188 | ||
e84bd953 | 3189 | it87_pdev[index] = pdev; |
b74f3fdd | 3190 | return 0; |
3191 | ||
3192 | exit_device_put: | |
3193 | platform_device_put(pdev); | |
b74f3fdd | 3194 | return err; |
3195 | } | |
3196 | ||
1da177e4 LT |
3197 | static int __init sm_it87_init(void) |
3198 | { | |
e84bd953 | 3199 | int sioaddr[2] = { REG_2E, REG_4E }; |
b74f3fdd | 3200 | struct it87_sio_data sio_data; |
8358378b | 3201 | unsigned short isa_address[2]; |
e84bd953 GR |
3202 | bool found = false; |
3203 | int i, err; | |
b74f3fdd | 3204 | |
b74f3fdd | 3205 | err = platform_driver_register(&it87_driver); |
3206 | if (err) | |
3207 | return err; | |
fde09509 | 3208 | |
e84bd953 GR |
3209 | for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { |
3210 | memset(&sio_data, 0, sizeof(struct it87_sio_data)); | |
8358378b GR |
3211 | isa_address[i] = 0; |
3212 | err = it87_find(sioaddr[i], &isa_address[i], &sio_data); | |
3213 | if (err || isa_address[i] == 0) | |
e84bd953 | 3214 | continue; |
8358378b GR |
3215 | /* |
3216 | * Don't register second chip if its ISA address matches | |
3217 | * the first chip's ISA address. | |
3218 | */ | |
3219 | if (i && isa_address[i] == isa_address[0]) | |
3220 | break; | |
e84bd953 | 3221 | |
8358378b | 3222 | err = it87_device_add(i, isa_address[i], &sio_data); |
e84bd953 GR |
3223 | if (err) |
3224 | goto exit_dev_unregister; | |
8358378b | 3225 | |
e84bd953 | 3226 | found = true; |
8358378b GR |
3227 | |
3228 | /* | |
3229 | * IT8705F may respond on both SIO addresses. | |
3230 | * Stop probing after finding one. | |
3231 | */ | |
3232 | if (sio_data.type == it87) | |
3233 | break; | |
b74f3fdd | 3234 | } |
3235 | ||
e84bd953 GR |
3236 | if (!found) { |
3237 | err = -ENODEV; | |
3238 | goto exit_unregister; | |
3239 | } | |
b74f3fdd | 3240 | return 0; |
e84bd953 GR |
3241 | |
3242 | exit_dev_unregister: | |
3243 | /* NULL check handled by platform_device_unregister */ | |
3244 | platform_device_unregister(it87_pdev[0]); | |
3245 | exit_unregister: | |
3246 | platform_driver_unregister(&it87_driver); | |
3247 | return err; | |
1da177e4 LT |
3248 | } |
3249 | ||
3250 | static void __exit sm_it87_exit(void) | |
3251 | { | |
e84bd953 GR |
3252 | /* NULL check handled by platform_device_unregister */ |
3253 | platform_device_unregister(it87_pdev[1]); | |
3254 | platform_device_unregister(it87_pdev[0]); | |
b74f3fdd | 3255 | platform_driver_unregister(&it87_driver); |
1da177e4 LT |
3256 | } |
3257 | ||
7c81c60f | 3258 | MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); |
44c1bcd4 | 3259 | MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); |
1da177e4 LT |
3260 | module_param(update_vbat, bool, 0); |
3261 | MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); | |
3262 | module_param(fix_pwm_polarity, bool, 0); | |
5f2dc798 JD |
3263 | MODULE_PARM_DESC(fix_pwm_polarity, |
3264 | "Force PWM polarity to active high (DANGEROUS)"); | |
1da177e4 LT |
3265 | MODULE_LICENSE("GPL"); |
3266 | ||
3267 | module_init(sm_it87_init); | |
3268 | module_exit(sm_it87_exit); |