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hwmon: (it87) Fix pwm_temp_map for system with 6 pwm channels
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
3ba9d977 14 * IT8620E Super I/O chip w/LPC interface
574e9bd8 15 * IT8623E Super I/O chip w/LPC interface
c145d5c6 16 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 17 * IT8712F Super I/O chip w/LPC interface
18 * IT8716F Super I/O chip w/LPC interface
19 * IT8718F Super I/O chip w/LPC interface
20 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8721F Super I/O chip w/LPC interface
5f2dc798 22 * IT8726F Super I/O chip w/LPC interface
16b5dda2 23 * IT8728F Super I/O chip w/LPC interface
ead80803 24 * IT8732F Super I/O chip w/LPC interface
44c1bcd4 25 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 26 * IT8771E Super I/O chip w/LPC interface
27 * IT8772E Super I/O chip w/LPC interface
7bc32d29 28 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 29 * IT8782F Super I/O chip w/LPC interface
30 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 31 * IT8786E Super I/O chip w/LPC interface
4ee07157 32 * IT8790E Super I/O chip w/LPC interface
5f2dc798
JD		 33 * Sis950 A clone of the IT8705F
34 *
35 * Copyright (C) 2001 Chris Gauthron
7c81c60f 36 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License as published by
40 * the Free Software Foundation; either version 2 of the License, or
41 * (at your option) any later version.
42 *
43 * This program is distributed in the hope that it will be useful,
44 * but WITHOUT ANY WARRANTY; without even the implied warranty of
45 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 * GNU General Public License for more details.
5f2dc798 47 */
1da177e4 48
a8ca1037
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
48b2ae7f 51#include <linux/bitops.h>
1da177e4
LT		 52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
b74f3fdd 56#include <linux/platform_device.h>
943b0830 57#include <linux/hwmon.h>
303760b4
JD		 58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
943b0830 60#include <linux/err.h>
9a61bf63 61#include <linux/mutex.h>
87808be4 62#include <linux/sysfs.h>
98dd22c3
JD		 63#include <linux/string.h>
64#include <linux/dmi.h>
b9acb64a 65#include <linux/acpi.h>
6055fae8 66#include <linux/io.h>
1da177e4 67
b74f3fdd 68#define DRVNAME "it87"
1da177e4 69
ead80803
JM		 70enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
71 it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
72 it8620 };
1da177e4 73
67b671bc
JD		 74static unsigned short force_id;
75module_param(force_id, ushort, 0);
76MODULE_PARM_DESC(force_id, "Override the detected device ID");
77
e84bd953 78static struct platform_device *it87_pdev[2];
b74f3fdd 79
3c2e3512 80#define REG_2E 0x2e /* The register to read/write */
e84bd953 81#define REG_4E 0x4e /* Secondary register to read/write */
3c2e3512 82
1da177e4 83#define DEV 0x07 /* Register: Logical device select */
1da177e4 84#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 85
86/* The device with the IT8718F/IT8720F VID value in it */
87#define GPIO 0x07
88
1da177e4
LT		 89#define DEVID 0x20 /* Register: Device ID */
90#define DEVREV 0x22 /* Register: Device Revision */
91
3c2e3512 92static inline int superio_inb(int ioreg, int reg)
1da177e4 93{
3c2e3512
GR		 94 outb(reg, ioreg);
95 return inb(ioreg + 1);
1da177e4
LT		 96}
97
3c2e3512 98static inline void superio_outb(int ioreg, int reg, int val)
436cad2a 99{
3c2e3512
GR		 100 outb(reg, ioreg);
101 outb(val, ioreg + 1);
436cad2a
JD		 102}
103
3c2e3512 104static int superio_inw(int ioreg, int reg)
1da177e4
LT		 105{
106 int val;
c962024e 107
3c2e3512
GR		 108 outb(reg++, ioreg);
109 val = inb(ioreg + 1) << 8;
110 outb(reg, ioreg);
111 val |= inb(ioreg + 1);
1da177e4
LT		 112 return val;
113}
114
3c2e3512 115static inline void superio_select(int ioreg, int ldn)
1da177e4 116{
3c2e3512
GR		 117 outb(DEV, ioreg);
118 outb(ldn, ioreg + 1);
1da177e4
LT		 119}
120
3c2e3512 121static inline int superio_enter(int ioreg)
1da177e4 122{
5b0380c9 123 /*
3c2e3512 124 * Try to reserve ioreg and ioreg + 1 for exclusive access.
5b0380c9 125 */
3c2e3512 126 if (!request_muxed_region(ioreg, 2, DRVNAME))
5b0380c9
NG		 127 return -EBUSY;
128
3c2e3512
GR		 129 outb(0x87, ioreg);
130 outb(0x01, ioreg);
131 outb(0x55, ioreg);
e84bd953 132 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
5b0380c9 133 return 0;
1da177e4
LT		 134}
135
3c2e3512 136static inline void superio_exit(int ioreg)
1da177e4 137{
3c2e3512
GR		 138 outb(0x02, ioreg);
139 outb(0x02, ioreg + 1);
140 release_region(ioreg, 2);
1da177e4
LT		 141}
142
87673dd7 143/* Logical device 4 registers */
1da177e4
LT		 144#define IT8712F_DEVID 0x8712
145#define IT8705F_DEVID 0x8705
17d648bf 146#define IT8716F_DEVID 0x8716
87673dd7 147#define IT8718F_DEVID 0x8718
b4da93e4 148#define IT8720F_DEVID 0x8720
44c1bcd4 149#define IT8721F_DEVID 0x8721
08a8f6e9 150#define IT8726F_DEVID 0x8726
16b5dda2 151#define IT8728F_DEVID 0x8728
ead80803 152#define IT8732F_DEVID 0x8732
b0636707
GR		 153#define IT8771E_DEVID 0x8771
154#define IT8772E_DEVID 0x8772
7bc32d29 155#define IT8781F_DEVID 0x8781
0531d98b
GR		 156#define IT8782F_DEVID 0x8782
157#define IT8783E_DEVID 0x8783
a0c1424a 158#define IT8786E_DEVID 0x8786
4ee07157 159#define IT8790E_DEVID 0x8790
7183ae8c 160#define IT8603E_DEVID 0x8603
3ba9d977 161#define IT8620E_DEVID 0x8620
574e9bd8 162#define IT8623E_DEVID 0x8623
1da177e4
LT		 163#define IT87_ACT_REG 0x30
164#define IT87_BASE_REG 0x60
165
87673dd7 166/* Logical device 7 registers (IT8712F and later) */
0531d98b 167#define IT87_SIO_GPIO1_REG 0x25
3ba9d977 168#define IT87_SIO_GPIO2_REG 0x26
895ff267 169#define IT87_SIO_GPIO3_REG 0x27
36c4d98a 170#define IT87_SIO_GPIO4_REG 0x28
591ec650 171#define IT87_SIO_GPIO5_REG 0x29
0531d98b 172#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 173#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 174#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 175#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 176#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 177
1da177e4 178/* Update battery voltage after every reading if true */
90ab5ee9 179static bool update_vbat;
1da177e4
LT		 180
181/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 182static bool fix_pwm_polarity;
1da177e4 183
1da177e4
LT		 184/* Many IT87 constants specified below */
185
186/* Length of ISA address segment */
187#define IT87_EXTENT 8
188
87b4b663
BH		 189/* Length of ISA address segment for Environmental Controller */
190#define IT87_EC_EXTENT 2
191
192/* Offset of EC registers from ISA base address */
193#define IT87_EC_OFFSET 5
194
195/* Where are the ISA address/data registers relative to the EC base address */
196#define IT87_ADDR_REG_OFFSET 0
197#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 198
199/*----- The IT87 registers -----*/
200
201#define IT87_REG_CONFIG 0x00
202
203#define IT87_REG_ALARM1 0x01
204#define IT87_REG_ALARM2 0x02
205#define IT87_REG_ALARM3 0x03
206
4a0d71cf
GR		 207/*
208 * The IT8718F and IT8720F have the VID value in a different register, in
209 * Super-I/O configuration space.
210 */
1da177e4 211#define IT87_REG_VID 0x0a
4a0d71cf
GR		 212/*
213 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
214 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
215 * mode.
216 */
1da177e4 217#define IT87_REG_FAN_DIV 0x0b
17d648bf 218#define IT87_REG_FAN_16BIT 0x0c
1da177e4 219
f838aa26
GR		 220/*
221 * Monitors:
222 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
223 * - up to 6 temp (1 to 6)
224 * - up to 6 fan (1 to 6)
225 */
1da177e4 226
fa3f70d6
GR		 227static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
228static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
229static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
230static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
231static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
161d898a 232
1da177e4
LT		 233#define IT87_REG_FAN_MAIN_CTRL 0x13
234#define IT87_REG_FAN_CTL 0x14
36c4d98a
GR		 235static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
236static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
1da177e4 237
559313c4 238static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
f838aa26 239 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
1da177e4 240
559313c4 241#define IT87_REG_TEMP(nr) (0x29 + (nr))
73055405 242
1da177e4
LT		 243#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
244#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
245#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
246#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
247
1da177e4
LT		 248#define IT87_REG_VIN_ENABLE 0x50
249#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 250#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 251#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 252
253#define IT87_REG_CHIPID 0x58
254
2cbb9c37
GR		 255static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
256
257#define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
258#define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
4f3f51bc 259
cc18da79
GR		 260#define IT87_REG_TEMP456_ENABLE 0x77
261
2310048d
GR		 262#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
263#define NUM_VIN_LIMIT 8
264#define NUM_TEMP 6
265#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
266#define NUM_TEMP_LIMIT 3
267#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
268#define NUM_FAN_DIV 3
269#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
270#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
271
483db43e
GR		 272struct it87_devices {
273 const char *name;
faf392fb 274 const char * const suffix;
cc18da79 275 u32 features;
19529784
GR		 276 u8 peci_mask;
277 u8 old_peci_mask;
483db43e
GR		 278};
279
48b2ae7f
GR		 280#define FEAT_12MV_ADC BIT(0)
281#define FEAT_NEWER_AUTOPWM BIT(1)
282#define FEAT_OLD_AUTOPWM BIT(2)
283#define FEAT_16BIT_FANS BIT(3)
284#define FEAT_TEMP_OFFSET BIT(4)
285#define FEAT_TEMP_PECI BIT(5)
286#define FEAT_TEMP_OLD_PECI BIT(6)
287#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
288#define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
289#define FEAT_VID BIT(9) /* Set if chip supports VID */
290#define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
291#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
292#define FEAT_10_9MV_ADC BIT(12)
293#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
294#define FEAT_SIX_PWM BIT(14) /* Chip supports 6 pwm chn */
295#define FEAT_PWM_FREQ2 BIT(15) /* Separate pwm freq 2 */
296#define FEAT_SIX_TEMP BIT(16) /* Up to 6 temp sensors */
483db43e
GR		 297
298static const struct it87_devices it87_devices[] = {
299 [it87] = {
300 .name = "it87",
faf392fb 301 .suffix = "F",
483db43e
GR		 302 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
303 },
304 [it8712] = {
305 .name = "it8712",
faf392fb 306 .suffix = "F",
32dd7c40
GR		 307 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
308 /* may need to overwrite */
483db43e
GR		 309 },
310 [it8716] = {
311 .name = "it8716",
faf392fb 312 .suffix = "F",
32dd7c40 313 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf 314 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
483db43e
GR		 315 },
316 [it8718] = {
317 .name = "it8718",
faf392fb 318 .suffix = "F",
32dd7c40 319 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 320 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
321 | FEAT_PWM_FREQ2,
19529784 322 .old_peci_mask = 0x4,
483db43e
GR		 323 },
324 [it8720] = {
325 .name = "it8720",
faf392fb 326 .suffix = "F",
32dd7c40 327 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 328 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
329 | FEAT_PWM_FREQ2,
19529784 330 .old_peci_mask = 0x4,
483db43e
GR		 331 },
332 [it8721] = {
333 .name = "it8721",
faf392fb 334 .suffix = "F",
483db43e 335 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 336 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
60878bcf
GR		 337 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
338 | FEAT_PWM_FREQ2,
5d8d2f2b 339 .peci_mask = 0x05,
19529784 340 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 341 },
342 [it8728] = {
343 .name = "it8728",
faf392fb 344 .suffix = "F",
483db43e 345 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 346 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
60878bcf 347 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
5d8d2f2b 348 .peci_mask = 0x07,
483db43e 349 },
ead80803
JM		 350 [it8732] = {
351 .name = "it8732",
352 .suffix = "F",
353 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
354 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
355 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
356 .peci_mask = 0x07,
357 .old_peci_mask = 0x02, /* Actually reports PCH */
358 },
b0636707
GR		 359 [it8771] = {
360 .name = "it8771",
faf392fb 361 .suffix = "E",
b0636707 362 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 363 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
364 | FEAT_PWM_FREQ2,
9faf28ca
GR		 365 /* PECI: guesswork */
366 /* 12mV ADC (OHM) */
367 /* 16 bit fans (OHM) */
368 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 369 .peci_mask = 0x07,
370 },
371 [it8772] = {
372 .name = "it8772",
faf392fb 373 .suffix = "E",
b0636707 374 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 375 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
376 | FEAT_PWM_FREQ2,
9faf28ca
GR		 377 /* PECI (coreboot) */
378 /* 12mV ADC (HWSensors4, OHM) */
379 /* 16 bit fans (HWSensors4, OHM) */
380 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 381 .peci_mask = 0x07,
382 },
7bc32d29
GR		 383 [it8781] = {
384 .name = "it8781",
faf392fb 385 .suffix = "F",
7bc32d29 386 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 387 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
7bc32d29
GR		 388 .old_peci_mask = 0x4,
389 },
483db43e
GR		 390 [it8782] = {
391 .name = "it8782",
faf392fb 392 .suffix = "F",
19529784 393 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 394 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 395 .old_peci_mask = 0x4,
483db43e
GR		 396 },
397 [it8783] = {
398 .name = "it8783",
faf392fb 399 .suffix = "E/F",
19529784 400 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 401 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 402 .old_peci_mask = 0x4,
483db43e 403 },
a0c1424a
TL		 404 [it8786] = {
405 .name = "it8786",
faf392fb 406 .suffix = "E",
a0c1424a 407 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 408 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
409 | FEAT_PWM_FREQ2,
a0c1424a
TL		 410 .peci_mask = 0x07,
411 },
4ee07157
GR		 412 [it8790] = {
413 .name = "it8790",
414 .suffix = "E",
415 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 416 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
417 | FEAT_PWM_FREQ2,
4ee07157
GR		 418 .peci_mask = 0x07,
419 },
c145d5c6
RM		 420 [it8603] = {
421 .name = "it8603",
faf392fb 422 .suffix = "E",
c145d5c6 423 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
73055405 424 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
60878bcf 425 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
c145d5c6
RM		 426 .peci_mask = 0x07,
427 },
3ba9d977
GR		 428 [it8620] = {
429 .name = "it8620",
430 .suffix = "E",
431 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
fa3f70d6 432 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
cc18da79
GR		 433 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
434 | FEAT_SIX_TEMP,
3ba9d977
GR		 435 .peci_mask = 0x07,
436 },
483db43e
GR		 437};
438
439#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
440#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
ead80803 441#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
483db43e
GR		 442#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
443#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
444#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b 445#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
48b2ae7f 446 ((data)->peci_mask & BIT(nr)))
19529784
GR		 447#define has_temp_old_peci(data, nr) \
448 (((data)->features & FEAT_TEMP_OLD_PECI) && \
48b2ae7f 449 ((data)->old_peci_mask & BIT(nr)))
9faf28ca 450#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
fa3f70d6
GR		 451#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
452 FEAT_SIX_FANS))
32dd7c40 453#define has_vid(data) ((data)->features & FEAT_VID)
7f5726c3 454#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
fa3f70d6 455#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
73055405 456#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
36c4d98a 457#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
60878bcf 458#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
cc18da79 459#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
1da177e4 460
b74f3fdd 461struct it87_sio_data {
462 enum chips type;
463 /* Values read from Super-I/O config space */
0475169c 464 u8 revision;
b74f3fdd 465 u8 vid_value;
d9b327c3 466 u8 beep_pin;
738e5e05 467 u8 internal; /* Internal sensors can be labeled */
591ec650 468 /* Features skipped based on config or DMI */
9172b5d1 469 u16 skip_in;
895ff267 470 u8 skip_vid;
591ec650 471 u8 skip_fan;
98dd22c3 472 u8 skip_pwm;
4573acbc 473 u8 skip_temp;
b74f3fdd 474};
475
4a0d71cf
GR		 476/*
477 * For each registered chip, we need to keep some data in memory.
478 * The structure is dynamically allocated.
479 */
1da177e4 480struct it87_data {
8638d0af 481 const struct attribute_group *groups[7];
1da177e4 482 enum chips type;
483db43e 483 u16 features;
19529784
GR		 484 u8 peci_mask;
485 u8 old_peci_mask;
1da177e4 486
b74f3fdd 487 unsigned short addr;
488 const char *name;
9a61bf63 489 struct mutex update_lock;
1da177e4
LT		 490 char valid; /* !=0 if following fields are valid */
491 unsigned long last_updated; /* In jiffies */
492
44c1bcd4 493 u16 in_scaled; /* Internal voltage sensors are scaled */
d3766848 494 u16 in_internal; /* Bitfield, internal sensors (for labels) */
52929715 495 u16 has_in; /* Bitfield, voltage sensors enabled */
2310048d 496 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 497 u8 has_fan; /* Bitfield, fans enabled */
2310048d 498 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 499 u8 has_temp; /* Bitfield, temp sensors enabled */
2310048d 500 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 501 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
502 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
2310048d 503 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
d3766848 504 bool has_vid; /* True if VID supported */
1da177e4 505 u8 vid; /* Register encoding, combined */
a7be58a1 506 u8 vrm;
1da177e4 507 u32 alarms; /* Register encoding, combined */
52929715 508 bool has_beep; /* true if beep supported */
d9b327c3 509 u8 beeps; /* Register encoding */
1da177e4 510 u8 fan_main_ctrl; /* Register value */
f8d0c19a 511 u8 fan_ctl; /* Register value */
b99883dc 512
4a0d71cf
GR		 513 /*
514 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 515 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
516 * 7, and we want to preserve settings on mode changes, so we have
517 * to track all values separately.
518 * Starting with the IT8721F, the manual PWM duty cycles are stored
519 * in separate registers (8-bit values), so the separate tracking
520 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 521 * simple.
522 */
5c391261 523 u8 has_pwm; /* Bitfield, pwm control enabled */
2310048d
GR		 524 u8 pwm_ctrl[NUM_PWM]; /* Register value */
525 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
526 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 527
528 /* Automatic fan speed control registers */
2310048d
GR		 529 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
530 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 531};
0df6454d 532
0531d98b 533static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 534{
ead80803
JM		 535 int lsb;
536
537 if (has_12mv_adc(data))
538 lsb = 120;
539 else if (has_10_9mv_adc(data))
540 lsb = 109;
541 else
542 lsb = 160;
48b2ae7f 543 if (data->in_scaled & BIT(nr))
0531d98b
GR		 544 lsb <<= 1;
545 return lsb;
546}
44c1bcd4 547
0531d98b
GR		 548static u8 in_to_reg(const struct it87_data *data, int nr, long val)
549{
ead80803 550 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
2a844c14 551 return clamp_val(val, 0, 255);
44c1bcd4
JD		 552}
553
554static int in_from_reg(const struct it87_data *data, int nr, int val)
555{
ead80803 556 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
44c1bcd4 557}
0df6454d
JD		 558
559static inline u8 FAN_TO_REG(long rpm, int div)
560{
561 if (rpm == 0)
562 return 255;
2a844c14
GR		 563 rpm = clamp_val(rpm, 1, 1000000);
564 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 565}
566
567static inline u16 FAN16_TO_REG(long rpm)
568{
569 if (rpm == 0)
570 return 0xffff;
2a844c14 571 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 572}
573
574#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
575 1350000 / ((val) * (div)))
576/* The divider is fixed to 2 in 16-bit mode */
577#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
578 1350000 / ((val) * 2))
579
2a844c14
GR		 580#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
581 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 582#define TEMP_FROM_REG(val) ((val) * 1000)
583
44c1bcd4
JD		 584static u8 pwm_to_reg(const struct it87_data *data, long val)
585{
16b5dda2 586 if (has_newer_autopwm(data))
44c1bcd4
JD		 587 return val;
588 else
589 return val >> 1;
590}
591
592static int pwm_from_reg(const struct it87_data *data, u8 reg)
593{
16b5dda2 594 if (has_newer_autopwm(data))
44c1bcd4
JD		 595 return reg;
596 else
597 return (reg & 0x7f) << 1;
598}
599
0df6454d
JD		 600static int DIV_TO_REG(int val)
601{
602 int answer = 0;
c962024e 603
0df6454d
JD		 604 while (answer < 7 && (val >>= 1))
605 answer++;
606 return answer;
607}
48b2ae7f
GR		 608
609#define DIV_FROM_REG(val) BIT(val)
0df6454d 610
f56c9c0a
GR		 611/*
612 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
613 * depending on the chip type, to calculate the actual PWM frequency.
614 *
615 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
616 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
617 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
618 * sometimes just one. It is unknown if this is a datasheet error or real,
619 * so this is ignored for now.
620 */
0df6454d 621static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 622 48000000,
623 24000000,
624 12000000,
625 8000000,
626 6000000,
627 3000000,
628 1500000,
629 750000,
0df6454d 630};
1da177e4 631
c1e7a4ca
GR		 632/*
633 * Must be called with data->update_lock held, except during initialization.
634 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
635 * would slow down the IT87 access and should not be necessary.
636 */
637static int it87_read_value(struct it87_data *data, u8 reg)
638{
639 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
640 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
641}
642
643/*
644 * Must be called with data->update_lock held, except during initialization.
645 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
646 * would slow down the IT87 access and should not be necessary.
647 */
648static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
649{
650 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
651 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
652}
653
654static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
655{
656 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
657 if (has_newer_autopwm(data)) {
0624d861 658 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
c1e7a4ca
GR		 659 data->pwm_duty[nr] = it87_read_value(data,
660 IT87_REG_PWM_DUTY[nr]);
661 } else {
662 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
663 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
664 else /* Manual mode */
665 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
666 }
1da177e4 667
c1e7a4ca
GR		 668 if (has_old_autopwm(data)) {
669 int i;
1da177e4 670
c1e7a4ca
GR		 671 for (i = 0; i < 5 ; i++)
672 data->auto_temp[nr][i] = it87_read_value(data,
673 IT87_REG_AUTO_TEMP(nr, i));
674 for (i = 0; i < 3 ; i++)
675 data->auto_pwm[nr][i] = it87_read_value(data,
676 IT87_REG_AUTO_PWM(nr, i));
2cbb9c37
GR		 677 } else if (has_newer_autopwm(data)) {
678 int i;
679
680 /*
681 * 0: temperature hysteresis (base + 5)
682 * 1: fan off temperature (base + 0)
683 * 2: fan start temperature (base + 1)
684 * 3: fan max temperature (base + 2)
685 */
686 data->auto_temp[nr][0] =
687 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
688
689 for (i = 0; i < 3 ; i++)
690 data->auto_temp[nr][i + 1] =
691 it87_read_value(data,
692 IT87_REG_AUTO_TEMP(nr, i));
693 /*
694 * 0: start pwm value (base + 3)
695 * 1: pwm slope (base + 4, 1/8th pwm)
696 */
697 data->auto_pwm[nr][0] =
698 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
699 data->auto_pwm[nr][1] =
700 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
c1e7a4ca
GR		 701 }
702}
1da177e4 703
c1e7a4ca
GR		 704static struct it87_data *it87_update_device(struct device *dev)
705{
706 struct it87_data *data = dev_get_drvdata(dev);
707 int i;
708
709 mutex_lock(&data->update_lock);
710
c962024e
GR		 711 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
712 !data->valid) {
c1e7a4ca
GR		 713 if (update_vbat) {
714 /*
715 * Cleared after each update, so reenable. Value
716 * returned by this read will be previous value
717 */
718 it87_write_value(data, IT87_REG_CONFIG,
719 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
720 }
2310048d 721 for (i = 0; i < NUM_VIN; i++) {
48b2ae7f 722 if (!(data->has_in & BIT(i)))
559313c4
GR		 723 continue;
724
c1e7a4ca 725 data->in[i][0] =
559313c4
GR		 726 it87_read_value(data, IT87_REG_VIN[i]);
727
728 /* VBAT and AVCC don't have limit registers */
2310048d 729 if (i >= NUM_VIN_LIMIT)
559313c4
GR		 730 continue;
731
c1e7a4ca
GR		 732 data->in[i][1] =
733 it87_read_value(data, IT87_REG_VIN_MIN(i));
734 data->in[i][2] =
735 it87_read_value(data, IT87_REG_VIN_MAX(i));
736 }
c1e7a4ca 737
2310048d 738 for (i = 0; i < NUM_FAN; i++) {
c1e7a4ca 739 /* Skip disabled fans */
48b2ae7f 740 if (!(data->has_fan & BIT(i)))
c1e7a4ca
GR		 741 continue;
742
743 data->fan[i][1] =
744 it87_read_value(data, IT87_REG_FAN_MIN[i]);
745 data->fan[i][0] = it87_read_value(data,
746 IT87_REG_FAN[i]);
747 /* Add high byte if in 16-bit mode */
748 if (has_16bit_fans(data)) {
749 data->fan[i][0] |= it87_read_value(data,
750 IT87_REG_FANX[i]) << 8;
751 data->fan[i][1] |= it87_read_value(data,
752 IT87_REG_FANX_MIN[i]) << 8;
753 }
754 }
2310048d 755 for (i = 0; i < NUM_TEMP; i++) {
48b2ae7f 756 if (!(data->has_temp & BIT(i)))
c1e7a4ca
GR		 757 continue;
758 data->temp[i][0] =
759 it87_read_value(data, IT87_REG_TEMP(i));
cc18da79 760
2310048d
GR		 761 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
762 data->temp[i][3] =
763 it87_read_value(data,
764 IT87_REG_TEMP_OFFSET[i]);
765
766 if (i >= NUM_TEMP_LIMIT)
cc18da79
GR		 767 continue;
768
c1e7a4ca
GR		 769 data->temp[i][1] =
770 it87_read_value(data, IT87_REG_TEMP_LOW(i));
771 data->temp[i][2] =
772 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c1e7a4ca
GR		 773 }
774
775 /* Newer chips don't have clock dividers */
776 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
777 i = it87_read_value(data, IT87_REG_FAN_DIV);
778 data->fan_div[0] = i & 0x07;
779 data->fan_div[1] = (i >> 3) & 0x07;
780 data->fan_div[2] = (i & 0x40) ? 3 : 1;
781 }
782
783 data->alarms =
784 it87_read_value(data, IT87_REG_ALARM1) |
785 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
786 (it87_read_value(data, IT87_REG_ALARM3) << 16);
787 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
788
789 data->fan_main_ctrl = it87_read_value(data,
790 IT87_REG_FAN_MAIN_CTRL);
791 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
0624d861
GR		 792 for (i = 0; i < NUM_PWM; i++) {
793 if (!(data->has_pwm & BIT(i)))
794 continue;
c1e7a4ca 795 it87_update_pwm_ctrl(data, i);
0624d861 796 }
c1e7a4ca
GR		 797
798 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
799 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
800 /*
801 * The IT8705F does not have VID capability.
802 * The IT8718F and later don't use IT87_REG_VID for the
803 * same purpose.
804 */
805 if (data->type == it8712 || data->type == it8716) {
806 data->vid = it87_read_value(data, IT87_REG_VID);
807 /*
808 * The older IT8712F revisions had only 5 VID pins,
809 * but we assume it is always safe to read 6 bits.
810 */
811 data->vid &= 0x3f;
812 }
813 data->last_updated = jiffies;
814 data->valid = 1;
815 }
816
817 mutex_unlock(&data->update_lock);
818
819 return data;
820}
fde09509 821
20ad93d4 822static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 823 char *buf)
1da177e4 824{
929c6a56 825 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
c962024e 826 struct it87_data *data = it87_update_device(dev);
929c6a56 827 int index = sattr->index;
c962024e 828 int nr = sattr->nr;
20ad93d4 829
929c6a56 830 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 831}
832
929c6a56
GR		 833static ssize_t set_in(struct device *dev, struct device_attribute *attr,
834 const char *buf, size_t count)
1da177e4 835{
929c6a56 836 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
b74f3fdd 837 struct it87_data *data = dev_get_drvdata(dev);
c962024e
GR		 838 int index = sattr->index;
839 int nr = sattr->nr;
f5f64501
JD		 840 unsigned long val;
841
179c4fdb 842 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 843 return -EINVAL;
1da177e4 844
9a61bf63 845 mutex_lock(&data->update_lock);
929c6a56
GR		 846 data->in[nr][index] = in_to_reg(data, nr, val);
847 it87_write_value(data,
848 index == 1 ? IT87_REG_VIN_MIN(nr)
849 : IT87_REG_VIN_MAX(nr),
850 data->in[nr][index]);
9a61bf63 851 mutex_unlock(&data->update_lock);
1da177e4
LT		 852 return count;
853}
20ad93d4 854
929c6a56
GR		 855static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
856static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
857 0, 1);
858static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
859 0, 2);
f5f64501 860
929c6a56
GR		 861static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
862static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
863 1, 1);
864static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
865 1, 2);
1da177e4 866
929c6a56
GR		 867static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
868static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
869 2, 1);
870static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
871 2, 2);
1da177e4 872
929c6a56
GR		 873static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
874static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
875 3, 1);
876static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
877 3, 2);
878
879static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
880static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
881 4, 1);
882static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
883 4, 2);
884
885static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
886static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
887 5, 1);
888static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
889 5, 2);
890
891static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
892static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
893 6, 1);
894static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
895 6, 2);
896
897static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
898static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
899 7, 1);
900static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
901 7, 2);
902
903static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 904static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
f838aa26
GR		 905static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
906static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
907static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1da177e4 908
cc18da79 909/* Up to 6 temperatures */
20ad93d4 910static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 911 char *buf)
1da177e4 912{
60ca385a
GR		 913 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
914 int nr = sattr->nr;
915 int index = sattr->index;
1da177e4 916 struct it87_data *data = it87_update_device(dev);
20ad93d4 917
60ca385a 918 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 919}
20ad93d4 920
60ca385a
GR		 921static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
922 const char *buf, size_t count)
1da177e4 923{
60ca385a
GR		 924 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
925 int nr = sattr->nr;
926 int index = sattr->index;
b74f3fdd 927 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 928 long val;
161d898a 929 u8 reg, regval;
f5f64501 930
179c4fdb 931 if (kstrtol(buf, 10, &val) < 0)
f5f64501 932 return -EINVAL;
1da177e4 933
9a61bf63 934 mutex_lock(&data->update_lock);
161d898a
GR		 935
936 switch (index) {
937 default:
938 case 1:
939 reg = IT87_REG_TEMP_LOW(nr);
940 break;
941 case 2:
942 reg = IT87_REG_TEMP_HIGH(nr);
943 break;
944 case 3:
945 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
946 if (!(regval & 0x80)) {
947 regval |= 0x80;
948 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
949 }
950 data->valid = 0;
951 reg = IT87_REG_TEMP_OFFSET[nr];
952 break;
953 }
954
60ca385a 955 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 956 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 957 mutex_unlock(&data->update_lock);
1da177e4
LT		 958 return count;
959}
1da177e4 960
60ca385a
GR		 961static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
962static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
963 0, 1);
964static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
965 0, 2);
161d898a
GR		 966static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
967 set_temp, 0, 3);
60ca385a
GR		 968static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
969static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
970 1, 1);
971static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
972 1, 2);
161d898a
GR		 973static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
974 set_temp, 1, 3);
60ca385a
GR		 975static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
976static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
977 2, 1);
978static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
979 2, 2);
161d898a
GR		 980static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
981 set_temp, 2, 3);
cc18da79
GR		 982static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
983static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
984static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1da177e4 985
2cece01f
GR		 986static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
987 char *buf)
1da177e4 988{
20ad93d4
JD		 989 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
990 int nr = sensor_attr->index;
1da177e4 991 struct it87_data *data = it87_update_device(dev);
4a0d71cf 992 u8 reg = data->sensor; /* In case value is updated while used */
19529784 993 u8 extra = data->extra;
5f2dc798 994
c962024e
GR		 995 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
996 (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 997 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 998 if (reg & (1 << nr))
999 return sprintf(buf, "3\n"); /* thermal diode */
1000 if (reg & (8 << nr))
4ed10779 1001 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 1002 return sprintf(buf, "0\n"); /* disabled */
1003}
2cece01f
GR		 1004
1005static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1006 const char *buf, size_t count)
1da177e4 1007{
20ad93d4
JD		 1008 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1009 int nr = sensor_attr->index;
1010
b74f3fdd 1011 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1012 long val;
19529784 1013 u8 reg, extra;
f5f64501 1014
179c4fdb 1015 if (kstrtol(buf, 10, &val) < 0)
f5f64501 1016 return -EINVAL;
1da177e4 1017
8acf07c5
JD		 1018 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1019 reg &= ~(1 << nr);
1020 reg &= ~(8 << nr);
5d8d2f2b
GR		 1021 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1022 reg &= 0x3f;
19529784
GR		 1023 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1024 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1025 extra &= 0x7f;
4ed10779 1026 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 1027 dev_warn(dev,
1028 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 1029 val = 4;
1030 }
5d8d2f2b 1031 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 1032 if (val == 3)
8acf07c5 1033 reg |= 1 << nr;
4ed10779 1034 else if (val == 4)
8acf07c5 1035 reg |= 8 << nr;
5d8d2f2b
GR		 1036 else if (has_temp_peci(data, nr) && val == 6)
1037 reg |= (nr + 1) << 6;
19529784
GR		 1038 else if (has_temp_old_peci(data, nr) && val == 6)
1039 extra |= 0x80;
8acf07c5 1040 else if (val != 0)
1da177e4 1041 return -EINVAL;
8acf07c5
JD		 1042
1043 mutex_lock(&data->update_lock);
1044 data->sensor = reg;
19529784 1045 data->extra = extra;
b74f3fdd 1046 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 1047 if (has_temp_old_peci(data, nr))
1048 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 1049 data->valid = 0; /* Force cache refresh */
9a61bf63 1050 mutex_unlock(&data->update_lock);
1da177e4
LT		 1051 return count;
1052}
1da177e4 1053
2cece01f
GR		 1054static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1055 set_temp_type, 0);
1056static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1057 set_temp_type, 1);
1058static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1059 set_temp_type, 2);
1da177e4 1060
f1bbe618 1061/* 6 Fans */
b99883dc
JD		 1062
1063static int pwm_mode(const struct it87_data *data, int nr)
1064{
f1bbe618
GR		 1065 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1066 return 0; /* Full speed */
1067 if (data->pwm_ctrl[nr] & 0x80)
1068 return 2; /* Automatic mode */
1069 if ((data->type == it8603 || nr >= 3) &&
1070 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1071 return 0; /* Full speed */
1072
1073 return 1; /* Manual mode */
b99883dc
JD		 1074}
1075
20ad93d4 1076static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 1077 char *buf)
1da177e4 1078{
e1169ba0
GR		 1079 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1080 int nr = sattr->nr;
1081 int index = sattr->index;
1082 int speed;
1da177e4 1083 struct it87_data *data = it87_update_device(dev);
20ad93d4 1084
e1169ba0
GR		 1085 speed = has_16bit_fans(data) ?
1086 FAN16_FROM_REG(data->fan[nr][index]) :
1087 FAN_FROM_REG(data->fan[nr][index],
1088 DIV_FROM_REG(data->fan_div[nr]));
1089 return sprintf(buf, "%d\n", speed);
1da177e4 1090}
e1169ba0 1091
20ad93d4 1092static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
c962024e 1093 char *buf)
1da177e4 1094{
20ad93d4 1095 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1096 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1097 int nr = sensor_attr->index;
1098
48b2ae7f 1099 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1da177e4 1100}
c962024e 1101
5f2dc798 1102static ssize_t show_pwm_enable(struct device *dev,
c962024e 1103 struct device_attribute *attr, char *buf)
1da177e4 1104{
20ad93d4 1105 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1106 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1107 int nr = sensor_attr->index;
1108
b99883dc 1109 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 1110}
c962024e 1111
20ad93d4 1112static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
c962024e 1113 char *buf)
1da177e4 1114{
20ad93d4 1115 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1116 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1117 int nr = sensor_attr->index;
1118
44c1bcd4
JD		 1119 return sprintf(buf, "%d\n",
1120 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 1121}
c962024e 1122
f8d0c19a 1123static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
c962024e 1124 char *buf)
f8d0c19a 1125{
60878bcf 1126 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
f8d0c19a 1127 struct it87_data *data = it87_update_device(dev);
60878bcf 1128 int nr = sensor_attr->index;
f56c9c0a 1129 unsigned int freq;
60878bcf
GR		 1130 int index;
1131
1132 if (has_pwm_freq2(data) && nr == 1)
1133 index = (data->extra >> 4) & 0x07;
1134 else
1135 index = (data->fan_ctl >> 4) & 0x07;
f8d0c19a 1136
f56c9c0a
GR		 1137 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1138
1139 return sprintf(buf, "%u\n", freq);
f8d0c19a 1140}
e1169ba0
GR		 1141
1142static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1143 const char *buf, size_t count)
1da177e4 1144{
e1169ba0
GR		 1145 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1146 int nr = sattr->nr;
1147 int index = sattr->index;
20ad93d4 1148
b74f3fdd 1149 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1150 long val;
7f999aa7 1151 u8 reg;
1da177e4 1152
179c4fdb 1153 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 1154 return -EINVAL;
1155
9a61bf63 1156 mutex_lock(&data->update_lock);
e1169ba0
GR		 1157
1158 if (has_16bit_fans(data)) {
1159 data->fan[nr][index] = FAN16_TO_REG(val);
1160 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1161 data->fan[nr][index] & 0xff);
1162 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1163 data->fan[nr][index] >> 8);
1164 } else {
1165 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1166 switch (nr) {
1167 case 0:
1168 data->fan_div[nr] = reg & 0x07;
1169 break;
1170 case 1:
1171 data->fan_div[nr] = (reg >> 3) & 0x07;
1172 break;
1173 case 2:
1174 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1175 break;
1176 }
1177 data->fan[nr][index] =
1178 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1179 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1180 data->fan[nr][index]);
07eab46d
JD		 1181 }
1182
9a61bf63 1183 mutex_unlock(&data->update_lock);
1da177e4
LT		 1184 return count;
1185}
e1169ba0 1186
20ad93d4 1187static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
c962024e 1188 const char *buf, size_t count)
1da177e4 1189{
20ad93d4 1190 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1191 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1192 int nr = sensor_attr->index;
f5f64501 1193 unsigned long val;
8ab4ec3e 1194 int min;
1da177e4
LT		 1195 u8 old;
1196
179c4fdb 1197 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1198 return -EINVAL;
1199
9a61bf63 1200 mutex_lock(&data->update_lock);
b74f3fdd 1201 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 1202
8ab4ec3e 1203 /* Save fan min limit */
e1169ba0 1204 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 1205
1206 switch (nr) {
1207 case 0:
1208 case 1:
1209 data->fan_div[nr] = DIV_TO_REG(val);
1210 break;
1211 case 2:
1212 if (val < 8)
1213 data->fan_div[nr] = 1;
1214 else
1215 data->fan_div[nr] = 3;
1216 }
1217 val = old & 0x80;
1218 val |= (data->fan_div[0] & 0x07);
1219 val |= (data->fan_div[1] & 0x07) << 3;
1220 if (data->fan_div[2] == 3)
1221 val |= 0x1 << 6;
b74f3fdd 1222 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 1223
8ab4ec3e 1224 /* Restore fan min limit */
e1169ba0
GR		 1225 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1226 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 1227
9a61bf63 1228 mutex_unlock(&data->update_lock);
1da177e4
LT		 1229 return count;
1230}
cccfc9c4
JD		 1231
1232/* Returns 0 if OK, -EINVAL otherwise */
1233static int check_trip_points(struct device *dev, int nr)
1234{
1235 const struct it87_data *data = dev_get_drvdata(dev);
1236 int i, err = 0;
1237
1238 if (has_old_autopwm(data)) {
1239 for (i = 0; i < 3; i++) {
1240 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1241 err = -EINVAL;
1242 }
1243 for (i = 0; i < 2; i++) {
1244 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1245 err = -EINVAL;
1246 }
2cbb9c37
GR		 1247 } else if (has_newer_autopwm(data)) {
1248 for (i = 1; i < 3; i++) {
1249 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1250 err = -EINVAL;
1251 }
cccfc9c4
JD		 1252 }
1253
1254 if (err) {
1d9bcf6a
GR		 1255 dev_err(dev,
1256 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 1257 dev_err(dev, "Adjust the trip points and try again\n");
1258 }
1259 return err;
1260}
1261
c962024e
GR		 1262static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1263 const char *buf, size_t count)
1da177e4 1264{
20ad93d4 1265 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1266 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1267 int nr = sensor_attr->index;
f5f64501 1268 long val;
1da177e4 1269
179c4fdb 1270 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 1271 return -EINVAL;
1272
cccfc9c4
JD		 1273 /* Check trip points before switching to automatic mode */
1274 if (val == 2) {
1275 if (check_trip_points(dev, nr) < 0)
1276 return -EINVAL;
1277 }
1278
9a61bf63 1279 mutex_lock(&data->update_lock);
1da177e4
LT		 1280
1281 if (val == 0) {
f1bbe618
GR		 1282 if (nr < 3 && data->type != it8603) {
1283 int tmp;
1284 /* make sure the fan is on when in on/off mode */
1285 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1286 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1287 /* set on/off mode */
1288 data->fan_main_ctrl &= ~BIT(nr);
1289 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1290 data->fan_main_ctrl);
1291 } else {
1292 /* No on/off mode, set maximum pwm value */
1293 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1294 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1295 data->pwm_duty[nr]);
1296 /* and set manual mode */
1297 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
1298 data->pwm_temp_map[nr] :
1299 data->pwm_duty[nr];
1300 it87_write_value(data, IT87_REG_PWM[nr],
1301 data->pwm_ctrl[nr]);
1302 }
b99883dc
JD		 1303 } else {
1304 if (val == 1) /* Manual mode */
16b5dda2 1305 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1306 data->pwm_temp_map[nr] :
1307 data->pwm_duty[nr];
b99883dc
JD		 1308 else /* Automatic mode */
1309 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1310 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
c145d5c6 1311
f1bbe618 1312 if (data->type != it8603 && nr < 3) {
c145d5c6 1313 /* set SmartGuardian mode */
48b2ae7f 1314 data->fan_main_ctrl |= BIT(nr);
c145d5c6
RM		 1315 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1316 data->fan_main_ctrl);
1317 }
1da177e4
LT		 1318 }
1319
9a61bf63 1320 mutex_unlock(&data->update_lock);
1da177e4
LT		 1321 return count;
1322}
c962024e 1323
20ad93d4 1324static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
c962024e 1325 const char *buf, size_t count)
1da177e4 1326{
20ad93d4 1327 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1328 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1329 int nr = sensor_attr->index;
f5f64501 1330 long val;
1da177e4 1331
179c4fdb 1332 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1333 return -EINVAL;
1334
9a61bf63 1335 mutex_lock(&data->update_lock);
16b5dda2 1336 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1337 /*
1338 * If we are in automatic mode, the PWM duty cycle register
1339 * is read-only so we can't write the value.
1340 */
6229cdb2
JD		 1341 if (data->pwm_ctrl[nr] & 0x80) {
1342 mutex_unlock(&data->update_lock);
1343 return -EBUSY;
1344 }
1345 data->pwm_duty[nr] = pwm_to_reg(data, val);
36c4d98a 1346 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
6229cdb2
JD		 1347 data->pwm_duty[nr]);
1348 } else {
1349 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1350 /*
1351 * If we are in manual mode, write the duty cycle immediately;
1352 * otherwise, just store it for later use.
1353 */
6229cdb2
JD		 1354 if (!(data->pwm_ctrl[nr] & 0x80)) {
1355 data->pwm_ctrl[nr] = data->pwm_duty[nr];
36c4d98a 1356 it87_write_value(data, IT87_REG_PWM[nr],
6229cdb2
JD		 1357 data->pwm_ctrl[nr]);
1358 }
b99883dc 1359 }
9a61bf63 1360 mutex_unlock(&data->update_lock);
1da177e4
LT		 1361 return count;
1362}
c962024e
GR		 1363
1364static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1365 const char *buf, size_t count)
f8d0c19a 1366{
60878bcf 1367 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1368 struct it87_data *data = dev_get_drvdata(dev);
60878bcf 1369 int nr = sensor_attr->index;
f5f64501 1370 unsigned long val;
f8d0c19a
JD		 1371 int i;
1372
179c4fdb 1373 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1374 return -EINVAL;
f56c9c0a
GR		 1375
1376 val = clamp_val(val, 0, 1000000);
1377 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1378
f8d0c19a
JD		 1379 /* Search for the nearest available frequency */
1380 for (i = 0; i < 7; i++) {
c962024e 1381 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
f8d0c19a
JD		 1382 break;
1383 }
1384
1385 mutex_lock(&data->update_lock);
60878bcf
GR		 1386 if (nr == 0) {
1387 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1388 data->fan_ctl |= i << 4;
1389 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1390 } else {
1391 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1392 data->extra |= i << 4;
1393 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1394 }
f8d0c19a
JD		 1395 mutex_unlock(&data->update_lock);
1396
1397 return count;
1398}
c962024e 1399
94ac7ee6 1400static ssize_t show_pwm_temp_map(struct device *dev,
c962024e 1401 struct device_attribute *attr, char *buf)
94ac7ee6
JD		 1402{
1403 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
94ac7ee6 1404 struct it87_data *data = it87_update_device(dev);
c962024e 1405 int nr = sensor_attr->index;
94ac7ee6
JD		 1406 int map;
1407
0624d861
GR		 1408 map = data->pwm_temp_map[nr];
1409 if (map >= 3)
1410 map = 0; /* Should never happen */
1411 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1412 map += 3;
1413
1414 return sprintf(buf, "%d\n", (int)BIT(map));
94ac7ee6 1415}
c962024e 1416
94ac7ee6 1417static ssize_t set_pwm_temp_map(struct device *dev,
c962024e
GR		 1418 struct device_attribute *attr, const char *buf,
1419 size_t count)
94ac7ee6
JD		 1420{
1421 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
94ac7ee6 1422 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1423 int nr = sensor_attr->index;
94ac7ee6
JD		 1424 long val;
1425 u8 reg;
1426
179c4fdb 1427 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1428 return -EINVAL;
1429
0624d861
GR		 1430 if (nr >= 3)
1431 val -= 3;
1432
94ac7ee6 1433 switch (val) {
48b2ae7f 1434 case BIT(0):
94ac7ee6
JD		 1435 reg = 0x00;
1436 break;
48b2ae7f 1437 case BIT(1):
94ac7ee6
JD		 1438 reg = 0x01;
1439 break;
48b2ae7f 1440 case BIT(2):
94ac7ee6
JD		 1441 reg = 0x02;
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446
1447 mutex_lock(&data->update_lock);
1448 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1449 /*
1450 * If we are in automatic mode, write the temp mapping immediately;
1451 * otherwise, just store it for later use.
1452 */
94ac7ee6
JD		 1453 if (data->pwm_ctrl[nr] & 0x80) {
1454 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1455 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
94ac7ee6
JD		 1456 }
1457 mutex_unlock(&data->update_lock);
1458 return count;
1459}
1da177e4 1460
c962024e
GR		 1461static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1462 char *buf)
4f3f51bc
JD		 1463{
1464 struct it87_data *data = it87_update_device(dev);
1465 struct sensor_device_attribute_2 *sensor_attr =
1466 to_sensor_dev_attr_2(attr);
1467 int nr = sensor_attr->nr;
1468 int point = sensor_attr->index;
1469
44c1bcd4
JD		 1470 return sprintf(buf, "%d\n",
1471 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1472}
1473
c962024e
GR		 1474static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1475 const char *buf, size_t count)
4f3f51bc
JD		 1476{
1477 struct it87_data *data = dev_get_drvdata(dev);
1478 struct sensor_device_attribute_2 *sensor_attr =
1479 to_sensor_dev_attr_2(attr);
1480 int nr = sensor_attr->nr;
1481 int point = sensor_attr->index;
2cbb9c37 1482 int regaddr;
4f3f51bc
JD		 1483 long val;
1484
179c4fdb 1485 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1486 return -EINVAL;
1487
1488 mutex_lock(&data->update_lock);
44c1bcd4 1489 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2cbb9c37
GR		 1490 if (has_newer_autopwm(data))
1491 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1492 else
1493 regaddr = IT87_REG_AUTO_PWM(nr, point);
1494 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1495 mutex_unlock(&data->update_lock);
1496 return count;
1497}
1498
1499static ssize_t show_auto_pwm_slope(struct device *dev,
1500 struct device_attribute *attr, char *buf)
1501{
1502 struct it87_data *data = it87_update_device(dev);
1503 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1504 int nr = sensor_attr->index;
1505
1506 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1507}
1508
1509static ssize_t set_auto_pwm_slope(struct device *dev,
1510 struct device_attribute *attr,
1511 const char *buf, size_t count)
1512{
1513 struct it87_data *data = dev_get_drvdata(dev);
1514 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1515 int nr = sensor_attr->index;
1516 unsigned long val;
1517
1518 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1519 return -EINVAL;
1520
1521 mutex_lock(&data->update_lock);
1522 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1523 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1524 data->auto_pwm[nr][1]);
4f3f51bc
JD		 1525 mutex_unlock(&data->update_lock);
1526 return count;
1527}
1528
c962024e
GR		 1529static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1530 char *buf)
4f3f51bc
JD		 1531{
1532 struct it87_data *data = it87_update_device(dev);
1533 struct sensor_device_attribute_2 *sensor_attr =
1534 to_sensor_dev_attr_2(attr);
1535 int nr = sensor_attr->nr;
1536 int point = sensor_attr->index;
2cbb9c37
GR		 1537 int reg;
1538
1539 if (has_old_autopwm(data) || point)
1540 reg = data->auto_temp[nr][point];
1541 else
1542 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
4f3f51bc 1543
2cbb9c37 1544 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
4f3f51bc
JD		 1545}
1546
c962024e
GR		 1547static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1548 const char *buf, size_t count)
4f3f51bc
JD		 1549{
1550 struct it87_data *data = dev_get_drvdata(dev);
1551 struct sensor_device_attribute_2 *sensor_attr =
1552 to_sensor_dev_attr_2(attr);
1553 int nr = sensor_attr->nr;
1554 int point = sensor_attr->index;
1555 long val;
2cbb9c37 1556 int reg;
4f3f51bc 1557
179c4fdb 1558 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1559 return -EINVAL;
1560
1561 mutex_lock(&data->update_lock);
2cbb9c37
GR		 1562 if (has_newer_autopwm(data) && !point) {
1563 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1564 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1565 data->auto_temp[nr][0] = reg;
1566 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1567 } else {
1568 reg = TEMP_TO_REG(val);
1569 data->auto_temp[nr][point] = reg;
1570 if (has_newer_autopwm(data))
1571 point--;
1572 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1573 }
4f3f51bc
JD		 1574 mutex_unlock(&data->update_lock);
1575 return count;
1576}
1577
e1169ba0
GR		 1578static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1579static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1580 0, 1);
1581static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1582 set_fan_div, 0);
1583
1584static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1585static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1586 1, 1);
1587static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1588 set_fan_div, 1);
1589
1590static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1591static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1592 2, 1);
1593static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1594 set_fan_div, 2);
1595
1596static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1597static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1598 3, 1);
1da177e4 1599
e1169ba0
GR		 1600static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1601static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1602 4, 1);
1da177e4 1603
fa3f70d6
GR		 1604static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1605static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1606 5, 1);
1607
c4458db3
GR		 1608static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1609 show_pwm_enable, set_pwm_enable, 0);
1610static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
60878bcf
GR		 1611static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1612 set_pwm_freq, 0);
5c391261 1613static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1614 show_pwm_temp_map, set_pwm_temp_map, 0);
1615static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1616 show_auto_pwm, set_auto_pwm, 0, 0);
1617static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1618 show_auto_pwm, set_auto_pwm, 0, 1);
1619static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1620 show_auto_pwm, set_auto_pwm, 0, 2);
1621static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1622 show_auto_pwm, NULL, 0, 3);
1623static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1624 show_auto_temp, set_auto_temp, 0, 1);
1625static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1626 show_auto_temp, set_auto_temp, 0, 0);
1627static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1628 show_auto_temp, set_auto_temp, 0, 2);
1629static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1630 show_auto_temp, set_auto_temp, 0, 3);
1631static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1632 show_auto_temp, set_auto_temp, 0, 4);
2cbb9c37
GR		 1633static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
1634 show_auto_pwm, set_auto_pwm, 0, 0);
1635static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
1636 show_auto_pwm_slope, set_auto_pwm_slope, 0);
c4458db3
GR		 1637
1638static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1639 show_pwm_enable, set_pwm_enable, 1);
1640static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
60878bcf 1641static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
5c391261 1642static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1643 show_pwm_temp_map, set_pwm_temp_map, 1);
1644static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1645 show_auto_pwm, set_auto_pwm, 1, 0);
1646static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1647 show_auto_pwm, set_auto_pwm, 1, 1);
1648static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1649 show_auto_pwm, set_auto_pwm, 1, 2);
1650static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1651 show_auto_pwm, NULL, 1, 3);
1652static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1653 show_auto_temp, set_auto_temp, 1, 1);
1654static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1655 show_auto_temp, set_auto_temp, 1, 0);
1656static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1657 show_auto_temp, set_auto_temp, 1, 2);
1658static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1659 show_auto_temp, set_auto_temp, 1, 3);
1660static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1661 show_auto_temp, set_auto_temp, 1, 4);
2cbb9c37
GR		 1662static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
1663 show_auto_pwm, set_auto_pwm, 1, 0);
1664static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
1665 show_auto_pwm_slope, set_auto_pwm_slope, 1);
c4458db3
GR		 1666
1667static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1668 show_pwm_enable, set_pwm_enable, 2);
1669static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
60878bcf 1670static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
5c391261 1671static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1672 show_pwm_temp_map, set_pwm_temp_map, 2);
1673static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1674 show_auto_pwm, set_auto_pwm, 2, 0);
1675static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1676 show_auto_pwm, set_auto_pwm, 2, 1);
1677static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1678 show_auto_pwm, set_auto_pwm, 2, 2);
1679static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1680 show_auto_pwm, NULL, 2, 3);
1681static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1682 show_auto_temp, set_auto_temp, 2, 1);
1683static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1684 show_auto_temp, set_auto_temp, 2, 0);
1685static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1686 show_auto_temp, set_auto_temp, 2, 2);
1687static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1688 show_auto_temp, set_auto_temp, 2, 3);
1689static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1690 show_auto_temp, set_auto_temp, 2, 4);
2cbb9c37
GR		 1691static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
1692 show_auto_pwm, set_auto_pwm, 2, 0);
1693static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
1694 show_auto_pwm_slope, set_auto_pwm_slope, 2);
1da177e4 1695
36c4d98a
GR		 1696static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1697 show_pwm_enable, set_pwm_enable, 3);
1698static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
60878bcf 1699static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
5c391261 1700static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
36c4d98a 1701 show_pwm_temp_map, set_pwm_temp_map, 3);
2cbb9c37
GR		 1702static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
1703 show_auto_temp, set_auto_temp, 2, 1);
1704static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1705 show_auto_temp, set_auto_temp, 2, 0);
1706static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
1707 show_auto_temp, set_auto_temp, 2, 2);
1708static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
1709 show_auto_temp, set_auto_temp, 2, 3);
1710static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
1711 show_auto_pwm, set_auto_pwm, 3, 0);
1712static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
1713 show_auto_pwm_slope, set_auto_pwm_slope, 3);
36c4d98a
GR		 1714
1715static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1716 show_pwm_enable, set_pwm_enable, 4);
1717static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
60878bcf 1718static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
5c391261 1719static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
36c4d98a 1720 show_pwm_temp_map, set_pwm_temp_map, 4);
2cbb9c37
GR		 1721static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
1722 show_auto_temp, set_auto_temp, 2, 1);
1723static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1724 show_auto_temp, set_auto_temp, 2, 0);
1725static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
1726 show_auto_temp, set_auto_temp, 2, 2);
1727static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
1728 show_auto_temp, set_auto_temp, 2, 3);
1729static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
1730 show_auto_pwm, set_auto_pwm, 4, 0);
1731static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
1732 show_auto_pwm_slope, set_auto_pwm_slope, 4);
36c4d98a
GR		 1733
1734static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1735 show_pwm_enable, set_pwm_enable, 5);
1736static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
60878bcf 1737static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
5c391261 1738static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
36c4d98a 1739 show_pwm_temp_map, set_pwm_temp_map, 5);
2cbb9c37
GR		 1740static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
1741 show_auto_temp, set_auto_temp, 2, 1);
1742static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1743 show_auto_temp, set_auto_temp, 2, 0);
1744static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
1745 show_auto_temp, set_auto_temp, 2, 2);
1746static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
1747 show_auto_temp, set_auto_temp, 2, 3);
1748static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
1749 show_auto_pwm, set_auto_pwm, 5, 0);
1750static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
1751 show_auto_pwm_slope, set_auto_pwm_slope, 5);
36c4d98a 1752
1da177e4 1753/* Alarms */
5f2dc798 1754static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
c962024e 1755 char *buf)
1da177e4
LT		 1756{
1757 struct it87_data *data = it87_update_device(dev);
c962024e 1758
68188ba7 1759 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1760}
1d66c64c 1761static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1762
0124dd78 1763static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
c962024e 1764 char *buf)
0124dd78 1765{
0124dd78 1766 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1767 int bitnr = to_sensor_dev_attr(attr)->index;
1768
0124dd78
JD		 1769 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1770}
3d30f9e6 1771
c962024e
GR		 1772static ssize_t clear_intrusion(struct device *dev,
1773 struct device_attribute *attr, const char *buf,
1774 size_t count)
3d30f9e6
JD		 1775{
1776 struct it87_data *data = dev_get_drvdata(dev);
3d30f9e6 1777 int config;
c962024e 1778 long val;
3d30f9e6 1779
179c4fdb 1780 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1781 return -EINVAL;
1782
1783 mutex_lock(&data->update_lock);
1784 config = it87_read_value(data, IT87_REG_CONFIG);
1785 if (config < 0) {
1786 count = config;
1787 } else {
48b2ae7f 1788 config |= BIT(5);
3d30f9e6
JD		 1789 it87_write_value(data, IT87_REG_CONFIG, config);
1790 /* Invalidate cache to force re-read */
1791 data->valid = 0;
1792 }
1793 mutex_unlock(&data->update_lock);
1794
1795 return count;
1796}
1797
0124dd78
JD		 1798static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1799static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1800static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1801static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1802static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1803static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1804static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1805static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1806static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1807static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1808static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1809static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1810static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
fa3f70d6 1811static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
0124dd78
JD		 1812static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1813static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1814static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1815static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1816 show_alarm, clear_intrusion, 4);
0124dd78 1817
d9b327c3 1818static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
c962024e 1819 char *buf)
d9b327c3 1820{
d9b327c3 1821 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1822 int bitnr = to_sensor_dev_attr(attr)->index;
1823
d9b327c3
JD		 1824 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1825}
c962024e 1826
d9b327c3 1827static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
c962024e 1828 const char *buf, size_t count)
d9b327c3
JD		 1829{
1830 int bitnr = to_sensor_dev_attr(attr)->index;
1831 struct it87_data *data = dev_get_drvdata(dev);
1832 long val;
1833
c962024e 1834 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
d9b327c3
JD		 1835 return -EINVAL;
1836
1837 mutex_lock(&data->update_lock);
1838 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1839 if (val)
48b2ae7f 1840 data->beeps |= BIT(bitnr);
d9b327c3 1841 else
48b2ae7f 1842 data->beeps &= ~BIT(bitnr);
d9b327c3
JD		 1843 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1844 mutex_unlock(&data->update_lock);
1845 return count;
1846}
1847
1848static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1849 show_beep, set_beep, 1);
1850static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1851static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1852static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1853static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1854static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1855static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1856static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1857/* fanX_beep writability is set later */
1858static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1859static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1860static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1861static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1862static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
fa3f70d6 1863static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
d9b327c3
JD		 1864static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1865 show_beep, set_beep, 2);
1866static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1867static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1868
5f2dc798 1869static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
c962024e 1870 char *buf)
1da177e4 1871{
90d6619a 1872 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1873
a7be58a1 1874 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1875}
c962024e 1876
5f2dc798 1877static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
c962024e 1878 const char *buf, size_t count)
1da177e4 1879{
b74f3fdd 1880 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1881 unsigned long val;
1882
179c4fdb 1883 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1884 return -EINVAL;
1da177e4 1885
1da177e4
LT		 1886 data->vrm = val;
1887
1888 return count;
1889}
1890static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1891
5f2dc798 1892static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
c962024e 1893 char *buf)
1da177e4
LT		 1894{
1895 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1896
1897 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1da177e4
LT		 1898}
1899static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1900
738e5e05 1901static ssize_t show_label(struct device *dev, struct device_attribute *attr,
c962024e 1902 char *buf)
738e5e05 1903{
3c4c4971 1904 static const char * const labels[] = {
738e5e05
JD		 1905 "+5V",
1906 "5VSB",
1907 "Vbat",
1908 };
3c4c4971 1909 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1910 "+3.3V",
1911 "3VSB",
1912 "Vbat",
1913 };
1914 struct it87_data *data = dev_get_drvdata(dev);
738e5e05 1915 int nr = to_sensor_dev_attr(attr)->index;
ead80803 1916 const char *label;
738e5e05 1917
ead80803
JM		 1918 if (has_12mv_adc(data) || has_10_9mv_adc(data))
1919 label = labels_it8721[nr];
1920 else
1921 label = labels[nr];
1922
1923 return sprintf(buf, "%s\n", label);
738e5e05
JD		 1924}
1925static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1926static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1927static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
73055405 1928/* AVCC3 */
c145d5c6 1929static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1930
52929715
GR		 1931static umode_t it87_in_is_visible(struct kobject *kobj,
1932 struct attribute *attr, int index)
9172b5d1 1933{
52929715
GR		 1934 struct device *dev = container_of(kobj, struct device, kobj);
1935 struct it87_data *data = dev_get_drvdata(dev);
1936 int i = index / 5; /* voltage index */
1937 int a = index % 5; /* attribute index */
1938
f838aa26 1939 if (index >= 40) { /* in8 and higher only have input attributes */
52929715
GR		 1940 i = index - 40 + 8;
1941 a = 0;
1942 }
1943
48b2ae7f 1944 if (!(data->has_in & BIT(i)))
52929715
GR		 1945 return 0;
1946
1947 if (a == 4 && !data->has_beep)
1948 return 0;
1949
1950 return attr->mode;
1951}
1952
1953static struct attribute *it87_attributes_in[] = {
87808be4 1954 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1955 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1956 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1957 &sensor_dev_attr_in0_alarm.dev_attr.attr,
52929715
GR		 1958 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
1959
9172b5d1
GR		 1960 &sensor_dev_attr_in1_input.dev_attr.attr,
1961 &sensor_dev_attr_in1_min.dev_attr.attr,
1962 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1963 &sensor_dev_attr_in1_alarm.dev_attr.attr,
52929715
GR		 1964 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
1965
9172b5d1
GR		 1966 &sensor_dev_attr_in2_input.dev_attr.attr,
1967 &sensor_dev_attr_in2_min.dev_attr.attr,
1968 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1969 &sensor_dev_attr_in2_alarm.dev_attr.attr,
52929715
GR		 1970 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
1971
9172b5d1
GR		 1972 &sensor_dev_attr_in3_input.dev_attr.attr,
1973 &sensor_dev_attr_in3_min.dev_attr.attr,
1974 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1975 &sensor_dev_attr_in3_alarm.dev_attr.attr,
52929715
GR		 1976 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
1977
9172b5d1
GR		 1978 &sensor_dev_attr_in4_input.dev_attr.attr,
1979 &sensor_dev_attr_in4_min.dev_attr.attr,
1980 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1981 &sensor_dev_attr_in4_alarm.dev_attr.attr,
52929715
GR		 1982 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
1983
9172b5d1
GR		 1984 &sensor_dev_attr_in5_input.dev_attr.attr,
1985 &sensor_dev_attr_in5_min.dev_attr.attr,
1986 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1987 &sensor_dev_attr_in5_alarm.dev_attr.attr,
52929715
GR		 1988 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
1989
9172b5d1
GR		 1990 &sensor_dev_attr_in6_input.dev_attr.attr,
1991 &sensor_dev_attr_in6_min.dev_attr.attr,
1992 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1993 &sensor_dev_attr_in6_alarm.dev_attr.attr,
52929715
GR		 1994 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
1995
9172b5d1
GR		 1996 &sensor_dev_attr_in7_input.dev_attr.attr,
1997 &sensor_dev_attr_in7_min.dev_attr.attr,
1998 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1999 &sensor_dev_attr_in7_alarm.dev_attr.attr,
52929715
GR		 2000 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2001
2002 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
52929715 2003 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
f838aa26
GR		 2004 &sensor_dev_attr_in10_input.dev_attr.attr, /* 41 */
2005 &sensor_dev_attr_in11_input.dev_attr.attr, /* 41 */
2006 &sensor_dev_attr_in12_input.dev_attr.attr, /* 41 */
52929715
GR		 2007};
2008
2009static const struct attribute_group it87_group_in = {
2010 .attrs = it87_attributes_in,
2011 .is_visible = it87_in_is_visible,
9172b5d1
GR		 2012};
2013
87533770
GR		 2014static umode_t it87_temp_is_visible(struct kobject *kobj,
2015 struct attribute *attr, int index)
4573acbc 2016{
87533770
GR		 2017 struct device *dev = container_of(kobj, struct device, kobj);
2018 struct it87_data *data = dev_get_drvdata(dev);
2019 int i = index / 7; /* temperature index */
2020 int a = index % 7; /* attribute index */
2021
cc18da79
GR		 2022 if (index >= 21) {
2023 i = index - 21 + 3;
2024 a = 0;
2025 }
2026
48b2ae7f 2027 if (!(data->has_temp & BIT(i)))
87533770
GR		 2028 return 0;
2029
2030 if (a == 5 && !has_temp_offset(data))
2031 return 0;
2032
2033 if (a == 6 && !data->has_beep)
2034 return 0;
2035
2036 return attr->mode;
2037}
2038
2039static struct attribute *it87_attributes_temp[] = {
87808be4 2040 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 2041 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 2042 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 2043 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 2044 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
87533770
GR		 2045 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2046 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2047
cc18da79 2048 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
4573acbc
GR		 2049 &sensor_dev_attr_temp2_max.dev_attr.attr,
2050 &sensor_dev_attr_temp2_min.dev_attr.attr,
2051 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 2052 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
87533770
GR		 2053 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2054 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2055
cc18da79 2056 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
4573acbc
GR		 2057 &sensor_dev_attr_temp3_max.dev_attr.attr,
2058 &sensor_dev_attr_temp3_min.dev_attr.attr,
2059 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 2060 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
87533770
GR		 2061 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2062 &sensor_dev_attr_temp3_beep.dev_attr.attr,
4573acbc 2063
cc18da79
GR		 2064 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2065 &sensor_dev_attr_temp5_input.dev_attr.attr,
2066 &sensor_dev_attr_temp6_input.dev_attr.attr,
87533770 2067 NULL
4573acbc 2068};
87808be4 2069
87533770
GR		 2070static const struct attribute_group it87_group_temp = {
2071 .attrs = it87_attributes_temp,
2072 .is_visible = it87_temp_is_visible,
161d898a
GR		 2073};
2074
d3766848
GR		 2075static umode_t it87_is_visible(struct kobject *kobj,
2076 struct attribute *attr, int index)
2077{
2078 struct device *dev = container_of(kobj, struct device, kobj);
2079 struct it87_data *data = dev_get_drvdata(dev);
2080
8638d0af 2081 if ((index == 2 || index == 3) && !data->has_vid)
d3766848
GR		 2082 return 0;
2083
48b2ae7f 2084 if (index > 3 && !(data->in_internal & BIT(index - 4)))
d3766848
GR		 2085 return 0;
2086
2087 return attr->mode;
2088}
2089
4573acbc 2090static struct attribute *it87_attributes[] = {
87808be4 2091 &dev_attr_alarms.attr,
3d30f9e6 2092 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
8638d0af
GR		 2093 &dev_attr_vrm.attr, /* 2 */
2094 &dev_attr_cpu0_vid.attr, /* 3 */
2095 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
d3766848
GR		 2096 &sensor_dev_attr_in7_label.dev_attr.attr,
2097 &sensor_dev_attr_in8_label.dev_attr.attr,
2098 &sensor_dev_attr_in9_label.dev_attr.attr,
87808be4
JD		 2099 NULL
2100};
2101
2102static const struct attribute_group it87_group = {
2103 .attrs = it87_attributes,
d3766848 2104 .is_visible = it87_is_visible,
87808be4
JD		 2105};
2106
9a70ee81
GR		 2107static umode_t it87_fan_is_visible(struct kobject *kobj,
2108 struct attribute *attr, int index)
2109{
2110 struct device *dev = container_of(kobj, struct device, kobj);
2111 struct it87_data *data = dev_get_drvdata(dev);
2112 int i = index / 5; /* fan index */
2113 int a = index % 5; /* attribute index */
2114
2115 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2116 i = (index - 15) / 4 + 3;
2117 a = (index - 15) % 4;
2118 }
2119
48b2ae7f 2120 if (!(data->has_fan & BIT(i)))
9a70ee81
GR		 2121 return 0;
2122
2123 if (a == 3) { /* beep */
2124 if (!data->has_beep)
2125 return 0;
2126 /* first fan beep attribute is writable */
2127 if (i == __ffs(data->has_fan))
2128 return attr->mode | S_IWUSR;
2129 }
2130
2131 if (a == 4 && has_16bit_fans(data)) /* divisor */
2132 return 0;
2133
2134 return attr->mode;
2135}
2136
2137static struct attribute *it87_attributes_fan[] = {
e1169ba0
GR		 2138 &sensor_dev_attr_fan1_input.dev_attr.attr,
2139 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0 2140 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
9a70ee81
GR		 2141 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2142 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2143
e1169ba0
GR		 2144 &sensor_dev_attr_fan2_input.dev_attr.attr,
2145 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0 2146 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
9a70ee81
GR		 2147 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2148 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2149
e1169ba0
GR		 2150 &sensor_dev_attr_fan3_input.dev_attr.attr,
2151 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0 2152 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
9a70ee81
GR		 2153 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2154 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2155
2156 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
e1169ba0 2157 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0 2158 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
9a70ee81
GR		 2159 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2160
2161 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
e1169ba0 2162 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0 2163 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
9a70ee81
GR		 2164 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2165
2166 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
fa3f70d6
GR		 2167 &sensor_dev_attr_fan6_min.dev_attr.attr,
2168 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
9a70ee81 2169 &sensor_dev_attr_fan6_beep.dev_attr.attr,
fa3f70d6 2170 NULL
723a0aa0 2171};
87808be4 2172
9a70ee81
GR		 2173static const struct attribute_group it87_group_fan = {
2174 .attrs = it87_attributes_fan,
2175 .is_visible = it87_fan_is_visible,
723a0aa0
JD		 2176};
2177
5c391261
GR		 2178static umode_t it87_pwm_is_visible(struct kobject *kobj,
2179 struct attribute *attr, int index)
2180{
2181 struct device *dev = container_of(kobj, struct device, kobj);
2182 struct it87_data *data = dev_get_drvdata(dev);
2183 int i = index / 4; /* pwm index */
2184 int a = index % 4; /* attribute index */
2185
48b2ae7f 2186 if (!(data->has_pwm & BIT(i)))
5c391261
GR		 2187 return 0;
2188
2cbb9c37
GR		 2189 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2190 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
5c391261
GR		 2191 return attr->mode | S_IWUSR;
2192
2193 /* pwm2_freq is writable if there are two pwm frequency selects */
2194 if (has_pwm_freq2(data) && i == 1 && a == 2)
2195 return attr->mode | S_IWUSR;
2196
2197 return attr->mode;
2198}
2199
2200static struct attribute *it87_attributes_pwm[] = {
87808be4 2201 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 2202 &sensor_dev_attr_pwm1.dev_attr.attr,
60878bcf 2203 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
94ac7ee6 2204 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
5c391261 2205
723a0aa0
JD		 2206 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2207 &sensor_dev_attr_pwm2.dev_attr.attr,
60878bcf 2208 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
94ac7ee6 2209 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
5c391261 2210
723a0aa0
JD		 2211 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2212 &sensor_dev_attr_pwm3.dev_attr.attr,
60878bcf 2213 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
94ac7ee6 2214 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
5c391261 2215
36c4d98a
GR		 2216 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2217 &sensor_dev_attr_pwm4.dev_attr.attr,
60878bcf 2218 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
36c4d98a 2219 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
5c391261 2220
36c4d98a
GR		 2221 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2222 &sensor_dev_attr_pwm5.dev_attr.attr,
60878bcf 2223 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
36c4d98a 2224 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
5c391261 2225
36c4d98a
GR		 2226 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2227 &sensor_dev_attr_pwm6.dev_attr.attr,
60878bcf 2228 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
36c4d98a 2229 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
5c391261 2230
36c4d98a 2231 NULL
5c391261 2232};
87808be4 2233
5c391261
GR		 2234static const struct attribute_group it87_group_pwm = {
2235 .attrs = it87_attributes_pwm,
2236 .is_visible = it87_pwm_is_visible,
2237};
2238
2239static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2240 struct attribute *attr, int index)
60878bcf
GR		 2241{
2242 struct device *dev = container_of(kobj, struct device, kobj);
2243 struct it87_data *data = dev_get_drvdata(dev);
2cbb9c37
GR		 2244 int i = index / 11; /* pwm index */
2245 int a = index % 11; /* attribute index */
2246
2247 if (index >= 33) { /* pwm 4..6 */
2248 i = (index - 33) / 6 + 3;
2249 a = (index - 33) % 6 + 4;
2250 }
60878bcf 2251
48b2ae7f 2252 if (!(data->has_pwm & BIT(i)))
5c391261 2253 return 0;
60878bcf 2254
2cbb9c37
GR		 2255 if (has_newer_autopwm(data)) {
2256 if (a < 4) /* no auto point pwm */
2257 return 0;
2258 if (a == 8) /* no auto_point4 */
2259 return 0;
2260 }
2261 if (has_old_autopwm(data)) {
2262 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2263 return 0;
2264 }
2265
60878bcf
GR		 2266 return attr->mode;
2267}
2268
5c391261 2269static struct attribute *it87_attributes_auto_pwm[] = {
4f3f51bc
JD		 2270 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2271 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2272 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2273 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2274 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2275 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2276 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2277 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2278 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2cbb9c37
GR		 2279 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2280 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
5c391261 2281
2cbb9c37 2282 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
4f3f51bc
JD		 2283 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2284 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2285 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2286 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2287 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2288 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2289 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2290 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2cbb9c37
GR		 2291 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2292 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
5c391261 2293
2cbb9c37 2294 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
4f3f51bc
JD		 2295 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2296 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2297 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2298 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2299 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2300 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2301 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2302 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2cbb9c37
GR		 2303 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2304 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2305
2306 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2307 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2308 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2309 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2310 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2311 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2312
2313 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2314 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2315 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2316 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2317 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2318 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2319
2320 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2321 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2322 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2323 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2324 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2325 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
4f3f51bc 2326
5c391261
GR		 2327 NULL,
2328};
2329
2330static const struct attribute_group it87_group_auto_pwm = {
2331 .attrs = it87_attributes_auto_pwm,
2332 .is_visible = it87_auto_pwm_is_visible,
4f3f51bc
JD		 2333};
2334
2d8672c5 2335/* SuperIO detection - will change isa_address if a chip is found */
3c2e3512
GR		 2336static int __init it87_find(int sioaddr, unsigned short *address,
2337 struct it87_sio_data *sio_data)
1da177e4 2338{
5b0380c9 2339 int err;
b74f3fdd 2340 u16 chip_type;
98dd22c3 2341 const char *board_vendor, *board_name;
f83a9cb6 2342 const struct it87_devices *config;
1da177e4 2343
3c2e3512 2344 err = superio_enter(sioaddr);
5b0380c9
NG		 2345 if (err)
2346 return err;
2347
2348 err = -ENODEV;
3c2e3512 2349 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
b74f3fdd 2350
2351 switch (chip_type) {
2352 case IT8705F_DEVID:
2353 sio_data->type = it87;
2354 break;
2355 case IT8712F_DEVID:
2356 sio_data->type = it8712;
2357 break;
2358 case IT8716F_DEVID:
2359 case IT8726F_DEVID:
2360 sio_data->type = it8716;
2361 break;
2362 case IT8718F_DEVID:
2363 sio_data->type = it8718;
2364 break;
b4da93e4
JMS		 2365 case IT8720F_DEVID:
2366 sio_data->type = it8720;
2367 break;
44c1bcd4
JD		 2368 case IT8721F_DEVID:
2369 sio_data->type = it8721;
2370 break;
16b5dda2
JD		 2371 case IT8728F_DEVID:
2372 sio_data->type = it8728;
2373 break;
ead80803
JM		 2374 case IT8732F_DEVID:
2375 sio_data->type = it8732;
2376 break;
b0636707
GR		 2377 case IT8771E_DEVID:
2378 sio_data->type = it8771;
2379 break;
2380 case IT8772E_DEVID:
2381 sio_data->type = it8772;
2382 break;
7bc32d29
GR		 2383 case IT8781F_DEVID:
2384 sio_data->type = it8781;
2385 break;
0531d98b
GR		 2386 case IT8782F_DEVID:
2387 sio_data->type = it8782;
2388 break;
2389 case IT8783E_DEVID:
2390 sio_data->type = it8783;
2391 break;
a0c1424a
TL		 2392 case IT8786E_DEVID:
2393 sio_data->type = it8786;
2394 break;
4ee07157
GR		 2395 case IT8790E_DEVID:
2396 sio_data->type = it8790;
2397 break;
7183ae8c 2398 case IT8603E_DEVID:
574e9bd8 2399 case IT8623E_DEVID:
c145d5c6
RM		 2400 sio_data->type = it8603;
2401 break;
3ba9d977
GR		 2402 case IT8620E_DEVID:
2403 sio_data->type = it8620;
2404 break;
b74f3fdd 2405 case 0xffff: /* No device at all */
2406 goto exit;
2407 default:
a8ca1037 2408 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 2409 goto exit;
2410 }
1da177e4 2411
3c2e3512
GR		 2412 superio_select(sioaddr, PME);
2413 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
a8ca1037 2414 pr_info("Device not activated, skipping\n");
1da177e4
LT		 2415 goto exit;
2416 }
2417
3c2e3512 2418 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1da177e4 2419 if (*address == 0) {
a8ca1037 2420 pr_info("Base address not set, skipping\n");
1da177e4
LT		 2421 goto exit;
2422 }
2423
2424 err = 0;
3c2e3512 2425 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
faf392fb
GR		 2426 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2427 it87_devices[sio_data->type].suffix,
a0c1424a 2428 *address, sio_data->revision);
1da177e4 2429
f83a9cb6
GR		 2430 config = &it87_devices[sio_data->type];
2431
7f5726c3 2432 /* in7 (VSB or VCCH5V) is always internal on some chips */
f83a9cb6 2433 if (has_in7_internal(config))
48b2ae7f 2434 sio_data->internal |= BIT(1);
7f5726c3 2435
738e5e05 2436 /* in8 (Vbat) is always internal */
48b2ae7f 2437 sio_data->internal |= BIT(2);
7f5726c3 2438
73055405
GR		 2439 /* in9 (AVCC3), always internal if supported */
2440 if (has_avcc3(config))
48b2ae7f 2441 sio_data->internal |= BIT(3); /* in9 is AVCC */
73055405 2442 else
48b2ae7f 2443 sio_data->skip_in |= BIT(9);
738e5e05 2444
36c4d98a 2445 if (!has_six_pwm(config))
48b2ae7f 2446 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
36c4d98a 2447
f83a9cb6 2448 if (!has_vid(config))
895ff267 2449 sio_data->skip_vid = 1;
d9b327c3 2450
32dd7c40
GR		 2451 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2452 if (sio_data->type == it87) {
d9b327c3 2453 /* The IT8705F has a different LD number for GPIO */
3c2e3512
GR		 2454 superio_select(sioaddr, 5);
2455 sio_data->beep_pin = superio_inb(sioaddr,
2456 IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 2457 } else if (sio_data->type == it8783) {
088ce2ac 2458 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 2459
3c2e3512 2460 superio_select(sioaddr, GPIO);
0531d98b 2461
3c2e3512
GR		 2462 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2463 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2464 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2465 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2466 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
0531d98b 2467
0531d98b 2468 /* Check if fan3 is there or not */
48b2ae7f
GR		 2469 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2470 sio_data->skip_fan |= BIT(2);
c962024e
GR		 2471 if ((reg25 & BIT(4)) ||
2472 (!(reg2a & BIT(1)) && (regef & BIT(0))))
48b2ae7f 2473 sio_data->skip_pwm |= BIT(2);
0531d98b
GR		 2474
2475 /* Check if fan2 is there or not */
48b2ae7f
GR		 2476 if (reg27 & BIT(7))
2477 sio_data->skip_fan |= BIT(1);
2478 if (reg27 & BIT(3))
2479 sio_data->skip_pwm |= BIT(1);
0531d98b
GR		 2480
2481 /* VIN5 */
48b2ae7f
GR		 2482 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2483 sio_data->skip_in |= BIT(5); /* No VIN5 */
0531d98b
GR		 2484
2485 /* VIN6 */
48b2ae7f
GR		 2486 if (reg27 & BIT(1))
2487 sio_data->skip_in |= BIT(6); /* No VIN6 */
0531d98b
GR		 2488
2489 /*
2490 * VIN7
2491 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2492 */
48b2ae7f 2493 if (reg27 & BIT(2)) {
9172b5d1
GR		 2494 /*
2495 * The data sheet is a bit unclear regarding the
2496 * internal voltage divider for VCCH5V. It says
2497 * "This bit enables and switches VIN7 (pin 91) to the
2498 * internal voltage divider for VCCH5V".
2499 * This is different to other chips, where the internal
2500 * voltage divider would connect VIN7 to an internal
2501 * voltage source. Maybe that is the case here as well.
2502 *
2503 * Since we don't know for sure, re-route it if that is
2504 * not the case, and ask the user to report if the
2505 * resulting voltage is sane.
2506 */
48b2ae7f
GR		 2507 if (!(reg2c & BIT(1))) {
2508 reg2c |= BIT(1);
3c2e3512
GR		 2509 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2510 reg2c);
9172b5d1
GR		 2511 pr_notice("Routing internal VCCH5V to in7.\n");
2512 }
2513 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2514 pr_notice("Please report if it displays a reasonable voltage.\n");
2515 }
0531d98b 2516
48b2ae7f
GR		 2517 if (reg2c & BIT(0))
2518 sio_data->internal |= BIT(0);
2519 if (reg2c & BIT(1))
2520 sio_data->internal |= BIT(1);
0531d98b 2521
3c2e3512
GR		 2522 sio_data->beep_pin = superio_inb(sioaddr,
2523 IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 2524 } else if (sio_data->type == it8603) {
2525 int reg27, reg29;
2526
3c2e3512 2527 superio_select(sioaddr, GPIO);
0531d98b 2528
3c2e3512 2529 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
c145d5c6
RM		 2530
2531 /* Check if fan3 is there or not */
48b2ae7f
GR		 2532 if (reg27 & BIT(6))
2533 sio_data->skip_pwm |= BIT(2);
2534 if (reg27 & BIT(7))
2535 sio_data->skip_fan |= BIT(2);
c145d5c6
RM		 2536
2537 /* Check if fan2 is there or not */
3c2e3512 2538 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2539 if (reg29 & BIT(1))
2540 sio_data->skip_pwm |= BIT(1);
2541 if (reg29 & BIT(2))
2542 sio_data->skip_fan |= BIT(1);
c145d5c6 2543
48b2ae7f
GR		 2544 sio_data->skip_in |= BIT(5); /* No VIN5 */
2545 sio_data->skip_in |= BIT(6); /* No VIN6 */
c145d5c6 2546
3c2e3512
GR		 2547 sio_data->beep_pin = superio_inb(sioaddr,
2548 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3ba9d977
GR		 2549 } else if (sio_data->type == it8620) {
2550 int reg;
2551
3c2e3512 2552 superio_select(sioaddr, GPIO);
3ba9d977 2553
36c4d98a 2554 /* Check for pwm5 */
3c2e3512 2555 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
48b2ae7f
GR		 2556 if (reg & BIT(6))
2557 sio_data->skip_pwm |= BIT(4);
36c4d98a 2558
3ba9d977 2559 /* Check for fan4, fan5 */
3c2e3512 2560 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
48b2ae7f
GR		 2561 if (!(reg & BIT(5)))
2562 sio_data->skip_fan |= BIT(3);
2563 if (!(reg & BIT(4)))
2564 sio_data->skip_fan |= BIT(4);
3ba9d977
GR		 2565
2566 /* Check for pwm3, fan3 */
3c2e3512 2567 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
48b2ae7f
GR		 2568 if (reg & BIT(6))
2569 sio_data->skip_pwm |= BIT(2);
2570 if (reg & BIT(7))
2571 sio_data->skip_fan |= BIT(2);
3ba9d977 2572
36c4d98a 2573 /* Check for pwm4 */
3c2e3512 2574 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
48b2ae7f
GR		 2575 if (!(reg & BIT(2)))
2576 sio_data->skip_pwm |= BIT(3);
36c4d98a 2577
3ba9d977 2578 /* Check for pwm2, fan2 */
3c2e3512 2579 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2580 if (reg & BIT(1))
2581 sio_data->skip_pwm |= BIT(1);
2582 if (reg & BIT(2))
2583 sio_data->skip_fan |= BIT(1);
36c4d98a 2584 /* Check for pwm6, fan6 */
48b2ae7f
GR		 2585 if (!(reg & BIT(7))) {
2586 sio_data->skip_pwm |= BIT(5);
2587 sio_data->skip_fan |= BIT(5);
36c4d98a 2588 }
3ba9d977 2589
3c2e3512
GR		 2590 sio_data->beep_pin = superio_inb(sioaddr,
2591 IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 2592 } else {
87673dd7 2593 int reg;
9172b5d1 2594 bool uart6;
87673dd7 2595
3c2e3512 2596 superio_select(sioaddr, GPIO);
44c1bcd4 2597
a0df926d
GR		 2598 /* Check for fan4, fan5 */
2599 if (has_five_fans(config)) {
2600 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2601 switch (sio_data->type) {
2602 case it8718:
2603 if (reg & BIT(5))
2604 sio_data->skip_fan |= BIT(3);
2605 if (reg & BIT(4))
2606 sio_data->skip_fan |= BIT(4);
2607 break;
2608 case it8720:
2609 case it8721:
2610 case it8728:
2611 if (!(reg & BIT(5)))
2612 sio_data->skip_fan |= BIT(3);
2613 if (!(reg & BIT(4)))
2614 sio_data->skip_fan |= BIT(4);
2615 break;
2616 default:
2617 break;
2618 }
2619 }
2620
3c2e3512 2621 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
32dd7c40 2622 if (!sio_data->skip_vid) {
44c1bcd4
JD		 2623 /* We need at least 4 VID pins */
2624 if (reg & 0x0f) {
a8ca1037 2625 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 2626 sio_data->skip_vid = 1;
2627 }
895ff267
JD		 2628 }
2629
591ec650 2630 /* Check if fan3 is there or not */
48b2ae7f
GR		 2631 if (reg & BIT(6))
2632 sio_data->skip_pwm |= BIT(2);
2633 if (reg & BIT(7))
2634 sio_data->skip_fan |= BIT(2);
591ec650
JD		 2635
2636 /* Check if fan2 is there or not */
3c2e3512 2637 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2638 if (reg & BIT(1))
2639 sio_data->skip_pwm |= BIT(1);
2640 if (reg & BIT(2))
2641 sio_data->skip_fan |= BIT(1);
591ec650 2642
c962024e
GR		 2643 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2644 !(sio_data->skip_vid))
3c2e3512
GR		 2645 sio_data->vid_value = superio_inb(sioaddr,
2646 IT87_SIO_VID_REG);
87673dd7 2647
3c2e3512 2648 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
9172b5d1 2649
48b2ae7f 2650 uart6 = sio_data->type == it8782 && (reg & BIT(2));
9172b5d1 2651
436cad2a
JD		 2652 /*
2653 * The IT8720F has no VIN7 pin, so VCCH should always be
2654 * routed internally to VIN7 with an internal divider.
2655 * Curiously, there still is a configuration bit to control
2656 * this, which means it can be set incorrectly. And even
2657 * more curiously, many boards out there are improperly
2658 * configured, even though the IT8720F datasheet claims
2659 * that the internal routing of VCCH to VIN7 is the default
2660 * setting. So we force the internal routing in this case.
0531d98b
GR		 2661 *
2662 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2663 * If UART6 is enabled, re-route VIN7 to the internal divider
2664 * if that is not already the case.
436cad2a 2665 */
48b2ae7f
GR		 2666 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2667 reg |= BIT(1);
3c2e3512 2668 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
a8ca1037 2669 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2670 }
48b2ae7f
GR		 2671 if (reg & BIT(0))
2672 sio_data->internal |= BIT(0);
2673 if (reg & BIT(1))
2674 sio_data->internal |= BIT(1);
d9b327c3 2675
9172b5d1
GR		 2676 /*
2677 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2678 * While VIN7 can be routed to the internal voltage divider,
2679 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2680 *
2681 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2682 * is the temperature source. Since we can not read the
2683 * temperature source here, skip_temp is preliminary.
9172b5d1 2684 */
4573acbc 2685 if (uart6) {
48b2ae7f
GR		 2686 sio_data->skip_in |= BIT(5) | BIT(6);
2687 sio_data->skip_temp |= BIT(2);
4573acbc 2688 }
9172b5d1 2689
3c2e3512
GR		 2690 sio_data->beep_pin = superio_inb(sioaddr,
2691 IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2692 }
d9b327c3 2693 if (sio_data->beep_pin)
a8ca1037 2694 pr_info("Beeping is supported\n");
87673dd7 2695
98dd22c3
JD		 2696 /* Disable specific features based on DMI strings */
2697 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2698 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2699 if (board_vendor && board_name) {
c962024e
GR		 2700 if (strcmp(board_vendor, "nVIDIA") == 0 &&
2701 strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2702 /*
2703 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2704 * connected to a fan, but to something else. One user
2705 * has reported instant system power-off when changing
2706 * the PWM2 duty cycle, so we disable it.
2707 * I use the board name string as the trigger in case
2708 * the same board is ever used in other systems.
2709 */
a8ca1037 2710 pr_info("Disabling pwm2 due to hardware constraints\n");
48b2ae7f 2711 sio_data->skip_pwm = BIT(1);
98dd22c3
JD		 2712 }
2713 }
2714
1da177e4 2715exit:
3c2e3512 2716 superio_exit(sioaddr);
1da177e4
LT		 2717 return err;
2718}
2719
c1e7a4ca
GR		 2720/* Called when we have found a new IT87. */
2721static void it87_init_device(struct platform_device *pdev)
1da177e4 2722{
c1e7a4ca
GR		 2723 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2724 struct it87_data *data = platform_get_drvdata(pdev);
2725 int tmp, i;
2726 u8 mask;
b74f3fdd 2727
c1e7a4ca
GR		 2728 /*
2729 * For each PWM channel:
2730 * - If it is in automatic mode, setting to manual mode should set
2731 * the fan to full speed by default.
2732 * - If it is in manual mode, we need a mapping to temperature
2733 * channels to use when later setting to automatic mode later.
2734 * Use a 1:1 mapping by default (we are clueless.)
2735 * In both cases, the value can (and should) be changed by the user
2736 * prior to switching to a different mode.
2737 * Note that this is no longer needed for the IT8721F and later, as
2738 * these have separate registers for the temperature mapping and the
2739 * manual duty cycle.
2740 */
2310048d 2741 for (i = 0; i < NUM_AUTO_PWM; i++) {
c1e7a4ca
GR		 2742 data->pwm_temp_map[i] = i;
2743 data->pwm_duty[i] = 0x7f; /* Full speed */
2744 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
8e9afcbb 2745 }
1da177e4 2746
483db43e 2747 /*
c1e7a4ca
GR		 2748 * Some chips seem to have default value 0xff for all limit
2749 * registers. For low voltage limits it makes no sense and triggers
2750 * alarms, so change to 0 instead. For high temperature limits, it
2751 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2752 * but is still confusing, so change to 127 degrees C.
483db43e 2753 */
2310048d 2754 for (i = 0; i < NUM_VIN_LIMIT; i++) {
c1e7a4ca
GR		 2755 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2756 if (tmp == 0xff)
2757 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2758 }
2310048d 2759 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
c1e7a4ca
GR		 2760 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2761 if (tmp == 0xff)
2762 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
483db43e 2763 }
1da177e4 2764
c1e7a4ca
GR		 2765 /*
2766 * Temperature channels are not forcibly enabled, as they can be
2767 * set to two different sensor types and we can't guess which one
2768 * is correct for a given system. These channels can be enabled at
2769 * run-time through the temp{1-3}_type sysfs accessors if needed.
2770 */
1da177e4 2771
c1e7a4ca
GR		 2772 /* Check if voltage monitors are reset manually or by some reason */
2773 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2774 if ((tmp & 0xff) == 0) {
2775 /* Enable all voltage monitors */
2776 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2777 }
2778
2779 /* Check if tachometers are reset manually or by some reason */
2780 mask = 0x70 & ~(sio_data->skip_fan << 4);
2781 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2782 if ((data->fan_main_ctrl & mask) == 0) {
2783 /* Enable all fan tachometers */
2784 data->fan_main_ctrl |= mask;
2785 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2786 data->fan_main_ctrl);
2787 }
2788 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2789
2790 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2791
2792 /* Set tachometers to 16-bit mode if needed */
2793 if (has_fan16_config(data)) {
2794 if (~tmp & 0x07 & data->has_fan) {
2795 dev_dbg(&pdev->dev,
2796 "Setting fan1-3 to 16-bit mode\n");
2797 it87_write_value(data, IT87_REG_FAN_16BIT,
2798 tmp | 0x07);
2799 }
2800 }
2801
2802 /* Check for additional fans */
2803 if (has_five_fans(data)) {
48b2ae7f
GR		 2804 if (tmp & BIT(4))
2805 data->has_fan |= BIT(3); /* fan4 enabled */
2806 if (tmp & BIT(5))
2807 data->has_fan |= BIT(4); /* fan5 enabled */
2808 if (has_six_fans(data) && (tmp & BIT(2)))
2809 data->has_fan |= BIT(5); /* fan6 enabled */
c1e7a4ca
GR		 2810 }
2811
2812 /* Fan input pins may be used for alternative functions */
2813 data->has_fan &= ~sio_data->skip_fan;
2814
2815 /* Check if pwm5, pwm6 are enabled */
2816 if (has_six_pwm(data)) {
2817 /* The following code may be IT8620E specific */
2818 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2819 if ((tmp & 0xc0) == 0xc0)
48b2ae7f
GR		 2820 sio_data->skip_pwm |= BIT(4);
2821 if (!(tmp & BIT(3)))
2822 sio_data->skip_pwm |= BIT(5);
c1e7a4ca
GR		 2823 }
2824
2825 /* Start monitoring */
2826 it87_write_value(data, IT87_REG_CONFIG,
2827 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2828 | (update_vbat ? 0x41 : 0x01));
2829}
2830
2831/* Return 1 if and only if the PWM interface is safe to use */
2832static int it87_check_pwm(struct device *dev)
2833{
2834 struct it87_data *data = dev_get_drvdata(dev);
2835 /*
2836 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2837 * and polarity set to active low is sign that this is the case so we
2838 * disable pwm control to protect the user.
2839 */
2840 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2841
2842 if ((tmp & 0x87) == 0) {
2843 if (fix_pwm_polarity) {
2844 /*
2845 * The user asks us to attempt a chip reconfiguration.
2846 * This means switching to active high polarity and
2847 * inverting all fan speed values.
2848 */
2849 int i;
2850 u8 pwm[3];
2851
2310048d 2852 for (i = 0; i < ARRAY_SIZE(pwm); i++)
c1e7a4ca
GR		 2853 pwm[i] = it87_read_value(data,
2854 IT87_REG_PWM[i]);
2855
2856 /*
2857 * If any fan is in automatic pwm mode, the polarity
2858 * might be correct, as suspicious as it seems, so we
2859 * better don't change anything (but still disable the
2860 * PWM interface).
2861 */
2862 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2863 dev_info(dev,
2864 "Reconfiguring PWM to active high polarity\n");
2865 it87_write_value(data, IT87_REG_FAN_CTL,
2866 tmp | 0x87);
2867 for (i = 0; i < 3; i++)
2868 it87_write_value(data,
2869 IT87_REG_PWM[i],
2870 0x7f & ~pwm[i]);
2871 return 1;
2872 }
2873
2874 dev_info(dev,
2875 "PWM configuration is too broken to be fixed\n");
2876 }
2877
2878 dev_info(dev,
2879 "Detected broken BIOS defaults, disabling PWM interface\n");
2880 return 0;
2881 } else if (fix_pwm_polarity) {
2882 dev_info(dev,
2883 "PWM configuration looks sane, won't touch\n");
2884 }
2885
2886 return 1;
2887}
2888
2889static int it87_probe(struct platform_device *pdev)
2890{
2891 struct it87_data *data;
2892 struct resource *res;
2893 struct device *dev = &pdev->dev;
2894 struct it87_sio_data *sio_data = dev_get_platdata(dev);
c1e7a4ca 2895 int enable_pwm_interface;
8638d0af 2896 struct device *hwmon_dev;
c1e7a4ca
GR		 2897
2898 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2899 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2900 DRVNAME)) {
2901 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2902 (unsigned long)res->start,
2903 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
2904 return -EBUSY;
2905 }
2906
2907 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2908 if (!data)
2909 return -ENOMEM;
2910
2911 data->addr = res->start;
2912 data->type = sio_data->type;
2913 data->features = it87_devices[sio_data->type].features;
2914 data->peci_mask = it87_devices[sio_data->type].peci_mask;
2915 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
c1e7a4ca
GR		 2916 /*
2917 * IT8705F Datasheet 0.4.1, 3h == Version G.
2918 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2919 * These are the first revisions with 16-bit tachometer support.
2920 */
2921 switch (data->type) {
2922 case it87:
2923 if (sio_data->revision >= 0x03) {
2924 data->features &= ~FEAT_OLD_AUTOPWM;
2925 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
2926 }
2927 break;
2928 case it8712:
2929 if (sio_data->revision >= 0x08) {
2930 data->features &= ~FEAT_OLD_AUTOPWM;
2931 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2932 FEAT_FIVE_FANS;
2933 }
2934 break;
2935 default:
2936 break;
2937 }
2938
2939 /* Now, we do the remaining detection. */
c962024e
GR		 2940 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
2941 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
c1e7a4ca
GR		 2942 return -ENODEV;
2943
2944 platform_set_drvdata(pdev, data);
1da177e4 2945
9a61bf63 2946 mutex_init(&data->update_lock);
1da177e4 2947
1da177e4 2948 /* Check PWM configuration */
b74f3fdd 2949 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2950
44c1bcd4 2951 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2952 if (has_12mv_adc(data)) {
48b2ae7f
GR		 2953 if (sio_data->internal & BIT(0))
2954 data->in_scaled |= BIT(3); /* in3 is AVCC */
2955 if (sio_data->internal & BIT(1))
2956 data->in_scaled |= BIT(7); /* in7 is VSB */
2957 if (sio_data->internal & BIT(2))
2958 data->in_scaled |= BIT(8); /* in8 is Vbat */
2959 if (sio_data->internal & BIT(3))
2960 data->in_scaled |= BIT(9); /* in9 is AVCC */
7bc32d29
GR		 2961 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2962 sio_data->type == it8783) {
48b2ae7f
GR		 2963 if (sio_data->internal & BIT(0))
2964 data->in_scaled |= BIT(3); /* in3 is VCC5V */
2965 if (sio_data->internal & BIT(1))
2966 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
44c1bcd4
JD		 2967 }
2968
4573acbc 2969 data->has_temp = 0x07;
48b2ae7f 2970 if (sio_data->skip_temp & BIT(2)) {
c962024e
GR		 2971 if (sio_data->type == it8782 &&
2972 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
48b2ae7f 2973 data->has_temp &= ~BIT(2);
4573acbc
GR		 2974 }
2975
d3766848 2976 data->in_internal = sio_data->internal;
52929715
GR		 2977 data->has_in = 0x3ff & ~sio_data->skip_in;
2978
cc18da79
GR		 2979 if (has_six_temp(data)) {
2980 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
2981
f838aa26 2982 /* Check for additional temperature sensors */
cc18da79 2983 if ((reg & 0x03) >= 0x02)
48b2ae7f 2984 data->has_temp |= BIT(3);
cc18da79 2985 if (((reg >> 2) & 0x03) >= 0x02)
48b2ae7f 2986 data->has_temp |= BIT(4);
cc18da79 2987 if (((reg >> 4) & 0x03) >= 0x02)
48b2ae7f 2988 data->has_temp |= BIT(5);
f838aa26
GR		 2989
2990 /* Check for additional voltage sensors */
2991 if ((reg & 0x03) == 0x01)
48b2ae7f 2992 data->has_in |= BIT(10);
f838aa26 2993 if (((reg >> 2) & 0x03) == 0x01)
48b2ae7f 2994 data->has_in |= BIT(11);
f838aa26 2995 if (((reg >> 4) & 0x03) == 0x01)
48b2ae7f 2996 data->has_in |= BIT(12);
cc18da79
GR		 2997 }
2998
52929715
GR		 2999 data->has_beep = !!sio_data->beep_pin;
3000
1da177e4 3001 /* Initialize the IT87 chip */
b74f3fdd 3002 it87_init_device(pdev);
1da177e4 3003
d3766848
GR		 3004 if (!sio_data->skip_vid) {
3005 data->has_vid = true;
3006 data->vrm = vid_which_vrm();
3007 /* VID reading from Super-I/O config space if available */
3008 data->vid = sio_data->vid_value;
3009 }
3010
8638d0af
GR		 3011 /* Prepare for sysfs hooks */
3012 data->groups[0] = &it87_group;
3013 data->groups[1] = &it87_group_in;
3014 data->groups[2] = &it87_group_temp;
3015 data->groups[3] = &it87_group_fan;
17d648bf 3016
1da177e4 3017 if (enable_pwm_interface) {
48b2ae7f 3018 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
5c391261 3019 data->has_pwm &= ~sio_data->skip_pwm;
4f3f51bc 3020
8638d0af 3021 data->groups[4] = &it87_group_pwm;
2cbb9c37 3022 if (has_old_autopwm(data) || has_newer_autopwm(data))
8638d0af 3023 data->groups[5] = &it87_group_auto_pwm;
1da177e4
LT		 3024 }
3025
8638d0af
GR		 3026 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3027 it87_devices[sio_data->type].name,
3028 data, data->groups);
3029 return PTR_ERR_OR_ZERO(hwmon_dev);
1da177e4
LT		 3030}
3031
c1e7a4ca
GR		 3032static struct platform_driver it87_driver = {
3033 .driver = {
3034 .name = DRVNAME,
3035 },
3036 .probe = it87_probe,
c1e7a4ca 3037};
1da177e4 3038
e84bd953 3039static int __init it87_device_add(int index, unsigned short address,
b74f3fdd 3040 const struct it87_sio_data *sio_data)
3041{
8e50e3c3 3042 struct platform_device *pdev;
b74f3fdd 3043 struct resource res = {
87b4b663
BH		 3044 .start = address + IT87_EC_OFFSET,
3045 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 3046 .name = DRVNAME,
3047 .flags = IORESOURCE_IO,
3048 };
3049 int err;
3050
b9acb64a
JD		 3051 err = acpi_check_resource_conflict(&res);
3052 if (err)
5cae84a5 3053 return err;
b9acb64a 3054
b74f3fdd 3055 pdev = platform_device_alloc(DRVNAME, address);
5cae84a5
GR		 3056 if (!pdev)
3057 return -ENOMEM;
b74f3fdd 3058
3059 err = platform_device_add_resources(pdev, &res, 1);
3060 if (err) {
a8ca1037 3061 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 3062 goto exit_device_put;
3063 }
3064
3065 err = platform_device_add_data(pdev, sio_data,
3066 sizeof(struct it87_sio_data));
3067 if (err) {
a8ca1037 3068 pr_err("Platform data allocation failed\n");
b74f3fdd 3069 goto exit_device_put;
3070 }
3071
3072 err = platform_device_add(pdev);
3073 if (err) {
a8ca1037 3074 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 3075 goto exit_device_put;
3076 }
3077
e84bd953 3078 it87_pdev[index] = pdev;
b74f3fdd 3079 return 0;
3080
3081exit_device_put:
3082 platform_device_put(pdev);
b74f3fdd 3083 return err;
3084}
3085
1da177e4
LT		 3086static int __init sm_it87_init(void)
3087{
e84bd953 3088 int sioaddr[2] = { REG_2E, REG_4E };
b74f3fdd 3089 struct it87_sio_data sio_data;
e84bd953
GR		 3090 unsigned short isa_address;
3091 bool found = false;
3092 int i, err;
b74f3fdd 3093
b74f3fdd 3094 err = platform_driver_register(&it87_driver);
3095 if (err)
3096 return err;
fde09509 3097
e84bd953
GR		 3098 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3099 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3100 isa_address = 0;
3101 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3102 if (err || isa_address == 0)
3103 continue;
3104
3105 err = it87_device_add(i, isa_address, &sio_data);
3106 if (err)
3107 goto exit_dev_unregister;
3108 found = true;
b74f3fdd 3109 }
3110
e84bd953
GR		 3111 if (!found) {
3112 err = -ENODEV;
3113 goto exit_unregister;
3114 }
b74f3fdd 3115 return 0;
e84bd953
GR		 3116
3117exit_dev_unregister:
3118 /* NULL check handled by platform_device_unregister */
3119 platform_device_unregister(it87_pdev[0]);
3120exit_unregister:
3121 platform_driver_unregister(&it87_driver);
3122 return err;
1da177e4
LT		 3123}
3124
3125static void __exit sm_it87_exit(void)
3126{
e84bd953
GR		 3127 /* NULL check handled by platform_device_unregister */
3128 platform_device_unregister(it87_pdev[1]);
3129 platform_device_unregister(it87_pdev[0]);
b74f3fdd 3130 platform_driver_unregister(&it87_driver);
1da177e4
LT		 3131}
3132
7c81c60f 3133MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 3134MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 3135module_param(update_vbat, bool, 0);
3136MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3137module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 3138MODULE_PARM_DESC(fix_pwm_polarity,
3139 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 3140MODULE_LICENSE("GPL");
3141
3142module_init(sm_it87_init);
3143module_exit(sm_it87_exit);
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