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hwmon: (it87) Use defines for array sizes and sensor counts
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / it87.c
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1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
3ba9d977 14 * IT8620E Super I/O chip w/LPC interface
574e9bd8 15 * IT8623E Super I/O chip w/LPC interface
c145d5c6 16 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 17 * IT8712F Super I/O chip w/LPC interface
18 * IT8716F Super I/O chip w/LPC interface
19 * IT8718F Super I/O chip w/LPC interface
20 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8721F Super I/O chip w/LPC interface
5f2dc798 22 * IT8726F Super I/O chip w/LPC interface
16b5dda2 23 * IT8728F Super I/O chip w/LPC interface
ead80803 24 * IT8732F Super I/O chip w/LPC interface
44c1bcd4 25 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 26 * IT8771E Super I/O chip w/LPC interface
27 * IT8772E Super I/O chip w/LPC interface
7bc32d29 28 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 29 * IT8782F Super I/O chip w/LPC interface
30 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 31 * IT8786E Super I/O chip w/LPC interface
4ee07157 32 * IT8790E Super I/O chip w/LPC interface
5f2dc798
JD		 33 * Sis950 A clone of the IT8705F
34 *
35 * Copyright (C) 2001 Chris Gauthron
7c81c60f 36 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License as published by
40 * the Free Software Foundation; either version 2 of the License, or
41 * (at your option) any later version.
42 *
43 * This program is distributed in the hope that it will be useful,
44 * but WITHOUT ANY WARRANTY; without even the implied warranty of
45 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 * GNU General Public License for more details.
47 *
48 * You should have received a copy of the GNU General Public License
49 * along with this program; if not, write to the Free Software
50 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
51 */
1da177e4 52
a8ca1037
JP		 53#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54
48b2ae7f 55#include <linux/bitops.h>
1da177e4
LT		 56#include <linux/module.h>
57#include <linux/init.h>
58#include <linux/slab.h>
59#include <linux/jiffies.h>
b74f3fdd 60#include <linux/platform_device.h>
943b0830 61#include <linux/hwmon.h>
303760b4
JD		 62#include <linux/hwmon-sysfs.h>
63#include <linux/hwmon-vid.h>
943b0830 64#include <linux/err.h>
9a61bf63 65#include <linux/mutex.h>
87808be4 66#include <linux/sysfs.h>
98dd22c3
JD		 67#include <linux/string.h>
68#include <linux/dmi.h>
b9acb64a 69#include <linux/acpi.h>
6055fae8 70#include <linux/io.h>
1da177e4 71
b74f3fdd 72#define DRVNAME "it87"
1da177e4 73
ead80803
JM		 74enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
75 it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
76 it8620 };
1da177e4 77
67b671bc
JD		 78static unsigned short force_id;
79module_param(force_id, ushort, 0);
80MODULE_PARM_DESC(force_id, "Override the detected device ID");
81
e84bd953 82static struct platform_device *it87_pdev[2];
b74f3fdd 83
3c2e3512 84#define REG_2E 0x2e /* The register to read/write */
e84bd953 85#define REG_4E 0x4e /* Secondary register to read/write */
3c2e3512 86
1da177e4 87#define DEV 0x07 /* Register: Logical device select */
1da177e4 88#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 89
90/* The device with the IT8718F/IT8720F VID value in it */
91#define GPIO 0x07
92
1da177e4
LT		 93#define DEVID 0x20 /* Register: Device ID */
94#define DEVREV 0x22 /* Register: Device Revision */
95
3c2e3512 96static inline int superio_inb(int ioreg, int reg)
1da177e4 97{
3c2e3512
GR		 98 outb(reg, ioreg);
99 return inb(ioreg + 1);
1da177e4
LT		 100}
101
3c2e3512 102static inline void superio_outb(int ioreg, int reg, int val)
436cad2a 103{
3c2e3512
GR		 104 outb(reg, ioreg);
105 outb(val, ioreg + 1);
436cad2a
JD		 106}
107
3c2e3512 108static int superio_inw(int ioreg, int reg)
1da177e4
LT		 109{
110 int val;
3c2e3512
GR		 111 outb(reg++, ioreg);
112 val = inb(ioreg + 1) << 8;
113 outb(reg, ioreg);
114 val |= inb(ioreg + 1);
1da177e4
LT		 115 return val;
116}
117
3c2e3512 118static inline void superio_select(int ioreg, int ldn)
1da177e4 119{
3c2e3512
GR		 120 outb(DEV, ioreg);
121 outb(ldn, ioreg + 1);
1da177e4
LT		 122}
123
3c2e3512 124static inline int superio_enter(int ioreg)
1da177e4 125{
5b0380c9 126 /*
3c2e3512 127 * Try to reserve ioreg and ioreg + 1 for exclusive access.
5b0380c9 128 */
3c2e3512 129 if (!request_muxed_region(ioreg, 2, DRVNAME))
5b0380c9
NG		 130 return -EBUSY;
131
3c2e3512
GR		 132 outb(0x87, ioreg);
133 outb(0x01, ioreg);
134 outb(0x55, ioreg);
e84bd953 135 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
5b0380c9 136 return 0;
1da177e4
LT		 137}
138
3c2e3512 139static inline void superio_exit(int ioreg)
1da177e4 140{
3c2e3512
GR		 141 outb(0x02, ioreg);
142 outb(0x02, ioreg + 1);
143 release_region(ioreg, 2);
1da177e4
LT		 144}
145
87673dd7 146/* Logical device 4 registers */
1da177e4
LT		 147#define IT8712F_DEVID 0x8712
148#define IT8705F_DEVID 0x8705
17d648bf 149#define IT8716F_DEVID 0x8716
87673dd7 150#define IT8718F_DEVID 0x8718
b4da93e4 151#define IT8720F_DEVID 0x8720
44c1bcd4 152#define IT8721F_DEVID 0x8721
08a8f6e9 153#define IT8726F_DEVID 0x8726
16b5dda2 154#define IT8728F_DEVID 0x8728
ead80803 155#define IT8732F_DEVID 0x8732
b0636707
GR		 156#define IT8771E_DEVID 0x8771
157#define IT8772E_DEVID 0x8772
7bc32d29 158#define IT8781F_DEVID 0x8781
0531d98b
GR		 159#define IT8782F_DEVID 0x8782
160#define IT8783E_DEVID 0x8783
a0c1424a 161#define IT8786E_DEVID 0x8786
4ee07157 162#define IT8790E_DEVID 0x8790
7183ae8c 163#define IT8603E_DEVID 0x8603
3ba9d977 164#define IT8620E_DEVID 0x8620
574e9bd8 165#define IT8623E_DEVID 0x8623
1da177e4
LT		 166#define IT87_ACT_REG 0x30
167#define IT87_BASE_REG 0x60
168
87673dd7 169/* Logical device 7 registers (IT8712F and later) */
0531d98b 170#define IT87_SIO_GPIO1_REG 0x25
3ba9d977 171#define IT87_SIO_GPIO2_REG 0x26
895ff267 172#define IT87_SIO_GPIO3_REG 0x27
36c4d98a 173#define IT87_SIO_GPIO4_REG 0x28
591ec650 174#define IT87_SIO_GPIO5_REG 0x29
0531d98b 175#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 176#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 177#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 178#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 179#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 180
1da177e4 181/* Update battery voltage after every reading if true */
90ab5ee9 182static bool update_vbat;
1da177e4
LT		 183
184/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 185static bool fix_pwm_polarity;
1da177e4 186
1da177e4
LT		 187/* Many IT87 constants specified below */
188
189/* Length of ISA address segment */
190#define IT87_EXTENT 8
191
87b4b663
BH		 192/* Length of ISA address segment for Environmental Controller */
193#define IT87_EC_EXTENT 2
194
195/* Offset of EC registers from ISA base address */
196#define IT87_EC_OFFSET 5
197
198/* Where are the ISA address/data registers relative to the EC base address */
199#define IT87_ADDR_REG_OFFSET 0
200#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 201
202/*----- The IT87 registers -----*/
203
204#define IT87_REG_CONFIG 0x00
205
206#define IT87_REG_ALARM1 0x01
207#define IT87_REG_ALARM2 0x02
208#define IT87_REG_ALARM3 0x03
209
4a0d71cf
GR		 210/*
211 * The IT8718F and IT8720F have the VID value in a different register, in
212 * Super-I/O configuration space.
213 */
1da177e4 214#define IT87_REG_VID 0x0a
4a0d71cf
GR		 215/*
216 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
217 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
218 * mode.
219 */
1da177e4 220#define IT87_REG_FAN_DIV 0x0b
17d648bf 221#define IT87_REG_FAN_16BIT 0x0c
1da177e4 222
f838aa26
GR		 223/*
224 * Monitors:
225 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
226 * - up to 6 temp (1 to 6)
227 * - up to 6 fan (1 to 6)
228 */
1da177e4 229
fa3f70d6
GR		 230static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
231static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
232static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
233static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
234static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
161d898a 235
1da177e4
LT		 236#define IT87_REG_FAN_MAIN_CTRL 0x13
237#define IT87_REG_FAN_CTL 0x14
36c4d98a
GR		 238static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
239static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
1da177e4 240
559313c4 241static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
f838aa26 242 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
1da177e4 243
559313c4 244#define IT87_REG_TEMP(nr) (0x29 + (nr))
73055405 245
1da177e4
LT		 246#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
247#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
248#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
249#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
250
1da177e4
LT		 251#define IT87_REG_VIN_ENABLE 0x50
252#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 253#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 254#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 255
256#define IT87_REG_CHIPID 0x58
257
4f3f51bc
JD		 258#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
259#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
260
cc18da79
GR		 261#define IT87_REG_TEMP456_ENABLE 0x77
262
2310048d
GR		 263#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
264#define NUM_VIN_LIMIT 8
265#define NUM_TEMP 6
266#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
267#define NUM_TEMP_LIMIT 3
268#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
269#define NUM_FAN_DIV 3
270#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
271#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
272
483db43e
GR		 273struct it87_devices {
274 const char *name;
faf392fb 275 const char * const suffix;
cc18da79 276 u32 features;
19529784
GR		 277 u8 peci_mask;
278 u8 old_peci_mask;
483db43e
GR		 279};
280
48b2ae7f
GR		 281#define FEAT_12MV_ADC BIT(0)
282#define FEAT_NEWER_AUTOPWM BIT(1)
283#define FEAT_OLD_AUTOPWM BIT(2)
284#define FEAT_16BIT_FANS BIT(3)
285#define FEAT_TEMP_OFFSET BIT(4)
286#define FEAT_TEMP_PECI BIT(5)
287#define FEAT_TEMP_OLD_PECI BIT(6)
288#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
289#define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
290#define FEAT_VID BIT(9) /* Set if chip supports VID */
291#define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
292#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
293#define FEAT_10_9MV_ADC BIT(12)
294#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
295#define FEAT_SIX_PWM BIT(14) /* Chip supports 6 pwm chn */
296#define FEAT_PWM_FREQ2 BIT(15) /* Separate pwm freq 2 */
297#define FEAT_SIX_TEMP BIT(16) /* Up to 6 temp sensors */
483db43e
GR		 298
299static const struct it87_devices it87_devices[] = {
300 [it87] = {
301 .name = "it87",
faf392fb 302 .suffix = "F",
483db43e
GR		 303 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
304 },
305 [it8712] = {
306 .name = "it8712",
faf392fb 307 .suffix = "F",
32dd7c40
GR		 308 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
309 /* may need to overwrite */
483db43e
GR		 310 },
311 [it8716] = {
312 .name = "it8716",
faf392fb 313 .suffix = "F",
32dd7c40 314 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf 315 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
483db43e
GR		 316 },
317 [it8718] = {
318 .name = "it8718",
faf392fb 319 .suffix = "F",
32dd7c40 320 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 321 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
322 | FEAT_PWM_FREQ2,
19529784 323 .old_peci_mask = 0x4,
483db43e
GR		 324 },
325 [it8720] = {
326 .name = "it8720",
faf392fb 327 .suffix = "F",
32dd7c40 328 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 329 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
330 | FEAT_PWM_FREQ2,
19529784 331 .old_peci_mask = 0x4,
483db43e
GR		 332 },
333 [it8721] = {
334 .name = "it8721",
faf392fb 335 .suffix = "F",
483db43e 336 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 337 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
60878bcf
GR		 338 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
339 | FEAT_PWM_FREQ2,
5d8d2f2b 340 .peci_mask = 0x05,
19529784 341 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 342 },
343 [it8728] = {
344 .name = "it8728",
faf392fb 345 .suffix = "F",
483db43e 346 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 347 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
60878bcf 348 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
5d8d2f2b 349 .peci_mask = 0x07,
483db43e 350 },
ead80803
JM		 351 [it8732] = {
352 .name = "it8732",
353 .suffix = "F",
354 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
355 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
356 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
357 .peci_mask = 0x07,
358 .old_peci_mask = 0x02, /* Actually reports PCH */
359 },
b0636707
GR		 360 [it8771] = {
361 .name = "it8771",
faf392fb 362 .suffix = "E",
b0636707 363 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 364 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
365 | FEAT_PWM_FREQ2,
9faf28ca
GR		 366 /* PECI: guesswork */
367 /* 12mV ADC (OHM) */
368 /* 16 bit fans (OHM) */
369 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 370 .peci_mask = 0x07,
371 },
372 [it8772] = {
373 .name = "it8772",
faf392fb 374 .suffix = "E",
b0636707 375 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 376 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
377 | FEAT_PWM_FREQ2,
9faf28ca
GR		 378 /* PECI (coreboot) */
379 /* 12mV ADC (HWSensors4, OHM) */
380 /* 16 bit fans (HWSensors4, OHM) */
381 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 382 .peci_mask = 0x07,
383 },
7bc32d29
GR		 384 [it8781] = {
385 .name = "it8781",
faf392fb 386 .suffix = "F",
7bc32d29 387 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 388 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
7bc32d29
GR		 389 .old_peci_mask = 0x4,
390 },
483db43e
GR		 391 [it8782] = {
392 .name = "it8782",
faf392fb 393 .suffix = "F",
19529784 394 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 395 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 396 .old_peci_mask = 0x4,
483db43e
GR		 397 },
398 [it8783] = {
399 .name = "it8783",
faf392fb 400 .suffix = "E/F",
19529784 401 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 402 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 403 .old_peci_mask = 0x4,
483db43e 404 },
a0c1424a
TL		 405 [it8786] = {
406 .name = "it8786",
faf392fb 407 .suffix = "E",
a0c1424a 408 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 409 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
410 | FEAT_PWM_FREQ2,
a0c1424a
TL		 411 .peci_mask = 0x07,
412 },
4ee07157
GR		 413 [it8790] = {
414 .name = "it8790",
415 .suffix = "E",
416 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 417 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
418 | FEAT_PWM_FREQ2,
4ee07157
GR		 419 .peci_mask = 0x07,
420 },
c145d5c6
RM		 421 [it8603] = {
422 .name = "it8603",
faf392fb 423 .suffix = "E",
c145d5c6 424 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
73055405 425 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
60878bcf 426 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
c145d5c6
RM		 427 .peci_mask = 0x07,
428 },
3ba9d977
GR		 429 [it8620] = {
430 .name = "it8620",
431 .suffix = "E",
432 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
fa3f70d6 433 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
cc18da79
GR		 434 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
435 | FEAT_SIX_TEMP,
3ba9d977
GR		 436 .peci_mask = 0x07,
437 },
483db43e
GR		 438};
439
440#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
441#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
ead80803 442#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
483db43e
GR		 443#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
444#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
445#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b 446#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
48b2ae7f 447 ((data)->peci_mask & BIT(nr)))
19529784
GR		 448#define has_temp_old_peci(data, nr) \
449 (((data)->features & FEAT_TEMP_OLD_PECI) && \
48b2ae7f 450 ((data)->old_peci_mask & BIT(nr)))
9faf28ca 451#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
fa3f70d6
GR		 452#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
453 FEAT_SIX_FANS))
32dd7c40 454#define has_vid(data) ((data)->features & FEAT_VID)
7f5726c3 455#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
fa3f70d6 456#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
73055405 457#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
36c4d98a 458#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
60878bcf 459#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
cc18da79 460#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
1da177e4 461
b74f3fdd 462struct it87_sio_data {
463 enum chips type;
464 /* Values read from Super-I/O config space */
0475169c 465 u8 revision;
b74f3fdd 466 u8 vid_value;
d9b327c3 467 u8 beep_pin;
738e5e05 468 u8 internal; /* Internal sensors can be labeled */
591ec650 469 /* Features skipped based on config or DMI */
9172b5d1 470 u16 skip_in;
895ff267 471 u8 skip_vid;
591ec650 472 u8 skip_fan;
98dd22c3 473 u8 skip_pwm;
4573acbc 474 u8 skip_temp;
b74f3fdd 475};
476
4a0d71cf
GR		 477/*
478 * For each registered chip, we need to keep some data in memory.
479 * The structure is dynamically allocated.
480 */
1da177e4 481struct it87_data {
8638d0af 482 const struct attribute_group *groups[7];
1da177e4 483 enum chips type;
483db43e 484 u16 features;
19529784
GR		 485 u8 peci_mask;
486 u8 old_peci_mask;
1da177e4 487
b74f3fdd 488 unsigned short addr;
489 const char *name;
9a61bf63 490 struct mutex update_lock;
1da177e4
LT		 491 char valid; /* !=0 if following fields are valid */
492 unsigned long last_updated; /* In jiffies */
493
44c1bcd4 494 u16 in_scaled; /* Internal voltage sensors are scaled */
d3766848 495 u16 in_internal; /* Bitfield, internal sensors (for labels) */
52929715 496 u16 has_in; /* Bitfield, voltage sensors enabled */
2310048d 497 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 498 u8 has_fan; /* Bitfield, fans enabled */
2310048d 499 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 500 u8 has_temp; /* Bitfield, temp sensors enabled */
2310048d 501 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 502 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
503 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
2310048d 504 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
d3766848 505 bool has_vid; /* True if VID supported */
1da177e4 506 u8 vid; /* Register encoding, combined */
a7be58a1 507 u8 vrm;
1da177e4 508 u32 alarms; /* Register encoding, combined */
52929715 509 bool has_beep; /* true if beep supported */
d9b327c3 510 u8 beeps; /* Register encoding */
1da177e4 511 u8 fan_main_ctrl; /* Register value */
f8d0c19a 512 u8 fan_ctl; /* Register value */
b99883dc 513
4a0d71cf
GR		 514 /*
515 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 516 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
517 * 7, and we want to preserve settings on mode changes, so we have
518 * to track all values separately.
519 * Starting with the IT8721F, the manual PWM duty cycles are stored
520 * in separate registers (8-bit values), so the separate tracking
521 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 522 * simple.
523 */
5c391261 524 u8 has_pwm; /* Bitfield, pwm control enabled */
2310048d
GR		 525 u8 pwm_ctrl[NUM_PWM]; /* Register value */
526 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
527 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 528
529 /* Automatic fan speed control registers */
2310048d
GR		 530 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
531 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 532};
0df6454d 533
0531d98b 534static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 535{
ead80803
JM		 536 int lsb;
537
538 if (has_12mv_adc(data))
539 lsb = 120;
540 else if (has_10_9mv_adc(data))
541 lsb = 109;
542 else
543 lsb = 160;
48b2ae7f 544 if (data->in_scaled & BIT(nr))
0531d98b
GR		 545 lsb <<= 1;
546 return lsb;
547}
44c1bcd4 548
0531d98b
GR		 549static u8 in_to_reg(const struct it87_data *data, int nr, long val)
550{
ead80803 551 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
2a844c14 552 return clamp_val(val, 0, 255);
44c1bcd4
JD		 553}
554
555static int in_from_reg(const struct it87_data *data, int nr, int val)
556{
ead80803 557 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
44c1bcd4 558}
0df6454d
JD		 559
560static inline u8 FAN_TO_REG(long rpm, int div)
561{
562 if (rpm == 0)
563 return 255;
2a844c14
GR		 564 rpm = clamp_val(rpm, 1, 1000000);
565 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 566}
567
568static inline u16 FAN16_TO_REG(long rpm)
569{
570 if (rpm == 0)
571 return 0xffff;
2a844c14 572 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 573}
574
575#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
576 1350000 / ((val) * (div)))
577/* The divider is fixed to 2 in 16-bit mode */
578#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
579 1350000 / ((val) * 2))
580
2a844c14
GR		 581#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
582 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 583#define TEMP_FROM_REG(val) ((val) * 1000)
584
44c1bcd4
JD		 585static u8 pwm_to_reg(const struct it87_data *data, long val)
586{
16b5dda2 587 if (has_newer_autopwm(data))
44c1bcd4
JD		 588 return val;
589 else
590 return val >> 1;
591}
592
593static int pwm_from_reg(const struct it87_data *data, u8 reg)
594{
16b5dda2 595 if (has_newer_autopwm(data))
44c1bcd4
JD		 596 return reg;
597 else
598 return (reg & 0x7f) << 1;
599}
600
0df6454d
JD		 601
602static int DIV_TO_REG(int val)
603{
604 int answer = 0;
605 while (answer < 7 && (val >>= 1))
606 answer++;
607 return answer;
608}
48b2ae7f
GR		 609
610#define DIV_FROM_REG(val) BIT(val)
0df6454d 611
f56c9c0a
GR		 612/*
613 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
614 * depending on the chip type, to calculate the actual PWM frequency.
615 *
616 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
617 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
618 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
619 * sometimes just one. It is unknown if this is a datasheet error or real,
620 * so this is ignored for now.
621 */
0df6454d 622static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 623 48000000,
624 24000000,
625 12000000,
626 8000000,
627 6000000,
628 3000000,
629 1500000,
630 750000,
0df6454d 631};
1da177e4 632
c1e7a4ca
GR		 633/*
634 * Must be called with data->update_lock held, except during initialization.
635 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
636 * would slow down the IT87 access and should not be necessary.
637 */
638static int it87_read_value(struct it87_data *data, u8 reg)
639{
640 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
641 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
642}
643
644/*
645 * Must be called with data->update_lock held, except during initialization.
646 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
647 * would slow down the IT87 access and should not be necessary.
648 */
649static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
650{
651 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
652 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
653}
654
655static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
656{
657 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
658 if (has_newer_autopwm(data)) {
659 data->pwm_temp_map[nr] = (data->pwm_ctrl[nr] & 0x03) +
660 nr < 3 ? 0 : 3;
661 data->pwm_duty[nr] = it87_read_value(data,
662 IT87_REG_PWM_DUTY[nr]);
663 } else {
664 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
665 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
666 else /* Manual mode */
667 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
668 }
1da177e4 669
c1e7a4ca
GR		 670 if (has_old_autopwm(data)) {
671 int i;
1da177e4 672
c1e7a4ca
GR		 673 for (i = 0; i < 5 ; i++)
674 data->auto_temp[nr][i] = it87_read_value(data,
675 IT87_REG_AUTO_TEMP(nr, i));
676 for (i = 0; i < 3 ; i++)
677 data->auto_pwm[nr][i] = it87_read_value(data,
678 IT87_REG_AUTO_PWM(nr, i));
679 }
680}
1da177e4 681
c1e7a4ca
GR		 682static struct it87_data *it87_update_device(struct device *dev)
683{
684 struct it87_data *data = dev_get_drvdata(dev);
685 int i;
686
687 mutex_lock(&data->update_lock);
688
689 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
690 || !data->valid) {
691 if (update_vbat) {
692 /*
693 * Cleared after each update, so reenable. Value
694 * returned by this read will be previous value
695 */
696 it87_write_value(data, IT87_REG_CONFIG,
697 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
698 }
2310048d 699 for (i = 0; i < NUM_VIN; i++) {
48b2ae7f 700 if (!(data->has_in & BIT(i)))
559313c4
GR		 701 continue;
702
c1e7a4ca 703 data->in[i][0] =
559313c4
GR		 704 it87_read_value(data, IT87_REG_VIN[i]);
705
706 /* VBAT and AVCC don't have limit registers */
2310048d 707 if (i >= NUM_VIN_LIMIT)
559313c4
GR		 708 continue;
709
c1e7a4ca
GR		 710 data->in[i][1] =
711 it87_read_value(data, IT87_REG_VIN_MIN(i));
712 data->in[i][2] =
713 it87_read_value(data, IT87_REG_VIN_MAX(i));
714 }
c1e7a4ca 715
2310048d 716 for (i = 0; i < NUM_FAN; i++) {
c1e7a4ca 717 /* Skip disabled fans */
48b2ae7f 718 if (!(data->has_fan & BIT(i)))
c1e7a4ca
GR		 719 continue;
720
721 data->fan[i][1] =
722 it87_read_value(data, IT87_REG_FAN_MIN[i]);
723 data->fan[i][0] = it87_read_value(data,
724 IT87_REG_FAN[i]);
725 /* Add high byte if in 16-bit mode */
726 if (has_16bit_fans(data)) {
727 data->fan[i][0] |= it87_read_value(data,
728 IT87_REG_FANX[i]) << 8;
729 data->fan[i][1] |= it87_read_value(data,
730 IT87_REG_FANX_MIN[i]) << 8;
731 }
732 }
2310048d 733 for (i = 0; i < NUM_TEMP; i++) {
48b2ae7f 734 if (!(data->has_temp & BIT(i)))
c1e7a4ca
GR		 735 continue;
736 data->temp[i][0] =
737 it87_read_value(data, IT87_REG_TEMP(i));
cc18da79 738
2310048d
GR		 739 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
740 data->temp[i][3] =
741 it87_read_value(data,
742 IT87_REG_TEMP_OFFSET[i]);
743
744 if (i >= NUM_TEMP_LIMIT)
cc18da79
GR		 745 continue;
746
c1e7a4ca
GR		 747 data->temp[i][1] =
748 it87_read_value(data, IT87_REG_TEMP_LOW(i));
749 data->temp[i][2] =
750 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c1e7a4ca
GR		 751 }
752
753 /* Newer chips don't have clock dividers */
754 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
755 i = it87_read_value(data, IT87_REG_FAN_DIV);
756 data->fan_div[0] = i & 0x07;
757 data->fan_div[1] = (i >> 3) & 0x07;
758 data->fan_div[2] = (i & 0x40) ? 3 : 1;
759 }
760
761 data->alarms =
762 it87_read_value(data, IT87_REG_ALARM1) |
763 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
764 (it87_read_value(data, IT87_REG_ALARM3) << 16);
765 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
766
767 data->fan_main_ctrl = it87_read_value(data,
768 IT87_REG_FAN_MAIN_CTRL);
769 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
2310048d 770 for (i = 0; i < NUM_PWM; i++)
c1e7a4ca
GR		 771 it87_update_pwm_ctrl(data, i);
772
773 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
774 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
775 /*
776 * The IT8705F does not have VID capability.
777 * The IT8718F and later don't use IT87_REG_VID for the
778 * same purpose.
779 */
780 if (data->type == it8712 || data->type == it8716) {
781 data->vid = it87_read_value(data, IT87_REG_VID);
782 /*
783 * The older IT8712F revisions had only 5 VID pins,
784 * but we assume it is always safe to read 6 bits.
785 */
786 data->vid &= 0x3f;
787 }
788 data->last_updated = jiffies;
789 data->valid = 1;
790 }
791
792 mutex_unlock(&data->update_lock);
793
794 return data;
795}
fde09509 796
20ad93d4 797static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 798 char *buf)
1da177e4 799{
929c6a56
GR		 800 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
801 int nr = sattr->nr;
802 int index = sattr->index;
20ad93d4 803
1da177e4 804 struct it87_data *data = it87_update_device(dev);
929c6a56 805 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 806}
807
929c6a56
GR		 808static ssize_t set_in(struct device *dev, struct device_attribute *attr,
809 const char *buf, size_t count)
1da177e4 810{
929c6a56
GR		 811 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
812 int nr = sattr->nr;
813 int index = sattr->index;
20ad93d4 814
b74f3fdd 815 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 816 unsigned long val;
817
179c4fdb 818 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 819 return -EINVAL;
1da177e4 820
9a61bf63 821 mutex_lock(&data->update_lock);
929c6a56
GR		 822 data->in[nr][index] = in_to_reg(data, nr, val);
823 it87_write_value(data,
824 index == 1 ? IT87_REG_VIN_MIN(nr)
825 : IT87_REG_VIN_MAX(nr),
826 data->in[nr][index]);
9a61bf63 827 mutex_unlock(&data->update_lock);
1da177e4
LT		 828 return count;
829}
20ad93d4 830
929c6a56
GR		 831static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
832static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
833 0, 1);
834static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
835 0, 2);
f5f64501 836
929c6a56
GR		 837static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
838static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
839 1, 1);
840static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
841 1, 2);
1da177e4 842
929c6a56
GR		 843static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
844static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
845 2, 1);
846static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
847 2, 2);
1da177e4 848
929c6a56
GR		 849static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
850static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
851 3, 1);
852static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
853 3, 2);
854
855static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
856static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
857 4, 1);
858static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
859 4, 2);
860
861static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
862static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
863 5, 1);
864static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
865 5, 2);
866
867static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
868static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
869 6, 1);
870static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
871 6, 2);
872
873static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
874static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
875 7, 1);
876static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
877 7, 2);
878
879static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 880static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
f838aa26
GR		 881static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
882static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
883static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1da177e4 884
cc18da79 885/* Up to 6 temperatures */
20ad93d4 886static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 887 char *buf)
1da177e4 888{
60ca385a
GR		 889 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
890 int nr = sattr->nr;
891 int index = sattr->index;
1da177e4 892 struct it87_data *data = it87_update_device(dev);
20ad93d4 893
60ca385a 894 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 895}
20ad93d4 896
60ca385a
GR		 897static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
898 const char *buf, size_t count)
1da177e4 899{
60ca385a
GR		 900 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
901 int nr = sattr->nr;
902 int index = sattr->index;
b74f3fdd 903 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 904 long val;
161d898a 905 u8 reg, regval;
f5f64501 906
179c4fdb 907 if (kstrtol(buf, 10, &val) < 0)
f5f64501 908 return -EINVAL;
1da177e4 909
9a61bf63 910 mutex_lock(&data->update_lock);
161d898a
GR		 911
912 switch (index) {
913 default:
914 case 1:
915 reg = IT87_REG_TEMP_LOW(nr);
916 break;
917 case 2:
918 reg = IT87_REG_TEMP_HIGH(nr);
919 break;
920 case 3:
921 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
922 if (!(regval & 0x80)) {
923 regval |= 0x80;
924 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
925 }
926 data->valid = 0;
927 reg = IT87_REG_TEMP_OFFSET[nr];
928 break;
929 }
930
60ca385a 931 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 932 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 933 mutex_unlock(&data->update_lock);
1da177e4
LT		 934 return count;
935}
1da177e4 936
60ca385a
GR		 937static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
938static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
939 0, 1);
940static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
941 0, 2);
161d898a
GR		 942static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
943 set_temp, 0, 3);
60ca385a
GR		 944static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
945static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
946 1, 1);
947static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
948 1, 2);
161d898a
GR		 949static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
950 set_temp, 1, 3);
60ca385a
GR		 951static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
952static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
953 2, 1);
954static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
955 2, 2);
161d898a
GR		 956static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
957 set_temp, 2, 3);
cc18da79
GR		 958static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
959static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
960static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1da177e4 961
2cece01f
GR		 962static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
963 char *buf)
1da177e4 964{
20ad93d4
JD		 965 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
966 int nr = sensor_attr->index;
1da177e4 967 struct it87_data *data = it87_update_device(dev);
4a0d71cf 968 u8 reg = data->sensor; /* In case value is updated while used */
19529784 969 u8 extra = data->extra;
5f2dc798 970
19529784
GR		 971 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
972 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 973 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 974 if (reg & (1 << nr))
975 return sprintf(buf, "3\n"); /* thermal diode */
976 if (reg & (8 << nr))
4ed10779 977 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 978 return sprintf(buf, "0\n"); /* disabled */
979}
2cece01f
GR		 980
981static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
982 const char *buf, size_t count)
1da177e4 983{
20ad93d4
JD		 984 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
985 int nr = sensor_attr->index;
986
b74f3fdd 987 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 988 long val;
19529784 989 u8 reg, extra;
f5f64501 990
179c4fdb 991 if (kstrtol(buf, 10, &val) < 0)
f5f64501 992 return -EINVAL;
1da177e4 993
8acf07c5
JD		 994 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
995 reg &= ~(1 << nr);
996 reg &= ~(8 << nr);
5d8d2f2b
GR		 997 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
998 reg &= 0x3f;
19529784
GR		 999 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1000 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1001 extra &= 0x7f;
4ed10779 1002 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 1003 dev_warn(dev,
1004 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 1005 val = 4;
1006 }
5d8d2f2b 1007 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 1008 if (val == 3)
8acf07c5 1009 reg |= 1 << nr;
4ed10779 1010 else if (val == 4)
8acf07c5 1011 reg |= 8 << nr;
5d8d2f2b
GR		 1012 else if (has_temp_peci(data, nr) && val == 6)
1013 reg |= (nr + 1) << 6;
19529784
GR		 1014 else if (has_temp_old_peci(data, nr) && val == 6)
1015 extra |= 0x80;
8acf07c5 1016 else if (val != 0)
1da177e4 1017 return -EINVAL;
8acf07c5
JD		 1018
1019 mutex_lock(&data->update_lock);
1020 data->sensor = reg;
19529784 1021 data->extra = extra;
b74f3fdd 1022 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 1023 if (has_temp_old_peci(data, nr))
1024 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 1025 data->valid = 0; /* Force cache refresh */
9a61bf63 1026 mutex_unlock(&data->update_lock);
1da177e4
LT		 1027 return count;
1028}
1da177e4 1029
2cece01f
GR		 1030static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1031 set_temp_type, 0);
1032static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1033 set_temp_type, 1);
1034static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1035 set_temp_type, 2);
1da177e4
LT		 1036
1037/* 3 Fans */
b99883dc
JD		 1038
1039static int pwm_mode(const struct it87_data *data, int nr)
1040{
48b2ae7f 1041 int ctrl = data->fan_main_ctrl & BIT(nr);
b99883dc 1042
c145d5c6 1043 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 1044 return 0;
1045 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
1046 return 2;
1047 else /* Manual mode */
1048 return 1;
1049}
1050
20ad93d4 1051static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 1052 char *buf)
1da177e4 1053{
e1169ba0
GR		 1054 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1055 int nr = sattr->nr;
1056 int index = sattr->index;
1057 int speed;
1da177e4 1058 struct it87_data *data = it87_update_device(dev);
20ad93d4 1059
e1169ba0
GR		 1060 speed = has_16bit_fans(data) ?
1061 FAN16_FROM_REG(data->fan[nr][index]) :
1062 FAN_FROM_REG(data->fan[nr][index],
1063 DIV_FROM_REG(data->fan_div[nr]));
1064 return sprintf(buf, "%d\n", speed);
1da177e4 1065}
e1169ba0 1066
20ad93d4
JD		 1067static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1068 char *buf)
1da177e4 1069{
20ad93d4
JD		 1070 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1071 int nr = sensor_attr->index;
1072
1da177e4 1073 struct it87_data *data = it87_update_device(dev);
48b2ae7f 1074 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1da177e4 1075}
5f2dc798
JD		 1076static ssize_t show_pwm_enable(struct device *dev,
1077 struct device_attribute *attr, char *buf)
1da177e4 1078{
20ad93d4
JD		 1079 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1080 int nr = sensor_attr->index;
1081
1da177e4 1082 struct it87_data *data = it87_update_device(dev);
b99883dc 1083 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 1084}
20ad93d4
JD		 1085static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1086 char *buf)
1da177e4 1087{
20ad93d4
JD		 1088 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1089 int nr = sensor_attr->index;
1090
1da177e4 1091 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 1092 return sprintf(buf, "%d\n",
1093 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 1094}
f8d0c19a
JD		 1095static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1096 char *buf)
1097{
60878bcf 1098 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
f8d0c19a 1099 struct it87_data *data = it87_update_device(dev);
60878bcf 1100 int nr = sensor_attr->index;
f56c9c0a 1101 unsigned int freq;
60878bcf
GR		 1102 int index;
1103
1104 if (has_pwm_freq2(data) && nr == 1)
1105 index = (data->extra >> 4) & 0x07;
1106 else
1107 index = (data->fan_ctl >> 4) & 0x07;
f8d0c19a 1108
f56c9c0a
GR		 1109 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1110
1111 return sprintf(buf, "%u\n", freq);
f8d0c19a 1112}
e1169ba0
GR		 1113
1114static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1115 const char *buf, size_t count)
1da177e4 1116{
e1169ba0
GR		 1117 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1118 int nr = sattr->nr;
1119 int index = sattr->index;
20ad93d4 1120
b74f3fdd 1121 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1122 long val;
7f999aa7 1123 u8 reg;
1da177e4 1124
179c4fdb 1125 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 1126 return -EINVAL;
1127
9a61bf63 1128 mutex_lock(&data->update_lock);
e1169ba0
GR		 1129
1130 if (has_16bit_fans(data)) {
1131 data->fan[nr][index] = FAN16_TO_REG(val);
1132 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1133 data->fan[nr][index] & 0xff);
1134 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1135 data->fan[nr][index] >> 8);
1136 } else {
1137 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1138 switch (nr) {
1139 case 0:
1140 data->fan_div[nr] = reg & 0x07;
1141 break;
1142 case 1:
1143 data->fan_div[nr] = (reg >> 3) & 0x07;
1144 break;
1145 case 2:
1146 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1147 break;
1148 }
1149 data->fan[nr][index] =
1150 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1151 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1152 data->fan[nr][index]);
07eab46d
JD		 1153 }
1154
9a61bf63 1155 mutex_unlock(&data->update_lock);
1da177e4
LT		 1156 return count;
1157}
e1169ba0 1158
20ad93d4
JD		 1159static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1160 const char *buf, size_t count)
1da177e4 1161{
20ad93d4
JD		 1162 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1163 int nr = sensor_attr->index;
1164
b74f3fdd 1165 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1166 unsigned long val;
8ab4ec3e 1167 int min;
1da177e4
LT		 1168 u8 old;
1169
179c4fdb 1170 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1171 return -EINVAL;
1172
9a61bf63 1173 mutex_lock(&data->update_lock);
b74f3fdd 1174 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 1175
8ab4ec3e 1176 /* Save fan min limit */
e1169ba0 1177 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 1178
1179 switch (nr) {
1180 case 0:
1181 case 1:
1182 data->fan_div[nr] = DIV_TO_REG(val);
1183 break;
1184 case 2:
1185 if (val < 8)
1186 data->fan_div[nr] = 1;
1187 else
1188 data->fan_div[nr] = 3;
1189 }
1190 val = old & 0x80;
1191 val |= (data->fan_div[0] & 0x07);
1192 val |= (data->fan_div[1] & 0x07) << 3;
1193 if (data->fan_div[2] == 3)
1194 val |= 0x1 << 6;
b74f3fdd 1195 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 1196
8ab4ec3e 1197 /* Restore fan min limit */
e1169ba0
GR		 1198 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1199 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 1200
9a61bf63 1201 mutex_unlock(&data->update_lock);
1da177e4
LT		 1202 return count;
1203}
cccfc9c4
JD		 1204
1205/* Returns 0 if OK, -EINVAL otherwise */
1206static int check_trip_points(struct device *dev, int nr)
1207{
1208 const struct it87_data *data = dev_get_drvdata(dev);
1209 int i, err = 0;
1210
1211 if (has_old_autopwm(data)) {
1212 for (i = 0; i < 3; i++) {
1213 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1214 err = -EINVAL;
1215 }
1216 for (i = 0; i < 2; i++) {
1217 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1218 err = -EINVAL;
1219 }
1220 }
1221
1222 if (err) {
1d9bcf6a
GR		 1223 dev_err(dev,
1224 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 1225 dev_err(dev, "Adjust the trip points and try again\n");
1226 }
1227 return err;
1228}
1229
20ad93d4
JD		 1230static ssize_t set_pwm_enable(struct device *dev,
1231 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 1232{
20ad93d4
JD		 1233 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1234 int nr = sensor_attr->index;
1235
b74f3fdd 1236 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1237 long val;
1da177e4 1238
179c4fdb 1239 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 1240 return -EINVAL;
1241
cccfc9c4
JD		 1242 /* Check trip points before switching to automatic mode */
1243 if (val == 2) {
1244 if (check_trip_points(dev, nr) < 0)
1245 return -EINVAL;
1246 }
1247
c145d5c6
RM		 1248 /* IT8603E does not have on/off mode */
1249 if (val == 0 && data->type == it8603)
1250 return -EINVAL;
1251
9a61bf63 1252 mutex_lock(&data->update_lock);
1da177e4
LT		 1253
1254 if (val == 0) {
1255 int tmp;
1256 /* make sure the fan is on when in on/off mode */
b74f3fdd 1257 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
48b2ae7f 1258 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1da177e4 1259 /* set on/off mode */
48b2ae7f 1260 data->fan_main_ctrl &= ~BIT(nr);
5f2dc798
JD		 1261 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1262 data->fan_main_ctrl);
b99883dc
JD		 1263 } else {
1264 if (val == 1) /* Manual mode */
16b5dda2 1265 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1266 data->pwm_temp_map[nr] :
1267 data->pwm_duty[nr];
b99883dc
JD		 1268 else /* Automatic mode */
1269 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1270 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
c145d5c6
RM		 1271
1272 if (data->type != it8603) {
1273 /* set SmartGuardian mode */
48b2ae7f 1274 data->fan_main_ctrl |= BIT(nr);
c145d5c6
RM		 1275 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1276 data->fan_main_ctrl);
1277 }
1da177e4
LT		 1278 }
1279
9a61bf63 1280 mutex_unlock(&data->update_lock);
1da177e4
LT		 1281 return count;
1282}
20ad93d4
JD		 1283static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1284 const char *buf, size_t count)
1da177e4 1285{
20ad93d4
JD		 1286 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1287 int nr = sensor_attr->index;
1288
b74f3fdd 1289 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1290 long val;
1da177e4 1291
179c4fdb 1292 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1293 return -EINVAL;
1294
9a61bf63 1295 mutex_lock(&data->update_lock);
16b5dda2 1296 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1297 /*
1298 * If we are in automatic mode, the PWM duty cycle register
1299 * is read-only so we can't write the value.
1300 */
6229cdb2
JD		 1301 if (data->pwm_ctrl[nr] & 0x80) {
1302 mutex_unlock(&data->update_lock);
1303 return -EBUSY;
1304 }
1305 data->pwm_duty[nr] = pwm_to_reg(data, val);
36c4d98a 1306 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
6229cdb2
JD		 1307 data->pwm_duty[nr]);
1308 } else {
1309 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1310 /*
1311 * If we are in manual mode, write the duty cycle immediately;
1312 * otherwise, just store it for later use.
1313 */
6229cdb2
JD		 1314 if (!(data->pwm_ctrl[nr] & 0x80)) {
1315 data->pwm_ctrl[nr] = data->pwm_duty[nr];
36c4d98a 1316 it87_write_value(data, IT87_REG_PWM[nr],
6229cdb2
JD		 1317 data->pwm_ctrl[nr]);
1318 }
b99883dc 1319 }
9a61bf63 1320 mutex_unlock(&data->update_lock);
1da177e4
LT		 1321 return count;
1322}
f8d0c19a
JD		 1323static ssize_t set_pwm_freq(struct device *dev,
1324 struct device_attribute *attr, const char *buf, size_t count)
1325{
60878bcf 1326 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1327 struct it87_data *data = dev_get_drvdata(dev);
60878bcf 1328 int nr = sensor_attr->index;
f5f64501 1329 unsigned long val;
f8d0c19a
JD		 1330 int i;
1331
179c4fdb 1332 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1333 return -EINVAL;
f56c9c0a
GR		 1334
1335 val = clamp_val(val, 0, 1000000);
1336 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1337
f8d0c19a
JD		 1338 /* Search for the nearest available frequency */
1339 for (i = 0; i < 7; i++) {
1340 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1341 break;
1342 }
1343
1344 mutex_lock(&data->update_lock);
60878bcf
GR		 1345 if (nr == 0) {
1346 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1347 data->fan_ctl |= i << 4;
1348 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1349 } else {
1350 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1351 data->extra |= i << 4;
1352 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1353 }
f8d0c19a
JD		 1354 mutex_unlock(&data->update_lock);
1355
1356 return count;
1357}
94ac7ee6
JD		 1358static ssize_t show_pwm_temp_map(struct device *dev,
1359 struct device_attribute *attr, char *buf)
1360{
1361 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1362 int nr = sensor_attr->index;
1363
1364 struct it87_data *data = it87_update_device(dev);
1365 int map;
1366
1367 if (data->pwm_temp_map[nr] < 3)
48b2ae7f 1368 map = BIT(data->pwm_temp_map[nr]);
94ac7ee6
JD		 1369 else
1370 map = 0; /* Should never happen */
1371 return sprintf(buf, "%d\n", map);
1372}
1373static ssize_t set_pwm_temp_map(struct device *dev,
1374 struct device_attribute *attr, const char *buf, size_t count)
1375{
1376 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1377 int nr = sensor_attr->index;
1378
1379 struct it87_data *data = dev_get_drvdata(dev);
1380 long val;
1381 u8 reg;
1382
179c4fdb 1383 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1384 return -EINVAL;
1385
1386 switch (val) {
48b2ae7f 1387 case BIT(0):
94ac7ee6
JD		 1388 reg = 0x00;
1389 break;
48b2ae7f 1390 case BIT(1):
94ac7ee6
JD		 1391 reg = 0x01;
1392 break;
48b2ae7f 1393 case BIT(2):
94ac7ee6
JD		 1394 reg = 0x02;
1395 break;
1396 default:
1397 return -EINVAL;
1398 }
1399
1400 mutex_lock(&data->update_lock);
1401 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1402 /*
1403 * If we are in automatic mode, write the temp mapping immediately;
1404 * otherwise, just store it for later use.
1405 */
94ac7ee6
JD		 1406 if (data->pwm_ctrl[nr] & 0x80) {
1407 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1408 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
94ac7ee6
JD		 1409 }
1410 mutex_unlock(&data->update_lock);
1411 return count;
1412}
1da177e4 1413
4f3f51bc
JD		 1414static ssize_t show_auto_pwm(struct device *dev,
1415 struct device_attribute *attr, char *buf)
1416{
1417 struct it87_data *data = it87_update_device(dev);
1418 struct sensor_device_attribute_2 *sensor_attr =
1419 to_sensor_dev_attr_2(attr);
1420 int nr = sensor_attr->nr;
1421 int point = sensor_attr->index;
1422
44c1bcd4
JD		 1423 return sprintf(buf, "%d\n",
1424 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1425}
1426
1427static ssize_t set_auto_pwm(struct device *dev,
1428 struct device_attribute *attr, const char *buf, size_t count)
1429{
1430 struct it87_data *data = dev_get_drvdata(dev);
1431 struct sensor_device_attribute_2 *sensor_attr =
1432 to_sensor_dev_attr_2(attr);
1433 int nr = sensor_attr->nr;
1434 int point = sensor_attr->index;
1435 long val;
1436
179c4fdb 1437 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1438 return -EINVAL;
1439
1440 mutex_lock(&data->update_lock);
44c1bcd4 1441 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1442 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1443 data->auto_pwm[nr][point]);
1444 mutex_unlock(&data->update_lock);
1445 return count;
1446}
1447
1448static ssize_t show_auto_temp(struct device *dev,
1449 struct device_attribute *attr, char *buf)
1450{
1451 struct it87_data *data = it87_update_device(dev);
1452 struct sensor_device_attribute_2 *sensor_attr =
1453 to_sensor_dev_attr_2(attr);
1454 int nr = sensor_attr->nr;
1455 int point = sensor_attr->index;
1456
1457 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1458}
1459
1460static ssize_t set_auto_temp(struct device *dev,
1461 struct device_attribute *attr, const char *buf, size_t count)
1462{
1463 struct it87_data *data = dev_get_drvdata(dev);
1464 struct sensor_device_attribute_2 *sensor_attr =
1465 to_sensor_dev_attr_2(attr);
1466 int nr = sensor_attr->nr;
1467 int point = sensor_attr->index;
1468 long val;
1469
179c4fdb 1470 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1471 return -EINVAL;
1472
1473 mutex_lock(&data->update_lock);
1474 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1475 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1476 data->auto_temp[nr][point]);
1477 mutex_unlock(&data->update_lock);
1478 return count;
1479}
1480
e1169ba0
GR		 1481static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1482static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1483 0, 1);
1484static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1485 set_fan_div, 0);
1486
1487static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1488static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1489 1, 1);
1490static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1491 set_fan_div, 1);
1492
1493static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1494static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1495 2, 1);
1496static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1497 set_fan_div, 2);
1498
1499static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1500static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1501 3, 1);
1da177e4 1502
e1169ba0
GR		 1503static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1504static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1505 4, 1);
1da177e4 1506
fa3f70d6
GR		 1507static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1508static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1509 5, 1);
1510
c4458db3
GR		 1511static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1512 show_pwm_enable, set_pwm_enable, 0);
1513static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
60878bcf
GR		 1514static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1515 set_pwm_freq, 0);
5c391261 1516static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1517 show_pwm_temp_map, set_pwm_temp_map, 0);
1518static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1519 show_auto_pwm, set_auto_pwm, 0, 0);
1520static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1521 show_auto_pwm, set_auto_pwm, 0, 1);
1522static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1523 show_auto_pwm, set_auto_pwm, 0, 2);
1524static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1525 show_auto_pwm, NULL, 0, 3);
1526static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1527 show_auto_temp, set_auto_temp, 0, 1);
1528static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1529 show_auto_temp, set_auto_temp, 0, 0);
1530static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1531 show_auto_temp, set_auto_temp, 0, 2);
1532static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1533 show_auto_temp, set_auto_temp, 0, 3);
1534static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1535 show_auto_temp, set_auto_temp, 0, 4);
1536
1537static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1538 show_pwm_enable, set_pwm_enable, 1);
1539static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
60878bcf 1540static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
5c391261 1541static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1542 show_pwm_temp_map, set_pwm_temp_map, 1);
1543static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1544 show_auto_pwm, set_auto_pwm, 1, 0);
1545static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1546 show_auto_pwm, set_auto_pwm, 1, 1);
1547static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1548 show_auto_pwm, set_auto_pwm, 1, 2);
1549static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1550 show_auto_pwm, NULL, 1, 3);
1551static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1552 show_auto_temp, set_auto_temp, 1, 1);
1553static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1554 show_auto_temp, set_auto_temp, 1, 0);
1555static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1556 show_auto_temp, set_auto_temp, 1, 2);
1557static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1558 show_auto_temp, set_auto_temp, 1, 3);
1559static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1560 show_auto_temp, set_auto_temp, 1, 4);
1561
1562static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1563 show_pwm_enable, set_pwm_enable, 2);
1564static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
60878bcf 1565static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
5c391261 1566static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1567 show_pwm_temp_map, set_pwm_temp_map, 2);
1568static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1569 show_auto_pwm, set_auto_pwm, 2, 0);
1570static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1571 show_auto_pwm, set_auto_pwm, 2, 1);
1572static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1573 show_auto_pwm, set_auto_pwm, 2, 2);
1574static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1575 show_auto_pwm, NULL, 2, 3);
1576static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1577 show_auto_temp, set_auto_temp, 2, 1);
1578static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1579 show_auto_temp, set_auto_temp, 2, 0);
1580static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1581 show_auto_temp, set_auto_temp, 2, 2);
1582static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1583 show_auto_temp, set_auto_temp, 2, 3);
1584static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1585 show_auto_temp, set_auto_temp, 2, 4);
1da177e4 1586
36c4d98a
GR		 1587static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1588 show_pwm_enable, set_pwm_enable, 3);
1589static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
60878bcf 1590static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
5c391261 1591static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1592 show_pwm_temp_map, set_pwm_temp_map, 3);
1593
1594static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1595 show_pwm_enable, set_pwm_enable, 4);
1596static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
60878bcf 1597static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
5c391261 1598static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1599 show_pwm_temp_map, set_pwm_temp_map, 4);
1600
1601static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1602 show_pwm_enable, set_pwm_enable, 5);
1603static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
60878bcf 1604static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
5c391261 1605static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1606 show_pwm_temp_map, set_pwm_temp_map, 5);
1607
1da177e4 1608/* Alarms */
5f2dc798
JD		 1609static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1610 char *buf)
1da177e4
LT		 1611{
1612 struct it87_data *data = it87_update_device(dev);
68188ba7 1613 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1614}
1d66c64c 1615static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1616
0124dd78
JD		 1617static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1618 char *buf)
1619{
1620 int bitnr = to_sensor_dev_attr(attr)->index;
1621 struct it87_data *data = it87_update_device(dev);
1622 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1623}
3d30f9e6
JD		 1624
1625static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1626 *attr, const char *buf, size_t count)
1627{
1628 struct it87_data *data = dev_get_drvdata(dev);
1629 long val;
1630 int config;
1631
179c4fdb 1632 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1633 return -EINVAL;
1634
1635 mutex_lock(&data->update_lock);
1636 config = it87_read_value(data, IT87_REG_CONFIG);
1637 if (config < 0) {
1638 count = config;
1639 } else {
48b2ae7f 1640 config |= BIT(5);
3d30f9e6
JD		 1641 it87_write_value(data, IT87_REG_CONFIG, config);
1642 /* Invalidate cache to force re-read */
1643 data->valid = 0;
1644 }
1645 mutex_unlock(&data->update_lock);
1646
1647 return count;
1648}
1649
0124dd78
JD		 1650static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1651static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1652static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1653static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1654static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1655static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1656static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1657static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1658static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1659static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1660static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1661static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1662static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
fa3f70d6 1663static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
0124dd78
JD		 1664static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1665static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1666static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1667static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1668 show_alarm, clear_intrusion, 4);
0124dd78 1669
d9b327c3
JD		 1670static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1671 char *buf)
1672{
1673 int bitnr = to_sensor_dev_attr(attr)->index;
1674 struct it87_data *data = it87_update_device(dev);
1675 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1676}
1677static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1678 const char *buf, size_t count)
1679{
1680 int bitnr = to_sensor_dev_attr(attr)->index;
1681 struct it87_data *data = dev_get_drvdata(dev);
1682 long val;
1683
179c4fdb 1684 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1685 || (val != 0 && val != 1))
1686 return -EINVAL;
1687
1688 mutex_lock(&data->update_lock);
1689 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1690 if (val)
48b2ae7f 1691 data->beeps |= BIT(bitnr);
d9b327c3 1692 else
48b2ae7f 1693 data->beeps &= ~BIT(bitnr);
d9b327c3
JD		 1694 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1695 mutex_unlock(&data->update_lock);
1696 return count;
1697}
1698
1699static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1700 show_beep, set_beep, 1);
1701static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1702static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1703static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1704static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1705static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1706static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1707static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1708/* fanX_beep writability is set later */
1709static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1710static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1711static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1712static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1713static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
fa3f70d6 1714static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
d9b327c3
JD		 1715static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1716 show_beep, set_beep, 2);
1717static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1718static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1719
5f2dc798
JD		 1720static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1721 char *buf)
1da177e4 1722{
90d6619a 1723 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1724 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1725}
5f2dc798
JD		 1726static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1727 const char *buf, size_t count)
1da177e4 1728{
b74f3fdd 1729 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1730 unsigned long val;
1731
179c4fdb 1732 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1733 return -EINVAL;
1da177e4 1734
1da177e4
LT		 1735 data->vrm = val;
1736
1737 return count;
1738}
1739static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1740
5f2dc798
JD		 1741static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1742 char *buf)
1da177e4
LT		 1743{
1744 struct it87_data *data = it87_update_device(dev);
1745 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1746}
1747static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1748
738e5e05
JD		 1749static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1750 char *buf)
1751{
3c4c4971 1752 static const char * const labels[] = {
738e5e05
JD		 1753 "+5V",
1754 "5VSB",
1755 "Vbat",
1756 };
3c4c4971 1757 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1758 "+3.3V",
1759 "3VSB",
1760 "Vbat",
1761 };
1762 struct it87_data *data = dev_get_drvdata(dev);
738e5e05 1763 int nr = to_sensor_dev_attr(attr)->index;
ead80803 1764 const char *label;
738e5e05 1765
ead80803
JM		 1766 if (has_12mv_adc(data) || has_10_9mv_adc(data))
1767 label = labels_it8721[nr];
1768 else
1769 label = labels[nr];
1770
1771 return sprintf(buf, "%s\n", label);
738e5e05
JD		 1772}
1773static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1774static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1775static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
73055405 1776/* AVCC3 */
c145d5c6 1777static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1778
52929715
GR		 1779static umode_t it87_in_is_visible(struct kobject *kobj,
1780 struct attribute *attr, int index)
9172b5d1 1781{
52929715
GR		 1782 struct device *dev = container_of(kobj, struct device, kobj);
1783 struct it87_data *data = dev_get_drvdata(dev);
1784 int i = index / 5; /* voltage index */
1785 int a = index % 5; /* attribute index */
1786
f838aa26 1787 if (index >= 40) { /* in8 and higher only have input attributes */
52929715
GR		 1788 i = index - 40 + 8;
1789 a = 0;
1790 }
1791
48b2ae7f 1792 if (!(data->has_in & BIT(i)))
52929715
GR		 1793 return 0;
1794
1795 if (a == 4 && !data->has_beep)
1796 return 0;
1797
1798 return attr->mode;
1799}
1800
1801static struct attribute *it87_attributes_in[] = {
87808be4 1802 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1803 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1804 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1805 &sensor_dev_attr_in0_alarm.dev_attr.attr,
52929715
GR		 1806 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
1807
9172b5d1
GR		 1808 &sensor_dev_attr_in1_input.dev_attr.attr,
1809 &sensor_dev_attr_in1_min.dev_attr.attr,
1810 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1811 &sensor_dev_attr_in1_alarm.dev_attr.attr,
52929715
GR		 1812 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
1813
9172b5d1
GR		 1814 &sensor_dev_attr_in2_input.dev_attr.attr,
1815 &sensor_dev_attr_in2_min.dev_attr.attr,
1816 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1817 &sensor_dev_attr_in2_alarm.dev_attr.attr,
52929715
GR		 1818 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
1819
9172b5d1
GR		 1820 &sensor_dev_attr_in3_input.dev_attr.attr,
1821 &sensor_dev_attr_in3_min.dev_attr.attr,
1822 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1823 &sensor_dev_attr_in3_alarm.dev_attr.attr,
52929715
GR		 1824 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
1825
9172b5d1
GR		 1826 &sensor_dev_attr_in4_input.dev_attr.attr,
1827 &sensor_dev_attr_in4_min.dev_attr.attr,
1828 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1829 &sensor_dev_attr_in4_alarm.dev_attr.attr,
52929715
GR		 1830 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
1831
9172b5d1
GR		 1832 &sensor_dev_attr_in5_input.dev_attr.attr,
1833 &sensor_dev_attr_in5_min.dev_attr.attr,
1834 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1835 &sensor_dev_attr_in5_alarm.dev_attr.attr,
52929715
GR		 1836 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
1837
9172b5d1
GR		 1838 &sensor_dev_attr_in6_input.dev_attr.attr,
1839 &sensor_dev_attr_in6_min.dev_attr.attr,
1840 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1841 &sensor_dev_attr_in6_alarm.dev_attr.attr,
52929715
GR		 1842 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
1843
9172b5d1
GR		 1844 &sensor_dev_attr_in7_input.dev_attr.attr,
1845 &sensor_dev_attr_in7_min.dev_attr.attr,
1846 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1847 &sensor_dev_attr_in7_alarm.dev_attr.attr,
52929715
GR		 1848 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
1849
1850 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
52929715 1851 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
f838aa26
GR		 1852 &sensor_dev_attr_in10_input.dev_attr.attr, /* 41 */
1853 &sensor_dev_attr_in11_input.dev_attr.attr, /* 41 */
1854 &sensor_dev_attr_in12_input.dev_attr.attr, /* 41 */
52929715
GR		 1855};
1856
1857static const struct attribute_group it87_group_in = {
1858 .attrs = it87_attributes_in,
1859 .is_visible = it87_in_is_visible,
9172b5d1
GR		 1860};
1861
87533770
GR		 1862static umode_t it87_temp_is_visible(struct kobject *kobj,
1863 struct attribute *attr, int index)
4573acbc 1864{
87533770
GR		 1865 struct device *dev = container_of(kobj, struct device, kobj);
1866 struct it87_data *data = dev_get_drvdata(dev);
1867 int i = index / 7; /* temperature index */
1868 int a = index % 7; /* attribute index */
1869
cc18da79
GR		 1870 if (index >= 21) {
1871 i = index - 21 + 3;
1872 a = 0;
1873 }
1874
48b2ae7f 1875 if (!(data->has_temp & BIT(i)))
87533770
GR		 1876 return 0;
1877
1878 if (a == 5 && !has_temp_offset(data))
1879 return 0;
1880
1881 if (a == 6 && !data->has_beep)
1882 return 0;
1883
1884 return attr->mode;
1885}
1886
1887static struct attribute *it87_attributes_temp[] = {
87808be4 1888 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1889 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1890 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1891 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1892 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
87533770
GR		 1893 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
1894 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
1895
cc18da79 1896 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
4573acbc
GR		 1897 &sensor_dev_attr_temp2_max.dev_attr.attr,
1898 &sensor_dev_attr_temp2_min.dev_attr.attr,
1899 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1900 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
87533770
GR		 1901 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1902 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1903
cc18da79 1904 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
4573acbc
GR		 1905 &sensor_dev_attr_temp3_max.dev_attr.attr,
1906 &sensor_dev_attr_temp3_min.dev_attr.attr,
1907 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1908 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
87533770
GR		 1909 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1910 &sensor_dev_attr_temp3_beep.dev_attr.attr,
4573acbc 1911
cc18da79
GR		 1912 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
1913 &sensor_dev_attr_temp5_input.dev_attr.attr,
1914 &sensor_dev_attr_temp6_input.dev_attr.attr,
87533770 1915 NULL
4573acbc 1916};
87808be4 1917
87533770
GR		 1918static const struct attribute_group it87_group_temp = {
1919 .attrs = it87_attributes_temp,
1920 .is_visible = it87_temp_is_visible,
161d898a
GR		 1921};
1922
d3766848
GR		 1923static umode_t it87_is_visible(struct kobject *kobj,
1924 struct attribute *attr, int index)
1925{
1926 struct device *dev = container_of(kobj, struct device, kobj);
1927 struct it87_data *data = dev_get_drvdata(dev);
1928
8638d0af 1929 if ((index == 2 || index == 3) && !data->has_vid)
d3766848
GR		 1930 return 0;
1931
48b2ae7f 1932 if (index > 3 && !(data->in_internal & BIT(index - 4)))
d3766848
GR		 1933 return 0;
1934
1935 return attr->mode;
1936}
1937
4573acbc 1938static struct attribute *it87_attributes[] = {
87808be4 1939 &dev_attr_alarms.attr,
3d30f9e6 1940 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
8638d0af
GR		 1941 &dev_attr_vrm.attr, /* 2 */
1942 &dev_attr_cpu0_vid.attr, /* 3 */
1943 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
d3766848
GR		 1944 &sensor_dev_attr_in7_label.dev_attr.attr,
1945 &sensor_dev_attr_in8_label.dev_attr.attr,
1946 &sensor_dev_attr_in9_label.dev_attr.attr,
87808be4
JD		 1947 NULL
1948};
1949
1950static const struct attribute_group it87_group = {
1951 .attrs = it87_attributes,
d3766848 1952 .is_visible = it87_is_visible,
87808be4
JD		 1953};
1954
9a70ee81
GR		 1955static umode_t it87_fan_is_visible(struct kobject *kobj,
1956 struct attribute *attr, int index)
1957{
1958 struct device *dev = container_of(kobj, struct device, kobj);
1959 struct it87_data *data = dev_get_drvdata(dev);
1960 int i = index / 5; /* fan index */
1961 int a = index % 5; /* attribute index */
1962
1963 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
1964 i = (index - 15) / 4 + 3;
1965 a = (index - 15) % 4;
1966 }
1967
48b2ae7f 1968 if (!(data->has_fan & BIT(i)))
9a70ee81
GR		 1969 return 0;
1970
1971 if (a == 3) { /* beep */
1972 if (!data->has_beep)
1973 return 0;
1974 /* first fan beep attribute is writable */
1975 if (i == __ffs(data->has_fan))
1976 return attr->mode | S_IWUSR;
1977 }
1978
1979 if (a == 4 && has_16bit_fans(data)) /* divisor */
1980 return 0;
1981
1982 return attr->mode;
1983}
1984
1985static struct attribute *it87_attributes_fan[] = {
e1169ba0
GR		 1986 &sensor_dev_attr_fan1_input.dev_attr.attr,
1987 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0 1988 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
9a70ee81
GR		 1989 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
1990 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
1991
e1169ba0
GR		 1992 &sensor_dev_attr_fan2_input.dev_attr.attr,
1993 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0 1994 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
9a70ee81
GR		 1995 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1996 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
1997
e1169ba0
GR		 1998 &sensor_dev_attr_fan3_input.dev_attr.attr,
1999 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0 2000 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
9a70ee81
GR		 2001 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2002 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2003
2004 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
e1169ba0 2005 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0 2006 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
9a70ee81
GR		 2007 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2008
2009 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
e1169ba0 2010 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0 2011 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
9a70ee81
GR		 2012 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2013
2014 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
fa3f70d6
GR		 2015 &sensor_dev_attr_fan6_min.dev_attr.attr,
2016 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
9a70ee81 2017 &sensor_dev_attr_fan6_beep.dev_attr.attr,
fa3f70d6 2018 NULL
723a0aa0 2019};
87808be4 2020
9a70ee81
GR		 2021static const struct attribute_group it87_group_fan = {
2022 .attrs = it87_attributes_fan,
2023 .is_visible = it87_fan_is_visible,
723a0aa0
JD		 2024};
2025
5c391261
GR		 2026static umode_t it87_pwm_is_visible(struct kobject *kobj,
2027 struct attribute *attr, int index)
2028{
2029 struct device *dev = container_of(kobj, struct device, kobj);
2030 struct it87_data *data = dev_get_drvdata(dev);
2031 int i = index / 4; /* pwm index */
2032 int a = index % 4; /* attribute index */
2033
48b2ae7f 2034 if (!(data->has_pwm & BIT(i)))
5c391261
GR		 2035 return 0;
2036
2037 /* pwmX_auto_channels_temp is only writable for old auto pwm */
2038 if (a == 3 && has_old_autopwm(data))
2039 return attr->mode | S_IWUSR;
2040
2041 /* pwm2_freq is writable if there are two pwm frequency selects */
2042 if (has_pwm_freq2(data) && i == 1 && a == 2)
2043 return attr->mode | S_IWUSR;
2044
2045 return attr->mode;
2046}
2047
2048static struct attribute *it87_attributes_pwm[] = {
87808be4 2049 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 2050 &sensor_dev_attr_pwm1.dev_attr.attr,
60878bcf 2051 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
94ac7ee6 2052 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
5c391261 2053
723a0aa0
JD		 2054 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2055 &sensor_dev_attr_pwm2.dev_attr.attr,
60878bcf 2056 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
94ac7ee6 2057 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
5c391261 2058
723a0aa0
JD		 2059 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2060 &sensor_dev_attr_pwm3.dev_attr.attr,
60878bcf 2061 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
94ac7ee6 2062 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
5c391261 2063
36c4d98a
GR		 2064 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2065 &sensor_dev_attr_pwm4.dev_attr.attr,
60878bcf 2066 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
36c4d98a 2067 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
5c391261 2068
36c4d98a
GR		 2069 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2070 &sensor_dev_attr_pwm5.dev_attr.attr,
60878bcf 2071 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
36c4d98a 2072 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
5c391261 2073
36c4d98a
GR		 2074 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2075 &sensor_dev_attr_pwm6.dev_attr.attr,
60878bcf 2076 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
36c4d98a 2077 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
5c391261 2078
36c4d98a 2079 NULL
5c391261 2080};
87808be4 2081
5c391261
GR		 2082static const struct attribute_group it87_group_pwm = {
2083 .attrs = it87_attributes_pwm,
2084 .is_visible = it87_pwm_is_visible,
2085};
2086
2087static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2088 struct attribute *attr, int index)
60878bcf
GR		 2089{
2090 struct device *dev = container_of(kobj, struct device, kobj);
2091 struct it87_data *data = dev_get_drvdata(dev);
5c391261 2092 int i = index / 9; /* pwm index */
60878bcf 2093
48b2ae7f 2094 if (!(data->has_pwm & BIT(i)))
5c391261 2095 return 0;
60878bcf
GR		 2096
2097 return attr->mode;
2098}
2099
5c391261 2100static struct attribute *it87_attributes_auto_pwm[] = {
4f3f51bc
JD		 2101 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2102 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2103 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2104 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2105 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2106 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2107 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2108 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2109 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
5c391261 2110
4f3f51bc
JD		 2111 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
2112 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2113 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2114 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2115 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2116 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2117 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2118 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2119 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
5c391261 2120
4f3f51bc
JD		 2121 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
2122 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2123 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2124 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2125 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2126 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2127 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2128 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2129 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
4f3f51bc 2130
5c391261
GR		 2131 NULL,
2132};
2133
2134static const struct attribute_group it87_group_auto_pwm = {
2135 .attrs = it87_attributes_auto_pwm,
2136 .is_visible = it87_auto_pwm_is_visible,
4f3f51bc
JD		 2137};
2138
2d8672c5 2139/* SuperIO detection - will change isa_address if a chip is found */
3c2e3512
GR		 2140static int __init it87_find(int sioaddr, unsigned short *address,
2141 struct it87_sio_data *sio_data)
1da177e4 2142{
5b0380c9 2143 int err;
b74f3fdd 2144 u16 chip_type;
98dd22c3 2145 const char *board_vendor, *board_name;
f83a9cb6 2146 const struct it87_devices *config;
1da177e4 2147
3c2e3512 2148 err = superio_enter(sioaddr);
5b0380c9
NG		 2149 if (err)
2150 return err;
2151
2152 err = -ENODEV;
3c2e3512 2153 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
b74f3fdd 2154
2155 switch (chip_type) {
2156 case IT8705F_DEVID:
2157 sio_data->type = it87;
2158 break;
2159 case IT8712F_DEVID:
2160 sio_data->type = it8712;
2161 break;
2162 case IT8716F_DEVID:
2163 case IT8726F_DEVID:
2164 sio_data->type = it8716;
2165 break;
2166 case IT8718F_DEVID:
2167 sio_data->type = it8718;
2168 break;
b4da93e4
JMS		 2169 case IT8720F_DEVID:
2170 sio_data->type = it8720;
2171 break;
44c1bcd4
JD		 2172 case IT8721F_DEVID:
2173 sio_data->type = it8721;
2174 break;
16b5dda2
JD		 2175 case IT8728F_DEVID:
2176 sio_data->type = it8728;
2177 break;
ead80803
JM		 2178 case IT8732F_DEVID:
2179 sio_data->type = it8732;
2180 break;
b0636707
GR		 2181 case IT8771E_DEVID:
2182 sio_data->type = it8771;
2183 break;
2184 case IT8772E_DEVID:
2185 sio_data->type = it8772;
2186 break;
7bc32d29
GR		 2187 case IT8781F_DEVID:
2188 sio_data->type = it8781;
2189 break;
0531d98b
GR		 2190 case IT8782F_DEVID:
2191 sio_data->type = it8782;
2192 break;
2193 case IT8783E_DEVID:
2194 sio_data->type = it8783;
2195 break;
a0c1424a
TL		 2196 case IT8786E_DEVID:
2197 sio_data->type = it8786;
2198 break;
4ee07157
GR		 2199 case IT8790E_DEVID:
2200 sio_data->type = it8790;
2201 break;
7183ae8c 2202 case IT8603E_DEVID:
574e9bd8 2203 case IT8623E_DEVID:
c145d5c6
RM		 2204 sio_data->type = it8603;
2205 break;
3ba9d977
GR		 2206 case IT8620E_DEVID:
2207 sio_data->type = it8620;
2208 break;
b74f3fdd 2209 case 0xffff: /* No device at all */
2210 goto exit;
2211 default:
a8ca1037 2212 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 2213 goto exit;
2214 }
1da177e4 2215
3c2e3512
GR		 2216 superio_select(sioaddr, PME);
2217 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
a8ca1037 2218 pr_info("Device not activated, skipping\n");
1da177e4
LT		 2219 goto exit;
2220 }
2221
3c2e3512 2222 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1da177e4 2223 if (*address == 0) {
a8ca1037 2224 pr_info("Base address not set, skipping\n");
1da177e4
LT		 2225 goto exit;
2226 }
2227
2228 err = 0;
3c2e3512 2229 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
faf392fb
GR		 2230 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2231 it87_devices[sio_data->type].suffix,
a0c1424a 2232 *address, sio_data->revision);
1da177e4 2233
f83a9cb6
GR		 2234 config = &it87_devices[sio_data->type];
2235
7f5726c3 2236 /* in7 (VSB or VCCH5V) is always internal on some chips */
f83a9cb6 2237 if (has_in7_internal(config))
48b2ae7f 2238 sio_data->internal |= BIT(1);
7f5726c3 2239
738e5e05 2240 /* in8 (Vbat) is always internal */
48b2ae7f 2241 sio_data->internal |= BIT(2);
7f5726c3 2242
73055405
GR		 2243 /* in9 (AVCC3), always internal if supported */
2244 if (has_avcc3(config))
48b2ae7f 2245 sio_data->internal |= BIT(3); /* in9 is AVCC */
73055405 2246 else
48b2ae7f 2247 sio_data->skip_in |= BIT(9);
738e5e05 2248
36c4d98a 2249 if (!has_six_pwm(config))
48b2ae7f 2250 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
36c4d98a 2251
f83a9cb6 2252 if (!has_vid(config))
895ff267 2253 sio_data->skip_vid = 1;
d9b327c3 2254
32dd7c40
GR		 2255 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2256 if (sio_data->type == it87) {
d9b327c3 2257 /* The IT8705F has a different LD number for GPIO */
3c2e3512
GR		 2258 superio_select(sioaddr, 5);
2259 sio_data->beep_pin = superio_inb(sioaddr,
2260 IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 2261 } else if (sio_data->type == it8783) {
088ce2ac 2262 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 2263
3c2e3512 2264 superio_select(sioaddr, GPIO);
0531d98b 2265
3c2e3512
GR		 2266 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2267 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2268 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2269 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2270 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
0531d98b 2271
0531d98b 2272 /* Check if fan3 is there or not */
48b2ae7f
GR		 2273 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2274 sio_data->skip_fan |= BIT(2);
2275 if ((reg25 & BIT(4))
2276 || (!(reg2a & BIT(1)) && (regef & BIT(0))))
2277 sio_data->skip_pwm |= BIT(2);
0531d98b
GR		 2278
2279 /* Check if fan2 is there or not */
48b2ae7f
GR		 2280 if (reg27 & BIT(7))
2281 sio_data->skip_fan |= BIT(1);
2282 if (reg27 & BIT(3))
2283 sio_data->skip_pwm |= BIT(1);
0531d98b
GR		 2284
2285 /* VIN5 */
48b2ae7f
GR		 2286 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2287 sio_data->skip_in |= BIT(5); /* No VIN5 */
0531d98b
GR		 2288
2289 /* VIN6 */
48b2ae7f
GR		 2290 if (reg27 & BIT(1))
2291 sio_data->skip_in |= BIT(6); /* No VIN6 */
0531d98b
GR		 2292
2293 /*
2294 * VIN7
2295 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2296 */
48b2ae7f 2297 if (reg27 & BIT(2)) {
9172b5d1
GR		 2298 /*
2299 * The data sheet is a bit unclear regarding the
2300 * internal voltage divider for VCCH5V. It says
2301 * "This bit enables and switches VIN7 (pin 91) to the
2302 * internal voltage divider for VCCH5V".
2303 * This is different to other chips, where the internal
2304 * voltage divider would connect VIN7 to an internal
2305 * voltage source. Maybe that is the case here as well.
2306 *
2307 * Since we don't know for sure, re-route it if that is
2308 * not the case, and ask the user to report if the
2309 * resulting voltage is sane.
2310 */
48b2ae7f
GR		 2311 if (!(reg2c & BIT(1))) {
2312 reg2c |= BIT(1);
3c2e3512
GR		 2313 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2314 reg2c);
9172b5d1
GR		 2315 pr_notice("Routing internal VCCH5V to in7.\n");
2316 }
2317 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2318 pr_notice("Please report if it displays a reasonable voltage.\n");
2319 }
0531d98b 2320
48b2ae7f
GR		 2321 if (reg2c & BIT(0))
2322 sio_data->internal |= BIT(0);
2323 if (reg2c & BIT(1))
2324 sio_data->internal |= BIT(1);
0531d98b 2325
3c2e3512
GR		 2326 sio_data->beep_pin = superio_inb(sioaddr,
2327 IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 2328 } else if (sio_data->type == it8603) {
2329 int reg27, reg29;
2330
3c2e3512 2331 superio_select(sioaddr, GPIO);
0531d98b 2332
3c2e3512 2333 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
c145d5c6
RM		 2334
2335 /* Check if fan3 is there or not */
48b2ae7f
GR		 2336 if (reg27 & BIT(6))
2337 sio_data->skip_pwm |= BIT(2);
2338 if (reg27 & BIT(7))
2339 sio_data->skip_fan |= BIT(2);
c145d5c6
RM		 2340
2341 /* Check if fan2 is there or not */
3c2e3512 2342 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2343 if (reg29 & BIT(1))
2344 sio_data->skip_pwm |= BIT(1);
2345 if (reg29 & BIT(2))
2346 sio_data->skip_fan |= BIT(1);
c145d5c6 2347
48b2ae7f
GR		 2348 sio_data->skip_in |= BIT(5); /* No VIN5 */
2349 sio_data->skip_in |= BIT(6); /* No VIN6 */
c145d5c6 2350
3c2e3512
GR		 2351 sio_data->beep_pin = superio_inb(sioaddr,
2352 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3ba9d977
GR		 2353 } else if (sio_data->type == it8620) {
2354 int reg;
2355
3c2e3512 2356 superio_select(sioaddr, GPIO);
3ba9d977 2357
36c4d98a 2358 /* Check for pwm5 */
3c2e3512 2359 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
48b2ae7f
GR		 2360 if (reg & BIT(6))
2361 sio_data->skip_pwm |= BIT(4);
36c4d98a 2362
3ba9d977 2363 /* Check for fan4, fan5 */
3c2e3512 2364 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
48b2ae7f
GR		 2365 if (!(reg & BIT(5)))
2366 sio_data->skip_fan |= BIT(3);
2367 if (!(reg & BIT(4)))
2368 sio_data->skip_fan |= BIT(4);
3ba9d977
GR		 2369
2370 /* Check for pwm3, fan3 */
3c2e3512 2371 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
48b2ae7f
GR		 2372 if (reg & BIT(6))
2373 sio_data->skip_pwm |= BIT(2);
2374 if (reg & BIT(7))
2375 sio_data->skip_fan |= BIT(2);
3ba9d977 2376
36c4d98a 2377 /* Check for pwm4 */
3c2e3512 2378 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
48b2ae7f
GR		 2379 if (!(reg & BIT(2)))
2380 sio_data->skip_pwm |= BIT(3);
36c4d98a 2381
3ba9d977 2382 /* Check for pwm2, fan2 */
3c2e3512 2383 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2384 if (reg & BIT(1))
2385 sio_data->skip_pwm |= BIT(1);
2386 if (reg & BIT(2))
2387 sio_data->skip_fan |= BIT(1);
36c4d98a 2388 /* Check for pwm6, fan6 */
48b2ae7f
GR		 2389 if (!(reg & BIT(7))) {
2390 sio_data->skip_pwm |= BIT(5);
2391 sio_data->skip_fan |= BIT(5);
36c4d98a 2392 }
3ba9d977 2393
3c2e3512
GR		 2394 sio_data->beep_pin = superio_inb(sioaddr,
2395 IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 2396 } else {
87673dd7 2397 int reg;
9172b5d1 2398 bool uart6;
87673dd7 2399
3c2e3512 2400 superio_select(sioaddr, GPIO);
44c1bcd4 2401
3c2e3512 2402 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
32dd7c40 2403 if (!sio_data->skip_vid) {
44c1bcd4
JD		 2404 /* We need at least 4 VID pins */
2405 if (reg & 0x0f) {
a8ca1037 2406 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 2407 sio_data->skip_vid = 1;
2408 }
895ff267
JD		 2409 }
2410
591ec650 2411 /* Check if fan3 is there or not */
48b2ae7f
GR		 2412 if (reg & BIT(6))
2413 sio_data->skip_pwm |= BIT(2);
2414 if (reg & BIT(7))
2415 sio_data->skip_fan |= BIT(2);
591ec650
JD		 2416
2417 /* Check if fan2 is there or not */
3c2e3512 2418 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2419 if (reg & BIT(1))
2420 sio_data->skip_pwm |= BIT(1);
2421 if (reg & BIT(2))
2422 sio_data->skip_fan |= BIT(1);
591ec650 2423
895ff267
JD		 2424 if ((sio_data->type == it8718 || sio_data->type == it8720)
2425 && !(sio_data->skip_vid))
3c2e3512
GR		 2426 sio_data->vid_value = superio_inb(sioaddr,
2427 IT87_SIO_VID_REG);
87673dd7 2428
3c2e3512 2429 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
9172b5d1 2430
48b2ae7f 2431 uart6 = sio_data->type == it8782 && (reg & BIT(2));
9172b5d1 2432
436cad2a
JD		 2433 /*
2434 * The IT8720F has no VIN7 pin, so VCCH should always be
2435 * routed internally to VIN7 with an internal divider.
2436 * Curiously, there still is a configuration bit to control
2437 * this, which means it can be set incorrectly. And even
2438 * more curiously, many boards out there are improperly
2439 * configured, even though the IT8720F datasheet claims
2440 * that the internal routing of VCCH to VIN7 is the default
2441 * setting. So we force the internal routing in this case.
0531d98b
GR		 2442 *
2443 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2444 * If UART6 is enabled, re-route VIN7 to the internal divider
2445 * if that is not already the case.
436cad2a 2446 */
48b2ae7f
GR		 2447 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2448 reg |= BIT(1);
3c2e3512 2449 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
a8ca1037 2450 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2451 }
48b2ae7f
GR		 2452 if (reg & BIT(0))
2453 sio_data->internal |= BIT(0);
2454 if (reg & BIT(1))
2455 sio_data->internal |= BIT(1);
d9b327c3 2456
9172b5d1
GR		 2457 /*
2458 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2459 * While VIN7 can be routed to the internal voltage divider,
2460 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2461 *
2462 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2463 * is the temperature source. Since we can not read the
2464 * temperature source here, skip_temp is preliminary.
9172b5d1 2465 */
4573acbc 2466 if (uart6) {
48b2ae7f
GR		 2467 sio_data->skip_in |= BIT(5) | BIT(6);
2468 sio_data->skip_temp |= BIT(2);
4573acbc 2469 }
9172b5d1 2470
3c2e3512
GR		 2471 sio_data->beep_pin = superio_inb(sioaddr,
2472 IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2473 }
d9b327c3 2474 if (sio_data->beep_pin)
a8ca1037 2475 pr_info("Beeping is supported\n");
87673dd7 2476
98dd22c3
JD		 2477 /* Disable specific features based on DMI strings */
2478 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2479 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2480 if (board_vendor && board_name) {
2481 if (strcmp(board_vendor, "nVIDIA") == 0
2482 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2483 /*
2484 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2485 * connected to a fan, but to something else. One user
2486 * has reported instant system power-off when changing
2487 * the PWM2 duty cycle, so we disable it.
2488 * I use the board name string as the trigger in case
2489 * the same board is ever used in other systems.
2490 */
a8ca1037 2491 pr_info("Disabling pwm2 due to hardware constraints\n");
48b2ae7f 2492 sio_data->skip_pwm = BIT(1);
98dd22c3
JD		 2493 }
2494 }
2495
1da177e4 2496exit:
3c2e3512 2497 superio_exit(sioaddr);
1da177e4
LT		 2498 return err;
2499}
2500
c1e7a4ca
GR		 2501/* Called when we have found a new IT87. */
2502static void it87_init_device(struct platform_device *pdev)
1da177e4 2503{
c1e7a4ca
GR		 2504 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2505 struct it87_data *data = platform_get_drvdata(pdev);
2506 int tmp, i;
2507 u8 mask;
b74f3fdd 2508
c1e7a4ca
GR		 2509 /*
2510 * For each PWM channel:
2511 * - If it is in automatic mode, setting to manual mode should set
2512 * the fan to full speed by default.
2513 * - If it is in manual mode, we need a mapping to temperature
2514 * channels to use when later setting to automatic mode later.
2515 * Use a 1:1 mapping by default (we are clueless.)
2516 * In both cases, the value can (and should) be changed by the user
2517 * prior to switching to a different mode.
2518 * Note that this is no longer needed for the IT8721F and later, as
2519 * these have separate registers for the temperature mapping and the
2520 * manual duty cycle.
2521 */
2310048d 2522 for (i = 0; i < NUM_AUTO_PWM; i++) {
c1e7a4ca
GR		 2523 data->pwm_temp_map[i] = i;
2524 data->pwm_duty[i] = 0x7f; /* Full speed */
2525 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
8e9afcbb 2526 }
1da177e4 2527
483db43e 2528 /*
c1e7a4ca
GR		 2529 * Some chips seem to have default value 0xff for all limit
2530 * registers. For low voltage limits it makes no sense and triggers
2531 * alarms, so change to 0 instead. For high temperature limits, it
2532 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2533 * but is still confusing, so change to 127 degrees C.
483db43e 2534 */
2310048d 2535 for (i = 0; i < NUM_VIN_LIMIT; i++) {
c1e7a4ca
GR		 2536 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2537 if (tmp == 0xff)
2538 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2539 }
2310048d 2540 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
c1e7a4ca
GR		 2541 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2542 if (tmp == 0xff)
2543 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
483db43e 2544 }
1da177e4 2545
c1e7a4ca
GR		 2546 /*
2547 * Temperature channels are not forcibly enabled, as they can be
2548 * set to two different sensor types and we can't guess which one
2549 * is correct for a given system. These channels can be enabled at
2550 * run-time through the temp{1-3}_type sysfs accessors if needed.
2551 */
1da177e4 2552
c1e7a4ca
GR		 2553 /* Check if voltage monitors are reset manually or by some reason */
2554 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2555 if ((tmp & 0xff) == 0) {
2556 /* Enable all voltage monitors */
2557 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2558 }
2559
2560 /* Check if tachometers are reset manually or by some reason */
2561 mask = 0x70 & ~(sio_data->skip_fan << 4);
2562 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2563 if ((data->fan_main_ctrl & mask) == 0) {
2564 /* Enable all fan tachometers */
2565 data->fan_main_ctrl |= mask;
2566 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2567 data->fan_main_ctrl);
2568 }
2569 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2570
2571 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2572
2573 /* Set tachometers to 16-bit mode if needed */
2574 if (has_fan16_config(data)) {
2575 if (~tmp & 0x07 & data->has_fan) {
2576 dev_dbg(&pdev->dev,
2577 "Setting fan1-3 to 16-bit mode\n");
2578 it87_write_value(data, IT87_REG_FAN_16BIT,
2579 tmp | 0x07);
2580 }
2581 }
2582
2583 /* Check for additional fans */
2584 if (has_five_fans(data)) {
48b2ae7f
GR		 2585 if (tmp & BIT(4))
2586 data->has_fan |= BIT(3); /* fan4 enabled */
2587 if (tmp & BIT(5))
2588 data->has_fan |= BIT(4); /* fan5 enabled */
2589 if (has_six_fans(data) && (tmp & BIT(2)))
2590 data->has_fan |= BIT(5); /* fan6 enabled */
c1e7a4ca
GR		 2591 }
2592
2593 /* Fan input pins may be used for alternative functions */
2594 data->has_fan &= ~sio_data->skip_fan;
2595
2596 /* Check if pwm5, pwm6 are enabled */
2597 if (has_six_pwm(data)) {
2598 /* The following code may be IT8620E specific */
2599 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2600 if ((tmp & 0xc0) == 0xc0)
48b2ae7f
GR		 2601 sio_data->skip_pwm |= BIT(4);
2602 if (!(tmp & BIT(3)))
2603 sio_data->skip_pwm |= BIT(5);
c1e7a4ca
GR		 2604 }
2605
2606 /* Start monitoring */
2607 it87_write_value(data, IT87_REG_CONFIG,
2608 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2609 | (update_vbat ? 0x41 : 0x01));
2610}
2611
2612/* Return 1 if and only if the PWM interface is safe to use */
2613static int it87_check_pwm(struct device *dev)
2614{
2615 struct it87_data *data = dev_get_drvdata(dev);
2616 /*
2617 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2618 * and polarity set to active low is sign that this is the case so we
2619 * disable pwm control to protect the user.
2620 */
2621 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2622
2623 if ((tmp & 0x87) == 0) {
2624 if (fix_pwm_polarity) {
2625 /*
2626 * The user asks us to attempt a chip reconfiguration.
2627 * This means switching to active high polarity and
2628 * inverting all fan speed values.
2629 */
2630 int i;
2631 u8 pwm[3];
2632
2310048d 2633 for (i = 0; i < ARRAY_SIZE(pwm); i++)
c1e7a4ca
GR		 2634 pwm[i] = it87_read_value(data,
2635 IT87_REG_PWM[i]);
2636
2637 /*
2638 * If any fan is in automatic pwm mode, the polarity
2639 * might be correct, as suspicious as it seems, so we
2640 * better don't change anything (but still disable the
2641 * PWM interface).
2642 */
2643 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2644 dev_info(dev,
2645 "Reconfiguring PWM to active high polarity\n");
2646 it87_write_value(data, IT87_REG_FAN_CTL,
2647 tmp | 0x87);
2648 for (i = 0; i < 3; i++)
2649 it87_write_value(data,
2650 IT87_REG_PWM[i],
2651 0x7f & ~pwm[i]);
2652 return 1;
2653 }
2654
2655 dev_info(dev,
2656 "PWM configuration is too broken to be fixed\n");
2657 }
2658
2659 dev_info(dev,
2660 "Detected broken BIOS defaults, disabling PWM interface\n");
2661 return 0;
2662 } else if (fix_pwm_polarity) {
2663 dev_info(dev,
2664 "PWM configuration looks sane, won't touch\n");
2665 }
2666
2667 return 1;
2668}
2669
2670static int it87_probe(struct platform_device *pdev)
2671{
2672 struct it87_data *data;
2673 struct resource *res;
2674 struct device *dev = &pdev->dev;
2675 struct it87_sio_data *sio_data = dev_get_platdata(dev);
c1e7a4ca 2676 int enable_pwm_interface;
8638d0af 2677 struct device *hwmon_dev;
c1e7a4ca
GR		 2678
2679 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2680 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2681 DRVNAME)) {
2682 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2683 (unsigned long)res->start,
2684 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
2685 return -EBUSY;
2686 }
2687
2688 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2689 if (!data)
2690 return -ENOMEM;
2691
2692 data->addr = res->start;
2693 data->type = sio_data->type;
2694 data->features = it87_devices[sio_data->type].features;
2695 data->peci_mask = it87_devices[sio_data->type].peci_mask;
2696 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
c1e7a4ca
GR		 2697 /*
2698 * IT8705F Datasheet 0.4.1, 3h == Version G.
2699 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2700 * These are the first revisions with 16-bit tachometer support.
2701 */
2702 switch (data->type) {
2703 case it87:
2704 if (sio_data->revision >= 0x03) {
2705 data->features &= ~FEAT_OLD_AUTOPWM;
2706 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
2707 }
2708 break;
2709 case it8712:
2710 if (sio_data->revision >= 0x08) {
2711 data->features &= ~FEAT_OLD_AUTOPWM;
2712 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2713 FEAT_FIVE_FANS;
2714 }
2715 break;
2716 default:
2717 break;
2718 }
2719
2720 /* Now, we do the remaining detection. */
2721 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
2722 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2723 return -ENODEV;
2724
2725 platform_set_drvdata(pdev, data);
1da177e4 2726
9a61bf63 2727 mutex_init(&data->update_lock);
1da177e4 2728
1da177e4 2729 /* Check PWM configuration */
b74f3fdd 2730 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2731
44c1bcd4 2732 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2733 if (has_12mv_adc(data)) {
48b2ae7f
GR		 2734 if (sio_data->internal & BIT(0))
2735 data->in_scaled |= BIT(3); /* in3 is AVCC */
2736 if (sio_data->internal & BIT(1))
2737 data->in_scaled |= BIT(7); /* in7 is VSB */
2738 if (sio_data->internal & BIT(2))
2739 data->in_scaled |= BIT(8); /* in8 is Vbat */
2740 if (sio_data->internal & BIT(3))
2741 data->in_scaled |= BIT(9); /* in9 is AVCC */
7bc32d29
GR		 2742 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2743 sio_data->type == it8783) {
48b2ae7f
GR		 2744 if (sio_data->internal & BIT(0))
2745 data->in_scaled |= BIT(3); /* in3 is VCC5V */
2746 if (sio_data->internal & BIT(1))
2747 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
44c1bcd4
JD		 2748 }
2749
4573acbc 2750 data->has_temp = 0x07;
48b2ae7f 2751 if (sio_data->skip_temp & BIT(2)) {
4573acbc
GR		 2752 if (sio_data->type == it8782
2753 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
48b2ae7f 2754 data->has_temp &= ~BIT(2);
4573acbc
GR		 2755 }
2756
d3766848 2757 data->in_internal = sio_data->internal;
52929715
GR		 2758 data->has_in = 0x3ff & ~sio_data->skip_in;
2759
cc18da79
GR		 2760 if (has_six_temp(data)) {
2761 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
2762
f838aa26 2763 /* Check for additional temperature sensors */
cc18da79 2764 if ((reg & 0x03) >= 0x02)
48b2ae7f 2765 data->has_temp |= BIT(3);
cc18da79 2766 if (((reg >> 2) & 0x03) >= 0x02)
48b2ae7f 2767 data->has_temp |= BIT(4);
cc18da79 2768 if (((reg >> 4) & 0x03) >= 0x02)
48b2ae7f 2769 data->has_temp |= BIT(5);
f838aa26
GR		 2770
2771 /* Check for additional voltage sensors */
2772 if ((reg & 0x03) == 0x01)
48b2ae7f 2773 data->has_in |= BIT(10);
f838aa26 2774 if (((reg >> 2) & 0x03) == 0x01)
48b2ae7f 2775 data->has_in |= BIT(11);
f838aa26 2776 if (((reg >> 4) & 0x03) == 0x01)
48b2ae7f 2777 data->has_in |= BIT(12);
cc18da79
GR		 2778 }
2779
52929715
GR		 2780 data->has_beep = !!sio_data->beep_pin;
2781
1da177e4 2782 /* Initialize the IT87 chip */
b74f3fdd 2783 it87_init_device(pdev);
1da177e4 2784
d3766848
GR		 2785 if (!sio_data->skip_vid) {
2786 data->has_vid = true;
2787 data->vrm = vid_which_vrm();
2788 /* VID reading from Super-I/O config space if available */
2789 data->vid = sio_data->vid_value;
2790 }
2791
8638d0af
GR		 2792 /* Prepare for sysfs hooks */
2793 data->groups[0] = &it87_group;
2794 data->groups[1] = &it87_group_in;
2795 data->groups[2] = &it87_group_temp;
2796 data->groups[3] = &it87_group_fan;
17d648bf 2797
1da177e4 2798 if (enable_pwm_interface) {
48b2ae7f 2799 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
5c391261 2800 data->has_pwm &= ~sio_data->skip_pwm;
4f3f51bc 2801
8638d0af
GR		 2802 data->groups[4] = &it87_group_pwm;
2803 if (has_old_autopwm(data))
2804 data->groups[5] = &it87_group_auto_pwm;
1da177e4
LT		 2805 }
2806
8638d0af
GR		 2807 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
2808 it87_devices[sio_data->type].name,
2809 data, data->groups);
2810 return PTR_ERR_OR_ZERO(hwmon_dev);
1da177e4
LT		 2811}
2812
c1e7a4ca
GR		 2813static struct platform_driver it87_driver = {
2814 .driver = {
2815 .name = DRVNAME,
2816 },
2817 .probe = it87_probe,
c1e7a4ca 2818};
1da177e4 2819
e84bd953 2820static int __init it87_device_add(int index, unsigned short address,
b74f3fdd 2821 const struct it87_sio_data *sio_data)
2822{
8e50e3c3 2823 struct platform_device *pdev;
b74f3fdd 2824 struct resource res = {
87b4b663
BH		 2825 .start = address + IT87_EC_OFFSET,
2826 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2827 .name = DRVNAME,
2828 .flags = IORESOURCE_IO,
2829 };
2830 int err;
2831
b9acb64a
JD		 2832 err = acpi_check_resource_conflict(&res);
2833 if (err)
5cae84a5 2834 return err;
b9acb64a 2835
b74f3fdd 2836 pdev = platform_device_alloc(DRVNAME, address);
5cae84a5
GR		 2837 if (!pdev)
2838 return -ENOMEM;
b74f3fdd 2839
2840 err = platform_device_add_resources(pdev, &res, 1);
2841 if (err) {
a8ca1037 2842 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2843 goto exit_device_put;
2844 }
2845
2846 err = platform_device_add_data(pdev, sio_data,
2847 sizeof(struct it87_sio_data));
2848 if (err) {
a8ca1037 2849 pr_err("Platform data allocation failed\n");
b74f3fdd 2850 goto exit_device_put;
2851 }
2852
2853 err = platform_device_add(pdev);
2854 if (err) {
a8ca1037 2855 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2856 goto exit_device_put;
2857 }
2858
e84bd953 2859 it87_pdev[index] = pdev;
b74f3fdd 2860 return 0;
2861
2862exit_device_put:
2863 platform_device_put(pdev);
b74f3fdd 2864 return err;
2865}
2866
1da177e4
LT		 2867static int __init sm_it87_init(void)
2868{
e84bd953 2869 int sioaddr[2] = { REG_2E, REG_4E };
b74f3fdd 2870 struct it87_sio_data sio_data;
e84bd953
GR		 2871 unsigned short isa_address;
2872 bool found = false;
2873 int i, err;
b74f3fdd 2874
b74f3fdd 2875 err = platform_driver_register(&it87_driver);
2876 if (err)
2877 return err;
fde09509 2878
e84bd953
GR		 2879 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
2880 memset(&sio_data, 0, sizeof(struct it87_sio_data));
2881 isa_address = 0;
2882 err = it87_find(sioaddr[i], &isa_address, &sio_data);
2883 if (err || isa_address == 0)
2884 continue;
2885
2886 err = it87_device_add(i, isa_address, &sio_data);
2887 if (err)
2888 goto exit_dev_unregister;
2889 found = true;
b74f3fdd 2890 }
2891
e84bd953
GR		 2892 if (!found) {
2893 err = -ENODEV;
2894 goto exit_unregister;
2895 }
b74f3fdd 2896 return 0;
e84bd953
GR		 2897
2898exit_dev_unregister:
2899 /* NULL check handled by platform_device_unregister */
2900 platform_device_unregister(it87_pdev[0]);
2901exit_unregister:
2902 platform_driver_unregister(&it87_driver);
2903 return err;
1da177e4
LT		 2904}
2905
2906static void __exit sm_it87_exit(void)
2907{
e84bd953
GR		 2908 /* NULL check handled by platform_device_unregister */
2909 platform_device_unregister(it87_pdev[1]);
2910 platform_device_unregister(it87_pdev[0]);
b74f3fdd 2911 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2912}
2913
2914
7c81c60f 2915MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2916MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2917module_param(update_vbat, bool, 0);
2918MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2919module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2920MODULE_PARM_DESC(fix_pwm_polarity,
2921 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2922MODULE_LICENSE("GPL");
2923
2924module_init(sm_it87_init);
2925module_exit(sm_it87_exit);
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