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hwmon: (it87) Report thermal sensor type as Intel PECI if appropriate
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
13 * Supports: IT8705F Super I/O chip w/LPC interface
14 * IT8712F Super I/O chip w/LPC interface
15 * IT8716F Super I/O chip w/LPC interface
16 * IT8718F Super I/O chip w/LPC interface
17 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 18 * IT8721F Super I/O chip w/LPC interface
5f2dc798 19 * IT8726F Super I/O chip w/LPC interface
16b5dda2 20 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8758E Super I/O chip w/LPC interface
0531d98b
GR		 22 * IT8782F Super I/O chip w/LPC interface
23 * IT8783E/F Super I/O chip w/LPC interface
5f2dc798
JD		 24 * Sis950 A clone of the IT8705F
25 *
26 * Copyright (C) 2001 Chris Gauthron
27 * Copyright (C) 2005-2010 Jean Delvare <khali@linux-fr.org>
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
42 */
1da177e4 43
a8ca1037
JP		 44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
1da177e4
LT		 46#include <linux/module.h>
47#include <linux/init.h>
48#include <linux/slab.h>
49#include <linux/jiffies.h>
b74f3fdd 50#include <linux/platform_device.h>
943b0830 51#include <linux/hwmon.h>
303760b4
JD		 52#include <linux/hwmon-sysfs.h>
53#include <linux/hwmon-vid.h>
943b0830 54#include <linux/err.h>
9a61bf63 55#include <linux/mutex.h>
87808be4 56#include <linux/sysfs.h>
98dd22c3
JD		 57#include <linux/string.h>
58#include <linux/dmi.h>
b9acb64a 59#include <linux/acpi.h>
6055fae8 60#include <linux/io.h>
1da177e4 61
b74f3fdd 62#define DRVNAME "it87"
1da177e4 63
0531d98b
GR		 64enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8782,
65 it8783 };
1da177e4 66
67b671bc
JD		 67static unsigned short force_id;
68module_param(force_id, ushort, 0);
69MODULE_PARM_DESC(force_id, "Override the detected device ID");
70
b74f3fdd 71static struct platform_device *pdev;
72
1da177e4
LT		 73#define REG 0x2e /* The register to read/write */
74#define DEV 0x07 /* Register: Logical device select */
75#define VAL 0x2f /* The value to read/write */
76#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 77
78/* The device with the IT8718F/IT8720F VID value in it */
79#define GPIO 0x07
80
1da177e4
LT		 81#define DEVID 0x20 /* Register: Device ID */
82#define DEVREV 0x22 /* Register: Device Revision */
83
5b0380c9 84static inline int superio_inb(int reg)
1da177e4
LT		 85{
86 outb(reg, REG);
87 return inb(VAL);
88}
89
5b0380c9 90static inline void superio_outb(int reg, int val)
436cad2a
JD		 91{
92 outb(reg, REG);
93 outb(val, VAL);
94}
95
1da177e4
LT		 96static int superio_inw(int reg)
97{
98 int val;
99 outb(reg++, REG);
100 val = inb(VAL) << 8;
101 outb(reg, REG);
102 val |= inb(VAL);
103 return val;
104}
105
5b0380c9 106static inline void superio_select(int ldn)
1da177e4
LT		 107{
108 outb(DEV, REG);
87673dd7 109 outb(ldn, VAL);
1da177e4
LT		 110}
111
5b0380c9 112static inline int superio_enter(void)
1da177e4 113{
5b0380c9
NG		 114 /*
115 * Try to reserve REG and REG + 1 for exclusive access.
116 */
117 if (!request_muxed_region(REG, 2, DRVNAME))
118 return -EBUSY;
119
1da177e4
LT		 120 outb(0x87, REG);
121 outb(0x01, REG);
122 outb(0x55, REG);
123 outb(0x55, REG);
5b0380c9 124 return 0;
1da177e4
LT		 125}
126
5b0380c9 127static inline void superio_exit(void)
1da177e4
LT		 128{
129 outb(0x02, REG);
130 outb(0x02, VAL);
5b0380c9 131 release_region(REG, 2);
1da177e4
LT		 132}
133
87673dd7 134/* Logical device 4 registers */
1da177e4
LT		 135#define IT8712F_DEVID 0x8712
136#define IT8705F_DEVID 0x8705
17d648bf 137#define IT8716F_DEVID 0x8716
87673dd7 138#define IT8718F_DEVID 0x8718
b4da93e4 139#define IT8720F_DEVID 0x8720
44c1bcd4 140#define IT8721F_DEVID 0x8721
08a8f6e9 141#define IT8726F_DEVID 0x8726
16b5dda2 142#define IT8728F_DEVID 0x8728
0531d98b
GR		 143#define IT8782F_DEVID 0x8782
144#define IT8783E_DEVID 0x8783
1da177e4
LT		 145#define IT87_ACT_REG 0x30
146#define IT87_BASE_REG 0x60
147
87673dd7 148/* Logical device 7 registers (IT8712F and later) */
0531d98b 149#define IT87_SIO_GPIO1_REG 0x25
895ff267 150#define IT87_SIO_GPIO3_REG 0x27
591ec650 151#define IT87_SIO_GPIO5_REG 0x29
0531d98b 152#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 153#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 154#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 155#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 156#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 157
1da177e4 158/* Update battery voltage after every reading if true */
90ab5ee9 159static bool update_vbat;
1da177e4
LT		 160
161/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 162static bool fix_pwm_polarity;
1da177e4 163
1da177e4
LT		 164/* Many IT87 constants specified below */
165
166/* Length of ISA address segment */
167#define IT87_EXTENT 8
168
87b4b663
BH		 169/* Length of ISA address segment for Environmental Controller */
170#define IT87_EC_EXTENT 2
171
172/* Offset of EC registers from ISA base address */
173#define IT87_EC_OFFSET 5
174
175/* Where are the ISA address/data registers relative to the EC base address */
176#define IT87_ADDR_REG_OFFSET 0
177#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 178
179/*----- The IT87 registers -----*/
180
181#define IT87_REG_CONFIG 0x00
182
183#define IT87_REG_ALARM1 0x01
184#define IT87_REG_ALARM2 0x02
185#define IT87_REG_ALARM3 0x03
186
4a0d71cf
GR		 187/*
188 * The IT8718F and IT8720F have the VID value in a different register, in
189 * Super-I/O configuration space.
190 */
1da177e4 191#define IT87_REG_VID 0x0a
4a0d71cf
GR		 192/*
193 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
194 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
195 * mode.
196 */
1da177e4 197#define IT87_REG_FAN_DIV 0x0b
17d648bf 198#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 199
200/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
201
c7f1f716
JD		 202static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
203static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
204static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
205static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 206static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
207
1da177e4
LT		 208#define IT87_REG_FAN_MAIN_CTRL 0x13
209#define IT87_REG_FAN_CTL 0x14
210#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 211#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 212
213#define IT87_REG_VIN(nr) (0x20 + (nr))
214#define IT87_REG_TEMP(nr) (0x29 + (nr))
215
216#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
217#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
218#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
219#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
220
1da177e4
LT		 221#define IT87_REG_VIN_ENABLE 0x50
222#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 223#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 224#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 225
226#define IT87_REG_CHIPID 0x58
227
4f3f51bc
JD		 228#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
229#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
230
483db43e
GR		 231struct it87_devices {
232 const char *name;
233 u16 features;
5d8d2f2b 234 u16 peci_mask;
483db43e
GR		 235};
236
237#define FEAT_12MV_ADC (1 << 0)
238#define FEAT_NEWER_AUTOPWM (1 << 1)
239#define FEAT_OLD_AUTOPWM (1 << 2)
240#define FEAT_16BIT_FANS (1 << 3)
241#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 242#define FEAT_TEMP_PECI (1 << 5)
483db43e
GR		 243
244static const struct it87_devices it87_devices[] = {
245 [it87] = {
246 .name = "it87",
247 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
248 },
249 [it8712] = {
250 .name = "it8712",
251 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
252 },
253 [it8716] = {
254 .name = "it8716",
255 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
256 },
257 [it8718] = {
258 .name = "it8718",
259 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
260 },
261 [it8720] = {
262 .name = "it8720",
263 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
264 },
265 [it8721] = {
266 .name = "it8721",
267 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
5d8d2f2b
GR		 268 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
269 .peci_mask = 0x05,
483db43e
GR		 270 },
271 [it8728] = {
272 .name = "it8728",
273 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
5d8d2f2b
GR		 274 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
275 .peci_mask = 0x07,
483db43e
GR		 276 },
277 [it8782] = {
278 .name = "it8782",
279 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
280 },
281 [it8783] = {
282 .name = "it8783",
283 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET,
284 },
285};
286
287#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
288#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
289#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
290#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
291#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 292#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
293 ((data)->peci_mask & (1 << nr)))
1da177e4 294
b74f3fdd 295struct it87_sio_data {
296 enum chips type;
297 /* Values read from Super-I/O config space */
0475169c 298 u8 revision;
b74f3fdd 299 u8 vid_value;
d9b327c3 300 u8 beep_pin;
738e5e05 301 u8 internal; /* Internal sensors can be labeled */
591ec650 302 /* Features skipped based on config or DMI */
9172b5d1 303 u16 skip_in;
895ff267 304 u8 skip_vid;
591ec650 305 u8 skip_fan;
98dd22c3 306 u8 skip_pwm;
4573acbc 307 u8 skip_temp;
b74f3fdd 308};
309
4a0d71cf
GR		 310/*
311 * For each registered chip, we need to keep some data in memory.
312 * The structure is dynamically allocated.
313 */
1da177e4 314struct it87_data {
1beeffe4 315 struct device *hwmon_dev;
1da177e4 316 enum chips type;
483db43e 317 u16 features;
5d8d2f2b 318 u16 peci_mask;
1da177e4 319
b74f3fdd 320 unsigned short addr;
321 const char *name;
9a61bf63 322 struct mutex update_lock;
1da177e4
LT		 323 char valid; /* !=0 if following fields are valid */
324 unsigned long last_updated; /* In jiffies */
325
44c1bcd4 326 u16 in_scaled; /* Internal voltage sensors are scaled */
929c6a56 327 u8 in[9][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 328 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 329 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 330 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 331 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
1da177e4
LT		 332 u8 sensor; /* Register value */
333 u8 fan_div[3]; /* Register encoding, shifted right */
334 u8 vid; /* Register encoding, combined */
a7be58a1 335 u8 vrm;
1da177e4 336 u32 alarms; /* Register encoding, combined */
d9b327c3 337 u8 beeps; /* Register encoding */
1da177e4 338 u8 fan_main_ctrl; /* Register value */
f8d0c19a 339 u8 fan_ctl; /* Register value */
b99883dc 340
4a0d71cf
GR		 341 /*
342 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 343 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
344 * 7, and we want to preserve settings on mode changes, so we have
345 * to track all values separately.
346 * Starting with the IT8721F, the manual PWM duty cycles are stored
347 * in separate registers (8-bit values), so the separate tracking
348 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 349 * simple.
350 */
b99883dc 351 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 352 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 353 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 354
355 /* Automatic fan speed control registers */
356 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
357 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 358};
0df6454d 359
0531d98b 360static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 361{
0531d98b
GR		 362 int lsb = has_12mv_adc(data) ? 12 : 16;
363 if (data->in_scaled & (1 << nr))
364 lsb <<= 1;
365 return lsb;
366}
44c1bcd4 367
0531d98b
GR		 368static u8 in_to_reg(const struct it87_data *data, int nr, long val)
369{
370 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
44c1bcd4
JD		 371 return SENSORS_LIMIT(val, 0, 255);
372}
373
374static int in_from_reg(const struct it87_data *data, int nr, int val)
375{
0531d98b 376 return val * adc_lsb(data, nr);
44c1bcd4 377}
0df6454d
JD		 378
379static inline u8 FAN_TO_REG(long rpm, int div)
380{
381 if (rpm == 0)
382 return 255;
383 rpm = SENSORS_LIMIT(rpm, 1, 1000000);
384 return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1,
385 254);
386}
387
388static inline u16 FAN16_TO_REG(long rpm)
389{
390 if (rpm == 0)
391 return 0xffff;
392 return SENSORS_LIMIT((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
393}
394
395#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
396 1350000 / ((val) * (div)))
397/* The divider is fixed to 2 in 16-bit mode */
398#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
399 1350000 / ((val) * 2))
400
401#define TEMP_TO_REG(val) (SENSORS_LIMIT(((val) < 0 ? (((val) - 500) / 1000) : \
402 ((val) + 500) / 1000), -128, 127))
403#define TEMP_FROM_REG(val) ((val) * 1000)
404
44c1bcd4
JD		 405static u8 pwm_to_reg(const struct it87_data *data, long val)
406{
16b5dda2 407 if (has_newer_autopwm(data))
44c1bcd4
JD		 408 return val;
409 else
410 return val >> 1;
411}
412
413static int pwm_from_reg(const struct it87_data *data, u8 reg)
414{
16b5dda2 415 if (has_newer_autopwm(data))
44c1bcd4
JD		 416 return reg;
417 else
418 return (reg & 0x7f) << 1;
419}
420
0df6454d
JD		 421
422static int DIV_TO_REG(int val)
423{
424 int answer = 0;
425 while (answer < 7 && (val >>= 1))
426 answer++;
427 return answer;
428}
429#define DIV_FROM_REG(val) (1 << (val))
430
431static const unsigned int pwm_freq[8] = {
432 48000000 / 128,
433 24000000 / 128,
434 12000000 / 128,
435 8000000 / 128,
436 6000000 / 128,
437 3000000 / 128,
438 1500000 / 128,
439 750000 / 128,
440};
1da177e4 441
b74f3fdd 442static int it87_probe(struct platform_device *pdev);
281dfd0b 443static int it87_remove(struct platform_device *pdev);
1da177e4 444
b74f3fdd 445static int it87_read_value(struct it87_data *data, u8 reg);
446static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 447static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 448static int it87_check_pwm(struct device *dev);
449static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 450
451
b74f3fdd 452static struct platform_driver it87_driver = {
cdaf7934 453 .driver = {
87218842 454 .owner = THIS_MODULE,
b74f3fdd 455 .name = DRVNAME,
cdaf7934 456 },
b74f3fdd 457 .probe = it87_probe,
9e5e9b7a 458 .remove = it87_remove,
fde09509
JD		 459};
460
20ad93d4 461static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 462 char *buf)
1da177e4 463{
929c6a56
GR		 464 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
465 int nr = sattr->nr;
466 int index = sattr->index;
20ad93d4 467
1da177e4 468 struct it87_data *data = it87_update_device(dev);
929c6a56 469 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 470}
471
929c6a56
GR		 472static ssize_t set_in(struct device *dev, struct device_attribute *attr,
473 const char *buf, size_t count)
1da177e4 474{
929c6a56
GR		 475 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
476 int nr = sattr->nr;
477 int index = sattr->index;
20ad93d4 478
b74f3fdd 479 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 480 unsigned long val;
481
179c4fdb 482 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 483 return -EINVAL;
1da177e4 484
9a61bf63 485 mutex_lock(&data->update_lock);
929c6a56
GR		 486 data->in[nr][index] = in_to_reg(data, nr, val);
487 it87_write_value(data,
488 index == 1 ? IT87_REG_VIN_MIN(nr)
489 : IT87_REG_VIN_MAX(nr),
490 data->in[nr][index]);
9a61bf63 491 mutex_unlock(&data->update_lock);
1da177e4
LT		 492 return count;
493}
20ad93d4 494
929c6a56
GR		 495static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
496static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
497 0, 1);
498static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
499 0, 2);
f5f64501 500
929c6a56
GR		 501static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
502static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
503 1, 1);
504static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
505 1, 2);
1da177e4 506
929c6a56
GR		 507static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
508static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
509 2, 1);
510static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
511 2, 2);
1da177e4 512
929c6a56
GR		 513static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
514static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
515 3, 1);
516static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
517 3, 2);
518
519static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
520static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
521 4, 1);
522static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
523 4, 2);
524
525static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
526static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
527 5, 1);
528static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
529 5, 2);
530
531static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
532static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
533 6, 1);
534static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
535 6, 2);
536
537static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
538static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
539 7, 1);
540static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
541 7, 2);
542
543static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1da177e4
LT		 544
545/* 3 temperatures */
20ad93d4 546static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 547 char *buf)
1da177e4 548{
60ca385a
GR		 549 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
550 int nr = sattr->nr;
551 int index = sattr->index;
1da177e4 552 struct it87_data *data = it87_update_device(dev);
20ad93d4 553
60ca385a 554 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 555}
20ad93d4 556
60ca385a
GR		 557static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
558 const char *buf, size_t count)
1da177e4 559{
60ca385a
GR		 560 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
561 int nr = sattr->nr;
562 int index = sattr->index;
b74f3fdd 563 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 564 long val;
161d898a 565 u8 reg, regval;
f5f64501 566
179c4fdb 567 if (kstrtol(buf, 10, &val) < 0)
f5f64501 568 return -EINVAL;
1da177e4 569
9a61bf63 570 mutex_lock(&data->update_lock);
161d898a
GR		 571
572 switch (index) {
573 default:
574 case 1:
575 reg = IT87_REG_TEMP_LOW(nr);
576 break;
577 case 2:
578 reg = IT87_REG_TEMP_HIGH(nr);
579 break;
580 case 3:
581 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
582 if (!(regval & 0x80)) {
583 regval |= 0x80;
584 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
585 }
586 data->valid = 0;
587 reg = IT87_REG_TEMP_OFFSET[nr];
588 break;
589 }
590
60ca385a 591 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 592 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 593 mutex_unlock(&data->update_lock);
1da177e4
LT		 594 return count;
595}
1da177e4 596
60ca385a
GR		 597static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
598static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
599 0, 1);
600static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
601 0, 2);
161d898a
GR		 602static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
603 set_temp, 0, 3);
60ca385a
GR		 604static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
605static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
606 1, 1);
607static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
608 1, 2);
161d898a
GR		 609static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
610 set_temp, 1, 3);
60ca385a
GR		 611static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
612static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
613 2, 1);
614static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
615 2, 2);
161d898a
GR		 616static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
617 set_temp, 2, 3);
1da177e4 618
2cece01f
GR		 619static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
620 char *buf)
1da177e4 621{
20ad93d4
JD		 622 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
623 int nr = sensor_attr->index;
1da177e4 624 struct it87_data *data = it87_update_device(dev);
4a0d71cf 625 u8 reg = data->sensor; /* In case value is updated while used */
5f2dc798 626
5d8d2f2b
GR		 627 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
628 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 629 if (reg & (1 << nr))
630 return sprintf(buf, "3\n"); /* thermal diode */
631 if (reg & (8 << nr))
4ed10779 632 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 633 return sprintf(buf, "0\n"); /* disabled */
634}
2cece01f
GR		 635
636static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
637 const char *buf, size_t count)
1da177e4 638{
20ad93d4
JD		 639 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
640 int nr = sensor_attr->index;
641
b74f3fdd 642 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 643 long val;
8acf07c5 644 u8 reg;
f5f64501 645
179c4fdb 646 if (kstrtol(buf, 10, &val) < 0)
f5f64501 647 return -EINVAL;
1da177e4 648
8acf07c5
JD		 649 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
650 reg &= ~(1 << nr);
651 reg &= ~(8 << nr);
5d8d2f2b
GR		 652 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
653 reg &= 0x3f;
4ed10779 654 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 655 dev_warn(dev,
656 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 657 val = 4;
658 }
5d8d2f2b 659 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 660 if (val == 3)
8acf07c5 661 reg |= 1 << nr;
4ed10779 662 else if (val == 4)
8acf07c5 663 reg |= 8 << nr;
5d8d2f2b
GR		 664 else if (has_temp_peci(data, nr) && val == 6)
665 reg |= (nr + 1) << 6;
8acf07c5 666 else if (val != 0)
1da177e4 667 return -EINVAL;
8acf07c5
JD		 668
669 mutex_lock(&data->update_lock);
670 data->sensor = reg;
b74f3fdd 671 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
2b3d1d87 672 data->valid = 0; /* Force cache refresh */
9a61bf63 673 mutex_unlock(&data->update_lock);
1da177e4
LT		 674 return count;
675}
1da177e4 676
2cece01f
GR		 677static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
678 set_temp_type, 0);
679static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
680 set_temp_type, 1);
681static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
682 set_temp_type, 2);
1da177e4
LT		 683
684/* 3 Fans */
b99883dc
JD		 685
686static int pwm_mode(const struct it87_data *data, int nr)
687{
688 int ctrl = data->fan_main_ctrl & (1 << nr);
689
690 if (ctrl == 0) /* Full speed */
691 return 0;
692 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
693 return 2;
694 else /* Manual mode */
695 return 1;
696}
697
20ad93d4 698static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 699 char *buf)
1da177e4 700{
e1169ba0
GR		 701 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
702 int nr = sattr->nr;
703 int index = sattr->index;
704 int speed;
1da177e4 705 struct it87_data *data = it87_update_device(dev);
20ad93d4 706
e1169ba0
GR		 707 speed = has_16bit_fans(data) ?
708 FAN16_FROM_REG(data->fan[nr][index]) :
709 FAN_FROM_REG(data->fan[nr][index],
710 DIV_FROM_REG(data->fan_div[nr]));
711 return sprintf(buf, "%d\n", speed);
1da177e4 712}
e1169ba0 713
20ad93d4
JD		 714static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
715 char *buf)
1da177e4 716{
20ad93d4
JD		 717 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
718 int nr = sensor_attr->index;
719
1da177e4
LT		 720 struct it87_data *data = it87_update_device(dev);
721 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
722}
5f2dc798
JD		 723static ssize_t show_pwm_enable(struct device *dev,
724 struct device_attribute *attr, char *buf)
1da177e4 725{
20ad93d4
JD		 726 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
727 int nr = sensor_attr->index;
728
1da177e4 729 struct it87_data *data = it87_update_device(dev);
b99883dc 730 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 731}
20ad93d4
JD		 732static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
733 char *buf)
1da177e4 734{
20ad93d4
JD		 735 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
736 int nr = sensor_attr->index;
737
1da177e4 738 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 739 return sprintf(buf, "%d\n",
740 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 741}
f8d0c19a
JD		 742static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
743 char *buf)
744{
745 struct it87_data *data = it87_update_device(dev);
746 int index = (data->fan_ctl >> 4) & 0x07;
747
748 return sprintf(buf, "%u\n", pwm_freq[index]);
749}
e1169ba0
GR		 750
751static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
752 const char *buf, size_t count)
1da177e4 753{
e1169ba0
GR		 754 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
755 int nr = sattr->nr;
756 int index = sattr->index;
20ad93d4 757
b74f3fdd 758 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 759 long val;
7f999aa7 760 u8 reg;
1da177e4 761
179c4fdb 762 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 763 return -EINVAL;
764
9a61bf63 765 mutex_lock(&data->update_lock);
e1169ba0
GR		 766
767 if (has_16bit_fans(data)) {
768 data->fan[nr][index] = FAN16_TO_REG(val);
769 it87_write_value(data, IT87_REG_FAN_MIN[nr],
770 data->fan[nr][index] & 0xff);
771 it87_write_value(data, IT87_REG_FANX_MIN[nr],
772 data->fan[nr][index] >> 8);
773 } else {
774 reg = it87_read_value(data, IT87_REG_FAN_DIV);
775 switch (nr) {
776 case 0:
777 data->fan_div[nr] = reg & 0x07;
778 break;
779 case 1:
780 data->fan_div[nr] = (reg >> 3) & 0x07;
781 break;
782 case 2:
783 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
784 break;
785 }
786 data->fan[nr][index] =
787 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
788 it87_write_value(data, IT87_REG_FAN_MIN[nr],
789 data->fan[nr][index]);
07eab46d
JD		 790 }
791
9a61bf63 792 mutex_unlock(&data->update_lock);
1da177e4
LT		 793 return count;
794}
e1169ba0 795
20ad93d4
JD		 796static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
797 const char *buf, size_t count)
1da177e4 798{
20ad93d4
JD		 799 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
800 int nr = sensor_attr->index;
801
b74f3fdd 802 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 803 unsigned long val;
8ab4ec3e 804 int min;
1da177e4
LT		 805 u8 old;
806
179c4fdb 807 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 808 return -EINVAL;
809
9a61bf63 810 mutex_lock(&data->update_lock);
b74f3fdd 811 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 812
8ab4ec3e 813 /* Save fan min limit */
e1169ba0 814 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 815
816 switch (nr) {
817 case 0:
818 case 1:
819 data->fan_div[nr] = DIV_TO_REG(val);
820 break;
821 case 2:
822 if (val < 8)
823 data->fan_div[nr] = 1;
824 else
825 data->fan_div[nr] = 3;
826 }
827 val = old & 0x80;
828 val |= (data->fan_div[0] & 0x07);
829 val |= (data->fan_div[1] & 0x07) << 3;
830 if (data->fan_div[2] == 3)
831 val |= 0x1 << 6;
b74f3fdd 832 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 833
8ab4ec3e 834 /* Restore fan min limit */
e1169ba0
GR		 835 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
836 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 837
9a61bf63 838 mutex_unlock(&data->update_lock);
1da177e4
LT		 839 return count;
840}
cccfc9c4
JD		 841
842/* Returns 0 if OK, -EINVAL otherwise */
843static int check_trip_points(struct device *dev, int nr)
844{
845 const struct it87_data *data = dev_get_drvdata(dev);
846 int i, err = 0;
847
848 if (has_old_autopwm(data)) {
849 for (i = 0; i < 3; i++) {
850 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
851 err = -EINVAL;
852 }
853 for (i = 0; i < 2; i++) {
854 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
855 err = -EINVAL;
856 }
857 }
858
859 if (err) {
1d9bcf6a
GR		 860 dev_err(dev,
861 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 862 dev_err(dev, "Adjust the trip points and try again\n");
863 }
864 return err;
865}
866
20ad93d4
JD		 867static ssize_t set_pwm_enable(struct device *dev,
868 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 869{
20ad93d4
JD		 870 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
871 int nr = sensor_attr->index;
872
b74f3fdd 873 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 874 long val;
1da177e4 875
179c4fdb 876 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 877 return -EINVAL;
878
cccfc9c4
JD		 879 /* Check trip points before switching to automatic mode */
880 if (val == 2) {
881 if (check_trip_points(dev, nr) < 0)
882 return -EINVAL;
883 }
884
9a61bf63 885 mutex_lock(&data->update_lock);
1da177e4
LT		 886
887 if (val == 0) {
888 int tmp;
889 /* make sure the fan is on when in on/off mode */
b74f3fdd 890 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
891 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 892 /* set on/off mode */
893 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 894 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
895 data->fan_main_ctrl);
b99883dc
JD		 896 } else {
897 if (val == 1) /* Manual mode */
16b5dda2 898 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 899 data->pwm_temp_map[nr] :
900 data->pwm_duty[nr];
b99883dc
JD		 901 else /* Automatic mode */
902 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
903 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1da177e4
LT		 904 /* set SmartGuardian mode */
905 data->fan_main_ctrl |= (1 << nr);
5f2dc798
JD		 906 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
907 data->fan_main_ctrl);
1da177e4
LT		 908 }
909
9a61bf63 910 mutex_unlock(&data->update_lock);
1da177e4
LT		 911 return count;
912}
20ad93d4
JD		 913static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
914 const char *buf, size_t count)
1da177e4 915{
20ad93d4
JD		 916 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
917 int nr = sensor_attr->index;
918
b74f3fdd 919 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 920 long val;
1da177e4 921
179c4fdb 922 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 923 return -EINVAL;
924
9a61bf63 925 mutex_lock(&data->update_lock);
16b5dda2 926 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 927 /*
928 * If we are in automatic mode, the PWM duty cycle register
929 * is read-only so we can't write the value.
930 */
6229cdb2
JD		 931 if (data->pwm_ctrl[nr] & 0x80) {
932 mutex_unlock(&data->update_lock);
933 return -EBUSY;
934 }
935 data->pwm_duty[nr] = pwm_to_reg(data, val);
936 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
937 data->pwm_duty[nr]);
938 } else {
939 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 940 /*
941 * If we are in manual mode, write the duty cycle immediately;
942 * otherwise, just store it for later use.
943 */
6229cdb2
JD		 944 if (!(data->pwm_ctrl[nr] & 0x80)) {
945 data->pwm_ctrl[nr] = data->pwm_duty[nr];
946 it87_write_value(data, IT87_REG_PWM(nr),
947 data->pwm_ctrl[nr]);
948 }
b99883dc 949 }
9a61bf63 950 mutex_unlock(&data->update_lock);
1da177e4
LT		 951 return count;
952}
f8d0c19a
JD		 953static ssize_t set_pwm_freq(struct device *dev,
954 struct device_attribute *attr, const char *buf, size_t count)
955{
b74f3fdd 956 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 957 unsigned long val;
f8d0c19a
JD		 958 int i;
959
179c4fdb 960 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 961 return -EINVAL;
962
f8d0c19a
JD		 963 /* Search for the nearest available frequency */
964 for (i = 0; i < 7; i++) {
965 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
966 break;
967 }
968
969 mutex_lock(&data->update_lock);
b74f3fdd 970 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 971 data->fan_ctl |= i << 4;
b74f3fdd 972 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 973 mutex_unlock(&data->update_lock);
974
975 return count;
976}
94ac7ee6
JD		 977static ssize_t show_pwm_temp_map(struct device *dev,
978 struct device_attribute *attr, char *buf)
979{
980 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
981 int nr = sensor_attr->index;
982
983 struct it87_data *data = it87_update_device(dev);
984 int map;
985
986 if (data->pwm_temp_map[nr] < 3)
987 map = 1 << data->pwm_temp_map[nr];
988 else
989 map = 0; /* Should never happen */
990 return sprintf(buf, "%d\n", map);
991}
992static ssize_t set_pwm_temp_map(struct device *dev,
993 struct device_attribute *attr, const char *buf, size_t count)
994{
995 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
996 int nr = sensor_attr->index;
997
998 struct it87_data *data = dev_get_drvdata(dev);
999 long val;
1000 u8 reg;
1001
4a0d71cf
GR		 1002 /*
1003 * This check can go away if we ever support automatic fan speed
1004 * control on newer chips.
1005 */
4f3f51bc
JD		 1006 if (!has_old_autopwm(data)) {
1007 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1008 return -EINVAL;
1009 }
1010
179c4fdb 1011 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1012 return -EINVAL;
1013
1014 switch (val) {
1015 case (1 << 0):
1016 reg = 0x00;
1017 break;
1018 case (1 << 1):
1019 reg = 0x01;
1020 break;
1021 case (1 << 2):
1022 reg = 0x02;
1023 break;
1024 default:
1025 return -EINVAL;
1026 }
1027
1028 mutex_lock(&data->update_lock);
1029 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1030 /*
1031 * If we are in automatic mode, write the temp mapping immediately;
1032 * otherwise, just store it for later use.
1033 */
94ac7ee6
JD		 1034 if (data->pwm_ctrl[nr] & 0x80) {
1035 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1036 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1037 }
1038 mutex_unlock(&data->update_lock);
1039 return count;
1040}
1da177e4 1041
4f3f51bc
JD		 1042static ssize_t show_auto_pwm(struct device *dev,
1043 struct device_attribute *attr, char *buf)
1044{
1045 struct it87_data *data = it87_update_device(dev);
1046 struct sensor_device_attribute_2 *sensor_attr =
1047 to_sensor_dev_attr_2(attr);
1048 int nr = sensor_attr->nr;
1049 int point = sensor_attr->index;
1050
44c1bcd4
JD		 1051 return sprintf(buf, "%d\n",
1052 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1053}
1054
1055static ssize_t set_auto_pwm(struct device *dev,
1056 struct device_attribute *attr, const char *buf, size_t count)
1057{
1058 struct it87_data *data = dev_get_drvdata(dev);
1059 struct sensor_device_attribute_2 *sensor_attr =
1060 to_sensor_dev_attr_2(attr);
1061 int nr = sensor_attr->nr;
1062 int point = sensor_attr->index;
1063 long val;
1064
179c4fdb 1065 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1066 return -EINVAL;
1067
1068 mutex_lock(&data->update_lock);
44c1bcd4 1069 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1070 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1071 data->auto_pwm[nr][point]);
1072 mutex_unlock(&data->update_lock);
1073 return count;
1074}
1075
1076static ssize_t show_auto_temp(struct device *dev,
1077 struct device_attribute *attr, char *buf)
1078{
1079 struct it87_data *data = it87_update_device(dev);
1080 struct sensor_device_attribute_2 *sensor_attr =
1081 to_sensor_dev_attr_2(attr);
1082 int nr = sensor_attr->nr;
1083 int point = sensor_attr->index;
1084
1085 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1086}
1087
1088static ssize_t set_auto_temp(struct device *dev,
1089 struct device_attribute *attr, const char *buf, size_t count)
1090{
1091 struct it87_data *data = dev_get_drvdata(dev);
1092 struct sensor_device_attribute_2 *sensor_attr =
1093 to_sensor_dev_attr_2(attr);
1094 int nr = sensor_attr->nr;
1095 int point = sensor_attr->index;
1096 long val;
1097
179c4fdb 1098 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1099 return -EINVAL;
1100
1101 mutex_lock(&data->update_lock);
1102 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1103 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1104 data->auto_temp[nr][point]);
1105 mutex_unlock(&data->update_lock);
1106 return count;
1107}
1108
e1169ba0
GR		 1109static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1110static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1111 0, 1);
1112static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1113 set_fan_div, 0);
1114
1115static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1116static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1117 1, 1);
1118static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1119 set_fan_div, 1);
1120
1121static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1122static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1123 2, 1);
1124static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1125 set_fan_div, 2);
1126
1127static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1128static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1129 3, 1);
1da177e4 1130
e1169ba0
GR		 1131static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1132static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1133 4, 1);
1da177e4 1134
c4458db3
GR		 1135static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1136 show_pwm_enable, set_pwm_enable, 0);
1137static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1138static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1139static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1140 show_pwm_temp_map, set_pwm_temp_map, 0);
1141static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1142 show_auto_pwm, set_auto_pwm, 0, 0);
1143static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1144 show_auto_pwm, set_auto_pwm, 0, 1);
1145static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1146 show_auto_pwm, set_auto_pwm, 0, 2);
1147static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1148 show_auto_pwm, NULL, 0, 3);
1149static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1150 show_auto_temp, set_auto_temp, 0, 1);
1151static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1152 show_auto_temp, set_auto_temp, 0, 0);
1153static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1154 show_auto_temp, set_auto_temp, 0, 2);
1155static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1156 show_auto_temp, set_auto_temp, 0, 3);
1157static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1158 show_auto_temp, set_auto_temp, 0, 4);
1159
1160static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1161 show_pwm_enable, set_pwm_enable, 1);
1162static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1163static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1164static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1165 show_pwm_temp_map, set_pwm_temp_map, 1);
1166static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1167 show_auto_pwm, set_auto_pwm, 1, 0);
1168static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1169 show_auto_pwm, set_auto_pwm, 1, 1);
1170static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1171 show_auto_pwm, set_auto_pwm, 1, 2);
1172static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1173 show_auto_pwm, NULL, 1, 3);
1174static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1175 show_auto_temp, set_auto_temp, 1, 1);
1176static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1177 show_auto_temp, set_auto_temp, 1, 0);
1178static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1179 show_auto_temp, set_auto_temp, 1, 2);
1180static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1181 show_auto_temp, set_auto_temp, 1, 3);
1182static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1183 show_auto_temp, set_auto_temp, 1, 4);
1184
1185static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1186 show_pwm_enable, set_pwm_enable, 2);
1187static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1188static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1189static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1190 show_pwm_temp_map, set_pwm_temp_map, 2);
1191static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1192 show_auto_pwm, set_auto_pwm, 2, 0);
1193static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1194 show_auto_pwm, set_auto_pwm, 2, 1);
1195static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1196 show_auto_pwm, set_auto_pwm, 2, 2);
1197static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1198 show_auto_pwm, NULL, 2, 3);
1199static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1200 show_auto_temp, set_auto_temp, 2, 1);
1201static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1202 show_auto_temp, set_auto_temp, 2, 0);
1203static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1204 show_auto_temp, set_auto_temp, 2, 2);
1205static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1206 show_auto_temp, set_auto_temp, 2, 3);
1207static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1208 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1209
1210/* Alarms */
5f2dc798
JD		 1211static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1212 char *buf)
1da177e4
LT		 1213{
1214 struct it87_data *data = it87_update_device(dev);
68188ba7 1215 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1216}
1d66c64c 1217static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1218
0124dd78
JD		 1219static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1220 char *buf)
1221{
1222 int bitnr = to_sensor_dev_attr(attr)->index;
1223 struct it87_data *data = it87_update_device(dev);
1224 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1225}
3d30f9e6
JD		 1226
1227static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1228 *attr, const char *buf, size_t count)
1229{
1230 struct it87_data *data = dev_get_drvdata(dev);
1231 long val;
1232 int config;
1233
179c4fdb 1234 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1235 return -EINVAL;
1236
1237 mutex_lock(&data->update_lock);
1238 config = it87_read_value(data, IT87_REG_CONFIG);
1239 if (config < 0) {
1240 count = config;
1241 } else {
1242 config |= 1 << 5;
1243 it87_write_value(data, IT87_REG_CONFIG, config);
1244 /* Invalidate cache to force re-read */
1245 data->valid = 0;
1246 }
1247 mutex_unlock(&data->update_lock);
1248
1249 return count;
1250}
1251
0124dd78
JD		 1252static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1253static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1254static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1255static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1256static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1257static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1258static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1259static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1260static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1261static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1262static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1263static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1264static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1265static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1266static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1267static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1268static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1269 show_alarm, clear_intrusion, 4);
0124dd78 1270
d9b327c3
JD		 1271static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1272 char *buf)
1273{
1274 int bitnr = to_sensor_dev_attr(attr)->index;
1275 struct it87_data *data = it87_update_device(dev);
1276 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1277}
1278static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1279 const char *buf, size_t count)
1280{
1281 int bitnr = to_sensor_dev_attr(attr)->index;
1282 struct it87_data *data = dev_get_drvdata(dev);
1283 long val;
1284
179c4fdb 1285 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1286 || (val != 0 && val != 1))
1287 return -EINVAL;
1288
1289 mutex_lock(&data->update_lock);
1290 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1291 if (val)
1292 data->beeps |= (1 << bitnr);
1293 else
1294 data->beeps &= ~(1 << bitnr);
1295 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1296 mutex_unlock(&data->update_lock);
1297 return count;
1298}
1299
1300static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1301 show_beep, set_beep, 1);
1302static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1303static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1304static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1305static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1306static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1307static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1308static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1309/* fanX_beep writability is set later */
1310static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1311static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1312static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1313static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1314static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1315static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1316 show_beep, set_beep, 2);
1317static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1318static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1319
5f2dc798
JD		 1320static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1321 char *buf)
1da177e4 1322{
90d6619a 1323 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1324 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1325}
5f2dc798
JD		 1326static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1327 const char *buf, size_t count)
1da177e4 1328{
b74f3fdd 1329 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1330 unsigned long val;
1331
179c4fdb 1332 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1333 return -EINVAL;
1da177e4 1334
1da177e4
LT		 1335 data->vrm = val;
1336
1337 return count;
1338}
1339static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1340
5f2dc798
JD		 1341static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1342 char *buf)
1da177e4
LT		 1343{
1344 struct it87_data *data = it87_update_device(dev);
1345 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1346}
1347static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1348
738e5e05
JD		 1349static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1350 char *buf)
1351{
3c4c4971 1352 static const char * const labels[] = {
738e5e05
JD		 1353 "+5V",
1354 "5VSB",
1355 "Vbat",
1356 };
3c4c4971 1357 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1358 "+3.3V",
1359 "3VSB",
1360 "Vbat",
1361 };
1362 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1363 int nr = to_sensor_dev_attr(attr)->index;
1364
16b5dda2
JD		 1365 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1366 : labels[nr]);
738e5e05
JD		 1367}
1368static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1369static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1370static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
1371
b74f3fdd 1372static ssize_t show_name(struct device *dev, struct device_attribute
1373 *devattr, char *buf)
1374{
1375 struct it87_data *data = dev_get_drvdata(dev);
1376 return sprintf(buf, "%s\n", data->name);
1377}
1378static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1379
9172b5d1
GR		 1380static struct attribute *it87_attributes_in[9][5] = {
1381{
87808be4 1382 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1383 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1384 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1385 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1386 NULL
1387}, {
1388 &sensor_dev_attr_in1_input.dev_attr.attr,
1389 &sensor_dev_attr_in1_min.dev_attr.attr,
1390 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1391 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1392 NULL
1393}, {
1394 &sensor_dev_attr_in2_input.dev_attr.attr,
1395 &sensor_dev_attr_in2_min.dev_attr.attr,
1396 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1397 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1398 NULL
1399}, {
1400 &sensor_dev_attr_in3_input.dev_attr.attr,
1401 &sensor_dev_attr_in3_min.dev_attr.attr,
1402 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1403 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1404 NULL
1405}, {
1406 &sensor_dev_attr_in4_input.dev_attr.attr,
1407 &sensor_dev_attr_in4_min.dev_attr.attr,
1408 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1409 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1410 NULL
1411}, {
1412 &sensor_dev_attr_in5_input.dev_attr.attr,
1413 &sensor_dev_attr_in5_min.dev_attr.attr,
1414 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1415 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1416 NULL
1417}, {
1418 &sensor_dev_attr_in6_input.dev_attr.attr,
1419 &sensor_dev_attr_in6_min.dev_attr.attr,
1420 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1421 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1422 NULL
1423}, {
1424 &sensor_dev_attr_in7_input.dev_attr.attr,
1425 &sensor_dev_attr_in7_min.dev_attr.attr,
1426 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1427 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1428 NULL
1429}, {
1430 &sensor_dev_attr_in8_input.dev_attr.attr,
1431 NULL
1432} };
87808be4 1433
9172b5d1
GR		 1434static const struct attribute_group it87_group_in[9] = {
1435 { .attrs = it87_attributes_in[0] },
1436 { .attrs = it87_attributes_in[1] },
1437 { .attrs = it87_attributes_in[2] },
1438 { .attrs = it87_attributes_in[3] },
1439 { .attrs = it87_attributes_in[4] },
1440 { .attrs = it87_attributes_in[5] },
1441 { .attrs = it87_attributes_in[6] },
1442 { .attrs = it87_attributes_in[7] },
1443 { .attrs = it87_attributes_in[8] },
1444};
1445
4573acbc
GR		 1446static struct attribute *it87_attributes_temp[3][6] = {
1447{
87808be4 1448 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1449 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1450 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1451 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1452 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1453 NULL
1454} , {
1455 &sensor_dev_attr_temp2_input.dev_attr.attr,
1456 &sensor_dev_attr_temp2_max.dev_attr.attr,
1457 &sensor_dev_attr_temp2_min.dev_attr.attr,
1458 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1459 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1460 NULL
1461} , {
1462 &sensor_dev_attr_temp3_input.dev_attr.attr,
1463 &sensor_dev_attr_temp3_max.dev_attr.attr,
1464 &sensor_dev_attr_temp3_min.dev_attr.attr,
1465 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1466 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1467 NULL
1468} };
1469
1470static const struct attribute_group it87_group_temp[3] = {
1471 { .attrs = it87_attributes_temp[0] },
1472 { .attrs = it87_attributes_temp[1] },
1473 { .attrs = it87_attributes_temp[2] },
1474};
87808be4 1475
161d898a
GR		 1476static struct attribute *it87_attributes_temp_offset[] = {
1477 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1478 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1479 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1480};
1481
4573acbc 1482static struct attribute *it87_attributes[] = {
87808be4 1483 &dev_attr_alarms.attr,
3d30f9e6 1484 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1485 &dev_attr_name.attr,
87808be4
JD		 1486 NULL
1487};
1488
1489static const struct attribute_group it87_group = {
1490 .attrs = it87_attributes,
1491};
1492
9172b5d1 1493static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1494 &sensor_dev_attr_in0_beep.dev_attr.attr,
1495 &sensor_dev_attr_in1_beep.dev_attr.attr,
1496 &sensor_dev_attr_in2_beep.dev_attr.attr,
1497 &sensor_dev_attr_in3_beep.dev_attr.attr,
1498 &sensor_dev_attr_in4_beep.dev_attr.attr,
1499 &sensor_dev_attr_in5_beep.dev_attr.attr,
1500 &sensor_dev_attr_in6_beep.dev_attr.attr,
1501 &sensor_dev_attr_in7_beep.dev_attr.attr,
9172b5d1
GR		 1502 NULL
1503};
d9b327c3 1504
4573acbc 1505static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1506 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1507 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1508 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1509};
1510
e1169ba0
GR		 1511static struct attribute *it87_attributes_fan[5][3+1] = { {
1512 &sensor_dev_attr_fan1_input.dev_attr.attr,
1513 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1514 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1515 NULL
1516}, {
e1169ba0
GR		 1517 &sensor_dev_attr_fan2_input.dev_attr.attr,
1518 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1519 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1520 NULL
1521}, {
e1169ba0
GR		 1522 &sensor_dev_attr_fan3_input.dev_attr.attr,
1523 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1524 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1525 NULL
1526}, {
e1169ba0
GR		 1527 &sensor_dev_attr_fan4_input.dev_attr.attr,
1528 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1529 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1530 NULL
1531}, {
e1169ba0
GR		 1532 &sensor_dev_attr_fan5_input.dev_attr.attr,
1533 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1534 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1535 NULL
1536} };
1537
e1169ba0
GR		 1538static const struct attribute_group it87_group_fan[5] = {
1539 { .attrs = it87_attributes_fan[0] },
1540 { .attrs = it87_attributes_fan[1] },
1541 { .attrs = it87_attributes_fan[2] },
1542 { .attrs = it87_attributes_fan[3] },
1543 { .attrs = it87_attributes_fan[4] },
723a0aa0 1544};
87808be4 1545
e1169ba0 1546static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1547 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1548 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1549 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1550};
1551
723a0aa0 1552static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1553 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1554 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1555 &dev_attr_pwm1_freq.attr,
94ac7ee6 1556 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1557 NULL
1558}, {
1559 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1560 &sensor_dev_attr_pwm2.dev_attr.attr,
1561 &dev_attr_pwm2_freq.attr,
94ac7ee6 1562 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1563 NULL
1564}, {
1565 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1566 &sensor_dev_attr_pwm3.dev_attr.attr,
1567 &dev_attr_pwm3_freq.attr,
94ac7ee6 1568 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1569 NULL
1570} };
87808be4 1571
723a0aa0
JD		 1572static const struct attribute_group it87_group_pwm[3] = {
1573 { .attrs = it87_attributes_pwm[0] },
1574 { .attrs = it87_attributes_pwm[1] },
1575 { .attrs = it87_attributes_pwm[2] },
1576};
1577
4f3f51bc
JD		 1578static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1579 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1580 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1581 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1582 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1583 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1584 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1585 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1586 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1587 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1588 NULL
1589}, {
1590 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1591 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1592 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1593 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1594 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1595 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1596 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1597 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1598 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1599 NULL
1600}, {
1601 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1602 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1603 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1604 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1605 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1606 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1607 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1608 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1609 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1610 NULL
1611} };
1612
1613static const struct attribute_group it87_group_autopwm[3] = {
1614 { .attrs = it87_attributes_autopwm[0] },
1615 { .attrs = it87_attributes_autopwm[1] },
1616 { .attrs = it87_attributes_autopwm[2] },
1617};
1618
d9b327c3
JD		 1619static struct attribute *it87_attributes_fan_beep[] = {
1620 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1621 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1622 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1623 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1624 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1625};
1626
6a8d7acf 1627static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1628 &dev_attr_vrm.attr,
1629 &dev_attr_cpu0_vid.attr,
1630 NULL
1631};
1632
6a8d7acf
JD		 1633static const struct attribute_group it87_group_vid = {
1634 .attrs = it87_attributes_vid,
87808be4 1635};
1da177e4 1636
738e5e05
JD		 1637static struct attribute *it87_attributes_label[] = {
1638 &sensor_dev_attr_in3_label.dev_attr.attr,
1639 &sensor_dev_attr_in7_label.dev_attr.attr,
1640 &sensor_dev_attr_in8_label.dev_attr.attr,
1641 NULL
1642};
1643
1644static const struct attribute_group it87_group_label = {
fa8b6975 1645 .attrs = it87_attributes_label,
738e5e05
JD		 1646};
1647
2d8672c5 1648/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1649static int __init it87_find(unsigned short *address,
1650 struct it87_sio_data *sio_data)
1da177e4 1651{
5b0380c9 1652 int err;
b74f3fdd 1653 u16 chip_type;
98dd22c3 1654 const char *board_vendor, *board_name;
1da177e4 1655
5b0380c9
NG		 1656 err = superio_enter();
1657 if (err)
1658 return err;
1659
1660 err = -ENODEV;
67b671bc 1661 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1662
1663 switch (chip_type) {
1664 case IT8705F_DEVID:
1665 sio_data->type = it87;
1666 break;
1667 case IT8712F_DEVID:
1668 sio_data->type = it8712;
1669 break;
1670 case IT8716F_DEVID:
1671 case IT8726F_DEVID:
1672 sio_data->type = it8716;
1673 break;
1674 case IT8718F_DEVID:
1675 sio_data->type = it8718;
1676 break;
b4da93e4
JMS		 1677 case IT8720F_DEVID:
1678 sio_data->type = it8720;
1679 break;
44c1bcd4
JD		 1680 case IT8721F_DEVID:
1681 sio_data->type = it8721;
1682 break;
16b5dda2
JD		 1683 case IT8728F_DEVID:
1684 sio_data->type = it8728;
1685 break;
0531d98b
GR		 1686 case IT8782F_DEVID:
1687 sio_data->type = it8782;
1688 break;
1689 case IT8783E_DEVID:
1690 sio_data->type = it8783;
1691 break;
b74f3fdd 1692 case 0xffff: /* No device at all */
1693 goto exit;
1694 default:
a8ca1037 1695 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1696 goto exit;
1697 }
1da177e4 1698
87673dd7 1699 superio_select(PME);
1da177e4 1700 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1701 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1702 goto exit;
1703 }
1704
1705 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1706 if (*address == 0) {
a8ca1037 1707 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1708 goto exit;
1709 }
1710
1711 err = 0;
0475169c 1712 sio_data->revision = superio_inb(DEVREV) & 0x0f;
a8ca1037 1713 pr_info("Found IT%04xF chip at 0x%x, revision %d\n",
0475169c 1714 chip_type, *address, sio_data->revision);
1da177e4 1715
738e5e05
JD		 1716 /* in8 (Vbat) is always internal */
1717 sio_data->internal = (1 << 2);
1718
87673dd7 1719 /* Read GPIO config and VID value from LDN 7 (GPIO) */
895ff267
JD		 1720 if (sio_data->type == it87) {
1721 /* The IT8705F doesn't have VID pins at all */
1722 sio_data->skip_vid = 1;
d9b327c3
JD		 1723
1724 /* The IT8705F has a different LD number for GPIO */
1725 superio_select(5);
1726 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b
GR		 1727 } else if (sio_data->type == it8783) {
1728 int reg25, reg27, reg2A, reg2C, regEF;
0531d98b
GR		 1729
1730 sio_data->skip_vid = 1; /* No VID */
1731
1732 superio_select(GPIO);
1733
1734 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1735 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1736 reg2A = superio_inb(IT87_SIO_PINX1_REG);
1737 reg2C = superio_inb(IT87_SIO_PINX2_REG);
1738 regEF = superio_inb(IT87_SIO_SPI_REG);
1739
0531d98b 1740 /* Check if fan3 is there or not */
9172b5d1 1741 if ((reg27 & (1 << 0)) || !(reg2C & (1 << 2)))
0531d98b
GR		 1742 sio_data->skip_fan |= (1 << 2);
1743 if ((reg25 & (1 << 4))
1744 || (!(reg2A & (1 << 1)) && (regEF & (1 << 0))))
1745 sio_data->skip_pwm |= (1 << 2);
1746
1747 /* Check if fan2 is there or not */
1748 if (reg27 & (1 << 7))
1749 sio_data->skip_fan |= (1 << 1);
1750 if (reg27 & (1 << 3))
1751 sio_data->skip_pwm |= (1 << 1);
1752
1753 /* VIN5 */
9172b5d1
GR		 1754 if ((reg27 & (1 << 0)) || (reg2C & (1 << 2)))
1755 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1756
1757 /* VIN6 */
9172b5d1
GR		 1758 if (reg27 & (1 << 1))
1759 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1760
1761 /*
1762 * VIN7
1763 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1764 */
9172b5d1
GR		 1765 if (reg27 & (1 << 2)) {
1766 /*
1767 * The data sheet is a bit unclear regarding the
1768 * internal voltage divider for VCCH5V. It says
1769 * "This bit enables and switches VIN7 (pin 91) to the
1770 * internal voltage divider for VCCH5V".
1771 * This is different to other chips, where the internal
1772 * voltage divider would connect VIN7 to an internal
1773 * voltage source. Maybe that is the case here as well.
1774 *
1775 * Since we don't know for sure, re-route it if that is
1776 * not the case, and ask the user to report if the
1777 * resulting voltage is sane.
1778 */
1779 if (!(reg2C & (1 << 1))) {
1780 reg2C |= (1 << 1);
1781 superio_outb(IT87_SIO_PINX2_REG, reg2C);
1782 pr_notice("Routing internal VCCH5V to in7.\n");
1783 }
1784 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1785 pr_notice("Please report if it displays a reasonable voltage.\n");
1786 }
0531d98b
GR		 1787
1788 if (reg2C & (1 << 0))
1789 sio_data->internal |= (1 << 0);
1790 if (reg2C & (1 << 1))
1791 sio_data->internal |= (1 << 1);
1792
1793 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
1794
895ff267 1795 } else {
87673dd7 1796 int reg;
9172b5d1 1797 bool uart6;
87673dd7
JD		 1798
1799 superio_select(GPIO);
44c1bcd4 1800
895ff267 1801 reg = superio_inb(IT87_SIO_GPIO3_REG);
0531d98b
GR		 1802 if (sio_data->type == it8721 || sio_data->type == it8728 ||
1803 sio_data->type == it8782) {
16b5dda2 1804 /*
0531d98b
GR		 1805 * IT8721F/IT8758E, and IT8782F don't have VID pins
1806 * at all, not sure about the IT8728F.
16b5dda2 1807 */
895ff267 1808 sio_data->skip_vid = 1;
44c1bcd4
JD		 1809 } else {
1810 /* We need at least 4 VID pins */
1811 if (reg & 0x0f) {
a8ca1037 1812 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1813 sio_data->skip_vid = 1;
1814 }
895ff267
JD		 1815 }
1816
591ec650
JD		 1817 /* Check if fan3 is there or not */
1818 if (reg & (1 << 6))
1819 sio_data->skip_pwm |= (1 << 2);
1820 if (reg & (1 << 7))
1821 sio_data->skip_fan |= (1 << 2);
1822
1823 /* Check if fan2 is there or not */
1824 reg = superio_inb(IT87_SIO_GPIO5_REG);
1825 if (reg & (1 << 1))
1826 sio_data->skip_pwm |= (1 << 1);
1827 if (reg & (1 << 2))
1828 sio_data->skip_fan |= (1 << 1);
1829
895ff267
JD		 1830 if ((sio_data->type == it8718 || sio_data->type == it8720)
1831 && !(sio_data->skip_vid))
b74f3fdd 1832 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 1833
1834 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 1835
1836 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
1837
436cad2a
JD		 1838 /*
1839 * The IT8720F has no VIN7 pin, so VCCH should always be
1840 * routed internally to VIN7 with an internal divider.
1841 * Curiously, there still is a configuration bit to control
1842 * this, which means it can be set incorrectly. And even
1843 * more curiously, many boards out there are improperly
1844 * configured, even though the IT8720F datasheet claims
1845 * that the internal routing of VCCH to VIN7 is the default
1846 * setting. So we force the internal routing in this case.
0531d98b
GR		 1847 *
1848 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 1849 * If UART6 is enabled, re-route VIN7 to the internal divider
1850 * if that is not already the case.
436cad2a 1851 */
9172b5d1 1852 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 1853 reg |= (1 << 1);
1854 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 1855 pr_notice("Routing internal VCCH to in7\n");
436cad2a 1856 }
87673dd7 1857 if (reg & (1 << 0))
738e5e05 1858 sio_data->internal |= (1 << 0);
16b5dda2
JD		 1859 if ((reg & (1 << 1)) || sio_data->type == it8721 ||
1860 sio_data->type == it8728)
738e5e05 1861 sio_data->internal |= (1 << 1);
d9b327c3 1862
9172b5d1
GR		 1863 /*
1864 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
1865 * While VIN7 can be routed to the internal voltage divider,
1866 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 1867 *
1868 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
1869 * is the temperature source. Since we can not read the
1870 * temperature source here, skip_temp is preliminary.
9172b5d1 1871 */
4573acbc 1872 if (uart6) {
9172b5d1 1873 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 1874 sio_data->skip_temp |= (1 << 2);
1875 }
9172b5d1 1876
d9b327c3 1877 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 1878 }
d9b327c3 1879 if (sio_data->beep_pin)
a8ca1037 1880 pr_info("Beeping is supported\n");
87673dd7 1881
98dd22c3
JD		 1882 /* Disable specific features based on DMI strings */
1883 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
1884 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1885 if (board_vendor && board_name) {
1886 if (strcmp(board_vendor, "nVIDIA") == 0
1887 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 1888 /*
1889 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
1890 * connected to a fan, but to something else. One user
1891 * has reported instant system power-off when changing
1892 * the PWM2 duty cycle, so we disable it.
1893 * I use the board name string as the trigger in case
1894 * the same board is ever used in other systems.
1895 */
a8ca1037 1896 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 1897 sio_data->skip_pwm = (1 << 1);
1898 }
1899 }
1900
1da177e4
LT		 1901exit:
1902 superio_exit();
1903 return err;
1904}
1905
723a0aa0
JD		 1906static void it87_remove_files(struct device *dev)
1907{
1908 struct it87_data *data = platform_get_drvdata(pdev);
1909 struct it87_sio_data *sio_data = dev->platform_data;
723a0aa0
JD		 1910 int i;
1911
1912 sysfs_remove_group(&dev->kobj, &it87_group);
9172b5d1
GR		 1913 for (i = 0; i < 9; i++) {
1914 if (sio_data->skip_in & (1 << i))
1915 continue;
1916 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
1917 if (it87_attributes_in_beep[i])
1918 sysfs_remove_file(&dev->kobj,
1919 it87_attributes_in_beep[i]);
1920 }
4573acbc
GR		 1921 for (i = 0; i < 3; i++) {
1922 if (!(data->has_temp & (1 << i)))
1923 continue;
1924 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 1925 if (has_temp_offset(data))
1926 sysfs_remove_file(&dev->kobj,
1927 it87_attributes_temp_offset[i]);
4573acbc
GR		 1928 if (sio_data->beep_pin)
1929 sysfs_remove_file(&dev->kobj,
1930 it87_attributes_temp_beep[i]);
1931 }
723a0aa0
JD		 1932 for (i = 0; i < 5; i++) {
1933 if (!(data->has_fan & (1 << i)))
1934 continue;
e1169ba0 1935 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 1936 if (sio_data->beep_pin)
1937 sysfs_remove_file(&dev->kobj,
1938 it87_attributes_fan_beep[i]);
e1169ba0
GR		 1939 if (i < 3 && !has_16bit_fans(data))
1940 sysfs_remove_file(&dev->kobj,
1941 it87_attributes_fan_div[i]);
723a0aa0
JD		 1942 }
1943 for (i = 0; i < 3; i++) {
1944 if (sio_data->skip_pwm & (1 << 0))
1945 continue;
1946 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 1947 if (has_old_autopwm(data))
1948 sysfs_remove_group(&dev->kobj,
1949 &it87_group_autopwm[i]);
723a0aa0 1950 }
6a8d7acf
JD		 1951 if (!sio_data->skip_vid)
1952 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 1953 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 1954}
1955
6c931ae1 1956static int it87_probe(struct platform_device *pdev)
1da177e4 1957{
1da177e4 1958 struct it87_data *data;
b74f3fdd 1959 struct resource *res;
1960 struct device *dev = &pdev->dev;
1961 struct it87_sio_data *sio_data = dev->platform_data;
723a0aa0 1962 int err = 0, i;
1da177e4 1963 int enable_pwm_interface;
d9b327c3 1964 int fan_beep_need_rw;
b74f3fdd 1965
1966 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 1967 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
1968 DRVNAME)) {
b74f3fdd 1969 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1970 (unsigned long)res->start,
87b4b663 1971 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 1972 return -EBUSY;
8e9afcbb 1973 }
1da177e4 1974
62a1d05f
GR		 1975 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
1976 if (!data)
1977 return -ENOMEM;
1da177e4 1978
b74f3fdd 1979 data->addr = res->start;
1980 data->type = sio_data->type;
483db43e 1981 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 1982 data->peci_mask = it87_devices[sio_data->type].peci_mask;
483db43e
GR		 1983 data->name = it87_devices[sio_data->type].name;
1984 /*
1985 * IT8705F Datasheet 0.4.1, 3h == Version G.
1986 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
1987 * These are the first revisions with 16-bit tachometer support.
1988 */
1989 switch (data->type) {
1990 case it87:
1991 if (sio_data->revision >= 0x03) {
1992 data->features &= ~FEAT_OLD_AUTOPWM;
1993 data->features |= FEAT_16BIT_FANS;
1994 }
1995 break;
1996 case it8712:
1997 if (sio_data->revision >= 0x08) {
1998 data->features &= ~FEAT_OLD_AUTOPWM;
1999 data->features |= FEAT_16BIT_FANS;
2000 }
2001 break;
2002 default:
2003 break;
2004 }
1da177e4
LT		 2005
2006 /* Now, we do the remaining detection. */
b74f3fdd 2007 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2008 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2009 return -ENODEV;
1da177e4 2010
b74f3fdd 2011 platform_set_drvdata(pdev, data);
1da177e4 2012
9a61bf63 2013 mutex_init(&data->update_lock);
1da177e4 2014
1da177e4 2015 /* Check PWM configuration */
b74f3fdd 2016 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2017
44c1bcd4 2018 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2019 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2020 if (sio_data->internal & (1 << 0))
2021 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2022 if (sio_data->internal & (1 << 1))
2023 data->in_scaled |= (1 << 7); /* in7 is VSB */
2024 if (sio_data->internal & (1 << 2))
2025 data->in_scaled |= (1 << 8); /* in8 is Vbat */
0531d98b
GR		 2026 } else if (sio_data->type == it8782 || sio_data->type == it8783) {
2027 if (sio_data->internal & (1 << 0))
2028 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2029 if (sio_data->internal & (1 << 1))
2030 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2031 }
2032
4573acbc
GR		 2033 data->has_temp = 0x07;
2034 if (sio_data->skip_temp & (1 << 2)) {
2035 if (sio_data->type == it8782
2036 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2037 data->has_temp &= ~(1 << 2);
2038 }
2039
1da177e4 2040 /* Initialize the IT87 chip */
b74f3fdd 2041 it87_init_device(pdev);
1da177e4
LT		 2042
2043 /* Register sysfs hooks */
5f2dc798
JD		 2044 err = sysfs_create_group(&dev->kobj, &it87_group);
2045 if (err)
62a1d05f 2046 return err;
17d648bf 2047
9172b5d1
GR		 2048 for (i = 0; i < 9; i++) {
2049 if (sio_data->skip_in & (1 << i))
2050 continue;
2051 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2052 if (err)
62a1d05f 2053 goto error;
9172b5d1
GR		 2054 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2055 err = sysfs_create_file(&dev->kobj,
2056 it87_attributes_in_beep[i]);
2057 if (err)
62a1d05f 2058 goto error;
9172b5d1
GR		 2059 }
2060 }
2061
4573acbc
GR		 2062 for (i = 0; i < 3; i++) {
2063 if (!(data->has_temp & (1 << i)))
2064 continue;
2065 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2066 if (err)
62a1d05f 2067 goto error;
161d898a
GR		 2068 if (has_temp_offset(data)) {
2069 err = sysfs_create_file(&dev->kobj,
2070 it87_attributes_temp_offset[i]);
2071 if (err)
2072 goto error;
2073 }
4573acbc
GR		 2074 if (sio_data->beep_pin) {
2075 err = sysfs_create_file(&dev->kobj,
2076 it87_attributes_temp_beep[i]);
2077 if (err)
2078 goto error;
2079 }
d9b327c3
JD		 2080 }
2081
9060f8bd 2082 /* Do not create fan files for disabled fans */
d9b327c3 2083 fan_beep_need_rw = 1;
723a0aa0
JD		 2084 for (i = 0; i < 5; i++) {
2085 if (!(data->has_fan & (1 << i)))
2086 continue;
e1169ba0 2087 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2088 if (err)
62a1d05f 2089 goto error;
d9b327c3 2090
e1169ba0
GR		 2091 if (i < 3 && !has_16bit_fans(data)) {
2092 err = sysfs_create_file(&dev->kobj,
2093 it87_attributes_fan_div[i]);
2094 if (err)
2095 goto error;
2096 }
2097
d9b327c3
JD		 2098 if (sio_data->beep_pin) {
2099 err = sysfs_create_file(&dev->kobj,
2100 it87_attributes_fan_beep[i]);
2101 if (err)
62a1d05f 2102 goto error;
d9b327c3
JD		 2103 if (!fan_beep_need_rw)
2104 continue;
2105
4a0d71cf
GR		 2106 /*
2107 * As we have a single beep enable bit for all fans,
d9b327c3 2108 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2109 * for it.
2110 */
d9b327c3
JD		 2111 if (sysfs_chmod_file(&dev->kobj,
2112 it87_attributes_fan_beep[i],
2113 S_IRUGO | S_IWUSR))
2114 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2115 i + 1);
2116 fan_beep_need_rw = 0;
2117 }
17d648bf
JD		 2118 }
2119
1da177e4 2120 if (enable_pwm_interface) {
723a0aa0
JD		 2121 for (i = 0; i < 3; i++) {
2122 if (sio_data->skip_pwm & (1 << i))
2123 continue;
2124 err = sysfs_create_group(&dev->kobj,
2125 &it87_group_pwm[i]);
2126 if (err)
62a1d05f 2127 goto error;
4f3f51bc
JD		 2128
2129 if (!has_old_autopwm(data))
2130 continue;
2131 err = sysfs_create_group(&dev->kobj,
2132 &it87_group_autopwm[i]);
2133 if (err)
62a1d05f 2134 goto error;
98dd22c3 2135 }
1da177e4
LT		 2136 }
2137
895ff267 2138 if (!sio_data->skip_vid) {
303760b4 2139 data->vrm = vid_which_vrm();
87673dd7 2140 /* VID reading from Super-I/O config space if available */
b74f3fdd 2141 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2142 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2143 if (err)
62a1d05f 2144 goto error;
87808be4
JD		 2145 }
2146
738e5e05
JD		 2147 /* Export labels for internal sensors */
2148 for (i = 0; i < 3; i++) {
2149 if (!(sio_data->internal & (1 << i)))
2150 continue;
2151 err = sysfs_create_file(&dev->kobj,
2152 it87_attributes_label[i]);
2153 if (err)
62a1d05f 2154 goto error;
738e5e05
JD		 2155 }
2156
1beeffe4
TJ		 2157 data->hwmon_dev = hwmon_device_register(dev);
2158 if (IS_ERR(data->hwmon_dev)) {
2159 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2160 goto error;
1da177e4
LT		 2161 }
2162
2163 return 0;
2164
62a1d05f 2165error:
723a0aa0 2166 it87_remove_files(dev);
1da177e4
LT		 2167 return err;
2168}
2169
281dfd0b 2170static int it87_remove(struct platform_device *pdev)
1da177e4 2171{
b74f3fdd 2172 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2173
1beeffe4 2174 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2175 it87_remove_files(&pdev->dev);
943b0830 2176
1da177e4
LT		 2177 return 0;
2178}
2179
4a0d71cf
GR		 2180/*
2181 * Must be called with data->update_lock held, except during initialization.
2182 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2183 * would slow down the IT87 access and should not be necessary.
2184 */
b74f3fdd 2185static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2186{
b74f3fdd 2187 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2188 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2189}
2190
4a0d71cf
GR		 2191/*
2192 * Must be called with data->update_lock held, except during initialization.
2193 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2194 * would slow down the IT87 access and should not be necessary.
2195 */
b74f3fdd 2196static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2197{
b74f3fdd 2198 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2199 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2200}
2201
2202/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2203static int it87_check_pwm(struct device *dev)
1da177e4 2204{
b74f3fdd 2205 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2206 /*
2207 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2208 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2209 * disable pwm control to protect the user.
2210 */
b74f3fdd 2211 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2212 if ((tmp & 0x87) == 0) {
2213 if (fix_pwm_polarity) {
4a0d71cf
GR		 2214 /*
2215 * The user asks us to attempt a chip reconfiguration.
1da177e4 2216 * This means switching to active high polarity and
4a0d71cf
GR		 2217 * inverting all fan speed values.
2218 */
1da177e4
LT		 2219 int i;
2220 u8 pwm[3];
2221
2222 for (i = 0; i < 3; i++)
b74f3fdd 2223 pwm[i] = it87_read_value(data,
1da177e4
LT		 2224 IT87_REG_PWM(i));
2225
4a0d71cf
GR		 2226 /*
2227 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2228 * might be correct, as suspicious as it seems, so we
2229 * better don't change anything (but still disable the
4a0d71cf
GR		 2230 * PWM interface).
2231 */
1da177e4 2232 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2233 dev_info(dev,
2234 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2235 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2236 tmp | 0x87);
2237 for (i = 0; i < 3; i++)
b74f3fdd 2238 it87_write_value(data,
1da177e4
LT		 2239 IT87_REG_PWM(i),
2240 0x7f & ~pwm[i]);
2241 return 1;
2242 }
2243
1d9bcf6a
GR		 2244 dev_info(dev,
2245 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2246 }
2247
1d9bcf6a
GR		 2248 dev_info(dev,
2249 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2250 return 0;
2251 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2252 dev_info(dev,
2253 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2254 }
2255
2256 return 1;
2257}
2258
2259/* Called when we have found a new IT87. */
6c931ae1 2260static void it87_init_device(struct platform_device *pdev)
1da177e4 2261{
591ec650 2262 struct it87_sio_data *sio_data = pdev->dev.platform_data;
b74f3fdd 2263 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2264 int tmp, i;
591ec650 2265 u8 mask;
1da177e4 2266
4a0d71cf
GR		 2267 /*
2268 * For each PWM channel:
b99883dc
JD		 2269 * - If it is in automatic mode, setting to manual mode should set
2270 * the fan to full speed by default.
2271 * - If it is in manual mode, we need a mapping to temperature
2272 * channels to use when later setting to automatic mode later.
2273 * Use a 1:1 mapping by default (we are clueless.)
2274 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2275 * prior to switching to a different mode.
2276 * Note that this is no longer needed for the IT8721F and later, as
2277 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2278 * manual duty cycle.
2279 */
1da177e4 2280 for (i = 0; i < 3; i++) {
b99883dc
JD		 2281 data->pwm_temp_map[i] = i;
2282 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2283 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2284 }
2285
4a0d71cf
GR		 2286 /*
2287 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2288 * registers. For low voltage limits it makes no sense and triggers
2289 * alarms, so change to 0 instead. For high temperature limits, it
2290 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2291 * but is still confusing, so change to 127 degrees C.
2292 */
c5df9b7a 2293 for (i = 0; i < 8; i++) {
b74f3fdd 2294 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2295 if (tmp == 0xff)
b74f3fdd 2296 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2297 }
2298 for (i = 0; i < 3; i++) {
b74f3fdd 2299 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2300 if (tmp == 0xff)
b74f3fdd 2301 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2302 }
2303
4a0d71cf
GR		 2304 /*
2305 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2306 * set to two different sensor types and we can't guess which one
2307 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2308 * run-time through the temp{1-3}_type sysfs accessors if needed.
2309 */
1da177e4
LT		 2310
2311 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2312 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2313 if ((tmp & 0xff) == 0) {
2314 /* Enable all voltage monitors */
b74f3fdd 2315 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2316 }
2317
2318 /* Check if tachometers are reset manually or by some reason */
591ec650 2319 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2320 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2321 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2322 /* Enable all fan tachometers */
591ec650 2323 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2324 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2325 data->fan_main_ctrl);
1da177e4 2326 }
9060f8bd 2327 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2328
17d648bf 2329 /* Set tachometers to 16-bit mode if needed */
0475169c 2330 if (has_16bit_fans(data)) {
b74f3fdd 2331 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2332 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2333 dev_dbg(&pdev->dev,
17d648bf 2334 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2335 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2336 tmp | 0x07);
2337 }
0531d98b
GR		 2338 /* IT8705F, IT8782F, and IT8783E/F only support three fans. */
2339 if (data->type != it87 && data->type != it8782 &&
2340 data->type != it8783) {
816d8c6a
AP		 2341 if (tmp & (1 << 4))
2342 data->has_fan |= (1 << 3); /* fan4 enabled */
2343 if (tmp & (1 << 5))
2344 data->has_fan |= (1 << 4); /* fan5 enabled */
2345 }
17d648bf
JD		 2346 }
2347
591ec650
JD		 2348 /* Fan input pins may be used for alternative functions */
2349 data->has_fan &= ~sio_data->skip_fan;
2350
1da177e4 2351 /* Start monitoring */
b74f3fdd 2352 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2353 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2354 | (update_vbat ? 0x41 : 0x01));
2355}
2356
b99883dc
JD		 2357static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2358{
2359 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2360 if (has_newer_autopwm(data)) {
b99883dc 2361 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2362 data->pwm_duty[nr] = it87_read_value(data,
2363 IT87_REG_PWM_DUTY(nr));
2364 } else {
2365 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2366 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2367 else /* Manual mode */
2368 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2369 }
4f3f51bc
JD		 2370
2371 if (has_old_autopwm(data)) {
2372 int i;
2373
2374 for (i = 0; i < 5 ; i++)
2375 data->auto_temp[nr][i] = it87_read_value(data,
2376 IT87_REG_AUTO_TEMP(nr, i));
2377 for (i = 0; i < 3 ; i++)
2378 data->auto_pwm[nr][i] = it87_read_value(data,
2379 IT87_REG_AUTO_PWM(nr, i));
2380 }
b99883dc
JD		 2381}
2382
1da177e4
LT		 2383static struct it87_data *it87_update_device(struct device *dev)
2384{
b74f3fdd 2385 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2386 int i;
2387
9a61bf63 2388 mutex_lock(&data->update_lock);
1da177e4
LT		 2389
2390 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2391 || !data->valid) {
1da177e4 2392 if (update_vbat) {
4a0d71cf
GR		 2393 /*
2394 * Cleared after each update, so reenable. Value
2395 * returned by this read will be previous value
2396 */
b74f3fdd 2397 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2398 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2399 }
2400 for (i = 0; i <= 7; i++) {
929c6a56 2401 data->in[i][0] =
5f2dc798 2402 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2403 data->in[i][1] =
5f2dc798 2404 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2405 data->in[i][2] =
5f2dc798 2406 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2407 }
3543a53f 2408 /* in8 (battery) has no limit registers */
929c6a56 2409 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
1da177e4 2410
c7f1f716 2411 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2412 /* Skip disabled fans */
2413 if (!(data->has_fan & (1 << i)))
2414 continue;
2415
e1169ba0 2416 data->fan[i][1] =
5f2dc798 2417 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2418 data->fan[i][0] = it87_read_value(data,
c7f1f716 2419 IT87_REG_FAN[i]);
17d648bf 2420 /* Add high byte if in 16-bit mode */
0475169c 2421 if (has_16bit_fans(data)) {
e1169ba0 2422 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2423 IT87_REG_FANX[i]) << 8;
e1169ba0 2424 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2425 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2426 }
1da177e4
LT		 2427 }
2428 for (i = 0; i < 3; i++) {
4573acbc
GR		 2429 if (!(data->has_temp & (1 << i)))
2430 continue;
60ca385a 2431 data->temp[i][0] =
5f2dc798 2432 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2433 data->temp[i][1] =
5f2dc798 2434 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2435 data->temp[i][2] =
2436 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2437 if (has_temp_offset(data))
2438 data->temp[i][3] =
2439 it87_read_value(data,
2440 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2441 }
2442
17d648bf 2443 /* Newer chips don't have clock dividers */
0475169c 2444 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2445 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2446 data->fan_div[0] = i & 0x07;
2447 data->fan_div[1] = (i >> 3) & 0x07;
2448 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2449 }
1da177e4
LT		 2450
2451 data->alarms =
b74f3fdd 2452 it87_read_value(data, IT87_REG_ALARM1) |
2453 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2454 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2455 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2456
b74f3fdd 2457 data->fan_main_ctrl = it87_read_value(data,
2458 IT87_REG_FAN_MAIN_CTRL);
2459 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2460 for (i = 0; i < 3; i++)
2461 it87_update_pwm_ctrl(data, i);
b74f3fdd 2462
2463 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
4a0d71cf
GR		 2464 /*
2465 * The IT8705F does not have VID capability.
2466 * The IT8718F and later don't use IT87_REG_VID for the
2467 * same purpose.
2468 */
17d648bf 2469 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2470 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2471 /*
2472 * The older IT8712F revisions had only 5 VID pins,
2473 * but we assume it is always safe to read 6 bits.
2474 */
17d648bf 2475 data->vid &= 0x3f;
1da177e4
LT		 2476 }
2477 data->last_updated = jiffies;
2478 data->valid = 1;
2479 }
2480
9a61bf63 2481 mutex_unlock(&data->update_lock);
1da177e4
LT		 2482
2483 return data;
2484}
2485
b74f3fdd 2486static int __init it87_device_add(unsigned short address,
2487 const struct it87_sio_data *sio_data)
2488{
2489 struct resource res = {
87b4b663
BH		 2490 .start = address + IT87_EC_OFFSET,
2491 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2492 .name = DRVNAME,
2493 .flags = IORESOURCE_IO,
2494 };
2495 int err;
2496
b9acb64a
JD		 2497 err = acpi_check_resource_conflict(&res);
2498 if (err)
2499 goto exit;
2500
b74f3fdd 2501 pdev = platform_device_alloc(DRVNAME, address);
2502 if (!pdev) {
2503 err = -ENOMEM;
a8ca1037 2504 pr_err("Device allocation failed\n");
b74f3fdd 2505 goto exit;
2506 }
2507
2508 err = platform_device_add_resources(pdev, &res, 1);
2509 if (err) {
a8ca1037 2510 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2511 goto exit_device_put;
2512 }
2513
2514 err = platform_device_add_data(pdev, sio_data,
2515 sizeof(struct it87_sio_data));
2516 if (err) {
a8ca1037 2517 pr_err("Platform data allocation failed\n");
b74f3fdd 2518 goto exit_device_put;
2519 }
2520
2521 err = platform_device_add(pdev);
2522 if (err) {
a8ca1037 2523 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2524 goto exit_device_put;
2525 }
2526
2527 return 0;
2528
2529exit_device_put:
2530 platform_device_put(pdev);
2531exit:
2532 return err;
2533}
2534
1da177e4
LT		 2535static int __init sm_it87_init(void)
2536{
b74f3fdd 2537 int err;
5f2dc798 2538 unsigned short isa_address = 0;
b74f3fdd 2539 struct it87_sio_data sio_data;
2540
98dd22c3 2541 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2542 err = it87_find(&isa_address, &sio_data);
2543 if (err)
2544 return err;
2545 err = platform_driver_register(&it87_driver);
2546 if (err)
2547 return err;
fde09509 2548
b74f3fdd 2549 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2550 if (err) {
b74f3fdd 2551 platform_driver_unregister(&it87_driver);
2552 return err;
2553 }
2554
2555 return 0;
1da177e4
LT		 2556}
2557
2558static void __exit sm_it87_exit(void)
2559{
b74f3fdd 2560 platform_device_unregister(pdev);
2561 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2562}
2563
2564
1d9bcf6a 2565MODULE_AUTHOR("Chris Gauthron, Jean Delvare <khali@linux-fr.org>");
44c1bcd4 2566MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2567module_param(update_vbat, bool, 0);
2568MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2569module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2570MODULE_PARM_DESC(fix_pwm_polarity,
2571 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2572MODULE_LICENSE("GPL");
2573
2574module_init(sm_it87_init);
2575module_exit(sm_it87_exit);
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