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hwmon: (it87) Add support for IT8786E
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
574e9bd8 14 * IT8623E Super I/O chip w/LPC interface
c145d5c6 15 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 16 * IT8712F Super I/O chip w/LPC interface
17 * IT8716F Super I/O chip w/LPC interface
18 * IT8718F Super I/O chip w/LPC interface
19 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 20 * IT8721F Super I/O chip w/LPC interface
5f2dc798 21 * IT8726F Super I/O chip w/LPC interface
16b5dda2 22 * IT8728F Super I/O chip w/LPC interface
44c1bcd4 23 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 24 * IT8771E Super I/O chip w/LPC interface
25 * IT8772E Super I/O chip w/LPC interface
7bc32d29 26 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 27 * IT8782F Super I/O chip w/LPC interface
28 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 29 * IT8786E Super I/O chip w/LPC interface
5f2dc798
JD		 30 * Sis950 A clone of the IT8705F
31 *
32 * Copyright (C) 2001 Chris Gauthron
7c81c60f 33 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 34 *
35 * This program is free software; you can redistribute it and/or modify
36 * it under the terms of the GNU General Public License as published by
37 * the Free Software Foundation; either version 2 of the License, or
38 * (at your option) any later version.
39 *
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
48 */
1da177e4 49
a8ca1037
JP		 50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
1da177e4
LT		 52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
b74f3fdd 56#include <linux/platform_device.h>
943b0830 57#include <linux/hwmon.h>
303760b4
JD		 58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
943b0830 60#include <linux/err.h>
9a61bf63 61#include <linux/mutex.h>
87808be4 62#include <linux/sysfs.h>
98dd22c3
JD		 63#include <linux/string.h>
64#include <linux/dmi.h>
b9acb64a 65#include <linux/acpi.h>
6055fae8 66#include <linux/io.h>
1da177e4 67
b74f3fdd 68#define DRVNAME "it87"
1da177e4 69
b0636707 70enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8771,
a0c1424a 71 it8772, it8781, it8782, it8783, it8786, it8603 };
1da177e4 72
67b671bc
JD		 73static unsigned short force_id;
74module_param(force_id, ushort, 0);
75MODULE_PARM_DESC(force_id, "Override the detected device ID");
76
b74f3fdd 77static struct platform_device *pdev;
78
1da177e4
LT		 79#define REG 0x2e /* The register to read/write */
80#define DEV 0x07 /* Register: Logical device select */
81#define VAL 0x2f /* The value to read/write */
82#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 83
84/* The device with the IT8718F/IT8720F VID value in it */
85#define GPIO 0x07
86
1da177e4
LT		 87#define DEVID 0x20 /* Register: Device ID */
88#define DEVREV 0x22 /* Register: Device Revision */
89
5b0380c9 90static inline int superio_inb(int reg)
1da177e4
LT		 91{
92 outb(reg, REG);
93 return inb(VAL);
94}
95
5b0380c9 96static inline void superio_outb(int reg, int val)
436cad2a
JD		 97{
98 outb(reg, REG);
99 outb(val, VAL);
100}
101
1da177e4
LT		 102static int superio_inw(int reg)
103{
104 int val;
105 outb(reg++, REG);
106 val = inb(VAL) << 8;
107 outb(reg, REG);
108 val |= inb(VAL);
109 return val;
110}
111
5b0380c9 112static inline void superio_select(int ldn)
1da177e4
LT		 113{
114 outb(DEV, REG);
87673dd7 115 outb(ldn, VAL);
1da177e4
LT		 116}
117
5b0380c9 118static inline int superio_enter(void)
1da177e4 119{
5b0380c9
NG		 120 /*
121 * Try to reserve REG and REG + 1 for exclusive access.
122 */
123 if (!request_muxed_region(REG, 2, DRVNAME))
124 return -EBUSY;
125
1da177e4
LT		 126 outb(0x87, REG);
127 outb(0x01, REG);
128 outb(0x55, REG);
129 outb(0x55, REG);
5b0380c9 130 return 0;
1da177e4
LT		 131}
132
5b0380c9 133static inline void superio_exit(void)
1da177e4
LT		 134{
135 outb(0x02, REG);
136 outb(0x02, VAL);
5b0380c9 137 release_region(REG, 2);
1da177e4
LT		 138}
139
87673dd7 140/* Logical device 4 registers */
1da177e4
LT		 141#define IT8712F_DEVID 0x8712
142#define IT8705F_DEVID 0x8705
17d648bf 143#define IT8716F_DEVID 0x8716
87673dd7 144#define IT8718F_DEVID 0x8718
b4da93e4 145#define IT8720F_DEVID 0x8720
44c1bcd4 146#define IT8721F_DEVID 0x8721
08a8f6e9 147#define IT8726F_DEVID 0x8726
16b5dda2 148#define IT8728F_DEVID 0x8728
b0636707
GR		 149#define IT8771E_DEVID 0x8771
150#define IT8772E_DEVID 0x8772
7bc32d29 151#define IT8781F_DEVID 0x8781
0531d98b
GR		 152#define IT8782F_DEVID 0x8782
153#define IT8783E_DEVID 0x8783
a0c1424a 154#define IT8786E_DEVID 0x8786
7183ae8c 155#define IT8603E_DEVID 0x8603
574e9bd8 156#define IT8623E_DEVID 0x8623
1da177e4
LT		 157#define IT87_ACT_REG 0x30
158#define IT87_BASE_REG 0x60
159
87673dd7 160/* Logical device 7 registers (IT8712F and later) */
0531d98b 161#define IT87_SIO_GPIO1_REG 0x25
895ff267 162#define IT87_SIO_GPIO3_REG 0x27
591ec650 163#define IT87_SIO_GPIO5_REG 0x29
0531d98b 164#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 165#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 166#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 167#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 168#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 169
1da177e4 170/* Update battery voltage after every reading if true */
90ab5ee9 171static bool update_vbat;
1da177e4
LT		 172
173/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 174static bool fix_pwm_polarity;
1da177e4 175
1da177e4
LT		 176/* Many IT87 constants specified below */
177
178/* Length of ISA address segment */
179#define IT87_EXTENT 8
180
87b4b663
BH		 181/* Length of ISA address segment for Environmental Controller */
182#define IT87_EC_EXTENT 2
183
184/* Offset of EC registers from ISA base address */
185#define IT87_EC_OFFSET 5
186
187/* Where are the ISA address/data registers relative to the EC base address */
188#define IT87_ADDR_REG_OFFSET 0
189#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 190
191/*----- The IT87 registers -----*/
192
193#define IT87_REG_CONFIG 0x00
194
195#define IT87_REG_ALARM1 0x01
196#define IT87_REG_ALARM2 0x02
197#define IT87_REG_ALARM3 0x03
198
4a0d71cf
GR		 199/*
200 * The IT8718F and IT8720F have the VID value in a different register, in
201 * Super-I/O configuration space.
202 */
1da177e4 203#define IT87_REG_VID 0x0a
4a0d71cf
GR		 204/*
205 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
206 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
207 * mode.
208 */
1da177e4 209#define IT87_REG_FAN_DIV 0x0b
17d648bf 210#define IT87_REG_FAN_16BIT 0x0c
1da177e4
LT		 211
212/* Monitors: 9 voltage (0 to 7, battery), 3 temp (1 to 3), 3 fan (1 to 3) */
213
c7f1f716
JD		 214static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82 };
215static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86 };
216static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83 };
217static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87 };
161d898a
GR		 218static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
219
1da177e4
LT		 220#define IT87_REG_FAN_MAIN_CTRL 0x13
221#define IT87_REG_FAN_CTL 0x14
222#define IT87_REG_PWM(nr) (0x15 + (nr))
6229cdb2 223#define IT87_REG_PWM_DUTY(nr) (0x63 + (nr) * 8)
1da177e4
LT		 224
225#define IT87_REG_VIN(nr) (0x20 + (nr))
226#define IT87_REG_TEMP(nr) (0x29 + (nr))
227
228#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
229#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
230#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
231#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
232
1da177e4
LT		 233#define IT87_REG_VIN_ENABLE 0x50
234#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 235#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 236#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 237
238#define IT87_REG_CHIPID 0x58
239
4f3f51bc
JD		 240#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
241#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
242
483db43e
GR		 243struct it87_devices {
244 const char *name;
245 u16 features;
19529784
GR		 246 u8 peci_mask;
247 u8 old_peci_mask;
483db43e
GR		 248};
249
250#define FEAT_12MV_ADC (1 << 0)
251#define FEAT_NEWER_AUTOPWM (1 << 1)
252#define FEAT_OLD_AUTOPWM (1 << 2)
253#define FEAT_16BIT_FANS (1 << 3)
254#define FEAT_TEMP_OFFSET (1 << 4)
5d8d2f2b 255#define FEAT_TEMP_PECI (1 << 5)
19529784 256#define FEAT_TEMP_OLD_PECI (1 << 6)
9faf28ca
GR		 257#define FEAT_FAN16_CONFIG (1 << 7) /* Need to enable 16-bit fans */
258#define FEAT_FIVE_FANS (1 << 8) /* Supports five fans */
32dd7c40 259#define FEAT_VID (1 << 9) /* Set if chip supports VID */
483db43e
GR		 260
261static const struct it87_devices it87_devices[] = {
262 [it87] = {
263 .name = "it87",
264 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
265 },
266 [it8712] = {
267 .name = "it8712",
32dd7c40
GR		 268 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
269 /* may need to overwrite */
483db43e
GR		 270 },
271 [it8716] = {
272 .name = "it8716",
32dd7c40 273 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 274 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
483db43e
GR		 275 },
276 [it8718] = {
277 .name = "it8718",
32dd7c40 278 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 279 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 280 .old_peci_mask = 0x4,
483db43e
GR		 281 },
282 [it8720] = {
283 .name = "it8720",
32dd7c40 284 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
9faf28ca 285 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
19529784 286 .old_peci_mask = 0x4,
483db43e
GR		 287 },
288 [it8721] = {
289 .name = "it8721",
290 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca
GR		 291 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
292 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS,
5d8d2f2b 293 .peci_mask = 0x05,
19529784 294 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 295 },
296 [it8728] = {
297 .name = "it8728",
298 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 299 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS,
5d8d2f2b 300 .peci_mask = 0x07,
483db43e 301 },
b0636707
GR		 302 [it8771] = {
303 .name = "it8771",
304 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
305 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
9faf28ca
GR		 306 /* PECI: guesswork */
307 /* 12mV ADC (OHM) */
308 /* 16 bit fans (OHM) */
309 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 310 .peci_mask = 0x07,
311 },
312 [it8772] = {
313 .name = "it8772",
314 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
315 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
9faf28ca
GR		 316 /* PECI (coreboot) */
317 /* 12mV ADC (HWSensors4, OHM) */
318 /* 16 bit fans (HWSensors4, OHM) */
319 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 320 .peci_mask = 0x07,
321 },
7bc32d29
GR		 322 [it8781] = {
323 .name = "it8781",
324 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 325 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
7bc32d29
GR		 326 .old_peci_mask = 0x4,
327 },
483db43e
GR		 328 [it8782] = {
329 .name = "it8782",
19529784 330 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 331 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 332 .old_peci_mask = 0x4,
483db43e
GR		 333 },
334 [it8783] = {
335 .name = "it8783",
19529784 336 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
9faf28ca 337 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG,
19529784 338 .old_peci_mask = 0x4,
483db43e 339 },
a0c1424a
TL		 340 [it8786] = {
341 .name = "it8786",
342 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
343 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
344 .peci_mask = 0x07,
345 },
c145d5c6
RM		 346 [it8603] = {
347 .name = "it8603",
348 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
349 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI,
350 .peci_mask = 0x07,
351 },
483db43e
GR		 352};
353
354#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
355#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
356#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
357#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
358#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b
GR		 359#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
360 ((data)->peci_mask & (1 << nr)))
19529784
GR		 361#define has_temp_old_peci(data, nr) \
362 (((data)->features & FEAT_TEMP_OLD_PECI) && \
363 ((data)->old_peci_mask & (1 << nr)))
9faf28ca
GR		 364#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
365#define has_five_fans(data) ((data)->features & FEAT_FIVE_FANS)
32dd7c40 366#define has_vid(data) ((data)->features & FEAT_VID)
1da177e4 367
b74f3fdd 368struct it87_sio_data {
369 enum chips type;
370 /* Values read from Super-I/O config space */
0475169c 371 u8 revision;
b74f3fdd 372 u8 vid_value;
d9b327c3 373 u8 beep_pin;
738e5e05 374 u8 internal; /* Internal sensors can be labeled */
591ec650 375 /* Features skipped based on config or DMI */
9172b5d1 376 u16 skip_in;
895ff267 377 u8 skip_vid;
591ec650 378 u8 skip_fan;
98dd22c3 379 u8 skip_pwm;
4573acbc 380 u8 skip_temp;
b74f3fdd 381};
382
4a0d71cf
GR		 383/*
384 * For each registered chip, we need to keep some data in memory.
385 * The structure is dynamically allocated.
386 */
1da177e4 387struct it87_data {
1beeffe4 388 struct device *hwmon_dev;
1da177e4 389 enum chips type;
483db43e 390 u16 features;
19529784
GR		 391 u8 peci_mask;
392 u8 old_peci_mask;
1da177e4 393
b74f3fdd 394 unsigned short addr;
395 const char *name;
9a61bf63 396 struct mutex update_lock;
1da177e4
LT		 397 char valid; /* !=0 if following fields are valid */
398 unsigned long last_updated; /* In jiffies */
399
44c1bcd4 400 u16 in_scaled; /* Internal voltage sensors are scaled */
c145d5c6 401 u8 in[10][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 402 u8 has_fan; /* Bitfield, fans enabled */
e1169ba0 403 u16 fan[5][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 404 u8 has_temp; /* Bitfield, temp sensors enabled */
161d898a 405 s8 temp[3][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 406 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
407 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
1da177e4
LT		 408 u8 fan_div[3]; /* Register encoding, shifted right */
409 u8 vid; /* Register encoding, combined */
a7be58a1 410 u8 vrm;
1da177e4 411 u32 alarms; /* Register encoding, combined */
d9b327c3 412 u8 beeps; /* Register encoding */
1da177e4 413 u8 fan_main_ctrl; /* Register value */
f8d0c19a 414 u8 fan_ctl; /* Register value */
b99883dc 415
4a0d71cf
GR		 416 /*
417 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 418 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
419 * 7, and we want to preserve settings on mode changes, so we have
420 * to track all values separately.
421 * Starting with the IT8721F, the manual PWM duty cycles are stored
422 * in separate registers (8-bit values), so the separate tracking
423 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 424 * simple.
425 */
b99883dc 426 u8 pwm_ctrl[3]; /* Register value */
6229cdb2 427 u8 pwm_duty[3]; /* Manual PWM value set by user */
b99883dc 428 u8 pwm_temp_map[3]; /* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 429
430 /* Automatic fan speed control registers */
431 u8 auto_pwm[3][4]; /* [nr][3] is hard-coded */
432 s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 433};
0df6454d 434
0531d98b 435static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 436{
0531d98b
GR		 437 int lsb = has_12mv_adc(data) ? 12 : 16;
438 if (data->in_scaled & (1 << nr))
439 lsb <<= 1;
440 return lsb;
441}
44c1bcd4 442
0531d98b
GR		 443static u8 in_to_reg(const struct it87_data *data, int nr, long val)
444{
445 val = DIV_ROUND_CLOSEST(val, adc_lsb(data, nr));
2a844c14 446 return clamp_val(val, 0, 255);
44c1bcd4
JD		 447}
448
449static int in_from_reg(const struct it87_data *data, int nr, int val)
450{
0531d98b 451 return val * adc_lsb(data, nr);
44c1bcd4 452}
0df6454d
JD		 453
454static inline u8 FAN_TO_REG(long rpm, int div)
455{
456 if (rpm == 0)
457 return 255;
2a844c14
GR		 458 rpm = clamp_val(rpm, 1, 1000000);
459 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 460}
461
462static inline u16 FAN16_TO_REG(long rpm)
463{
464 if (rpm == 0)
465 return 0xffff;
2a844c14 466 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 467}
468
469#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
470 1350000 / ((val) * (div)))
471/* The divider is fixed to 2 in 16-bit mode */
472#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
473 1350000 / ((val) * 2))
474
2a844c14
GR		 475#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
476 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 477#define TEMP_FROM_REG(val) ((val) * 1000)
478
44c1bcd4
JD		 479static u8 pwm_to_reg(const struct it87_data *data, long val)
480{
16b5dda2 481 if (has_newer_autopwm(data))
44c1bcd4
JD		 482 return val;
483 else
484 return val >> 1;
485}
486
487static int pwm_from_reg(const struct it87_data *data, u8 reg)
488{
16b5dda2 489 if (has_newer_autopwm(data))
44c1bcd4
JD		 490 return reg;
491 else
492 return (reg & 0x7f) << 1;
493}
494
0df6454d
JD		 495
496static int DIV_TO_REG(int val)
497{
498 int answer = 0;
499 while (answer < 7 && (val >>= 1))
500 answer++;
501 return answer;
502}
503#define DIV_FROM_REG(val) (1 << (val))
504
505static const unsigned int pwm_freq[8] = {
506 48000000 / 128,
507 24000000 / 128,
508 12000000 / 128,
509 8000000 / 128,
510 6000000 / 128,
511 3000000 / 128,
512 1500000 / 128,
513 750000 / 128,
514};
1da177e4 515
b74f3fdd 516static int it87_probe(struct platform_device *pdev);
281dfd0b 517static int it87_remove(struct platform_device *pdev);
1da177e4 518
b74f3fdd 519static int it87_read_value(struct it87_data *data, u8 reg);
520static void it87_write_value(struct it87_data *data, u8 reg, u8 value);
1da177e4 521static struct it87_data *it87_update_device(struct device *dev);
b74f3fdd 522static int it87_check_pwm(struct device *dev);
523static void it87_init_device(struct platform_device *pdev);
1da177e4
LT		 524
525
b74f3fdd 526static struct platform_driver it87_driver = {
cdaf7934 527 .driver = {
b74f3fdd 528 .name = DRVNAME,
cdaf7934 529 },
b74f3fdd 530 .probe = it87_probe,
9e5e9b7a 531 .remove = it87_remove,
fde09509
JD		 532};
533
20ad93d4 534static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 535 char *buf)
1da177e4 536{
929c6a56
GR		 537 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
538 int nr = sattr->nr;
539 int index = sattr->index;
20ad93d4 540
1da177e4 541 struct it87_data *data = it87_update_device(dev);
929c6a56 542 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 543}
544
929c6a56
GR		 545static ssize_t set_in(struct device *dev, struct device_attribute *attr,
546 const char *buf, size_t count)
1da177e4 547{
929c6a56
GR		 548 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
549 int nr = sattr->nr;
550 int index = sattr->index;
20ad93d4 551
b74f3fdd 552 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 553 unsigned long val;
554
179c4fdb 555 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 556 return -EINVAL;
1da177e4 557
9a61bf63 558 mutex_lock(&data->update_lock);
929c6a56
GR		 559 data->in[nr][index] = in_to_reg(data, nr, val);
560 it87_write_value(data,
561 index == 1 ? IT87_REG_VIN_MIN(nr)
562 : IT87_REG_VIN_MAX(nr),
563 data->in[nr][index]);
9a61bf63 564 mutex_unlock(&data->update_lock);
1da177e4
LT		 565 return count;
566}
20ad93d4 567
929c6a56
GR		 568static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
569static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
570 0, 1);
571static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
572 0, 2);
f5f64501 573
929c6a56
GR		 574static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
575static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
576 1, 1);
577static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
578 1, 2);
1da177e4 579
929c6a56
GR		 580static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
581static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
582 2, 1);
583static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
584 2, 2);
1da177e4 585
929c6a56
GR		 586static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
587static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
588 3, 1);
589static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
590 3, 2);
591
592static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
593static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
594 4, 1);
595static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
596 4, 2);
597
598static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
599static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
600 5, 1);
601static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
602 5, 2);
603
604static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
605static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
606 6, 1);
607static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
608 6, 2);
609
610static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
611static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
612 7, 1);
613static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
614 7, 2);
615
616static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 617static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1da177e4
LT		 618
619/* 3 temperatures */
20ad93d4 620static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 621 char *buf)
1da177e4 622{
60ca385a
GR		 623 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
624 int nr = sattr->nr;
625 int index = sattr->index;
1da177e4 626 struct it87_data *data = it87_update_device(dev);
20ad93d4 627
60ca385a 628 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 629}
20ad93d4 630
60ca385a
GR		 631static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
632 const char *buf, size_t count)
1da177e4 633{
60ca385a
GR		 634 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
635 int nr = sattr->nr;
636 int index = sattr->index;
b74f3fdd 637 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 638 long val;
161d898a 639 u8 reg, regval;
f5f64501 640
179c4fdb 641 if (kstrtol(buf, 10, &val) < 0)
f5f64501 642 return -EINVAL;
1da177e4 643
9a61bf63 644 mutex_lock(&data->update_lock);
161d898a
GR		 645
646 switch (index) {
647 default:
648 case 1:
649 reg = IT87_REG_TEMP_LOW(nr);
650 break;
651 case 2:
652 reg = IT87_REG_TEMP_HIGH(nr);
653 break;
654 case 3:
655 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
656 if (!(regval & 0x80)) {
657 regval |= 0x80;
658 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
659 }
660 data->valid = 0;
661 reg = IT87_REG_TEMP_OFFSET[nr];
662 break;
663 }
664
60ca385a 665 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 666 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 667 mutex_unlock(&data->update_lock);
1da177e4
LT		 668 return count;
669}
1da177e4 670
60ca385a
GR		 671static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
672static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
673 0, 1);
674static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
675 0, 2);
161d898a
GR		 676static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
677 set_temp, 0, 3);
60ca385a
GR		 678static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
679static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
680 1, 1);
681static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
682 1, 2);
161d898a
GR		 683static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
684 set_temp, 1, 3);
60ca385a
GR		 685static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
686static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
687 2, 1);
688static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
689 2, 2);
161d898a
GR		 690static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
691 set_temp, 2, 3);
1da177e4 692
2cece01f
GR		 693static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
694 char *buf)
1da177e4 695{
20ad93d4
JD		 696 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
697 int nr = sensor_attr->index;
1da177e4 698 struct it87_data *data = it87_update_device(dev);
4a0d71cf 699 u8 reg = data->sensor; /* In case value is updated while used */
19529784 700 u8 extra = data->extra;
5f2dc798 701
19529784
GR		 702 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1))
703 || (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 704 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 705 if (reg & (1 << nr))
706 return sprintf(buf, "3\n"); /* thermal diode */
707 if (reg & (8 << nr))
4ed10779 708 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 709 return sprintf(buf, "0\n"); /* disabled */
710}
2cece01f
GR		 711
712static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
713 const char *buf, size_t count)
1da177e4 714{
20ad93d4
JD		 715 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
716 int nr = sensor_attr->index;
717
b74f3fdd 718 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 719 long val;
19529784 720 u8 reg, extra;
f5f64501 721
179c4fdb 722 if (kstrtol(buf, 10, &val) < 0)
f5f64501 723 return -EINVAL;
1da177e4 724
8acf07c5
JD		 725 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
726 reg &= ~(1 << nr);
727 reg &= ~(8 << nr);
5d8d2f2b
GR		 728 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
729 reg &= 0x3f;
19529784
GR		 730 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
731 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
732 extra &= 0x7f;
4ed10779 733 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 734 dev_warn(dev,
735 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 736 val = 4;
737 }
5d8d2f2b 738 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 739 if (val == 3)
8acf07c5 740 reg |= 1 << nr;
4ed10779 741 else if (val == 4)
8acf07c5 742 reg |= 8 << nr;
5d8d2f2b
GR		 743 else if (has_temp_peci(data, nr) && val == 6)
744 reg |= (nr + 1) << 6;
19529784
GR		 745 else if (has_temp_old_peci(data, nr) && val == 6)
746 extra |= 0x80;
8acf07c5 747 else if (val != 0)
1da177e4 748 return -EINVAL;
8acf07c5
JD		 749
750 mutex_lock(&data->update_lock);
751 data->sensor = reg;
19529784 752 data->extra = extra;
b74f3fdd 753 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 754 if (has_temp_old_peci(data, nr))
755 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 756 data->valid = 0; /* Force cache refresh */
9a61bf63 757 mutex_unlock(&data->update_lock);
1da177e4
LT		 758 return count;
759}
1da177e4 760
2cece01f
GR		 761static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
762 set_temp_type, 0);
763static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
764 set_temp_type, 1);
765static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
766 set_temp_type, 2);
1da177e4
LT		 767
768/* 3 Fans */
b99883dc
JD		 769
770static int pwm_mode(const struct it87_data *data, int nr)
771{
772 int ctrl = data->fan_main_ctrl & (1 << nr);
773
c145d5c6 774 if (ctrl == 0 && data->type != it8603) /* Full speed */
b99883dc
JD		 775 return 0;
776 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
777 return 2;
778 else /* Manual mode */
779 return 1;
780}
781
20ad93d4 782static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 783 char *buf)
1da177e4 784{
e1169ba0
GR		 785 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
786 int nr = sattr->nr;
787 int index = sattr->index;
788 int speed;
1da177e4 789 struct it87_data *data = it87_update_device(dev);
20ad93d4 790
e1169ba0
GR		 791 speed = has_16bit_fans(data) ?
792 FAN16_FROM_REG(data->fan[nr][index]) :
793 FAN_FROM_REG(data->fan[nr][index],
794 DIV_FROM_REG(data->fan_div[nr]));
795 return sprintf(buf, "%d\n", speed);
1da177e4 796}
e1169ba0 797
20ad93d4
JD		 798static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
799 char *buf)
1da177e4 800{
20ad93d4
JD		 801 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
802 int nr = sensor_attr->index;
803
1da177e4
LT		 804 struct it87_data *data = it87_update_device(dev);
805 return sprintf(buf, "%d\n", DIV_FROM_REG(data->fan_div[nr]));
806}
5f2dc798
JD		 807static ssize_t show_pwm_enable(struct device *dev,
808 struct device_attribute *attr, char *buf)
1da177e4 809{
20ad93d4
JD		 810 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
811 int nr = sensor_attr->index;
812
1da177e4 813 struct it87_data *data = it87_update_device(dev);
b99883dc 814 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 815}
20ad93d4
JD		 816static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
817 char *buf)
1da177e4 818{
20ad93d4
JD		 819 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
820 int nr = sensor_attr->index;
821
1da177e4 822 struct it87_data *data = it87_update_device(dev);
44c1bcd4
JD		 823 return sprintf(buf, "%d\n",
824 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 825}
f8d0c19a
JD		 826static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
827 char *buf)
828{
829 struct it87_data *data = it87_update_device(dev);
830 int index = (data->fan_ctl >> 4) & 0x07;
831
832 return sprintf(buf, "%u\n", pwm_freq[index]);
833}
e1169ba0
GR		 834
835static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
836 const char *buf, size_t count)
1da177e4 837{
e1169ba0
GR		 838 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
839 int nr = sattr->nr;
840 int index = sattr->index;
20ad93d4 841
b74f3fdd 842 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 843 long val;
7f999aa7 844 u8 reg;
1da177e4 845
179c4fdb 846 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 847 return -EINVAL;
848
9a61bf63 849 mutex_lock(&data->update_lock);
e1169ba0
GR		 850
851 if (has_16bit_fans(data)) {
852 data->fan[nr][index] = FAN16_TO_REG(val);
853 it87_write_value(data, IT87_REG_FAN_MIN[nr],
854 data->fan[nr][index] & 0xff);
855 it87_write_value(data, IT87_REG_FANX_MIN[nr],
856 data->fan[nr][index] >> 8);
857 } else {
858 reg = it87_read_value(data, IT87_REG_FAN_DIV);
859 switch (nr) {
860 case 0:
861 data->fan_div[nr] = reg & 0x07;
862 break;
863 case 1:
864 data->fan_div[nr] = (reg >> 3) & 0x07;
865 break;
866 case 2:
867 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
868 break;
869 }
870 data->fan[nr][index] =
871 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
872 it87_write_value(data, IT87_REG_FAN_MIN[nr],
873 data->fan[nr][index]);
07eab46d
JD		 874 }
875
9a61bf63 876 mutex_unlock(&data->update_lock);
1da177e4
LT		 877 return count;
878}
e1169ba0 879
20ad93d4
JD		 880static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
881 const char *buf, size_t count)
1da177e4 882{
20ad93d4
JD		 883 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
884 int nr = sensor_attr->index;
885
b74f3fdd 886 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 887 unsigned long val;
8ab4ec3e 888 int min;
1da177e4
LT		 889 u8 old;
890
179c4fdb 891 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 892 return -EINVAL;
893
9a61bf63 894 mutex_lock(&data->update_lock);
b74f3fdd 895 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 896
8ab4ec3e 897 /* Save fan min limit */
e1169ba0 898 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 899
900 switch (nr) {
901 case 0:
902 case 1:
903 data->fan_div[nr] = DIV_TO_REG(val);
904 break;
905 case 2:
906 if (val < 8)
907 data->fan_div[nr] = 1;
908 else
909 data->fan_div[nr] = 3;
910 }
911 val = old & 0x80;
912 val |= (data->fan_div[0] & 0x07);
913 val |= (data->fan_div[1] & 0x07) << 3;
914 if (data->fan_div[2] == 3)
915 val |= 0x1 << 6;
b74f3fdd 916 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 917
8ab4ec3e 918 /* Restore fan min limit */
e1169ba0
GR		 919 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
920 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 921
9a61bf63 922 mutex_unlock(&data->update_lock);
1da177e4
LT		 923 return count;
924}
cccfc9c4
JD		 925
926/* Returns 0 if OK, -EINVAL otherwise */
927static int check_trip_points(struct device *dev, int nr)
928{
929 const struct it87_data *data = dev_get_drvdata(dev);
930 int i, err = 0;
931
932 if (has_old_autopwm(data)) {
933 for (i = 0; i < 3; i++) {
934 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
935 err = -EINVAL;
936 }
937 for (i = 0; i < 2; i++) {
938 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
939 err = -EINVAL;
940 }
941 }
942
943 if (err) {
1d9bcf6a
GR		 944 dev_err(dev,
945 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 946 dev_err(dev, "Adjust the trip points and try again\n");
947 }
948 return err;
949}
950
20ad93d4
JD		 951static ssize_t set_pwm_enable(struct device *dev,
952 struct device_attribute *attr, const char *buf, size_t count)
1da177e4 953{
20ad93d4
JD		 954 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
955 int nr = sensor_attr->index;
956
b74f3fdd 957 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 958 long val;
1da177e4 959
179c4fdb 960 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 961 return -EINVAL;
962
cccfc9c4
JD		 963 /* Check trip points before switching to automatic mode */
964 if (val == 2) {
965 if (check_trip_points(dev, nr) < 0)
966 return -EINVAL;
967 }
968
c145d5c6
RM		 969 /* IT8603E does not have on/off mode */
970 if (val == 0 && data->type == it8603)
971 return -EINVAL;
972
9a61bf63 973 mutex_lock(&data->update_lock);
1da177e4
LT		 974
975 if (val == 0) {
976 int tmp;
977 /* make sure the fan is on when in on/off mode */
b74f3fdd 978 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
979 it87_write_value(data, IT87_REG_FAN_CTL, tmp | (1 << nr));
1da177e4
LT		 980 /* set on/off mode */
981 data->fan_main_ctrl &= ~(1 << nr);
5f2dc798
JD		 982 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
983 data->fan_main_ctrl);
b99883dc
JD		 984 } else {
985 if (val == 1) /* Manual mode */
16b5dda2 986 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 987 data->pwm_temp_map[nr] :
988 data->pwm_duty[nr];
b99883dc
JD		 989 else /* Automatic mode */
990 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
991 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
c145d5c6
RM		 992
993 if (data->type != it8603) {
994 /* set SmartGuardian mode */
995 data->fan_main_ctrl |= (1 << nr);
996 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
997 data->fan_main_ctrl);
998 }
1da177e4
LT		 999 }
1000
9a61bf63 1001 mutex_unlock(&data->update_lock);
1da177e4
LT		 1002 return count;
1003}
20ad93d4
JD		 1004static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1005 const char *buf, size_t count)
1da177e4 1006{
20ad93d4
JD		 1007 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1008 int nr = sensor_attr->index;
1009
b74f3fdd 1010 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1011 long val;
1da177e4 1012
179c4fdb 1013 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1014 return -EINVAL;
1015
9a61bf63 1016 mutex_lock(&data->update_lock);
16b5dda2 1017 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1018 /*
1019 * If we are in automatic mode, the PWM duty cycle register
1020 * is read-only so we can't write the value.
1021 */
6229cdb2
JD		 1022 if (data->pwm_ctrl[nr] & 0x80) {
1023 mutex_unlock(&data->update_lock);
1024 return -EBUSY;
1025 }
1026 data->pwm_duty[nr] = pwm_to_reg(data, val);
1027 it87_write_value(data, IT87_REG_PWM_DUTY(nr),
1028 data->pwm_duty[nr]);
1029 } else {
1030 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1031 /*
1032 * If we are in manual mode, write the duty cycle immediately;
1033 * otherwise, just store it for later use.
1034 */
6229cdb2
JD		 1035 if (!(data->pwm_ctrl[nr] & 0x80)) {
1036 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1037 it87_write_value(data, IT87_REG_PWM(nr),
1038 data->pwm_ctrl[nr]);
1039 }
b99883dc 1040 }
9a61bf63 1041 mutex_unlock(&data->update_lock);
1da177e4
LT		 1042 return count;
1043}
f8d0c19a
JD		 1044static ssize_t set_pwm_freq(struct device *dev,
1045 struct device_attribute *attr, const char *buf, size_t count)
1046{
b74f3fdd 1047 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1048 unsigned long val;
f8d0c19a
JD		 1049 int i;
1050
179c4fdb 1051 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1052 return -EINVAL;
1053
f8d0c19a
JD		 1054 /* Search for the nearest available frequency */
1055 for (i = 0; i < 7; i++) {
1056 if (val > (pwm_freq[i] + pwm_freq[i+1]) / 2)
1057 break;
1058 }
1059
1060 mutex_lock(&data->update_lock);
b74f3fdd 1061 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
f8d0c19a 1062 data->fan_ctl |= i << 4;
b74f3fdd 1063 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
f8d0c19a
JD		 1064 mutex_unlock(&data->update_lock);
1065
1066 return count;
1067}
94ac7ee6
JD		 1068static ssize_t show_pwm_temp_map(struct device *dev,
1069 struct device_attribute *attr, char *buf)
1070{
1071 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1072 int nr = sensor_attr->index;
1073
1074 struct it87_data *data = it87_update_device(dev);
1075 int map;
1076
1077 if (data->pwm_temp_map[nr] < 3)
1078 map = 1 << data->pwm_temp_map[nr];
1079 else
1080 map = 0; /* Should never happen */
1081 return sprintf(buf, "%d\n", map);
1082}
1083static ssize_t set_pwm_temp_map(struct device *dev,
1084 struct device_attribute *attr, const char *buf, size_t count)
1085{
1086 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1087 int nr = sensor_attr->index;
1088
1089 struct it87_data *data = dev_get_drvdata(dev);
1090 long val;
1091 u8 reg;
1092
4a0d71cf
GR		 1093 /*
1094 * This check can go away if we ever support automatic fan speed
1095 * control on newer chips.
1096 */
4f3f51bc
JD		 1097 if (!has_old_autopwm(data)) {
1098 dev_notice(dev, "Mapping change disabled for safety reasons\n");
1099 return -EINVAL;
1100 }
1101
179c4fdb 1102 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1103 return -EINVAL;
1104
1105 switch (val) {
1106 case (1 << 0):
1107 reg = 0x00;
1108 break;
1109 case (1 << 1):
1110 reg = 0x01;
1111 break;
1112 case (1 << 2):
1113 reg = 0x02;
1114 break;
1115 default:
1116 return -EINVAL;
1117 }
1118
1119 mutex_lock(&data->update_lock);
1120 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1121 /*
1122 * If we are in automatic mode, write the temp mapping immediately;
1123 * otherwise, just store it for later use.
1124 */
94ac7ee6
JD		 1125 if (data->pwm_ctrl[nr] & 0x80) {
1126 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
1127 it87_write_value(data, IT87_REG_PWM(nr), data->pwm_ctrl[nr]);
1128 }
1129 mutex_unlock(&data->update_lock);
1130 return count;
1131}
1da177e4 1132
4f3f51bc
JD		 1133static ssize_t show_auto_pwm(struct device *dev,
1134 struct device_attribute *attr, char *buf)
1135{
1136 struct it87_data *data = it87_update_device(dev);
1137 struct sensor_device_attribute_2 *sensor_attr =
1138 to_sensor_dev_attr_2(attr);
1139 int nr = sensor_attr->nr;
1140 int point = sensor_attr->index;
1141
44c1bcd4
JD		 1142 return sprintf(buf, "%d\n",
1143 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1144}
1145
1146static ssize_t set_auto_pwm(struct device *dev,
1147 struct device_attribute *attr, const char *buf, size_t count)
1148{
1149 struct it87_data *data = dev_get_drvdata(dev);
1150 struct sensor_device_attribute_2 *sensor_attr =
1151 to_sensor_dev_attr_2(attr);
1152 int nr = sensor_attr->nr;
1153 int point = sensor_attr->index;
1154 long val;
1155
179c4fdb 1156 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1157 return -EINVAL;
1158
1159 mutex_lock(&data->update_lock);
44c1bcd4 1160 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1161 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1162 data->auto_pwm[nr][point]);
1163 mutex_unlock(&data->update_lock);
1164 return count;
1165}
1166
1167static ssize_t show_auto_temp(struct device *dev,
1168 struct device_attribute *attr, char *buf)
1169{
1170 struct it87_data *data = it87_update_device(dev);
1171 struct sensor_device_attribute_2 *sensor_attr =
1172 to_sensor_dev_attr_2(attr);
1173 int nr = sensor_attr->nr;
1174 int point = sensor_attr->index;
1175
1176 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1177}
1178
1179static ssize_t set_auto_temp(struct device *dev,
1180 struct device_attribute *attr, const char *buf, size_t count)
1181{
1182 struct it87_data *data = dev_get_drvdata(dev);
1183 struct sensor_device_attribute_2 *sensor_attr =
1184 to_sensor_dev_attr_2(attr);
1185 int nr = sensor_attr->nr;
1186 int point = sensor_attr->index;
1187 long val;
1188
179c4fdb 1189 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1190 return -EINVAL;
1191
1192 mutex_lock(&data->update_lock);
1193 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1194 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1195 data->auto_temp[nr][point]);
1196 mutex_unlock(&data->update_lock);
1197 return count;
1198}
1199
e1169ba0
GR		 1200static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1201static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1202 0, 1);
1203static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1204 set_fan_div, 0);
1205
1206static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1207static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1208 1, 1);
1209static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1210 set_fan_div, 1);
1211
1212static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1213static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1214 2, 1);
1215static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1216 set_fan_div, 2);
1217
1218static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1219static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1220 3, 1);
1da177e4 1221
e1169ba0
GR		 1222static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1223static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1224 4, 1);
1da177e4 1225
c4458db3
GR		 1226static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1227 show_pwm_enable, set_pwm_enable, 0);
1228static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1229static DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, set_pwm_freq);
1230static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO | S_IWUSR,
1231 show_pwm_temp_map, set_pwm_temp_map, 0);
1232static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1233 show_auto_pwm, set_auto_pwm, 0, 0);
1234static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1235 show_auto_pwm, set_auto_pwm, 0, 1);
1236static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1237 show_auto_pwm, set_auto_pwm, 0, 2);
1238static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1239 show_auto_pwm, NULL, 0, 3);
1240static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1241 show_auto_temp, set_auto_temp, 0, 1);
1242static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1243 show_auto_temp, set_auto_temp, 0, 0);
1244static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1245 show_auto_temp, set_auto_temp, 0, 2);
1246static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1247 show_auto_temp, set_auto_temp, 0, 3);
1248static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1249 show_auto_temp, set_auto_temp, 0, 4);
1250
1251static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1252 show_pwm_enable, set_pwm_enable, 1);
1253static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
1254static DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, NULL);
1255static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO | S_IWUSR,
1256 show_pwm_temp_map, set_pwm_temp_map, 1);
1257static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1258 show_auto_pwm, set_auto_pwm, 1, 0);
1259static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1260 show_auto_pwm, set_auto_pwm, 1, 1);
1261static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1262 show_auto_pwm, set_auto_pwm, 1, 2);
1263static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1264 show_auto_pwm, NULL, 1, 3);
1265static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1266 show_auto_temp, set_auto_temp, 1, 1);
1267static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1268 show_auto_temp, set_auto_temp, 1, 0);
1269static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1270 show_auto_temp, set_auto_temp, 1, 2);
1271static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1272 show_auto_temp, set_auto_temp, 1, 3);
1273static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1274 show_auto_temp, set_auto_temp, 1, 4);
1275
1276static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1277 show_pwm_enable, set_pwm_enable, 2);
1278static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
1279static DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL);
1280static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO | S_IWUSR,
1281 show_pwm_temp_map, set_pwm_temp_map, 2);
1282static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1283 show_auto_pwm, set_auto_pwm, 2, 0);
1284static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1285 show_auto_pwm, set_auto_pwm, 2, 1);
1286static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1287 show_auto_pwm, set_auto_pwm, 2, 2);
1288static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1289 show_auto_pwm, NULL, 2, 3);
1290static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1291 show_auto_temp, set_auto_temp, 2, 1);
1292static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1293 show_auto_temp, set_auto_temp, 2, 0);
1294static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1295 show_auto_temp, set_auto_temp, 2, 2);
1296static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1297 show_auto_temp, set_auto_temp, 2, 3);
1298static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1299 show_auto_temp, set_auto_temp, 2, 4);
1da177e4
LT		 1300
1301/* Alarms */
5f2dc798
JD		 1302static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
1303 char *buf)
1da177e4
LT		 1304{
1305 struct it87_data *data = it87_update_device(dev);
68188ba7 1306 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1307}
1d66c64c 1308static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1309
0124dd78
JD		 1310static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
1311 char *buf)
1312{
1313 int bitnr = to_sensor_dev_attr(attr)->index;
1314 struct it87_data *data = it87_update_device(dev);
1315 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1316}
3d30f9e6
JD		 1317
1318static ssize_t clear_intrusion(struct device *dev, struct device_attribute
1319 *attr, const char *buf, size_t count)
1320{
1321 struct it87_data *data = dev_get_drvdata(dev);
1322 long val;
1323 int config;
1324
179c4fdb 1325 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1326 return -EINVAL;
1327
1328 mutex_lock(&data->update_lock);
1329 config = it87_read_value(data, IT87_REG_CONFIG);
1330 if (config < 0) {
1331 count = config;
1332 } else {
1333 config |= 1 << 5;
1334 it87_write_value(data, IT87_REG_CONFIG, config);
1335 /* Invalidate cache to force re-read */
1336 data->valid = 0;
1337 }
1338 mutex_unlock(&data->update_lock);
1339
1340 return count;
1341}
1342
0124dd78
JD		 1343static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1344static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1345static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1346static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1347static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1348static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1349static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1350static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1351static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1352static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1353static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1354static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1355static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
1356static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1357static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1358static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1359static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1360 show_alarm, clear_intrusion, 4);
0124dd78 1361
d9b327c3
JD		 1362static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
1363 char *buf)
1364{
1365 int bitnr = to_sensor_dev_attr(attr)->index;
1366 struct it87_data *data = it87_update_device(dev);
1367 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1368}
1369static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
1370 const char *buf, size_t count)
1371{
1372 int bitnr = to_sensor_dev_attr(attr)->index;
1373 struct it87_data *data = dev_get_drvdata(dev);
1374 long val;
1375
179c4fdb 1376 if (kstrtol(buf, 10, &val) < 0
d9b327c3
JD		 1377 || (val != 0 && val != 1))
1378 return -EINVAL;
1379
1380 mutex_lock(&data->update_lock);
1381 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1382 if (val)
1383 data->beeps |= (1 << bitnr);
1384 else
1385 data->beeps &= ~(1 << bitnr);
1386 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1387 mutex_unlock(&data->update_lock);
1388 return count;
1389}
1390
1391static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1392 show_beep, set_beep, 1);
1393static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1394static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1395static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1396static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1397static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1398static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1399static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1400/* fanX_beep writability is set later */
1401static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1402static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1403static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1404static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1405static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
1406static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1407 show_beep, set_beep, 2);
1408static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1409static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1410
5f2dc798
JD		 1411static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
1412 char *buf)
1da177e4 1413{
90d6619a 1414 struct it87_data *data = dev_get_drvdata(dev);
a7be58a1 1415 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1416}
5f2dc798
JD		 1417static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
1418 const char *buf, size_t count)
1da177e4 1419{
b74f3fdd 1420 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1421 unsigned long val;
1422
179c4fdb 1423 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1424 return -EINVAL;
1da177e4 1425
1da177e4
LT		 1426 data->vrm = val;
1427
1428 return count;
1429}
1430static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1431
5f2dc798
JD		 1432static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
1433 char *buf)
1da177e4
LT		 1434{
1435 struct it87_data *data = it87_update_device(dev);
1436 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
1437}
1438static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1439
738e5e05
JD		 1440static ssize_t show_label(struct device *dev, struct device_attribute *attr,
1441 char *buf)
1442{
3c4c4971 1443 static const char * const labels[] = {
738e5e05
JD		 1444 "+5V",
1445 "5VSB",
1446 "Vbat",
1447 };
3c4c4971 1448 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1449 "+3.3V",
1450 "3VSB",
1451 "Vbat",
1452 };
1453 struct it87_data *data = dev_get_drvdata(dev);
738e5e05
JD		 1454 int nr = to_sensor_dev_attr(attr)->index;
1455
16b5dda2
JD		 1456 return sprintf(buf, "%s\n", has_12mv_adc(data) ? labels_it8721[nr]
1457 : labels[nr]);
738e5e05
JD		 1458}
1459static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1460static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1461static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
7183ae8c 1462/* special AVCC3 IT8603E in9 */
c145d5c6 1463static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1464
b74f3fdd 1465static ssize_t show_name(struct device *dev, struct device_attribute
1466 *devattr, char *buf)
1467{
1468 struct it87_data *data = dev_get_drvdata(dev);
1469 return sprintf(buf, "%s\n", data->name);
1470}
1471static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1472
c145d5c6 1473static struct attribute *it87_attributes_in[10][5] = {
9172b5d1 1474{
87808be4 1475 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1476 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1477 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1478 &sensor_dev_attr_in0_alarm.dev_attr.attr,
9172b5d1
GR		 1479 NULL
1480}, {
1481 &sensor_dev_attr_in1_input.dev_attr.attr,
1482 &sensor_dev_attr_in1_min.dev_attr.attr,
1483 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1484 &sensor_dev_attr_in1_alarm.dev_attr.attr,
9172b5d1
GR		 1485 NULL
1486}, {
1487 &sensor_dev_attr_in2_input.dev_attr.attr,
1488 &sensor_dev_attr_in2_min.dev_attr.attr,
1489 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1490 &sensor_dev_attr_in2_alarm.dev_attr.attr,
9172b5d1
GR		 1491 NULL
1492}, {
1493 &sensor_dev_attr_in3_input.dev_attr.attr,
1494 &sensor_dev_attr_in3_min.dev_attr.attr,
1495 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1496 &sensor_dev_attr_in3_alarm.dev_attr.attr,
9172b5d1
GR		 1497 NULL
1498}, {
1499 &sensor_dev_attr_in4_input.dev_attr.attr,
1500 &sensor_dev_attr_in4_min.dev_attr.attr,
1501 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1502 &sensor_dev_attr_in4_alarm.dev_attr.attr,
9172b5d1
GR		 1503 NULL
1504}, {
1505 &sensor_dev_attr_in5_input.dev_attr.attr,
1506 &sensor_dev_attr_in5_min.dev_attr.attr,
1507 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1508 &sensor_dev_attr_in5_alarm.dev_attr.attr,
9172b5d1
GR		 1509 NULL
1510}, {
1511 &sensor_dev_attr_in6_input.dev_attr.attr,
1512 &sensor_dev_attr_in6_min.dev_attr.attr,
1513 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1514 &sensor_dev_attr_in6_alarm.dev_attr.attr,
9172b5d1
GR		 1515 NULL
1516}, {
1517 &sensor_dev_attr_in7_input.dev_attr.attr,
1518 &sensor_dev_attr_in7_min.dev_attr.attr,
1519 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1520 &sensor_dev_attr_in7_alarm.dev_attr.attr,
9172b5d1
GR		 1521 NULL
1522}, {
1523 &sensor_dev_attr_in8_input.dev_attr.attr,
1524 NULL
c145d5c6
RM		 1525}, {
1526 &sensor_dev_attr_in9_input.dev_attr.attr,
1527 NULL
9172b5d1 1528} };
87808be4 1529
c145d5c6 1530static const struct attribute_group it87_group_in[10] = {
9172b5d1
GR		 1531 { .attrs = it87_attributes_in[0] },
1532 { .attrs = it87_attributes_in[1] },
1533 { .attrs = it87_attributes_in[2] },
1534 { .attrs = it87_attributes_in[3] },
1535 { .attrs = it87_attributes_in[4] },
1536 { .attrs = it87_attributes_in[5] },
1537 { .attrs = it87_attributes_in[6] },
1538 { .attrs = it87_attributes_in[7] },
1539 { .attrs = it87_attributes_in[8] },
c145d5c6 1540 { .attrs = it87_attributes_in[9] },
9172b5d1
GR		 1541};
1542
4573acbc
GR		 1543static struct attribute *it87_attributes_temp[3][6] = {
1544{
87808be4 1545 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1546 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1547 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1548 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1549 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
4573acbc
GR		 1550 NULL
1551} , {
1552 &sensor_dev_attr_temp2_input.dev_attr.attr,
1553 &sensor_dev_attr_temp2_max.dev_attr.attr,
1554 &sensor_dev_attr_temp2_min.dev_attr.attr,
1555 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1556 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
4573acbc
GR		 1557 NULL
1558} , {
1559 &sensor_dev_attr_temp3_input.dev_attr.attr,
1560 &sensor_dev_attr_temp3_max.dev_attr.attr,
1561 &sensor_dev_attr_temp3_min.dev_attr.attr,
1562 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1563 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
4573acbc
GR		 1564 NULL
1565} };
1566
1567static const struct attribute_group it87_group_temp[3] = {
1568 { .attrs = it87_attributes_temp[0] },
1569 { .attrs = it87_attributes_temp[1] },
1570 { .attrs = it87_attributes_temp[2] },
1571};
87808be4 1572
161d898a
GR		 1573static struct attribute *it87_attributes_temp_offset[] = {
1574 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1575 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1576 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1577};
1578
4573acbc 1579static struct attribute *it87_attributes[] = {
87808be4 1580 &dev_attr_alarms.attr,
3d30f9e6 1581 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
b74f3fdd 1582 &dev_attr_name.attr,
87808be4
JD		 1583 NULL
1584};
1585
1586static const struct attribute_group it87_group = {
1587 .attrs = it87_attributes,
1588};
1589
9172b5d1 1590static struct attribute *it87_attributes_in_beep[] = {
d9b327c3
JD		 1591 &sensor_dev_attr_in0_beep.dev_attr.attr,
1592 &sensor_dev_attr_in1_beep.dev_attr.attr,
1593 &sensor_dev_attr_in2_beep.dev_attr.attr,
1594 &sensor_dev_attr_in3_beep.dev_attr.attr,
1595 &sensor_dev_attr_in4_beep.dev_attr.attr,
1596 &sensor_dev_attr_in5_beep.dev_attr.attr,
1597 &sensor_dev_attr_in6_beep.dev_attr.attr,
1598 &sensor_dev_attr_in7_beep.dev_attr.attr,
c145d5c6
RM		 1599 NULL,
1600 NULL,
9172b5d1 1601};
d9b327c3 1602
4573acbc 1603static struct attribute *it87_attributes_temp_beep[] = {
d9b327c3
JD		 1604 &sensor_dev_attr_temp1_beep.dev_attr.attr,
1605 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1606 &sensor_dev_attr_temp3_beep.dev_attr.attr,
d9b327c3
JD		 1607};
1608
e1169ba0
GR		 1609static struct attribute *it87_attributes_fan[5][3+1] = { {
1610 &sensor_dev_attr_fan1_input.dev_attr.attr,
1611 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0
JD		 1612 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1613 NULL
1614}, {
e1169ba0
GR		 1615 &sensor_dev_attr_fan2_input.dev_attr.attr,
1616 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0
JD		 1617 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1618 NULL
1619}, {
e1169ba0
GR		 1620 &sensor_dev_attr_fan3_input.dev_attr.attr,
1621 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0
JD		 1622 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1623 NULL
1624}, {
e1169ba0
GR		 1625 &sensor_dev_attr_fan4_input.dev_attr.attr,
1626 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0
JD		 1627 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1628 NULL
1629}, {
e1169ba0
GR		 1630 &sensor_dev_attr_fan5_input.dev_attr.attr,
1631 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0
JD		 1632 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1633 NULL
1634} };
1635
e1169ba0
GR		 1636static const struct attribute_group it87_group_fan[5] = {
1637 { .attrs = it87_attributes_fan[0] },
1638 { .attrs = it87_attributes_fan[1] },
1639 { .attrs = it87_attributes_fan[2] },
1640 { .attrs = it87_attributes_fan[3] },
1641 { .attrs = it87_attributes_fan[4] },
723a0aa0 1642};
87808be4 1643
e1169ba0 1644static const struct attribute *it87_attributes_fan_div[] = {
87808be4 1645 &sensor_dev_attr_fan1_div.dev_attr.attr,
87808be4 1646 &sensor_dev_attr_fan2_div.dev_attr.attr,
87808be4 1647 &sensor_dev_attr_fan3_div.dev_attr.attr,
723a0aa0
JD		 1648};
1649
723a0aa0 1650static struct attribute *it87_attributes_pwm[3][4+1] = { {
87808be4 1651 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 1652 &sensor_dev_attr_pwm1.dev_attr.attr,
d5b0b5d6 1653 &dev_attr_pwm1_freq.attr,
94ac7ee6 1654 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1655 NULL
1656}, {
1657 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1658 &sensor_dev_attr_pwm2.dev_attr.attr,
1659 &dev_attr_pwm2_freq.attr,
94ac7ee6 1660 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1661 NULL
1662}, {
1663 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1664 &sensor_dev_attr_pwm3.dev_attr.attr,
1665 &dev_attr_pwm3_freq.attr,
94ac7ee6 1666 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
723a0aa0
JD		 1667 NULL
1668} };
87808be4 1669
723a0aa0
JD		 1670static const struct attribute_group it87_group_pwm[3] = {
1671 { .attrs = it87_attributes_pwm[0] },
1672 { .attrs = it87_attributes_pwm[1] },
1673 { .attrs = it87_attributes_pwm[2] },
1674};
1675
4f3f51bc
JD		 1676static struct attribute *it87_attributes_autopwm[3][9+1] = { {
1677 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1678 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
1679 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
1680 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
1681 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
1682 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
1683 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
1684 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
1685 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
1686 NULL
1687}, {
1688 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1689 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
1690 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
1691 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
1692 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
1693 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
1694 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
1695 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
1696 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
1697 NULL
1698}, {
1699 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1700 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
1701 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
1702 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
1703 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
1704 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
1705 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
1706 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
1707 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
1708 NULL
1709} };
1710
1711static const struct attribute_group it87_group_autopwm[3] = {
1712 { .attrs = it87_attributes_autopwm[0] },
1713 { .attrs = it87_attributes_autopwm[1] },
1714 { .attrs = it87_attributes_autopwm[2] },
1715};
1716
d9b327c3
JD		 1717static struct attribute *it87_attributes_fan_beep[] = {
1718 &sensor_dev_attr_fan1_beep.dev_attr.attr,
1719 &sensor_dev_attr_fan2_beep.dev_attr.attr,
1720 &sensor_dev_attr_fan3_beep.dev_attr.attr,
1721 &sensor_dev_attr_fan4_beep.dev_attr.attr,
1722 &sensor_dev_attr_fan5_beep.dev_attr.attr,
1723};
1724
6a8d7acf 1725static struct attribute *it87_attributes_vid[] = {
87808be4
JD		 1726 &dev_attr_vrm.attr,
1727 &dev_attr_cpu0_vid.attr,
1728 NULL
1729};
1730
6a8d7acf
JD		 1731static const struct attribute_group it87_group_vid = {
1732 .attrs = it87_attributes_vid,
87808be4 1733};
1da177e4 1734
738e5e05
JD		 1735static struct attribute *it87_attributes_label[] = {
1736 &sensor_dev_attr_in3_label.dev_attr.attr,
1737 &sensor_dev_attr_in7_label.dev_attr.attr,
1738 &sensor_dev_attr_in8_label.dev_attr.attr,
c145d5c6 1739 &sensor_dev_attr_in9_label.dev_attr.attr,
738e5e05
JD		 1740 NULL
1741};
1742
1743static const struct attribute_group it87_group_label = {
fa8b6975 1744 .attrs = it87_attributes_label,
738e5e05
JD		 1745};
1746
2d8672c5 1747/* SuperIO detection - will change isa_address if a chip is found */
b74f3fdd 1748static int __init it87_find(unsigned short *address,
1749 struct it87_sio_data *sio_data)
1da177e4 1750{
5b0380c9 1751 int err;
b74f3fdd 1752 u16 chip_type;
98dd22c3 1753 const char *board_vendor, *board_name;
1da177e4 1754
5b0380c9
NG		 1755 err = superio_enter();
1756 if (err)
1757 return err;
1758
1759 err = -ENODEV;
67b671bc 1760 chip_type = force_id ? force_id : superio_inw(DEVID);
b74f3fdd 1761
1762 switch (chip_type) {
1763 case IT8705F_DEVID:
1764 sio_data->type = it87;
1765 break;
1766 case IT8712F_DEVID:
1767 sio_data->type = it8712;
1768 break;
1769 case IT8716F_DEVID:
1770 case IT8726F_DEVID:
1771 sio_data->type = it8716;
1772 break;
1773 case IT8718F_DEVID:
1774 sio_data->type = it8718;
1775 break;
b4da93e4
JMS		 1776 case IT8720F_DEVID:
1777 sio_data->type = it8720;
1778 break;
44c1bcd4
JD		 1779 case IT8721F_DEVID:
1780 sio_data->type = it8721;
1781 break;
16b5dda2
JD		 1782 case IT8728F_DEVID:
1783 sio_data->type = it8728;
1784 break;
b0636707
GR		 1785 case IT8771E_DEVID:
1786 sio_data->type = it8771;
1787 break;
1788 case IT8772E_DEVID:
1789 sio_data->type = it8772;
1790 break;
7bc32d29
GR		 1791 case IT8781F_DEVID:
1792 sio_data->type = it8781;
1793 break;
0531d98b
GR		 1794 case IT8782F_DEVID:
1795 sio_data->type = it8782;
1796 break;
1797 case IT8783E_DEVID:
1798 sio_data->type = it8783;
1799 break;
a0c1424a
TL		 1800 case IT8786E_DEVID:
1801 sio_data->type = it8786;
1802 break;
7183ae8c 1803 case IT8603E_DEVID:
574e9bd8 1804 case IT8623E_DEVID:
c145d5c6
RM		 1805 sio_data->type = it8603;
1806 break;
b74f3fdd 1807 case 0xffff: /* No device at all */
1808 goto exit;
1809 default:
a8ca1037 1810 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 1811 goto exit;
1812 }
1da177e4 1813
87673dd7 1814 superio_select(PME);
1da177e4 1815 if (!(superio_inb(IT87_ACT_REG) & 0x01)) {
a8ca1037 1816 pr_info("Device not activated, skipping\n");
1da177e4
LT		 1817 goto exit;
1818 }
1819
1820 *address = superio_inw(IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1821 if (*address == 0) {
a8ca1037 1822 pr_info("Base address not set, skipping\n");
1da177e4
LT		 1823 goto exit;
1824 }
1825
1826 err = 0;
0475169c 1827 sio_data->revision = superio_inb(DEVREV) & 0x0f;
c145d5c6 1828 pr_info("Found IT%04x%c chip at 0x%x, revision %d\n", chip_type,
b523bb75 1829 chip_type == 0x8771 || chip_type == 0x8772 ||
a0c1424a
TL		 1830 chip_type == 0x8786 || chip_type == 0x8603 ? 'E' : 'F',
1831 *address, sio_data->revision);
1da177e4 1832
738e5e05
JD		 1833 /* in8 (Vbat) is always internal */
1834 sio_data->internal = (1 << 2);
c145d5c6
RM		 1835 /* Only the IT8603E has in9 */
1836 if (sio_data->type != it8603)
1837 sio_data->skip_in |= (1 << 9);
738e5e05 1838
32dd7c40 1839 if (!(it87_devices[sio_data->type].features & FEAT_VID))
895ff267 1840 sio_data->skip_vid = 1;
d9b327c3 1841
32dd7c40
GR		 1842 /* Read GPIO config and VID value from LDN 7 (GPIO) */
1843 if (sio_data->type == it87) {
d9b327c3
JD		 1844 /* The IT8705F has a different LD number for GPIO */
1845 superio_select(5);
1846 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 1847 } else if (sio_data->type == it8783) {
088ce2ac 1848 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 1849
0531d98b
GR		 1850 superio_select(GPIO);
1851
1852 reg25 = superio_inb(IT87_SIO_GPIO1_REG);
1853 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
088ce2ac
GR		 1854 reg2a = superio_inb(IT87_SIO_PINX1_REG);
1855 reg2c = superio_inb(IT87_SIO_PINX2_REG);
1856 regef = superio_inb(IT87_SIO_SPI_REG);
0531d98b 1857
0531d98b 1858 /* Check if fan3 is there or not */
088ce2ac 1859 if ((reg27 & (1 << 0)) || !(reg2c & (1 << 2)))
0531d98b
GR		 1860 sio_data->skip_fan |= (1 << 2);
1861 if ((reg25 & (1 << 4))
088ce2ac 1862 || (!(reg2a & (1 << 1)) && (regef & (1 << 0))))
0531d98b
GR		 1863 sio_data->skip_pwm |= (1 << 2);
1864
1865 /* Check if fan2 is there or not */
1866 if (reg27 & (1 << 7))
1867 sio_data->skip_fan |= (1 << 1);
1868 if (reg27 & (1 << 3))
1869 sio_data->skip_pwm |= (1 << 1);
1870
1871 /* VIN5 */
088ce2ac 1872 if ((reg27 & (1 << 0)) || (reg2c & (1 << 2)))
9172b5d1 1873 sio_data->skip_in |= (1 << 5); /* No VIN5 */
0531d98b
GR		 1874
1875 /* VIN6 */
9172b5d1
GR		 1876 if (reg27 & (1 << 1))
1877 sio_data->skip_in |= (1 << 6); /* No VIN6 */
0531d98b
GR		 1878
1879 /*
1880 * VIN7
1881 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
1882 */
9172b5d1
GR		 1883 if (reg27 & (1 << 2)) {
1884 /*
1885 * The data sheet is a bit unclear regarding the
1886 * internal voltage divider for VCCH5V. It says
1887 * "This bit enables and switches VIN7 (pin 91) to the
1888 * internal voltage divider for VCCH5V".
1889 * This is different to other chips, where the internal
1890 * voltage divider would connect VIN7 to an internal
1891 * voltage source. Maybe that is the case here as well.
1892 *
1893 * Since we don't know for sure, re-route it if that is
1894 * not the case, and ask the user to report if the
1895 * resulting voltage is sane.
1896 */
088ce2ac
GR		 1897 if (!(reg2c & (1 << 1))) {
1898 reg2c |= (1 << 1);
1899 superio_outb(IT87_SIO_PINX2_REG, reg2c);
9172b5d1
GR		 1900 pr_notice("Routing internal VCCH5V to in7.\n");
1901 }
1902 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
1903 pr_notice("Please report if it displays a reasonable voltage.\n");
1904 }
0531d98b 1905
088ce2ac 1906 if (reg2c & (1 << 0))
0531d98b 1907 sio_data->internal |= (1 << 0);
088ce2ac 1908 if (reg2c & (1 << 1))
0531d98b
GR		 1909 sio_data->internal |= (1 << 1);
1910
1911 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 1912 } else if (sio_data->type == it8603) {
1913 int reg27, reg29;
1914
c145d5c6 1915 superio_select(GPIO);
0531d98b 1916
c145d5c6
RM		 1917 reg27 = superio_inb(IT87_SIO_GPIO3_REG);
1918
1919 /* Check if fan3 is there or not */
1920 if (reg27 & (1 << 6))
1921 sio_data->skip_pwm |= (1 << 2);
1922 if (reg27 & (1 << 7))
1923 sio_data->skip_fan |= (1 << 2);
1924
1925 /* Check if fan2 is there or not */
1926 reg29 = superio_inb(IT87_SIO_GPIO5_REG);
1927 if (reg29 & (1 << 1))
1928 sio_data->skip_pwm |= (1 << 1);
1929 if (reg29 & (1 << 2))
1930 sio_data->skip_fan |= (1 << 1);
1931
1932 sio_data->skip_in |= (1 << 5); /* No VIN5 */
1933 sio_data->skip_in |= (1 << 6); /* No VIN6 */
1934
1935 /* no fan4 */
1936 sio_data->skip_pwm |= (1 << 3);
1937 sio_data->skip_fan |= (1 << 3);
1938
1939 sio_data->internal |= (1 << 1); /* in7 is VSB */
1940 sio_data->internal |= (1 << 3); /* in9 is AVCC */
1941
1942 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 1943 } else {
87673dd7 1944 int reg;
9172b5d1 1945 bool uart6;
87673dd7
JD		 1946
1947 superio_select(GPIO);
44c1bcd4 1948
895ff267 1949 reg = superio_inb(IT87_SIO_GPIO3_REG);
32dd7c40 1950 if (!sio_data->skip_vid) {
44c1bcd4
JD		 1951 /* We need at least 4 VID pins */
1952 if (reg & 0x0f) {
a8ca1037 1953 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 1954 sio_data->skip_vid = 1;
1955 }
895ff267
JD		 1956 }
1957
591ec650
JD		 1958 /* Check if fan3 is there or not */
1959 if (reg & (1 << 6))
1960 sio_data->skip_pwm |= (1 << 2);
1961 if (reg & (1 << 7))
1962 sio_data->skip_fan |= (1 << 2);
1963
1964 /* Check if fan2 is there or not */
1965 reg = superio_inb(IT87_SIO_GPIO5_REG);
1966 if (reg & (1 << 1))
1967 sio_data->skip_pwm |= (1 << 1);
1968 if (reg & (1 << 2))
1969 sio_data->skip_fan |= (1 << 1);
1970
895ff267
JD		 1971 if ((sio_data->type == it8718 || sio_data->type == it8720)
1972 && !(sio_data->skip_vid))
b74f3fdd 1973 sio_data->vid_value = superio_inb(IT87_SIO_VID_REG);
87673dd7
JD		 1974
1975 reg = superio_inb(IT87_SIO_PINX2_REG);
9172b5d1
GR		 1976
1977 uart6 = sio_data->type == it8782 && (reg & (1 << 2));
1978
436cad2a
JD		 1979 /*
1980 * The IT8720F has no VIN7 pin, so VCCH should always be
1981 * routed internally to VIN7 with an internal divider.
1982 * Curiously, there still is a configuration bit to control
1983 * this, which means it can be set incorrectly. And even
1984 * more curiously, many boards out there are improperly
1985 * configured, even though the IT8720F datasheet claims
1986 * that the internal routing of VCCH to VIN7 is the default
1987 * setting. So we force the internal routing in this case.
0531d98b
GR		 1988 *
1989 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 1990 * If UART6 is enabled, re-route VIN7 to the internal divider
1991 * if that is not already the case.
436cad2a 1992 */
9172b5d1 1993 if ((sio_data->type == it8720 || uart6) && !(reg & (1 << 1))) {
436cad2a
JD		 1994 reg |= (1 << 1);
1995 superio_outb(IT87_SIO_PINX2_REG, reg);
a8ca1037 1996 pr_notice("Routing internal VCCH to in7\n");
436cad2a 1997 }
87673dd7 1998 if (reg & (1 << 0))
738e5e05 1999 sio_data->internal |= (1 << 0);
16b5dda2 2000 if ((reg & (1 << 1)) || sio_data->type == it8721 ||
a0c1424a
TL		 2001 sio_data->type == it8728 || sio_data->type == it8771 ||
2002 sio_data->type == it8772 || sio_data->type == it8786)
738e5e05 2003 sio_data->internal |= (1 << 1);
d9b327c3 2004
9172b5d1
GR		 2005 /*
2006 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2007 * While VIN7 can be routed to the internal voltage divider,
2008 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2009 *
2010 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2011 * is the temperature source. Since we can not read the
2012 * temperature source here, skip_temp is preliminary.
9172b5d1 2013 */
4573acbc 2014 if (uart6) {
9172b5d1 2015 sio_data->skip_in |= (1 << 5) | (1 << 6);
4573acbc
GR		 2016 sio_data->skip_temp |= (1 << 2);
2017 }
9172b5d1 2018
d9b327c3 2019 sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2020 }
d9b327c3 2021 if (sio_data->beep_pin)
a8ca1037 2022 pr_info("Beeping is supported\n");
87673dd7 2023
98dd22c3
JD		 2024 /* Disable specific features based on DMI strings */
2025 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2026 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2027 if (board_vendor && board_name) {
2028 if (strcmp(board_vendor, "nVIDIA") == 0
2029 && strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2030 /*
2031 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2032 * connected to a fan, but to something else. One user
2033 * has reported instant system power-off when changing
2034 * the PWM2 duty cycle, so we disable it.
2035 * I use the board name string as the trigger in case
2036 * the same board is ever used in other systems.
2037 */
a8ca1037 2038 pr_info("Disabling pwm2 due to hardware constraints\n");
98dd22c3
JD		 2039 sio_data->skip_pwm = (1 << 1);
2040 }
2041 }
2042
1da177e4
LT		 2043exit:
2044 superio_exit();
2045 return err;
2046}
2047
723a0aa0
JD		 2048static void it87_remove_files(struct device *dev)
2049{
2050 struct it87_data *data = platform_get_drvdata(pdev);
a8b3a3a5 2051 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0
JD		 2052 int i;
2053
2054 sysfs_remove_group(&dev->kobj, &it87_group);
c145d5c6 2055 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2056 if (sio_data->skip_in & (1 << i))
2057 continue;
2058 sysfs_remove_group(&dev->kobj, &it87_group_in[i]);
2059 if (it87_attributes_in_beep[i])
2060 sysfs_remove_file(&dev->kobj,
2061 it87_attributes_in_beep[i]);
2062 }
4573acbc
GR		 2063 for (i = 0; i < 3; i++) {
2064 if (!(data->has_temp & (1 << i)))
2065 continue;
2066 sysfs_remove_group(&dev->kobj, &it87_group_temp[i]);
161d898a
GR		 2067 if (has_temp_offset(data))
2068 sysfs_remove_file(&dev->kobj,
2069 it87_attributes_temp_offset[i]);
4573acbc
GR		 2070 if (sio_data->beep_pin)
2071 sysfs_remove_file(&dev->kobj,
2072 it87_attributes_temp_beep[i]);
2073 }
723a0aa0
JD		 2074 for (i = 0; i < 5; i++) {
2075 if (!(data->has_fan & (1 << i)))
2076 continue;
e1169ba0 2077 sysfs_remove_group(&dev->kobj, &it87_group_fan[i]);
d9b327c3
JD		 2078 if (sio_data->beep_pin)
2079 sysfs_remove_file(&dev->kobj,
2080 it87_attributes_fan_beep[i]);
e1169ba0
GR		 2081 if (i < 3 && !has_16bit_fans(data))
2082 sysfs_remove_file(&dev->kobj,
2083 it87_attributes_fan_div[i]);
723a0aa0
JD		 2084 }
2085 for (i = 0; i < 3; i++) {
2086 if (sio_data->skip_pwm & (1 << 0))
2087 continue;
2088 sysfs_remove_group(&dev->kobj, &it87_group_pwm[i]);
4f3f51bc
JD		 2089 if (has_old_autopwm(data))
2090 sysfs_remove_group(&dev->kobj,
2091 &it87_group_autopwm[i]);
723a0aa0 2092 }
6a8d7acf
JD		 2093 if (!sio_data->skip_vid)
2094 sysfs_remove_group(&dev->kobj, &it87_group_vid);
738e5e05 2095 sysfs_remove_group(&dev->kobj, &it87_group_label);
723a0aa0
JD		 2096}
2097
6c931ae1 2098static int it87_probe(struct platform_device *pdev)
1da177e4 2099{
1da177e4 2100 struct it87_data *data;
b74f3fdd 2101 struct resource *res;
2102 struct device *dev = &pdev->dev;
a8b3a3a5 2103 struct it87_sio_data *sio_data = dev_get_platdata(dev);
723a0aa0 2104 int err = 0, i;
1da177e4 2105 int enable_pwm_interface;
d9b327c3 2106 int fan_beep_need_rw;
b74f3fdd 2107
2108 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
62a1d05f
GR		 2109 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2110 DRVNAME)) {
b74f3fdd 2111 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2112 (unsigned long)res->start,
87b4b663 2113 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
62a1d05f 2114 return -EBUSY;
8e9afcbb 2115 }
1da177e4 2116
62a1d05f
GR		 2117 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2118 if (!data)
2119 return -ENOMEM;
1da177e4 2120
b74f3fdd 2121 data->addr = res->start;
2122 data->type = sio_data->type;
483db43e 2123 data->features = it87_devices[sio_data->type].features;
5d8d2f2b 2124 data->peci_mask = it87_devices[sio_data->type].peci_mask;
19529784 2125 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
483db43e
GR		 2126 data->name = it87_devices[sio_data->type].name;
2127 /*
2128 * IT8705F Datasheet 0.4.1, 3h == Version G.
2129 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2130 * These are the first revisions with 16-bit tachometer support.
2131 */
2132 switch (data->type) {
2133 case it87:
2134 if (sio_data->revision >= 0x03) {
2135 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca 2136 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
483db43e
GR		 2137 }
2138 break;
2139 case it8712:
2140 if (sio_data->revision >= 0x08) {
2141 data->features &= ~FEAT_OLD_AUTOPWM;
9faf28ca
GR		 2142 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2143 FEAT_FIVE_FANS;
483db43e
GR		 2144 }
2145 break;
2146 default:
2147 break;
2148 }
1da177e4
LT		 2149
2150 /* Now, we do the remaining detection. */
b74f3fdd 2151 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80)
62a1d05f
GR		 2152 || it87_read_value(data, IT87_REG_CHIPID) != 0x90)
2153 return -ENODEV;
1da177e4 2154
b74f3fdd 2155 platform_set_drvdata(pdev, data);
1da177e4 2156
9a61bf63 2157 mutex_init(&data->update_lock);
1da177e4 2158
1da177e4 2159 /* Check PWM configuration */
b74f3fdd 2160 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2161
44c1bcd4 2162 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2163 if (has_12mv_adc(data)) {
44c1bcd4
JD		 2164 if (sio_data->internal & (1 << 0))
2165 data->in_scaled |= (1 << 3); /* in3 is AVCC */
2166 if (sio_data->internal & (1 << 1))
2167 data->in_scaled |= (1 << 7); /* in7 is VSB */
2168 if (sio_data->internal & (1 << 2))
2169 data->in_scaled |= (1 << 8); /* in8 is Vbat */
c145d5c6
RM		 2170 if (sio_data->internal & (1 << 3))
2171 data->in_scaled |= (1 << 9); /* in9 is AVCC */
7bc32d29
GR		 2172 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2173 sio_data->type == it8783) {
0531d98b
GR		 2174 if (sio_data->internal & (1 << 0))
2175 data->in_scaled |= (1 << 3); /* in3 is VCC5V */
2176 if (sio_data->internal & (1 << 1))
2177 data->in_scaled |= (1 << 7); /* in7 is VCCH5V */
44c1bcd4
JD		 2178 }
2179
4573acbc
GR		 2180 data->has_temp = 0x07;
2181 if (sio_data->skip_temp & (1 << 2)) {
2182 if (sio_data->type == it8782
2183 && !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
2184 data->has_temp &= ~(1 << 2);
2185 }
2186
1da177e4 2187 /* Initialize the IT87 chip */
b74f3fdd 2188 it87_init_device(pdev);
1da177e4
LT		 2189
2190 /* Register sysfs hooks */
5f2dc798
JD		 2191 err = sysfs_create_group(&dev->kobj, &it87_group);
2192 if (err)
62a1d05f 2193 return err;
17d648bf 2194
c145d5c6 2195 for (i = 0; i < 10; i++) {
9172b5d1
GR		 2196 if (sio_data->skip_in & (1 << i))
2197 continue;
2198 err = sysfs_create_group(&dev->kobj, &it87_group_in[i]);
2199 if (err)
62a1d05f 2200 goto error;
9172b5d1
GR		 2201 if (sio_data->beep_pin && it87_attributes_in_beep[i]) {
2202 err = sysfs_create_file(&dev->kobj,
2203 it87_attributes_in_beep[i]);
2204 if (err)
62a1d05f 2205 goto error;
9172b5d1
GR		 2206 }
2207 }
2208
4573acbc
GR		 2209 for (i = 0; i < 3; i++) {
2210 if (!(data->has_temp & (1 << i)))
2211 continue;
2212 err = sysfs_create_group(&dev->kobj, &it87_group_temp[i]);
d9b327c3 2213 if (err)
62a1d05f 2214 goto error;
161d898a
GR		 2215 if (has_temp_offset(data)) {
2216 err = sysfs_create_file(&dev->kobj,
2217 it87_attributes_temp_offset[i]);
2218 if (err)
2219 goto error;
2220 }
4573acbc
GR		 2221 if (sio_data->beep_pin) {
2222 err = sysfs_create_file(&dev->kobj,
2223 it87_attributes_temp_beep[i]);
2224 if (err)
2225 goto error;
2226 }
d9b327c3
JD		 2227 }
2228
9060f8bd 2229 /* Do not create fan files for disabled fans */
d9b327c3 2230 fan_beep_need_rw = 1;
723a0aa0
JD		 2231 for (i = 0; i < 5; i++) {
2232 if (!(data->has_fan & (1 << i)))
2233 continue;
e1169ba0 2234 err = sysfs_create_group(&dev->kobj, &it87_group_fan[i]);
723a0aa0 2235 if (err)
62a1d05f 2236 goto error;
d9b327c3 2237
e1169ba0
GR		 2238 if (i < 3 && !has_16bit_fans(data)) {
2239 err = sysfs_create_file(&dev->kobj,
2240 it87_attributes_fan_div[i]);
2241 if (err)
2242 goto error;
2243 }
2244
d9b327c3
JD		 2245 if (sio_data->beep_pin) {
2246 err = sysfs_create_file(&dev->kobj,
2247 it87_attributes_fan_beep[i]);
2248 if (err)
62a1d05f 2249 goto error;
d9b327c3
JD		 2250 if (!fan_beep_need_rw)
2251 continue;
2252
4a0d71cf
GR		 2253 /*
2254 * As we have a single beep enable bit for all fans,
d9b327c3 2255 * only the first enabled fan has a writable attribute
4a0d71cf
GR		 2256 * for it.
2257 */
d9b327c3
JD		 2258 if (sysfs_chmod_file(&dev->kobj,
2259 it87_attributes_fan_beep[i],
2260 S_IRUGO | S_IWUSR))
2261 dev_dbg(dev, "chmod +w fan%d_beep failed\n",
2262 i + 1);
2263 fan_beep_need_rw = 0;
2264 }
17d648bf
JD		 2265 }
2266
1da177e4 2267 if (enable_pwm_interface) {
723a0aa0
JD		 2268 for (i = 0; i < 3; i++) {
2269 if (sio_data->skip_pwm & (1 << i))
2270 continue;
2271 err = sysfs_create_group(&dev->kobj,
2272 &it87_group_pwm[i]);
2273 if (err)
62a1d05f 2274 goto error;
4f3f51bc
JD		 2275
2276 if (!has_old_autopwm(data))
2277 continue;
2278 err = sysfs_create_group(&dev->kobj,
2279 &it87_group_autopwm[i]);
2280 if (err)
62a1d05f 2281 goto error;
98dd22c3 2282 }
1da177e4
LT		 2283 }
2284
895ff267 2285 if (!sio_data->skip_vid) {
303760b4 2286 data->vrm = vid_which_vrm();
87673dd7 2287 /* VID reading from Super-I/O config space if available */
b74f3fdd 2288 data->vid = sio_data->vid_value;
6a8d7acf
JD		 2289 err = sysfs_create_group(&dev->kobj, &it87_group_vid);
2290 if (err)
62a1d05f 2291 goto error;
87808be4
JD		 2292 }
2293
738e5e05 2294 /* Export labels for internal sensors */
c145d5c6 2295 for (i = 0; i < 4; i++) {
738e5e05
JD		 2296 if (!(sio_data->internal & (1 << i)))
2297 continue;
2298 err = sysfs_create_file(&dev->kobj,
2299 it87_attributes_label[i]);
2300 if (err)
62a1d05f 2301 goto error;
738e5e05
JD		 2302 }
2303
1beeffe4
TJ		 2304 data->hwmon_dev = hwmon_device_register(dev);
2305 if (IS_ERR(data->hwmon_dev)) {
2306 err = PTR_ERR(data->hwmon_dev);
62a1d05f 2307 goto error;
1da177e4
LT		 2308 }
2309
2310 return 0;
2311
62a1d05f 2312error:
723a0aa0 2313 it87_remove_files(dev);
1da177e4
LT		 2314 return err;
2315}
2316
281dfd0b 2317static int it87_remove(struct platform_device *pdev)
1da177e4 2318{
b74f3fdd 2319 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2320
1beeffe4 2321 hwmon_device_unregister(data->hwmon_dev);
723a0aa0 2322 it87_remove_files(&pdev->dev);
943b0830 2323
1da177e4
LT		 2324 return 0;
2325}
2326
4a0d71cf
GR		 2327/*
2328 * Must be called with data->update_lock held, except during initialization.
2329 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2330 * would slow down the IT87 access and should not be necessary.
2331 */
b74f3fdd 2332static int it87_read_value(struct it87_data *data, u8 reg)
1da177e4 2333{
b74f3fdd 2334 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2335 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2336}
2337
4a0d71cf
GR		 2338/*
2339 * Must be called with data->update_lock held, except during initialization.
2340 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
2341 * would slow down the IT87 access and should not be necessary.
2342 */
b74f3fdd 2343static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
1da177e4 2344{
b74f3fdd 2345 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
2346 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1da177e4
LT		 2347}
2348
2349/* Return 1 if and only if the PWM interface is safe to use */
6c931ae1 2350static int it87_check_pwm(struct device *dev)
1da177e4 2351{
b74f3fdd 2352 struct it87_data *data = dev_get_drvdata(dev);
4a0d71cf
GR		 2353 /*
2354 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
1da177e4 2355 * and polarity set to active low is sign that this is the case so we
4a0d71cf
GR		 2356 * disable pwm control to protect the user.
2357 */
b74f3fdd 2358 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1da177e4
LT		 2359 if ((tmp & 0x87) == 0) {
2360 if (fix_pwm_polarity) {
4a0d71cf
GR		 2361 /*
2362 * The user asks us to attempt a chip reconfiguration.
1da177e4 2363 * This means switching to active high polarity and
4a0d71cf
GR		 2364 * inverting all fan speed values.
2365 */
1da177e4
LT		 2366 int i;
2367 u8 pwm[3];
2368
2369 for (i = 0; i < 3; i++)
b74f3fdd 2370 pwm[i] = it87_read_value(data,
1da177e4
LT		 2371 IT87_REG_PWM(i));
2372
4a0d71cf
GR		 2373 /*
2374 * If any fan is in automatic pwm mode, the polarity
1da177e4
LT		 2375 * might be correct, as suspicious as it seems, so we
2376 * better don't change anything (but still disable the
4a0d71cf
GR		 2377 * PWM interface).
2378 */
1da177e4 2379 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
1d9bcf6a
GR		 2380 dev_info(dev,
2381 "Reconfiguring PWM to active high polarity\n");
b74f3fdd 2382 it87_write_value(data, IT87_REG_FAN_CTL,
1da177e4
LT		 2383 tmp | 0x87);
2384 for (i = 0; i < 3; i++)
b74f3fdd 2385 it87_write_value(data,
1da177e4
LT		 2386 IT87_REG_PWM(i),
2387 0x7f & ~pwm[i]);
2388 return 1;
2389 }
2390
1d9bcf6a
GR		 2391 dev_info(dev,
2392 "PWM configuration is too broken to be fixed\n");
1da177e4
LT		 2393 }
2394
1d9bcf6a
GR		 2395 dev_info(dev,
2396 "Detected broken BIOS defaults, disabling PWM interface\n");
1da177e4
LT		 2397 return 0;
2398 } else if (fix_pwm_polarity) {
1d9bcf6a
GR		 2399 dev_info(dev,
2400 "PWM configuration looks sane, won't touch\n");
1da177e4
LT		 2401 }
2402
2403 return 1;
2404}
2405
2406/* Called when we have found a new IT87. */
6c931ae1 2407static void it87_init_device(struct platform_device *pdev)
1da177e4 2408{
a8b3a3a5 2409 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
b74f3fdd 2410 struct it87_data *data = platform_get_drvdata(pdev);
1da177e4 2411 int tmp, i;
591ec650 2412 u8 mask;
1da177e4 2413
4a0d71cf
GR		 2414 /*
2415 * For each PWM channel:
b99883dc
JD		 2416 * - If it is in automatic mode, setting to manual mode should set
2417 * the fan to full speed by default.
2418 * - If it is in manual mode, we need a mapping to temperature
2419 * channels to use when later setting to automatic mode later.
2420 * Use a 1:1 mapping by default (we are clueless.)
2421 * In both cases, the value can (and should) be changed by the user
6229cdb2
JD		 2422 * prior to switching to a different mode.
2423 * Note that this is no longer needed for the IT8721F and later, as
2424 * these have separate registers for the temperature mapping and the
4a0d71cf
GR		 2425 * manual duty cycle.
2426 */
1da177e4 2427 for (i = 0; i < 3; i++) {
b99883dc
JD		 2428 data->pwm_temp_map[i] = i;
2429 data->pwm_duty[i] = 0x7f; /* Full speed */
4f3f51bc 2430 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
1da177e4
LT		 2431 }
2432
4a0d71cf
GR		 2433 /*
2434 * Some chips seem to have default value 0xff for all limit
c5df9b7a
JD		 2435 * registers. For low voltage limits it makes no sense and triggers
2436 * alarms, so change to 0 instead. For high temperature limits, it
2437 * means -1 degree C, which surprisingly doesn't trigger an alarm,
4a0d71cf
GR		 2438 * but is still confusing, so change to 127 degrees C.
2439 */
c5df9b7a 2440 for (i = 0; i < 8; i++) {
b74f3fdd 2441 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
c5df9b7a 2442 if (tmp == 0xff)
b74f3fdd 2443 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
c5df9b7a
JD		 2444 }
2445 for (i = 0; i < 3; i++) {
b74f3fdd 2446 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c5df9b7a 2447 if (tmp == 0xff)
b74f3fdd 2448 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
c5df9b7a
JD		 2449 }
2450
4a0d71cf
GR		 2451 /*
2452 * Temperature channels are not forcibly enabled, as they can be
a00afb97
JD		 2453 * set to two different sensor types and we can't guess which one
2454 * is correct for a given system. These channels can be enabled at
4a0d71cf
GR		 2455 * run-time through the temp{1-3}_type sysfs accessors if needed.
2456 */
1da177e4
LT		 2457
2458 /* Check if voltage monitors are reset manually or by some reason */
b74f3fdd 2459 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
1da177e4
LT		 2460 if ((tmp & 0xff) == 0) {
2461 /* Enable all voltage monitors */
b74f3fdd 2462 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
1da177e4
LT		 2463 }
2464
2465 /* Check if tachometers are reset manually or by some reason */
591ec650 2466 mask = 0x70 & ~(sio_data->skip_fan << 4);
b74f3fdd 2467 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
591ec650 2468 if ((data->fan_main_ctrl & mask) == 0) {
1da177e4 2469 /* Enable all fan tachometers */
591ec650 2470 data->fan_main_ctrl |= mask;
5f2dc798
JD		 2471 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2472 data->fan_main_ctrl);
1da177e4 2473 }
9060f8bd 2474 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
1da177e4 2475
9faf28ca
GR		 2476 /* Set tachometers to 16-bit mode if needed */
2477 if (has_fan16_config(data)) {
b74f3fdd 2478 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
9060f8bd 2479 if (~tmp & 0x07 & data->has_fan) {
b74f3fdd 2480 dev_dbg(&pdev->dev,
17d648bf 2481 "Setting fan1-3 to 16-bit mode\n");
b74f3fdd 2482 it87_write_value(data, IT87_REG_FAN_16BIT,
17d648bf
JD		 2483 tmp | 0x07);
2484 }
9faf28ca
GR		 2485 }
2486
2487 /* Check for additional fans */
2488 if (has_five_fans(data)) {
2489 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2490 if (tmp & (1 << 4))
2491 data->has_fan |= (1 << 3); /* fan4 enabled */
2492 if (tmp & (1 << 5))
2493 data->has_fan |= (1 << 4); /* fan5 enabled */
17d648bf
JD		 2494 }
2495
591ec650
JD		 2496 /* Fan input pins may be used for alternative functions */
2497 data->has_fan &= ~sio_data->skip_fan;
2498
1da177e4 2499 /* Start monitoring */
b74f3fdd 2500 it87_write_value(data, IT87_REG_CONFIG,
41002f8d 2501 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
1da177e4
LT		 2502 | (update_vbat ? 0x41 : 0x01));
2503}
2504
b99883dc
JD		 2505static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
2506{
2507 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr));
16b5dda2 2508 if (has_newer_autopwm(data)) {
b99883dc 2509 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
6229cdb2
JD		 2510 data->pwm_duty[nr] = it87_read_value(data,
2511 IT87_REG_PWM_DUTY(nr));
2512 } else {
2513 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
2514 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
2515 else /* Manual mode */
2516 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
2517 }
4f3f51bc
JD		 2518
2519 if (has_old_autopwm(data)) {
2520 int i;
2521
2522 for (i = 0; i < 5 ; i++)
2523 data->auto_temp[nr][i] = it87_read_value(data,
2524 IT87_REG_AUTO_TEMP(nr, i));
2525 for (i = 0; i < 3 ; i++)
2526 data->auto_pwm[nr][i] = it87_read_value(data,
2527 IT87_REG_AUTO_PWM(nr, i));
2528 }
b99883dc
JD		 2529}
2530
1da177e4
LT		 2531static struct it87_data *it87_update_device(struct device *dev)
2532{
b74f3fdd 2533 struct it87_data *data = dev_get_drvdata(dev);
1da177e4
LT		 2534 int i;
2535
9a61bf63 2536 mutex_lock(&data->update_lock);
1da177e4
LT		 2537
2538 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
2539 || !data->valid) {
1da177e4 2540 if (update_vbat) {
4a0d71cf
GR		 2541 /*
2542 * Cleared after each update, so reenable. Value
2543 * returned by this read will be previous value
2544 */
b74f3fdd 2545 it87_write_value(data, IT87_REG_CONFIG,
5f2dc798 2546 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1da177e4
LT		 2547 }
2548 for (i = 0; i <= 7; i++) {
929c6a56 2549 data->in[i][0] =
5f2dc798 2550 it87_read_value(data, IT87_REG_VIN(i));
929c6a56 2551 data->in[i][1] =
5f2dc798 2552 it87_read_value(data, IT87_REG_VIN_MIN(i));
929c6a56 2553 data->in[i][2] =
5f2dc798 2554 it87_read_value(data, IT87_REG_VIN_MAX(i));
1da177e4 2555 }
3543a53f 2556 /* in8 (battery) has no limit registers */
929c6a56 2557 data->in[8][0] = it87_read_value(data, IT87_REG_VIN(8));
c145d5c6
RM		 2558 if (data->type == it8603)
2559 data->in[9][0] = it87_read_value(data, 0x2f);
1da177e4 2560
c7f1f716 2561 for (i = 0; i < 5; i++) {
9060f8bd
JD		 2562 /* Skip disabled fans */
2563 if (!(data->has_fan & (1 << i)))
2564 continue;
2565
e1169ba0 2566 data->fan[i][1] =
5f2dc798 2567 it87_read_value(data, IT87_REG_FAN_MIN[i]);
e1169ba0 2568 data->fan[i][0] = it87_read_value(data,
c7f1f716 2569 IT87_REG_FAN[i]);
17d648bf 2570 /* Add high byte if in 16-bit mode */
0475169c 2571 if (has_16bit_fans(data)) {
e1169ba0 2572 data->fan[i][0] |= it87_read_value(data,
c7f1f716 2573 IT87_REG_FANX[i]) << 8;
e1169ba0 2574 data->fan[i][1] |= it87_read_value(data,
c7f1f716 2575 IT87_REG_FANX_MIN[i]) << 8;
17d648bf 2576 }
1da177e4
LT		 2577 }
2578 for (i = 0; i < 3; i++) {
4573acbc
GR		 2579 if (!(data->has_temp & (1 << i)))
2580 continue;
60ca385a 2581 data->temp[i][0] =
5f2dc798 2582 it87_read_value(data, IT87_REG_TEMP(i));
60ca385a 2583 data->temp[i][1] =
5f2dc798 2584 it87_read_value(data, IT87_REG_TEMP_LOW(i));
60ca385a
GR		 2585 data->temp[i][2] =
2586 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
161d898a
GR		 2587 if (has_temp_offset(data))
2588 data->temp[i][3] =
2589 it87_read_value(data,
2590 IT87_REG_TEMP_OFFSET[i]);
1da177e4
LT		 2591 }
2592
17d648bf 2593 /* Newer chips don't have clock dividers */
0475169c 2594 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
b74f3fdd 2595 i = it87_read_value(data, IT87_REG_FAN_DIV);
17d648bf
JD		 2596 data->fan_div[0] = i & 0x07;
2597 data->fan_div[1] = (i >> 3) & 0x07;
2598 data->fan_div[2] = (i & 0x40) ? 3 : 1;
2599 }
1da177e4
LT		 2600
2601 data->alarms =
b74f3fdd 2602 it87_read_value(data, IT87_REG_ALARM1) |
2603 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
2604 (it87_read_value(data, IT87_REG_ALARM3) << 16);
d9b327c3 2605 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
b99883dc 2606
b74f3fdd 2607 data->fan_main_ctrl = it87_read_value(data,
2608 IT87_REG_FAN_MAIN_CTRL);
2609 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
b99883dc
JD		 2610 for (i = 0; i < 3; i++)
2611 it87_update_pwm_ctrl(data, i);
b74f3fdd 2612
2613 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
19529784 2614 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
4a0d71cf
GR		 2615 /*
2616 * The IT8705F does not have VID capability.
2617 * The IT8718F and later don't use IT87_REG_VID for the
2618 * same purpose.
2619 */
17d648bf 2620 if (data->type == it8712 || data->type == it8716) {
b74f3fdd 2621 data->vid = it87_read_value(data, IT87_REG_VID);
4a0d71cf
GR		 2622 /*
2623 * The older IT8712F revisions had only 5 VID pins,
2624 * but we assume it is always safe to read 6 bits.
2625 */
17d648bf 2626 data->vid &= 0x3f;
1da177e4
LT		 2627 }
2628 data->last_updated = jiffies;
2629 data->valid = 1;
2630 }
2631
9a61bf63 2632 mutex_unlock(&data->update_lock);
1da177e4
LT		 2633
2634 return data;
2635}
2636
b74f3fdd 2637static int __init it87_device_add(unsigned short address,
2638 const struct it87_sio_data *sio_data)
2639{
2640 struct resource res = {
87b4b663
BH		 2641 .start = address + IT87_EC_OFFSET,
2642 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2643 .name = DRVNAME,
2644 .flags = IORESOURCE_IO,
2645 };
2646 int err;
2647
b9acb64a
JD		 2648 err = acpi_check_resource_conflict(&res);
2649 if (err)
2650 goto exit;
2651
b74f3fdd 2652 pdev = platform_device_alloc(DRVNAME, address);
2653 if (!pdev) {
2654 err = -ENOMEM;
a8ca1037 2655 pr_err("Device allocation failed\n");
b74f3fdd 2656 goto exit;
2657 }
2658
2659 err = platform_device_add_resources(pdev, &res, 1);
2660 if (err) {
a8ca1037 2661 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2662 goto exit_device_put;
2663 }
2664
2665 err = platform_device_add_data(pdev, sio_data,
2666 sizeof(struct it87_sio_data));
2667 if (err) {
a8ca1037 2668 pr_err("Platform data allocation failed\n");
b74f3fdd 2669 goto exit_device_put;
2670 }
2671
2672 err = platform_device_add(pdev);
2673 if (err) {
a8ca1037 2674 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2675 goto exit_device_put;
2676 }
2677
2678 return 0;
2679
2680exit_device_put:
2681 platform_device_put(pdev);
2682exit:
2683 return err;
2684}
2685
1da177e4
LT		 2686static int __init sm_it87_init(void)
2687{
b74f3fdd 2688 int err;
5f2dc798 2689 unsigned short isa_address = 0;
b74f3fdd 2690 struct it87_sio_data sio_data;
2691
98dd22c3 2692 memset(&sio_data, 0, sizeof(struct it87_sio_data));
b74f3fdd 2693 err = it87_find(&isa_address, &sio_data);
2694 if (err)
2695 return err;
2696 err = platform_driver_register(&it87_driver);
2697 if (err)
2698 return err;
fde09509 2699
b74f3fdd 2700 err = it87_device_add(isa_address, &sio_data);
5f2dc798 2701 if (err) {
b74f3fdd 2702 platform_driver_unregister(&it87_driver);
2703 return err;
2704 }
2705
2706 return 0;
1da177e4
LT		 2707}
2708
2709static void __exit sm_it87_exit(void)
2710{
b74f3fdd 2711 platform_device_unregister(pdev);
2712 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2713}
2714
2715
7c81c60f 2716MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2717MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2718module_param(update_vbat, bool, 0);
2719MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2720module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2721MODULE_PARM_DESC(fix_pwm_polarity,
2722 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2723MODULE_LICENSE("GPL");
2724
2725module_init(sm_it87_init);
2726module_exit(sm_it87_exit);
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