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hwmon: (it87) Enhance validation for fan4 and fan5
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / it87.c
CommitLineData
1da177e4 1/*
5f2dc798
JD		 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
3 * monitoring.
4 *
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
8 * Fan Controller)
9 *
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
12 *
c145d5c6 13 * Supports: IT8603E Super I/O chip w/LPC interface
3ba9d977 14 * IT8620E Super I/O chip w/LPC interface
574e9bd8 15 * IT8623E Super I/O chip w/LPC interface
c145d5c6 16 * IT8705F Super I/O chip w/LPC interface
5f2dc798
JD		 17 * IT8712F Super I/O chip w/LPC interface
18 * IT8716F Super I/O chip w/LPC interface
19 * IT8718F Super I/O chip w/LPC interface
20 * IT8720F Super I/O chip w/LPC interface
44c1bcd4 21 * IT8721F Super I/O chip w/LPC interface
5f2dc798 22 * IT8726F Super I/O chip w/LPC interface
16b5dda2 23 * IT8728F Super I/O chip w/LPC interface
ead80803 24 * IT8732F Super I/O chip w/LPC interface
44c1bcd4 25 * IT8758E Super I/O chip w/LPC interface
b0636707
GR		 26 * IT8771E Super I/O chip w/LPC interface
27 * IT8772E Super I/O chip w/LPC interface
7bc32d29 28 * IT8781F Super I/O chip w/LPC interface
0531d98b
GR		 29 * IT8782F Super I/O chip w/LPC interface
30 * IT8783E/F Super I/O chip w/LPC interface
a0c1424a 31 * IT8786E Super I/O chip w/LPC interface
4ee07157 32 * IT8790E Super I/O chip w/LPC interface
5f2dc798
JD		 33 * Sis950 A clone of the IT8705F
34 *
35 * Copyright (C) 2001 Chris Gauthron
7c81c60f 36 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
5f2dc798
JD		 37 *
38 * This program is free software; you can redistribute it and/or modify
39 * it under the terms of the GNU General Public License as published by
40 * the Free Software Foundation; either version 2 of the License, or
41 * (at your option) any later version.
42 *
43 * This program is distributed in the hope that it will be useful,
44 * but WITHOUT ANY WARRANTY; without even the implied warranty of
45 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
46 * GNU General Public License for more details.
5f2dc798 47 */
1da177e4 48
a8ca1037
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
48b2ae7f 51#include <linux/bitops.h>
1da177e4
LT		 52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
b74f3fdd 56#include <linux/platform_device.h>
943b0830 57#include <linux/hwmon.h>
303760b4
JD		 58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
943b0830 60#include <linux/err.h>
9a61bf63 61#include <linux/mutex.h>
87808be4 62#include <linux/sysfs.h>
98dd22c3
JD		 63#include <linux/string.h>
64#include <linux/dmi.h>
b9acb64a 65#include <linux/acpi.h>
6055fae8 66#include <linux/io.h>
1da177e4 67
b74f3fdd 68#define DRVNAME "it87"
1da177e4 69
ead80803
JM		 70enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
71 it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
72 it8620 };
1da177e4 73
67b671bc
JD		 74static unsigned short force_id;
75module_param(force_id, ushort, 0);
76MODULE_PARM_DESC(force_id, "Override the detected device ID");
77
e84bd953 78static struct platform_device *it87_pdev[2];
b74f3fdd 79
3c2e3512 80#define REG_2E 0x2e /* The register to read/write */
e84bd953 81#define REG_4E 0x4e /* Secondary register to read/write */
3c2e3512 82
1da177e4 83#define DEV 0x07 /* Register: Logical device select */
1da177e4 84#define PME 0x04 /* The device with the fan registers in it */
b4da93e4
JMS		 85
86/* The device with the IT8718F/IT8720F VID value in it */
87#define GPIO 0x07
88
1da177e4
LT		 89#define DEVID 0x20 /* Register: Device ID */
90#define DEVREV 0x22 /* Register: Device Revision */
91
3c2e3512 92static inline int superio_inb(int ioreg, int reg)
1da177e4 93{
3c2e3512
GR		 94 outb(reg, ioreg);
95 return inb(ioreg + 1);
1da177e4
LT		 96}
97
3c2e3512 98static inline void superio_outb(int ioreg, int reg, int val)
436cad2a 99{
3c2e3512
GR		 100 outb(reg, ioreg);
101 outb(val, ioreg + 1);
436cad2a
JD		 102}
103
3c2e3512 104static int superio_inw(int ioreg, int reg)
1da177e4
LT		 105{
106 int val;
c962024e 107
3c2e3512
GR		 108 outb(reg++, ioreg);
109 val = inb(ioreg + 1) << 8;
110 outb(reg, ioreg);
111 val |= inb(ioreg + 1);
1da177e4
LT		 112 return val;
113}
114
3c2e3512 115static inline void superio_select(int ioreg, int ldn)
1da177e4 116{
3c2e3512
GR		 117 outb(DEV, ioreg);
118 outb(ldn, ioreg + 1);
1da177e4
LT		 119}
120
3c2e3512 121static inline int superio_enter(int ioreg)
1da177e4 122{
5b0380c9 123 /*
3c2e3512 124 * Try to reserve ioreg and ioreg + 1 for exclusive access.
5b0380c9 125 */
3c2e3512 126 if (!request_muxed_region(ioreg, 2, DRVNAME))
5b0380c9
NG		 127 return -EBUSY;
128
3c2e3512
GR		 129 outb(0x87, ioreg);
130 outb(0x01, ioreg);
131 outb(0x55, ioreg);
e84bd953 132 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
5b0380c9 133 return 0;
1da177e4
LT		 134}
135
3c2e3512 136static inline void superio_exit(int ioreg)
1da177e4 137{
3c2e3512
GR		 138 outb(0x02, ioreg);
139 outb(0x02, ioreg + 1);
140 release_region(ioreg, 2);
1da177e4
LT		 141}
142
87673dd7 143/* Logical device 4 registers */
1da177e4
LT		 144#define IT8712F_DEVID 0x8712
145#define IT8705F_DEVID 0x8705
17d648bf 146#define IT8716F_DEVID 0x8716
87673dd7 147#define IT8718F_DEVID 0x8718
b4da93e4 148#define IT8720F_DEVID 0x8720
44c1bcd4 149#define IT8721F_DEVID 0x8721
08a8f6e9 150#define IT8726F_DEVID 0x8726
16b5dda2 151#define IT8728F_DEVID 0x8728
ead80803 152#define IT8732F_DEVID 0x8732
b0636707
GR		 153#define IT8771E_DEVID 0x8771
154#define IT8772E_DEVID 0x8772
7bc32d29 155#define IT8781F_DEVID 0x8781
0531d98b
GR		 156#define IT8782F_DEVID 0x8782
157#define IT8783E_DEVID 0x8783
a0c1424a 158#define IT8786E_DEVID 0x8786
4ee07157 159#define IT8790E_DEVID 0x8790
7183ae8c 160#define IT8603E_DEVID 0x8603
3ba9d977 161#define IT8620E_DEVID 0x8620
574e9bd8 162#define IT8623E_DEVID 0x8623
1da177e4
LT		 163#define IT87_ACT_REG 0x30
164#define IT87_BASE_REG 0x60
165
87673dd7 166/* Logical device 7 registers (IT8712F and later) */
0531d98b 167#define IT87_SIO_GPIO1_REG 0x25
3ba9d977 168#define IT87_SIO_GPIO2_REG 0x26
895ff267 169#define IT87_SIO_GPIO3_REG 0x27
36c4d98a 170#define IT87_SIO_GPIO4_REG 0x28
591ec650 171#define IT87_SIO_GPIO5_REG 0x29
0531d98b 172#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
87673dd7 173#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
0531d98b 174#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
87673dd7 175#define IT87_SIO_VID_REG 0xfc /* VID value */
d9b327c3 176#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
87673dd7 177
1da177e4 178/* Update battery voltage after every reading if true */
90ab5ee9 179static bool update_vbat;
1da177e4
LT		 180
181/* Not all BIOSes properly configure the PWM registers */
90ab5ee9 182static bool fix_pwm_polarity;
1da177e4 183
1da177e4
LT		 184/* Many IT87 constants specified below */
185
186/* Length of ISA address segment */
187#define IT87_EXTENT 8
188
87b4b663
BH		 189/* Length of ISA address segment for Environmental Controller */
190#define IT87_EC_EXTENT 2
191
192/* Offset of EC registers from ISA base address */
193#define IT87_EC_OFFSET 5
194
195/* Where are the ISA address/data registers relative to the EC base address */
196#define IT87_ADDR_REG_OFFSET 0
197#define IT87_DATA_REG_OFFSET 1
1da177e4
LT		 198
199/*----- The IT87 registers -----*/
200
201#define IT87_REG_CONFIG 0x00
202
203#define IT87_REG_ALARM1 0x01
204#define IT87_REG_ALARM2 0x02
205#define IT87_REG_ALARM3 0x03
206
4a0d71cf
GR		 207/*
208 * The IT8718F and IT8720F have the VID value in a different register, in
209 * Super-I/O configuration space.
210 */
1da177e4 211#define IT87_REG_VID 0x0a
4a0d71cf
GR		 212/*
213 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
214 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
215 * mode.
216 */
1da177e4 217#define IT87_REG_FAN_DIV 0x0b
17d648bf 218#define IT87_REG_FAN_16BIT 0x0c
1da177e4 219
f838aa26
GR		 220/*
221 * Monitors:
222 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
223 * - up to 6 temp (1 to 6)
224 * - up to 6 fan (1 to 6)
225 */
1da177e4 226
fa3f70d6
GR		 227static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
228static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
229static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
230static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
231static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
161d898a 232
1da177e4
LT		 233#define IT87_REG_FAN_MAIN_CTRL 0x13
234#define IT87_REG_FAN_CTL 0x14
36c4d98a
GR		 235static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
236static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
1da177e4 237
559313c4 238static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
f838aa26 239 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
1da177e4 240
559313c4 241#define IT87_REG_TEMP(nr) (0x29 + (nr))
73055405 242
1da177e4
LT		 243#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
244#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
245#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
246#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
247
1da177e4
LT		 248#define IT87_REG_VIN_ENABLE 0x50
249#define IT87_REG_TEMP_ENABLE 0x51
4573acbc 250#define IT87_REG_TEMP_EXTRA 0x55
d9b327c3 251#define IT87_REG_BEEP_ENABLE 0x5c
1da177e4
LT		 252
253#define IT87_REG_CHIPID 0x58
254
4f3f51bc
JD		 255#define IT87_REG_AUTO_TEMP(nr, i) (0x60 + (nr) * 8 + (i))
256#define IT87_REG_AUTO_PWM(nr, i) (0x65 + (nr) * 8 + (i))
257
cc18da79
GR		 258#define IT87_REG_TEMP456_ENABLE 0x77
259
2310048d
GR		 260#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
261#define NUM_VIN_LIMIT 8
262#define NUM_TEMP 6
263#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
264#define NUM_TEMP_LIMIT 3
265#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
266#define NUM_FAN_DIV 3
267#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
268#define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
269
483db43e
GR		 270struct it87_devices {
271 const char *name;
faf392fb 272 const char * const suffix;
cc18da79 273 u32 features;
19529784
GR		 274 u8 peci_mask;
275 u8 old_peci_mask;
483db43e
GR		 276};
277
48b2ae7f
GR		 278#define FEAT_12MV_ADC BIT(0)
279#define FEAT_NEWER_AUTOPWM BIT(1)
280#define FEAT_OLD_AUTOPWM BIT(2)
281#define FEAT_16BIT_FANS BIT(3)
282#define FEAT_TEMP_OFFSET BIT(4)
283#define FEAT_TEMP_PECI BIT(5)
284#define FEAT_TEMP_OLD_PECI BIT(6)
285#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
286#define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
287#define FEAT_VID BIT(9) /* Set if chip supports VID */
288#define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
289#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
290#define FEAT_10_9MV_ADC BIT(12)
291#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
292#define FEAT_SIX_PWM BIT(14) /* Chip supports 6 pwm chn */
293#define FEAT_PWM_FREQ2 BIT(15) /* Separate pwm freq 2 */
294#define FEAT_SIX_TEMP BIT(16) /* Up to 6 temp sensors */
483db43e
GR		 295
296static const struct it87_devices it87_devices[] = {
297 [it87] = {
298 .name = "it87",
faf392fb 299 .suffix = "F",
483db43e
GR		 300 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
301 },
302 [it8712] = {
303 .name = "it8712",
faf392fb 304 .suffix = "F",
32dd7c40
GR		 305 .features = FEAT_OLD_AUTOPWM | FEAT_VID,
306 /* may need to overwrite */
483db43e
GR		 307 },
308 [it8716] = {
309 .name = "it8716",
faf392fb 310 .suffix = "F",
32dd7c40 311 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf 312 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
483db43e
GR		 313 },
314 [it8718] = {
315 .name = "it8718",
faf392fb 316 .suffix = "F",
32dd7c40 317 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 318 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
319 | FEAT_PWM_FREQ2,
19529784 320 .old_peci_mask = 0x4,
483db43e
GR		 321 },
322 [it8720] = {
323 .name = "it8720",
faf392fb 324 .suffix = "F",
32dd7c40 325 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
60878bcf
GR		 326 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
327 | FEAT_PWM_FREQ2,
19529784 328 .old_peci_mask = 0x4,
483db43e
GR		 329 },
330 [it8721] = {
331 .name = "it8721",
faf392fb 332 .suffix = "F",
483db43e 333 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
9faf28ca 334 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
60878bcf
GR		 335 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
336 | FEAT_PWM_FREQ2,
5d8d2f2b 337 .peci_mask = 0x05,
19529784 338 .old_peci_mask = 0x02, /* Actually reports PCH */
483db43e
GR		 339 },
340 [it8728] = {
341 .name = "it8728",
faf392fb 342 .suffix = "F",
483db43e 343 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
7f5726c3 344 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
60878bcf 345 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
5d8d2f2b 346 .peci_mask = 0x07,
483db43e 347 },
ead80803
JM		 348 [it8732] = {
349 .name = "it8732",
350 .suffix = "F",
351 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
352 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
353 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
354 .peci_mask = 0x07,
355 .old_peci_mask = 0x02, /* Actually reports PCH */
356 },
b0636707
GR		 357 [it8771] = {
358 .name = "it8771",
faf392fb 359 .suffix = "E",
b0636707 360 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 361 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
362 | FEAT_PWM_FREQ2,
9faf28ca
GR		 363 /* PECI: guesswork */
364 /* 12mV ADC (OHM) */
365 /* 16 bit fans (OHM) */
366 /* three fans, always 16 bit (guesswork) */
b0636707
GR		 367 .peci_mask = 0x07,
368 },
369 [it8772] = {
370 .name = "it8772",
faf392fb 371 .suffix = "E",
b0636707 372 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 373 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
374 | FEAT_PWM_FREQ2,
9faf28ca
GR		 375 /* PECI (coreboot) */
376 /* 12mV ADC (HWSensors4, OHM) */
377 /* 16 bit fans (HWSensors4, OHM) */
378 /* three fans, always 16 bit (datasheet) */
b0636707
GR		 379 .peci_mask = 0x07,
380 },
7bc32d29
GR		 381 [it8781] = {
382 .name = "it8781",
faf392fb 383 .suffix = "F",
7bc32d29 384 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 385 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
7bc32d29
GR		 386 .old_peci_mask = 0x4,
387 },
483db43e
GR		 388 [it8782] = {
389 .name = "it8782",
faf392fb 390 .suffix = "F",
19529784 391 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 392 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 393 .old_peci_mask = 0x4,
483db43e
GR		 394 },
395 [it8783] = {
396 .name = "it8783",
faf392fb 397 .suffix = "E/F",
19529784 398 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
60878bcf 399 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
19529784 400 .old_peci_mask = 0x4,
483db43e 401 },
a0c1424a
TL		 402 [it8786] = {
403 .name = "it8786",
faf392fb 404 .suffix = "E",
a0c1424a 405 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 406 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
407 | FEAT_PWM_FREQ2,
a0c1424a
TL		 408 .peci_mask = 0x07,
409 },
4ee07157
GR		 410 [it8790] = {
411 .name = "it8790",
412 .suffix = "E",
413 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
60878bcf
GR		 414 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
415 | FEAT_PWM_FREQ2,
4ee07157
GR		 416 .peci_mask = 0x07,
417 },
c145d5c6
RM		 418 [it8603] = {
419 .name = "it8603",
faf392fb 420 .suffix = "E",
c145d5c6 421 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
73055405 422 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
60878bcf 423 | FEAT_AVCC3 | FEAT_PWM_FREQ2,
c145d5c6
RM		 424 .peci_mask = 0x07,
425 },
3ba9d977
GR		 426 [it8620] = {
427 .name = "it8620",
428 .suffix = "E",
429 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
fa3f70d6 430 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
cc18da79
GR		 431 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
432 | FEAT_SIX_TEMP,
3ba9d977
GR		 433 .peci_mask = 0x07,
434 },
483db43e
GR		 435};
436
437#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
438#define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
ead80803 439#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
483db43e
GR		 440#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
441#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
442#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
5d8d2f2b 443#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
48b2ae7f 444 ((data)->peci_mask & BIT(nr)))
19529784
GR		 445#define has_temp_old_peci(data, nr) \
446 (((data)->features & FEAT_TEMP_OLD_PECI) && \
48b2ae7f 447 ((data)->old_peci_mask & BIT(nr)))
9faf28ca 448#define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
fa3f70d6
GR		 449#define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
450 FEAT_SIX_FANS))
32dd7c40 451#define has_vid(data) ((data)->features & FEAT_VID)
7f5726c3 452#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
fa3f70d6 453#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
73055405 454#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
36c4d98a 455#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
60878bcf 456#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
cc18da79 457#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
1da177e4 458
b74f3fdd 459struct it87_sio_data {
460 enum chips type;
461 /* Values read from Super-I/O config space */
0475169c 462 u8 revision;
b74f3fdd 463 u8 vid_value;
d9b327c3 464 u8 beep_pin;
738e5e05 465 u8 internal; /* Internal sensors can be labeled */
591ec650 466 /* Features skipped based on config or DMI */
9172b5d1 467 u16 skip_in;
895ff267 468 u8 skip_vid;
591ec650 469 u8 skip_fan;
98dd22c3 470 u8 skip_pwm;
4573acbc 471 u8 skip_temp;
b74f3fdd 472};
473
4a0d71cf
GR		 474/*
475 * For each registered chip, we need to keep some data in memory.
476 * The structure is dynamically allocated.
477 */
1da177e4 478struct it87_data {
8638d0af 479 const struct attribute_group *groups[7];
1da177e4 480 enum chips type;
483db43e 481 u16 features;
19529784
GR		 482 u8 peci_mask;
483 u8 old_peci_mask;
1da177e4 484
b74f3fdd 485 unsigned short addr;
486 const char *name;
9a61bf63 487 struct mutex update_lock;
1da177e4
LT		 488 char valid; /* !=0 if following fields are valid */
489 unsigned long last_updated; /* In jiffies */
490
44c1bcd4 491 u16 in_scaled; /* Internal voltage sensors are scaled */
d3766848 492 u16 in_internal; /* Bitfield, internal sensors (for labels) */
52929715 493 u16 has_in; /* Bitfield, voltage sensors enabled */
2310048d 494 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
9060f8bd 495 u8 has_fan; /* Bitfield, fans enabled */
2310048d 496 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
4573acbc 497 u8 has_temp; /* Bitfield, temp sensors enabled */
2310048d 498 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
19529784
GR		 499 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
500 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
2310048d 501 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
d3766848 502 bool has_vid; /* True if VID supported */
1da177e4 503 u8 vid; /* Register encoding, combined */
a7be58a1 504 u8 vrm;
1da177e4 505 u32 alarms; /* Register encoding, combined */
52929715 506 bool has_beep; /* true if beep supported */
d9b327c3 507 u8 beeps; /* Register encoding */
1da177e4 508 u8 fan_main_ctrl; /* Register value */
f8d0c19a 509 u8 fan_ctl; /* Register value */
b99883dc 510
4a0d71cf
GR		 511 /*
512 * The following 3 arrays correspond to the same registers up to
6229cdb2
JD		 513 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
514 * 7, and we want to preserve settings on mode changes, so we have
515 * to track all values separately.
516 * Starting with the IT8721F, the manual PWM duty cycles are stored
517 * in separate registers (8-bit values), so the separate tracking
518 * is no longer needed, but it is still done to keep the driver
4a0d71cf
GR		 519 * simple.
520 */
5c391261 521 u8 has_pwm; /* Bitfield, pwm control enabled */
2310048d
GR		 522 u8 pwm_ctrl[NUM_PWM]; /* Register value */
523 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
524 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
4f3f51bc
JD		 525
526 /* Automatic fan speed control registers */
2310048d
GR		 527 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
528 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
1da177e4 529};
0df6454d 530
0531d98b 531static int adc_lsb(const struct it87_data *data, int nr)
44c1bcd4 532{
ead80803
JM		 533 int lsb;
534
535 if (has_12mv_adc(data))
536 lsb = 120;
537 else if (has_10_9mv_adc(data))
538 lsb = 109;
539 else
540 lsb = 160;
48b2ae7f 541 if (data->in_scaled & BIT(nr))
0531d98b
GR		 542 lsb <<= 1;
543 return lsb;
544}
44c1bcd4 545
0531d98b
GR		 546static u8 in_to_reg(const struct it87_data *data, int nr, long val)
547{
ead80803 548 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
2a844c14 549 return clamp_val(val, 0, 255);
44c1bcd4
JD		 550}
551
552static int in_from_reg(const struct it87_data *data, int nr, int val)
553{
ead80803 554 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
44c1bcd4 555}
0df6454d
JD		 556
557static inline u8 FAN_TO_REG(long rpm, int div)
558{
559 if (rpm == 0)
560 return 255;
2a844c14
GR		 561 rpm = clamp_val(rpm, 1, 1000000);
562 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
0df6454d
JD		 563}
564
565static inline u16 FAN16_TO_REG(long rpm)
566{
567 if (rpm == 0)
568 return 0xffff;
2a844c14 569 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
0df6454d
JD		 570}
571
572#define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
573 1350000 / ((val) * (div)))
574/* The divider is fixed to 2 in 16-bit mode */
575#define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
576 1350000 / ((val) * 2))
577
2a844c14
GR		 578#define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
579 ((val) + 500) / 1000), -128, 127))
0df6454d
JD		 580#define TEMP_FROM_REG(val) ((val) * 1000)
581
44c1bcd4
JD		 582static u8 pwm_to_reg(const struct it87_data *data, long val)
583{
16b5dda2 584 if (has_newer_autopwm(data))
44c1bcd4
JD		 585 return val;
586 else
587 return val >> 1;
588}
589
590static int pwm_from_reg(const struct it87_data *data, u8 reg)
591{
16b5dda2 592 if (has_newer_autopwm(data))
44c1bcd4
JD		 593 return reg;
594 else
595 return (reg & 0x7f) << 1;
596}
597
0df6454d
JD		 598static int DIV_TO_REG(int val)
599{
600 int answer = 0;
c962024e 601
0df6454d
JD		 602 while (answer < 7 && (val >>= 1))
603 answer++;
604 return answer;
605}
48b2ae7f
GR		 606
607#define DIV_FROM_REG(val) BIT(val)
0df6454d 608
f56c9c0a
GR		 609/*
610 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
611 * depending on the chip type, to calculate the actual PWM frequency.
612 *
613 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
614 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
615 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
616 * sometimes just one. It is unknown if this is a datasheet error or real,
617 * so this is ignored for now.
618 */
0df6454d 619static const unsigned int pwm_freq[8] = {
f56c9c0a
GR		 620 48000000,
621 24000000,
622 12000000,
623 8000000,
624 6000000,
625 3000000,
626 1500000,
627 750000,
0df6454d 628};
1da177e4 629
c1e7a4ca
GR		 630/*
631 * Must be called with data->update_lock held, except during initialization.
632 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
633 * would slow down the IT87 access and should not be necessary.
634 */
635static int it87_read_value(struct it87_data *data, u8 reg)
636{
637 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
638 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
639}
640
641/*
642 * Must be called with data->update_lock held, except during initialization.
643 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
644 * would slow down the IT87 access and should not be necessary.
645 */
646static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
647{
648 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
649 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
650}
651
652static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
653{
654 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
655 if (has_newer_autopwm(data)) {
656 data->pwm_temp_map[nr] = (data->pwm_ctrl[nr] & 0x03) +
657 nr < 3 ? 0 : 3;
658 data->pwm_duty[nr] = it87_read_value(data,
659 IT87_REG_PWM_DUTY[nr]);
660 } else {
661 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
662 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
663 else /* Manual mode */
664 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
665 }
1da177e4 666
c1e7a4ca
GR		 667 if (has_old_autopwm(data)) {
668 int i;
1da177e4 669
c1e7a4ca
GR		 670 for (i = 0; i < 5 ; i++)
671 data->auto_temp[nr][i] = it87_read_value(data,
672 IT87_REG_AUTO_TEMP(nr, i));
673 for (i = 0; i < 3 ; i++)
674 data->auto_pwm[nr][i] = it87_read_value(data,
675 IT87_REG_AUTO_PWM(nr, i));
676 }
677}
1da177e4 678
c1e7a4ca
GR		 679static struct it87_data *it87_update_device(struct device *dev)
680{
681 struct it87_data *data = dev_get_drvdata(dev);
682 int i;
683
684 mutex_lock(&data->update_lock);
685
c962024e
GR		 686 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
687 !data->valid) {
c1e7a4ca
GR		 688 if (update_vbat) {
689 /*
690 * Cleared after each update, so reenable. Value
691 * returned by this read will be previous value
692 */
693 it87_write_value(data, IT87_REG_CONFIG,
694 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
695 }
2310048d 696 for (i = 0; i < NUM_VIN; i++) {
48b2ae7f 697 if (!(data->has_in & BIT(i)))
559313c4
GR		 698 continue;
699
c1e7a4ca 700 data->in[i][0] =
559313c4
GR		 701 it87_read_value(data, IT87_REG_VIN[i]);
702
703 /* VBAT and AVCC don't have limit registers */
2310048d 704 if (i >= NUM_VIN_LIMIT)
559313c4
GR		 705 continue;
706
c1e7a4ca
GR		 707 data->in[i][1] =
708 it87_read_value(data, IT87_REG_VIN_MIN(i));
709 data->in[i][2] =
710 it87_read_value(data, IT87_REG_VIN_MAX(i));
711 }
c1e7a4ca 712
2310048d 713 for (i = 0; i < NUM_FAN; i++) {
c1e7a4ca 714 /* Skip disabled fans */
48b2ae7f 715 if (!(data->has_fan & BIT(i)))
c1e7a4ca
GR		 716 continue;
717
718 data->fan[i][1] =
719 it87_read_value(data, IT87_REG_FAN_MIN[i]);
720 data->fan[i][0] = it87_read_value(data,
721 IT87_REG_FAN[i]);
722 /* Add high byte if in 16-bit mode */
723 if (has_16bit_fans(data)) {
724 data->fan[i][0] |= it87_read_value(data,
725 IT87_REG_FANX[i]) << 8;
726 data->fan[i][1] |= it87_read_value(data,
727 IT87_REG_FANX_MIN[i]) << 8;
728 }
729 }
2310048d 730 for (i = 0; i < NUM_TEMP; i++) {
48b2ae7f 731 if (!(data->has_temp & BIT(i)))
c1e7a4ca
GR		 732 continue;
733 data->temp[i][0] =
734 it87_read_value(data, IT87_REG_TEMP(i));
cc18da79 735
2310048d
GR		 736 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
737 data->temp[i][3] =
738 it87_read_value(data,
739 IT87_REG_TEMP_OFFSET[i]);
740
741 if (i >= NUM_TEMP_LIMIT)
cc18da79
GR		 742 continue;
743
c1e7a4ca
GR		 744 data->temp[i][1] =
745 it87_read_value(data, IT87_REG_TEMP_LOW(i));
746 data->temp[i][2] =
747 it87_read_value(data, IT87_REG_TEMP_HIGH(i));
c1e7a4ca
GR		 748 }
749
750 /* Newer chips don't have clock dividers */
751 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
752 i = it87_read_value(data, IT87_REG_FAN_DIV);
753 data->fan_div[0] = i & 0x07;
754 data->fan_div[1] = (i >> 3) & 0x07;
755 data->fan_div[2] = (i & 0x40) ? 3 : 1;
756 }
757
758 data->alarms =
759 it87_read_value(data, IT87_REG_ALARM1) |
760 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
761 (it87_read_value(data, IT87_REG_ALARM3) << 16);
762 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
763
764 data->fan_main_ctrl = it87_read_value(data,
765 IT87_REG_FAN_MAIN_CTRL);
766 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
2310048d 767 for (i = 0; i < NUM_PWM; i++)
c1e7a4ca
GR		 768 it87_update_pwm_ctrl(data, i);
769
770 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
771 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
772 /*
773 * The IT8705F does not have VID capability.
774 * The IT8718F and later don't use IT87_REG_VID for the
775 * same purpose.
776 */
777 if (data->type == it8712 || data->type == it8716) {
778 data->vid = it87_read_value(data, IT87_REG_VID);
779 /*
780 * The older IT8712F revisions had only 5 VID pins,
781 * but we assume it is always safe to read 6 bits.
782 */
783 data->vid &= 0x3f;
784 }
785 data->last_updated = jiffies;
786 data->valid = 1;
787 }
788
789 mutex_unlock(&data->update_lock);
790
791 return data;
792}
fde09509 793
20ad93d4 794static ssize_t show_in(struct device *dev, struct device_attribute *attr,
929c6a56 795 char *buf)
1da177e4 796{
929c6a56 797 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
c962024e 798 struct it87_data *data = it87_update_device(dev);
929c6a56 799 int index = sattr->index;
c962024e 800 int nr = sattr->nr;
20ad93d4 801
929c6a56 802 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1da177e4
LT		 803}
804
929c6a56
GR		 805static ssize_t set_in(struct device *dev, struct device_attribute *attr,
806 const char *buf, size_t count)
1da177e4 807{
929c6a56 808 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
b74f3fdd 809 struct it87_data *data = dev_get_drvdata(dev);
c962024e
GR		 810 int index = sattr->index;
811 int nr = sattr->nr;
f5f64501
JD		 812 unsigned long val;
813
179c4fdb 814 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 815 return -EINVAL;
1da177e4 816
9a61bf63 817 mutex_lock(&data->update_lock);
929c6a56
GR		 818 data->in[nr][index] = in_to_reg(data, nr, val);
819 it87_write_value(data,
820 index == 1 ? IT87_REG_VIN_MIN(nr)
821 : IT87_REG_VIN_MAX(nr),
822 data->in[nr][index]);
9a61bf63 823 mutex_unlock(&data->update_lock);
1da177e4
LT		 824 return count;
825}
20ad93d4 826
929c6a56
GR		 827static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
828static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
829 0, 1);
830static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
831 0, 2);
f5f64501 832
929c6a56
GR		 833static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
834static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
835 1, 1);
836static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
837 1, 2);
1da177e4 838
929c6a56
GR		 839static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
840static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
841 2, 1);
842static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
843 2, 2);
1da177e4 844
929c6a56
GR		 845static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
846static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
847 3, 1);
848static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
849 3, 2);
850
851static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
852static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
853 4, 1);
854static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
855 4, 2);
856
857static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
858static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
859 5, 1);
860static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
861 5, 2);
862
863static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
864static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
865 6, 1);
866static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
867 6, 2);
868
869static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
870static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
871 7, 1);
872static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
873 7, 2);
874
875static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
c145d5c6 876static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
f838aa26
GR		 877static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
878static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
879static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1da177e4 880
cc18da79 881/* Up to 6 temperatures */
20ad93d4 882static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
60ca385a 883 char *buf)
1da177e4 884{
60ca385a
GR		 885 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
886 int nr = sattr->nr;
887 int index = sattr->index;
1da177e4 888 struct it87_data *data = it87_update_device(dev);
20ad93d4 889
60ca385a 890 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1da177e4 891}
20ad93d4 892
60ca385a
GR		 893static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
894 const char *buf, size_t count)
1da177e4 895{
60ca385a
GR		 896 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
897 int nr = sattr->nr;
898 int index = sattr->index;
b74f3fdd 899 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 900 long val;
161d898a 901 u8 reg, regval;
f5f64501 902
179c4fdb 903 if (kstrtol(buf, 10, &val) < 0)
f5f64501 904 return -EINVAL;
1da177e4 905
9a61bf63 906 mutex_lock(&data->update_lock);
161d898a
GR		 907
908 switch (index) {
909 default:
910 case 1:
911 reg = IT87_REG_TEMP_LOW(nr);
912 break;
913 case 2:
914 reg = IT87_REG_TEMP_HIGH(nr);
915 break;
916 case 3:
917 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
918 if (!(regval & 0x80)) {
919 regval |= 0x80;
920 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
921 }
922 data->valid = 0;
923 reg = IT87_REG_TEMP_OFFSET[nr];
924 break;
925 }
926
60ca385a 927 data->temp[nr][index] = TEMP_TO_REG(val);
161d898a 928 it87_write_value(data, reg, data->temp[nr][index]);
9a61bf63 929 mutex_unlock(&data->update_lock);
1da177e4
LT		 930 return count;
931}
1da177e4 932
60ca385a
GR		 933static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
934static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
935 0, 1);
936static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
937 0, 2);
161d898a
GR		 938static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
939 set_temp, 0, 3);
60ca385a
GR		 940static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
941static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
942 1, 1);
943static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
944 1, 2);
161d898a
GR		 945static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
946 set_temp, 1, 3);
60ca385a
GR		 947static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
948static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
949 2, 1);
950static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
951 2, 2);
161d898a
GR		 952static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
953 set_temp, 2, 3);
cc18da79
GR		 954static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
955static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
956static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1da177e4 957
2cece01f
GR		 958static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
959 char *buf)
1da177e4 960{
20ad93d4
JD		 961 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
962 int nr = sensor_attr->index;
1da177e4 963 struct it87_data *data = it87_update_device(dev);
4a0d71cf 964 u8 reg = data->sensor; /* In case value is updated while used */
19529784 965 u8 extra = data->extra;
5f2dc798 966
c962024e
GR		 967 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
968 (has_temp_old_peci(data, nr) && (extra & 0x80)))
5d8d2f2b 969 return sprintf(buf, "6\n"); /* Intel PECI */
1da177e4
LT		 970 if (reg & (1 << nr))
971 return sprintf(buf, "3\n"); /* thermal diode */
972 if (reg & (8 << nr))
4ed10779 973 return sprintf(buf, "4\n"); /* thermistor */
1da177e4
LT		 974 return sprintf(buf, "0\n"); /* disabled */
975}
2cece01f
GR		 976
977static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
978 const char *buf, size_t count)
1da177e4 979{
20ad93d4
JD		 980 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
981 int nr = sensor_attr->index;
982
b74f3fdd 983 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 984 long val;
19529784 985 u8 reg, extra;
f5f64501 986
179c4fdb 987 if (kstrtol(buf, 10, &val) < 0)
f5f64501 988 return -EINVAL;
1da177e4 989
8acf07c5
JD		 990 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
991 reg &= ~(1 << nr);
992 reg &= ~(8 << nr);
5d8d2f2b
GR		 993 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
994 reg &= 0x3f;
19529784
GR		 995 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
996 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
997 extra &= 0x7f;
4ed10779 998 if (val == 2) { /* backwards compatibility */
1d9bcf6a
GR		 999 dev_warn(dev,
1000 "Sensor type 2 is deprecated, please use 4 instead\n");
4ed10779
JD		 1001 val = 4;
1002 }
5d8d2f2b 1003 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1da177e4 1004 if (val == 3)
8acf07c5 1005 reg |= 1 << nr;
4ed10779 1006 else if (val == 4)
8acf07c5 1007 reg |= 8 << nr;
5d8d2f2b
GR		 1008 else if (has_temp_peci(data, nr) && val == 6)
1009 reg |= (nr + 1) << 6;
19529784
GR		 1010 else if (has_temp_old_peci(data, nr) && val == 6)
1011 extra |= 0x80;
8acf07c5 1012 else if (val != 0)
1da177e4 1013 return -EINVAL;
8acf07c5
JD		 1014
1015 mutex_lock(&data->update_lock);
1016 data->sensor = reg;
19529784 1017 data->extra = extra;
b74f3fdd 1018 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
19529784
GR		 1019 if (has_temp_old_peci(data, nr))
1020 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
2b3d1d87 1021 data->valid = 0; /* Force cache refresh */
9a61bf63 1022 mutex_unlock(&data->update_lock);
1da177e4
LT		 1023 return count;
1024}
1da177e4 1025
2cece01f
GR		 1026static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1027 set_temp_type, 0);
1028static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1029 set_temp_type, 1);
1030static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1031 set_temp_type, 2);
1da177e4 1032
f1bbe618 1033/* 6 Fans */
b99883dc
JD		 1034
1035static int pwm_mode(const struct it87_data *data, int nr)
1036{
f1bbe618
GR		 1037 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
1038 return 0; /* Full speed */
1039 if (data->pwm_ctrl[nr] & 0x80)
1040 return 2; /* Automatic mode */
1041 if ((data->type == it8603 || nr >= 3) &&
1042 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1043 return 0; /* Full speed */
1044
1045 return 1; /* Manual mode */
b99883dc
JD		 1046}
1047
20ad93d4 1048static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
e1169ba0 1049 char *buf)
1da177e4 1050{
e1169ba0
GR		 1051 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1052 int nr = sattr->nr;
1053 int index = sattr->index;
1054 int speed;
1da177e4 1055 struct it87_data *data = it87_update_device(dev);
20ad93d4 1056
e1169ba0
GR		 1057 speed = has_16bit_fans(data) ?
1058 FAN16_FROM_REG(data->fan[nr][index]) :
1059 FAN_FROM_REG(data->fan[nr][index],
1060 DIV_FROM_REG(data->fan_div[nr]));
1061 return sprintf(buf, "%d\n", speed);
1da177e4 1062}
e1169ba0 1063
20ad93d4 1064static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
c962024e 1065 char *buf)
1da177e4 1066{
20ad93d4 1067 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1068 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1069 int nr = sensor_attr->index;
1070
48b2ae7f 1071 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1da177e4 1072}
c962024e 1073
5f2dc798 1074static ssize_t show_pwm_enable(struct device *dev,
c962024e 1075 struct device_attribute *attr, char *buf)
1da177e4 1076{
20ad93d4 1077 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1078 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1079 int nr = sensor_attr->index;
1080
b99883dc 1081 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1da177e4 1082}
c962024e 1083
20ad93d4 1084static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
c962024e 1085 char *buf)
1da177e4 1086{
20ad93d4 1087 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
c962024e 1088 struct it87_data *data = it87_update_device(dev);
20ad93d4
JD		 1089 int nr = sensor_attr->index;
1090
44c1bcd4
JD		 1091 return sprintf(buf, "%d\n",
1092 pwm_from_reg(data, data->pwm_duty[nr]));
1da177e4 1093}
c962024e 1094
f8d0c19a 1095static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
c962024e 1096 char *buf)
f8d0c19a 1097{
60878bcf 1098 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
f8d0c19a 1099 struct it87_data *data = it87_update_device(dev);
60878bcf 1100 int nr = sensor_attr->index;
f56c9c0a 1101 unsigned int freq;
60878bcf
GR		 1102 int index;
1103
1104 if (has_pwm_freq2(data) && nr == 1)
1105 index = (data->extra >> 4) & 0x07;
1106 else
1107 index = (data->fan_ctl >> 4) & 0x07;
f8d0c19a 1108
f56c9c0a
GR		 1109 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1110
1111 return sprintf(buf, "%u\n", freq);
f8d0c19a 1112}
e1169ba0
GR		 1113
1114static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1115 const char *buf, size_t count)
1da177e4 1116{
e1169ba0
GR		 1117 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1118 int nr = sattr->nr;
1119 int index = sattr->index;
20ad93d4 1120
b74f3fdd 1121 struct it87_data *data = dev_get_drvdata(dev);
f5f64501 1122 long val;
7f999aa7 1123 u8 reg;
1da177e4 1124
179c4fdb 1125 if (kstrtol(buf, 10, &val) < 0)
f5f64501
JD		 1126 return -EINVAL;
1127
9a61bf63 1128 mutex_lock(&data->update_lock);
e1169ba0
GR		 1129
1130 if (has_16bit_fans(data)) {
1131 data->fan[nr][index] = FAN16_TO_REG(val);
1132 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1133 data->fan[nr][index] & 0xff);
1134 it87_write_value(data, IT87_REG_FANX_MIN[nr],
1135 data->fan[nr][index] >> 8);
1136 } else {
1137 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1138 switch (nr) {
1139 case 0:
1140 data->fan_div[nr] = reg & 0x07;
1141 break;
1142 case 1:
1143 data->fan_div[nr] = (reg >> 3) & 0x07;
1144 break;
1145 case 2:
1146 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1147 break;
1148 }
1149 data->fan[nr][index] =
1150 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1151 it87_write_value(data, IT87_REG_FAN_MIN[nr],
1152 data->fan[nr][index]);
07eab46d
JD		 1153 }
1154
9a61bf63 1155 mutex_unlock(&data->update_lock);
1da177e4
LT		 1156 return count;
1157}
e1169ba0 1158
20ad93d4 1159static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
c962024e 1160 const char *buf, size_t count)
1da177e4 1161{
20ad93d4 1162 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1163 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1164 int nr = sensor_attr->index;
f5f64501 1165 unsigned long val;
8ab4ec3e 1166 int min;
1da177e4
LT		 1167 u8 old;
1168
179c4fdb 1169 if (kstrtoul(buf, 10, &val) < 0)
f5f64501
JD		 1170 return -EINVAL;
1171
9a61bf63 1172 mutex_lock(&data->update_lock);
b74f3fdd 1173 old = it87_read_value(data, IT87_REG_FAN_DIV);
1da177e4 1174
8ab4ec3e 1175 /* Save fan min limit */
e1169ba0 1176 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1da177e4
LT		 1177
1178 switch (nr) {
1179 case 0:
1180 case 1:
1181 data->fan_div[nr] = DIV_TO_REG(val);
1182 break;
1183 case 2:
1184 if (val < 8)
1185 data->fan_div[nr] = 1;
1186 else
1187 data->fan_div[nr] = 3;
1188 }
1189 val = old & 0x80;
1190 val |= (data->fan_div[0] & 0x07);
1191 val |= (data->fan_div[1] & 0x07) << 3;
1192 if (data->fan_div[2] == 3)
1193 val |= 0x1 << 6;
b74f3fdd 1194 it87_write_value(data, IT87_REG_FAN_DIV, val);
1da177e4 1195
8ab4ec3e 1196 /* Restore fan min limit */
e1169ba0
GR		 1197 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1198 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
8ab4ec3e 1199
9a61bf63 1200 mutex_unlock(&data->update_lock);
1da177e4
LT		 1201 return count;
1202}
cccfc9c4
JD		 1203
1204/* Returns 0 if OK, -EINVAL otherwise */
1205static int check_trip_points(struct device *dev, int nr)
1206{
1207 const struct it87_data *data = dev_get_drvdata(dev);
1208 int i, err = 0;
1209
1210 if (has_old_autopwm(data)) {
1211 for (i = 0; i < 3; i++) {
1212 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1213 err = -EINVAL;
1214 }
1215 for (i = 0; i < 2; i++) {
1216 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1217 err = -EINVAL;
1218 }
1219 }
1220
1221 if (err) {
1d9bcf6a
GR		 1222 dev_err(dev,
1223 "Inconsistent trip points, not switching to automatic mode\n");
cccfc9c4
JD		 1224 dev_err(dev, "Adjust the trip points and try again\n");
1225 }
1226 return err;
1227}
1228
c962024e
GR		 1229static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1230 const char *buf, size_t count)
1da177e4 1231{
20ad93d4 1232 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1233 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1234 int nr = sensor_attr->index;
f5f64501 1235 long val;
1da177e4 1236
179c4fdb 1237 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
b99883dc
JD		 1238 return -EINVAL;
1239
cccfc9c4
JD		 1240 /* Check trip points before switching to automatic mode */
1241 if (val == 2) {
1242 if (check_trip_points(dev, nr) < 0)
1243 return -EINVAL;
1244 }
1245
9a61bf63 1246 mutex_lock(&data->update_lock);
1da177e4
LT		 1247
1248 if (val == 0) {
f1bbe618
GR		 1249 if (nr < 3 && data->type != it8603) {
1250 int tmp;
1251 /* make sure the fan is on when in on/off mode */
1252 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1253 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1254 /* set on/off mode */
1255 data->fan_main_ctrl &= ~BIT(nr);
1256 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1257 data->fan_main_ctrl);
1258 } else {
1259 /* No on/off mode, set maximum pwm value */
1260 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1261 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1262 data->pwm_duty[nr]);
1263 /* and set manual mode */
1264 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
1265 data->pwm_temp_map[nr] :
1266 data->pwm_duty[nr];
1267 it87_write_value(data, IT87_REG_PWM[nr],
1268 data->pwm_ctrl[nr]);
1269 }
b99883dc
JD		 1270 } else {
1271 if (val == 1) /* Manual mode */
16b5dda2 1272 data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
6229cdb2
JD		 1273 data->pwm_temp_map[nr] :
1274 data->pwm_duty[nr];
b99883dc
JD		 1275 else /* Automatic mode */
1276 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1277 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
c145d5c6 1278
f1bbe618 1279 if (data->type != it8603 && nr < 3) {
c145d5c6 1280 /* set SmartGuardian mode */
48b2ae7f 1281 data->fan_main_ctrl |= BIT(nr);
c145d5c6
RM		 1282 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1283 data->fan_main_ctrl);
1284 }
1da177e4
LT		 1285 }
1286
9a61bf63 1287 mutex_unlock(&data->update_lock);
1da177e4
LT		 1288 return count;
1289}
c962024e 1290
20ad93d4 1291static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
c962024e 1292 const char *buf, size_t count)
1da177e4 1293{
20ad93d4 1294 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1295 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1296 int nr = sensor_attr->index;
f5f64501 1297 long val;
1da177e4 1298
179c4fdb 1299 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1da177e4
LT		 1300 return -EINVAL;
1301
9a61bf63 1302 mutex_lock(&data->update_lock);
16b5dda2 1303 if (has_newer_autopwm(data)) {
4a0d71cf
GR		 1304 /*
1305 * If we are in automatic mode, the PWM duty cycle register
1306 * is read-only so we can't write the value.
1307 */
6229cdb2
JD		 1308 if (data->pwm_ctrl[nr] & 0x80) {
1309 mutex_unlock(&data->update_lock);
1310 return -EBUSY;
1311 }
1312 data->pwm_duty[nr] = pwm_to_reg(data, val);
36c4d98a 1313 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
6229cdb2
JD		 1314 data->pwm_duty[nr]);
1315 } else {
1316 data->pwm_duty[nr] = pwm_to_reg(data, val);
4a0d71cf
GR		 1317 /*
1318 * If we are in manual mode, write the duty cycle immediately;
1319 * otherwise, just store it for later use.
1320 */
6229cdb2
JD		 1321 if (!(data->pwm_ctrl[nr] & 0x80)) {
1322 data->pwm_ctrl[nr] = data->pwm_duty[nr];
36c4d98a 1323 it87_write_value(data, IT87_REG_PWM[nr],
6229cdb2
JD		 1324 data->pwm_ctrl[nr]);
1325 }
b99883dc 1326 }
9a61bf63 1327 mutex_unlock(&data->update_lock);
1da177e4
LT		 1328 return count;
1329}
c962024e
GR		 1330
1331static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1332 const char *buf, size_t count)
f8d0c19a 1333{
60878bcf 1334 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
b74f3fdd 1335 struct it87_data *data = dev_get_drvdata(dev);
60878bcf 1336 int nr = sensor_attr->index;
f5f64501 1337 unsigned long val;
f8d0c19a
JD		 1338 int i;
1339
179c4fdb 1340 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1341 return -EINVAL;
f56c9c0a
GR		 1342
1343 val = clamp_val(val, 0, 1000000);
1344 val *= has_newer_autopwm(data) ? 256 : 128;
f5f64501 1345
f8d0c19a
JD		 1346 /* Search for the nearest available frequency */
1347 for (i = 0; i < 7; i++) {
c962024e 1348 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
f8d0c19a
JD		 1349 break;
1350 }
1351
1352 mutex_lock(&data->update_lock);
60878bcf
GR		 1353 if (nr == 0) {
1354 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1355 data->fan_ctl |= i << 4;
1356 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1357 } else {
1358 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1359 data->extra |= i << 4;
1360 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1361 }
f8d0c19a
JD		 1362 mutex_unlock(&data->update_lock);
1363
1364 return count;
1365}
c962024e 1366
94ac7ee6 1367static ssize_t show_pwm_temp_map(struct device *dev,
c962024e 1368 struct device_attribute *attr, char *buf)
94ac7ee6
JD		 1369{
1370 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
94ac7ee6 1371 struct it87_data *data = it87_update_device(dev);
c962024e 1372 int nr = sensor_attr->index;
94ac7ee6
JD		 1373 int map;
1374
1375 if (data->pwm_temp_map[nr] < 3)
48b2ae7f 1376 map = BIT(data->pwm_temp_map[nr]);
94ac7ee6
JD		 1377 else
1378 map = 0; /* Should never happen */
1379 return sprintf(buf, "%d\n", map);
1380}
c962024e 1381
94ac7ee6 1382static ssize_t set_pwm_temp_map(struct device *dev,
c962024e
GR		 1383 struct device_attribute *attr, const char *buf,
1384 size_t count)
94ac7ee6
JD		 1385{
1386 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
94ac7ee6 1387 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1388 int nr = sensor_attr->index;
94ac7ee6
JD		 1389 long val;
1390 u8 reg;
1391
179c4fdb 1392 if (kstrtol(buf, 10, &val) < 0)
94ac7ee6
JD		 1393 return -EINVAL;
1394
1395 switch (val) {
48b2ae7f 1396 case BIT(0):
94ac7ee6
JD		 1397 reg = 0x00;
1398 break;
48b2ae7f 1399 case BIT(1):
94ac7ee6
JD		 1400 reg = 0x01;
1401 break;
48b2ae7f 1402 case BIT(2):
94ac7ee6
JD		 1403 reg = 0x02;
1404 break;
1405 default:
1406 return -EINVAL;
1407 }
1408
1409 mutex_lock(&data->update_lock);
1410 data->pwm_temp_map[nr] = reg;
4a0d71cf
GR		 1411 /*
1412 * If we are in automatic mode, write the temp mapping immediately;
1413 * otherwise, just store it for later use.
1414 */
94ac7ee6
JD		 1415 if (data->pwm_ctrl[nr] & 0x80) {
1416 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
36c4d98a 1417 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
94ac7ee6
JD		 1418 }
1419 mutex_unlock(&data->update_lock);
1420 return count;
1421}
1da177e4 1422
c962024e
GR		 1423static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1424 char *buf)
4f3f51bc
JD		 1425{
1426 struct it87_data *data = it87_update_device(dev);
1427 struct sensor_device_attribute_2 *sensor_attr =
1428 to_sensor_dev_attr_2(attr);
1429 int nr = sensor_attr->nr;
1430 int point = sensor_attr->index;
1431
44c1bcd4
JD		 1432 return sprintf(buf, "%d\n",
1433 pwm_from_reg(data, data->auto_pwm[nr][point]));
4f3f51bc
JD		 1434}
1435
c962024e
GR		 1436static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1437 const char *buf, size_t count)
4f3f51bc
JD		 1438{
1439 struct it87_data *data = dev_get_drvdata(dev);
1440 struct sensor_device_attribute_2 *sensor_attr =
1441 to_sensor_dev_attr_2(attr);
1442 int nr = sensor_attr->nr;
1443 int point = sensor_attr->index;
1444 long val;
1445
179c4fdb 1446 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
4f3f51bc
JD		 1447 return -EINVAL;
1448
1449 mutex_lock(&data->update_lock);
44c1bcd4 1450 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
4f3f51bc
JD		 1451 it87_write_value(data, IT87_REG_AUTO_PWM(nr, point),
1452 data->auto_pwm[nr][point]);
1453 mutex_unlock(&data->update_lock);
1454 return count;
1455}
1456
c962024e
GR		 1457static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1458 char *buf)
4f3f51bc
JD		 1459{
1460 struct it87_data *data = it87_update_device(dev);
1461 struct sensor_device_attribute_2 *sensor_attr =
1462 to_sensor_dev_attr_2(attr);
1463 int nr = sensor_attr->nr;
1464 int point = sensor_attr->index;
1465
1466 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->auto_temp[nr][point]));
1467}
1468
c962024e
GR		 1469static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1470 const char *buf, size_t count)
4f3f51bc
JD		 1471{
1472 struct it87_data *data = dev_get_drvdata(dev);
1473 struct sensor_device_attribute_2 *sensor_attr =
1474 to_sensor_dev_attr_2(attr);
1475 int nr = sensor_attr->nr;
1476 int point = sensor_attr->index;
1477 long val;
1478
179c4fdb 1479 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
4f3f51bc
JD		 1480 return -EINVAL;
1481
1482 mutex_lock(&data->update_lock);
1483 data->auto_temp[nr][point] = TEMP_TO_REG(val);
1484 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point),
1485 data->auto_temp[nr][point]);
1486 mutex_unlock(&data->update_lock);
1487 return count;
1488}
1489
e1169ba0
GR		 1490static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1491static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1492 0, 1);
1493static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1494 set_fan_div, 0);
1495
1496static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1497static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1498 1, 1);
1499static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1500 set_fan_div, 1);
1501
1502static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1503static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1504 2, 1);
1505static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1506 set_fan_div, 2);
1507
1508static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1509static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1510 3, 1);
1da177e4 1511
e1169ba0
GR		 1512static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1513static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1514 4, 1);
1da177e4 1515
fa3f70d6
GR		 1516static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1517static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1518 5, 1);
1519
c4458db3
GR		 1520static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1521 show_pwm_enable, set_pwm_enable, 0);
1522static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
60878bcf
GR		 1523static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1524 set_pwm_freq, 0);
5c391261 1525static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1526 show_pwm_temp_map, set_pwm_temp_map, 0);
1527static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
1528 show_auto_pwm, set_auto_pwm, 0, 0);
1529static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
1530 show_auto_pwm, set_auto_pwm, 0, 1);
1531static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
1532 show_auto_pwm, set_auto_pwm, 0, 2);
1533static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
1534 show_auto_pwm, NULL, 0, 3);
1535static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
1536 show_auto_temp, set_auto_temp, 0, 1);
1537static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1538 show_auto_temp, set_auto_temp, 0, 0);
1539static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
1540 show_auto_temp, set_auto_temp, 0, 2);
1541static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
1542 show_auto_temp, set_auto_temp, 0, 3);
1543static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
1544 show_auto_temp, set_auto_temp, 0, 4);
1545
1546static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
1547 show_pwm_enable, set_pwm_enable, 1);
1548static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
60878bcf 1549static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
5c391261 1550static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1551 show_pwm_temp_map, set_pwm_temp_map, 1);
1552static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
1553 show_auto_pwm, set_auto_pwm, 1, 0);
1554static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
1555 show_auto_pwm, set_auto_pwm, 1, 1);
1556static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
1557 show_auto_pwm, set_auto_pwm, 1, 2);
1558static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
1559 show_auto_pwm, NULL, 1, 3);
1560static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
1561 show_auto_temp, set_auto_temp, 1, 1);
1562static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1563 show_auto_temp, set_auto_temp, 1, 0);
1564static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
1565 show_auto_temp, set_auto_temp, 1, 2);
1566static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
1567 show_auto_temp, set_auto_temp, 1, 3);
1568static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
1569 show_auto_temp, set_auto_temp, 1, 4);
1570
1571static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
1572 show_pwm_enable, set_pwm_enable, 2);
1573static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
60878bcf 1574static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
5c391261 1575static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
c4458db3
GR		 1576 show_pwm_temp_map, set_pwm_temp_map, 2);
1577static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
1578 show_auto_pwm, set_auto_pwm, 2, 0);
1579static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
1580 show_auto_pwm, set_auto_pwm, 2, 1);
1581static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
1582 show_auto_pwm, set_auto_pwm, 2, 2);
1583static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
1584 show_auto_pwm, NULL, 2, 3);
1585static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
1586 show_auto_temp, set_auto_temp, 2, 1);
1587static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
1588 show_auto_temp, set_auto_temp, 2, 0);
1589static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
1590 show_auto_temp, set_auto_temp, 2, 2);
1591static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
1592 show_auto_temp, set_auto_temp, 2, 3);
1593static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
1594 show_auto_temp, set_auto_temp, 2, 4);
1da177e4 1595
36c4d98a
GR		 1596static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
1597 show_pwm_enable, set_pwm_enable, 3);
1598static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
60878bcf 1599static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
5c391261 1600static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1601 show_pwm_temp_map, set_pwm_temp_map, 3);
1602
1603static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
1604 show_pwm_enable, set_pwm_enable, 4);
1605static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
60878bcf 1606static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
5c391261 1607static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1608 show_pwm_temp_map, set_pwm_temp_map, 4);
1609
1610static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
1611 show_pwm_enable, set_pwm_enable, 5);
1612static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
60878bcf 1613static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
5c391261 1614static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
36c4d98a
GR		 1615 show_pwm_temp_map, set_pwm_temp_map, 5);
1616
1da177e4 1617/* Alarms */
5f2dc798 1618static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
c962024e 1619 char *buf)
1da177e4
LT		 1620{
1621 struct it87_data *data = it87_update_device(dev);
c962024e 1622
68188ba7 1623 return sprintf(buf, "%u\n", data->alarms);
1da177e4 1624}
1d66c64c 1625static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
1da177e4 1626
0124dd78 1627static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
c962024e 1628 char *buf)
0124dd78 1629{
0124dd78 1630 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1631 int bitnr = to_sensor_dev_attr(attr)->index;
1632
0124dd78
JD		 1633 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
1634}
3d30f9e6 1635
c962024e
GR		 1636static ssize_t clear_intrusion(struct device *dev,
1637 struct device_attribute *attr, const char *buf,
1638 size_t count)
3d30f9e6
JD		 1639{
1640 struct it87_data *data = dev_get_drvdata(dev);
3d30f9e6 1641 int config;
c962024e 1642 long val;
3d30f9e6 1643
179c4fdb 1644 if (kstrtol(buf, 10, &val) < 0 || val != 0)
3d30f9e6
JD		 1645 return -EINVAL;
1646
1647 mutex_lock(&data->update_lock);
1648 config = it87_read_value(data, IT87_REG_CONFIG);
1649 if (config < 0) {
1650 count = config;
1651 } else {
48b2ae7f 1652 config |= BIT(5);
3d30f9e6
JD		 1653 it87_write_value(data, IT87_REG_CONFIG, config);
1654 /* Invalidate cache to force re-read */
1655 data->valid = 0;
1656 }
1657 mutex_unlock(&data->update_lock);
1658
1659 return count;
1660}
1661
0124dd78
JD		 1662static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
1663static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
1664static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
1665static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
1666static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
1667static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
1668static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
1669static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
1670static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
1671static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
1672static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
1673static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
1674static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
fa3f70d6 1675static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
0124dd78
JD		 1676static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
1677static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
1678static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
3d30f9e6
JD		 1679static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
1680 show_alarm, clear_intrusion, 4);
0124dd78 1681
d9b327c3 1682static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
c962024e 1683 char *buf)
d9b327c3 1684{
d9b327c3 1685 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1686 int bitnr = to_sensor_dev_attr(attr)->index;
1687
d9b327c3
JD		 1688 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
1689}
c962024e 1690
d9b327c3 1691static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
c962024e 1692 const char *buf, size_t count)
d9b327c3
JD		 1693{
1694 int bitnr = to_sensor_dev_attr(attr)->index;
1695 struct it87_data *data = dev_get_drvdata(dev);
1696 long val;
1697
c962024e 1698 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
d9b327c3
JD		 1699 return -EINVAL;
1700
1701 mutex_lock(&data->update_lock);
1702 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1703 if (val)
48b2ae7f 1704 data->beeps |= BIT(bitnr);
d9b327c3 1705 else
48b2ae7f 1706 data->beeps &= ~BIT(bitnr);
d9b327c3
JD		 1707 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
1708 mutex_unlock(&data->update_lock);
1709 return count;
1710}
1711
1712static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
1713 show_beep, set_beep, 1);
1714static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
1715static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
1716static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
1717static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
1718static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
1719static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
1720static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
1721/* fanX_beep writability is set later */
1722static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
1723static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
1724static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
1725static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
1726static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
fa3f70d6 1727static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
d9b327c3
JD		 1728static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
1729 show_beep, set_beep, 2);
1730static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
1731static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
1732
5f2dc798 1733static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
c962024e 1734 char *buf)
1da177e4 1735{
90d6619a 1736 struct it87_data *data = dev_get_drvdata(dev);
c962024e 1737
a7be58a1 1738 return sprintf(buf, "%u\n", data->vrm);
1da177e4 1739}
c962024e 1740
5f2dc798 1741static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
c962024e 1742 const char *buf, size_t count)
1da177e4 1743{
b74f3fdd 1744 struct it87_data *data = dev_get_drvdata(dev);
f5f64501
JD		 1745 unsigned long val;
1746
179c4fdb 1747 if (kstrtoul(buf, 10, &val) < 0)
f5f64501 1748 return -EINVAL;
1da177e4 1749
1da177e4
LT		 1750 data->vrm = val;
1751
1752 return count;
1753}
1754static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
1da177e4 1755
5f2dc798 1756static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
c962024e 1757 char *buf)
1da177e4
LT		 1758{
1759 struct it87_data *data = it87_update_device(dev);
c962024e
GR		 1760
1761 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
1da177e4
LT		 1762}
1763static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
87808be4 1764
738e5e05 1765static ssize_t show_label(struct device *dev, struct device_attribute *attr,
c962024e 1766 char *buf)
738e5e05 1767{
3c4c4971 1768 static const char * const labels[] = {
738e5e05
JD		 1769 "+5V",
1770 "5VSB",
1771 "Vbat",
1772 };
3c4c4971 1773 static const char * const labels_it8721[] = {
44c1bcd4
JD		 1774 "+3.3V",
1775 "3VSB",
1776 "Vbat",
1777 };
1778 struct it87_data *data = dev_get_drvdata(dev);
738e5e05 1779 int nr = to_sensor_dev_attr(attr)->index;
ead80803 1780 const char *label;
738e5e05 1781
ead80803
JM		 1782 if (has_12mv_adc(data) || has_10_9mv_adc(data))
1783 label = labels_it8721[nr];
1784 else
1785 label = labels[nr];
1786
1787 return sprintf(buf, "%s\n", label);
738e5e05
JD		 1788}
1789static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
1790static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
1791static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
73055405 1792/* AVCC3 */
c145d5c6 1793static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
738e5e05 1794
52929715
GR		 1795static umode_t it87_in_is_visible(struct kobject *kobj,
1796 struct attribute *attr, int index)
9172b5d1 1797{
52929715
GR		 1798 struct device *dev = container_of(kobj, struct device, kobj);
1799 struct it87_data *data = dev_get_drvdata(dev);
1800 int i = index / 5; /* voltage index */
1801 int a = index % 5; /* attribute index */
1802
f838aa26 1803 if (index >= 40) { /* in8 and higher only have input attributes */
52929715
GR		 1804 i = index - 40 + 8;
1805 a = 0;
1806 }
1807
48b2ae7f 1808 if (!(data->has_in & BIT(i)))
52929715
GR		 1809 return 0;
1810
1811 if (a == 4 && !data->has_beep)
1812 return 0;
1813
1814 return attr->mode;
1815}
1816
1817static struct attribute *it87_attributes_in[] = {
87808be4 1818 &sensor_dev_attr_in0_input.dev_attr.attr,
87808be4 1819 &sensor_dev_attr_in0_min.dev_attr.attr,
87808be4 1820 &sensor_dev_attr_in0_max.dev_attr.attr,
0124dd78 1821 &sensor_dev_attr_in0_alarm.dev_attr.attr,
52929715
GR		 1822 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
1823
9172b5d1
GR		 1824 &sensor_dev_attr_in1_input.dev_attr.attr,
1825 &sensor_dev_attr_in1_min.dev_attr.attr,
1826 &sensor_dev_attr_in1_max.dev_attr.attr,
0124dd78 1827 &sensor_dev_attr_in1_alarm.dev_attr.attr,
52929715
GR		 1828 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
1829
9172b5d1
GR		 1830 &sensor_dev_attr_in2_input.dev_attr.attr,
1831 &sensor_dev_attr_in2_min.dev_attr.attr,
1832 &sensor_dev_attr_in2_max.dev_attr.attr,
0124dd78 1833 &sensor_dev_attr_in2_alarm.dev_attr.attr,
52929715
GR		 1834 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
1835
9172b5d1
GR		 1836 &sensor_dev_attr_in3_input.dev_attr.attr,
1837 &sensor_dev_attr_in3_min.dev_attr.attr,
1838 &sensor_dev_attr_in3_max.dev_attr.attr,
0124dd78 1839 &sensor_dev_attr_in3_alarm.dev_attr.attr,
52929715
GR		 1840 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
1841
9172b5d1
GR		 1842 &sensor_dev_attr_in4_input.dev_attr.attr,
1843 &sensor_dev_attr_in4_min.dev_attr.attr,
1844 &sensor_dev_attr_in4_max.dev_attr.attr,
0124dd78 1845 &sensor_dev_attr_in4_alarm.dev_attr.attr,
52929715
GR		 1846 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
1847
9172b5d1
GR		 1848 &sensor_dev_attr_in5_input.dev_attr.attr,
1849 &sensor_dev_attr_in5_min.dev_attr.attr,
1850 &sensor_dev_attr_in5_max.dev_attr.attr,
0124dd78 1851 &sensor_dev_attr_in5_alarm.dev_attr.attr,
52929715
GR		 1852 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
1853
9172b5d1
GR		 1854 &sensor_dev_attr_in6_input.dev_attr.attr,
1855 &sensor_dev_attr_in6_min.dev_attr.attr,
1856 &sensor_dev_attr_in6_max.dev_attr.attr,
0124dd78 1857 &sensor_dev_attr_in6_alarm.dev_attr.attr,
52929715
GR		 1858 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
1859
9172b5d1
GR		 1860 &sensor_dev_attr_in7_input.dev_attr.attr,
1861 &sensor_dev_attr_in7_min.dev_attr.attr,
1862 &sensor_dev_attr_in7_max.dev_attr.attr,
0124dd78 1863 &sensor_dev_attr_in7_alarm.dev_attr.attr,
52929715
GR		 1864 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
1865
1866 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
52929715 1867 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
f838aa26
GR		 1868 &sensor_dev_attr_in10_input.dev_attr.attr, /* 41 */
1869 &sensor_dev_attr_in11_input.dev_attr.attr, /* 41 */
1870 &sensor_dev_attr_in12_input.dev_attr.attr, /* 41 */
52929715
GR		 1871};
1872
1873static const struct attribute_group it87_group_in = {
1874 .attrs = it87_attributes_in,
1875 .is_visible = it87_in_is_visible,
9172b5d1
GR		 1876};
1877
87533770
GR		 1878static umode_t it87_temp_is_visible(struct kobject *kobj,
1879 struct attribute *attr, int index)
4573acbc 1880{
87533770
GR		 1881 struct device *dev = container_of(kobj, struct device, kobj);
1882 struct it87_data *data = dev_get_drvdata(dev);
1883 int i = index / 7; /* temperature index */
1884 int a = index % 7; /* attribute index */
1885
cc18da79
GR		 1886 if (index >= 21) {
1887 i = index - 21 + 3;
1888 a = 0;
1889 }
1890
48b2ae7f 1891 if (!(data->has_temp & BIT(i)))
87533770
GR		 1892 return 0;
1893
1894 if (a == 5 && !has_temp_offset(data))
1895 return 0;
1896
1897 if (a == 6 && !data->has_beep)
1898 return 0;
1899
1900 return attr->mode;
1901}
1902
1903static struct attribute *it87_attributes_temp[] = {
87808be4 1904 &sensor_dev_attr_temp1_input.dev_attr.attr,
87808be4 1905 &sensor_dev_attr_temp1_max.dev_attr.attr,
87808be4 1906 &sensor_dev_attr_temp1_min.dev_attr.attr,
87808be4 1907 &sensor_dev_attr_temp1_type.dev_attr.attr,
0124dd78 1908 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
87533770
GR		 1909 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
1910 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
1911
cc18da79 1912 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
4573acbc
GR		 1913 &sensor_dev_attr_temp2_max.dev_attr.attr,
1914 &sensor_dev_attr_temp2_min.dev_attr.attr,
1915 &sensor_dev_attr_temp2_type.dev_attr.attr,
0124dd78 1916 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
87533770
GR		 1917 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1918 &sensor_dev_attr_temp2_beep.dev_attr.attr,
1919
cc18da79 1920 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
4573acbc
GR		 1921 &sensor_dev_attr_temp3_max.dev_attr.attr,
1922 &sensor_dev_attr_temp3_min.dev_attr.attr,
1923 &sensor_dev_attr_temp3_type.dev_attr.attr,
0124dd78 1924 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
87533770
GR		 1925 &sensor_dev_attr_temp3_offset.dev_attr.attr,
1926 &sensor_dev_attr_temp3_beep.dev_attr.attr,
4573acbc 1927
cc18da79
GR		 1928 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
1929 &sensor_dev_attr_temp5_input.dev_attr.attr,
1930 &sensor_dev_attr_temp6_input.dev_attr.attr,
87533770 1931 NULL
4573acbc 1932};
87808be4 1933
87533770
GR		 1934static const struct attribute_group it87_group_temp = {
1935 .attrs = it87_attributes_temp,
1936 .is_visible = it87_temp_is_visible,
161d898a
GR		 1937};
1938
d3766848
GR		 1939static umode_t it87_is_visible(struct kobject *kobj,
1940 struct attribute *attr, int index)
1941{
1942 struct device *dev = container_of(kobj, struct device, kobj);
1943 struct it87_data *data = dev_get_drvdata(dev);
1944
8638d0af 1945 if ((index == 2 || index == 3) && !data->has_vid)
d3766848
GR		 1946 return 0;
1947
48b2ae7f 1948 if (index > 3 && !(data->in_internal & BIT(index - 4)))
d3766848
GR		 1949 return 0;
1950
1951 return attr->mode;
1952}
1953
4573acbc 1954static struct attribute *it87_attributes[] = {
87808be4 1955 &dev_attr_alarms.attr,
3d30f9e6 1956 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
8638d0af
GR		 1957 &dev_attr_vrm.attr, /* 2 */
1958 &dev_attr_cpu0_vid.attr, /* 3 */
1959 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
d3766848
GR		 1960 &sensor_dev_attr_in7_label.dev_attr.attr,
1961 &sensor_dev_attr_in8_label.dev_attr.attr,
1962 &sensor_dev_attr_in9_label.dev_attr.attr,
87808be4
JD		 1963 NULL
1964};
1965
1966static const struct attribute_group it87_group = {
1967 .attrs = it87_attributes,
d3766848 1968 .is_visible = it87_is_visible,
87808be4
JD		 1969};
1970
9a70ee81
GR		 1971static umode_t it87_fan_is_visible(struct kobject *kobj,
1972 struct attribute *attr, int index)
1973{
1974 struct device *dev = container_of(kobj, struct device, kobj);
1975 struct it87_data *data = dev_get_drvdata(dev);
1976 int i = index / 5; /* fan index */
1977 int a = index % 5; /* attribute index */
1978
1979 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
1980 i = (index - 15) / 4 + 3;
1981 a = (index - 15) % 4;
1982 }
1983
48b2ae7f 1984 if (!(data->has_fan & BIT(i)))
9a70ee81
GR		 1985 return 0;
1986
1987 if (a == 3) { /* beep */
1988 if (!data->has_beep)
1989 return 0;
1990 /* first fan beep attribute is writable */
1991 if (i == __ffs(data->has_fan))
1992 return attr->mode | S_IWUSR;
1993 }
1994
1995 if (a == 4 && has_16bit_fans(data)) /* divisor */
1996 return 0;
1997
1998 return attr->mode;
1999}
2000
2001static struct attribute *it87_attributes_fan[] = {
e1169ba0
GR		 2002 &sensor_dev_attr_fan1_input.dev_attr.attr,
2003 &sensor_dev_attr_fan1_min.dev_attr.attr,
723a0aa0 2004 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
9a70ee81
GR		 2005 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2006 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2007
e1169ba0
GR		 2008 &sensor_dev_attr_fan2_input.dev_attr.attr,
2009 &sensor_dev_attr_fan2_min.dev_attr.attr,
723a0aa0 2010 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
9a70ee81
GR		 2011 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2012 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2013
e1169ba0
GR		 2014 &sensor_dev_attr_fan3_input.dev_attr.attr,
2015 &sensor_dev_attr_fan3_min.dev_attr.attr,
723a0aa0 2016 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
9a70ee81
GR		 2017 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2018 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2019
2020 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
e1169ba0 2021 &sensor_dev_attr_fan4_min.dev_attr.attr,
723a0aa0 2022 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
9a70ee81
GR		 2023 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2024
2025 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
e1169ba0 2026 &sensor_dev_attr_fan5_min.dev_attr.attr,
723a0aa0 2027 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
9a70ee81
GR		 2028 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2029
2030 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
fa3f70d6
GR		 2031 &sensor_dev_attr_fan6_min.dev_attr.attr,
2032 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
9a70ee81 2033 &sensor_dev_attr_fan6_beep.dev_attr.attr,
fa3f70d6 2034 NULL
723a0aa0 2035};
87808be4 2036
9a70ee81
GR		 2037static const struct attribute_group it87_group_fan = {
2038 .attrs = it87_attributes_fan,
2039 .is_visible = it87_fan_is_visible,
723a0aa0
JD		 2040};
2041
5c391261
GR		 2042static umode_t it87_pwm_is_visible(struct kobject *kobj,
2043 struct attribute *attr, int index)
2044{
2045 struct device *dev = container_of(kobj, struct device, kobj);
2046 struct it87_data *data = dev_get_drvdata(dev);
2047 int i = index / 4; /* pwm index */
2048 int a = index % 4; /* attribute index */
2049
48b2ae7f 2050 if (!(data->has_pwm & BIT(i)))
5c391261
GR		 2051 return 0;
2052
2053 /* pwmX_auto_channels_temp is only writable for old auto pwm */
2054 if (a == 3 && has_old_autopwm(data))
2055 return attr->mode | S_IWUSR;
2056
2057 /* pwm2_freq is writable if there are two pwm frequency selects */
2058 if (has_pwm_freq2(data) && i == 1 && a == 2)
2059 return attr->mode | S_IWUSR;
2060
2061 return attr->mode;
2062}
2063
2064static struct attribute *it87_attributes_pwm[] = {
87808be4 2065 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
87808be4 2066 &sensor_dev_attr_pwm1.dev_attr.attr,
60878bcf 2067 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
94ac7ee6 2068 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
5c391261 2069
723a0aa0
JD		 2070 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2071 &sensor_dev_attr_pwm2.dev_attr.attr,
60878bcf 2072 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
94ac7ee6 2073 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
5c391261 2074
723a0aa0
JD		 2075 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2076 &sensor_dev_attr_pwm3.dev_attr.attr,
60878bcf 2077 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
94ac7ee6 2078 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
5c391261 2079
36c4d98a
GR		 2080 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2081 &sensor_dev_attr_pwm4.dev_attr.attr,
60878bcf 2082 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
36c4d98a 2083 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
5c391261 2084
36c4d98a
GR		 2085 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2086 &sensor_dev_attr_pwm5.dev_attr.attr,
60878bcf 2087 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
36c4d98a 2088 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
5c391261 2089
36c4d98a
GR		 2090 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2091 &sensor_dev_attr_pwm6.dev_attr.attr,
60878bcf 2092 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
36c4d98a 2093 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
5c391261 2094
36c4d98a 2095 NULL
5c391261 2096};
87808be4 2097
5c391261
GR		 2098static const struct attribute_group it87_group_pwm = {
2099 .attrs = it87_attributes_pwm,
2100 .is_visible = it87_pwm_is_visible,
2101};
2102
2103static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2104 struct attribute *attr, int index)
60878bcf
GR		 2105{
2106 struct device *dev = container_of(kobj, struct device, kobj);
2107 struct it87_data *data = dev_get_drvdata(dev);
5c391261 2108 int i = index / 9; /* pwm index */
60878bcf 2109
48b2ae7f 2110 if (!(data->has_pwm & BIT(i)))
5c391261 2111 return 0;
60878bcf
GR		 2112
2113 return attr->mode;
2114}
2115
5c391261 2116static struct attribute *it87_attributes_auto_pwm[] = {
4f3f51bc
JD		 2117 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2118 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2119 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2120 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2121 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2122 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2123 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2124 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2125 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
5c391261 2126
4f3f51bc
JD		 2127 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
2128 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2129 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2130 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2131 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2132 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2133 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2134 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2135 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
5c391261 2136
4f3f51bc
JD		 2137 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
2138 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2139 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2140 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2141 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2142 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2143 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2144 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2145 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
4f3f51bc 2146
5c391261
GR		 2147 NULL,
2148};
2149
2150static const struct attribute_group it87_group_auto_pwm = {
2151 .attrs = it87_attributes_auto_pwm,
2152 .is_visible = it87_auto_pwm_is_visible,
4f3f51bc
JD		 2153};
2154
2d8672c5 2155/* SuperIO detection - will change isa_address if a chip is found */
3c2e3512
GR		 2156static int __init it87_find(int sioaddr, unsigned short *address,
2157 struct it87_sio_data *sio_data)
1da177e4 2158{
5b0380c9 2159 int err;
b74f3fdd 2160 u16 chip_type;
98dd22c3 2161 const char *board_vendor, *board_name;
f83a9cb6 2162 const struct it87_devices *config;
1da177e4 2163
3c2e3512 2164 err = superio_enter(sioaddr);
5b0380c9
NG		 2165 if (err)
2166 return err;
2167
2168 err = -ENODEV;
3c2e3512 2169 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
b74f3fdd 2170
2171 switch (chip_type) {
2172 case IT8705F_DEVID:
2173 sio_data->type = it87;
2174 break;
2175 case IT8712F_DEVID:
2176 sio_data->type = it8712;
2177 break;
2178 case IT8716F_DEVID:
2179 case IT8726F_DEVID:
2180 sio_data->type = it8716;
2181 break;
2182 case IT8718F_DEVID:
2183 sio_data->type = it8718;
2184 break;
b4da93e4
JMS		 2185 case IT8720F_DEVID:
2186 sio_data->type = it8720;
2187 break;
44c1bcd4
JD		 2188 case IT8721F_DEVID:
2189 sio_data->type = it8721;
2190 break;
16b5dda2
JD		 2191 case IT8728F_DEVID:
2192 sio_data->type = it8728;
2193 break;
ead80803
JM		 2194 case IT8732F_DEVID:
2195 sio_data->type = it8732;
2196 break;
b0636707
GR		 2197 case IT8771E_DEVID:
2198 sio_data->type = it8771;
2199 break;
2200 case IT8772E_DEVID:
2201 sio_data->type = it8772;
2202 break;
7bc32d29
GR		 2203 case IT8781F_DEVID:
2204 sio_data->type = it8781;
2205 break;
0531d98b
GR		 2206 case IT8782F_DEVID:
2207 sio_data->type = it8782;
2208 break;
2209 case IT8783E_DEVID:
2210 sio_data->type = it8783;
2211 break;
a0c1424a
TL		 2212 case IT8786E_DEVID:
2213 sio_data->type = it8786;
2214 break;
4ee07157
GR		 2215 case IT8790E_DEVID:
2216 sio_data->type = it8790;
2217 break;
7183ae8c 2218 case IT8603E_DEVID:
574e9bd8 2219 case IT8623E_DEVID:
c145d5c6
RM		 2220 sio_data->type = it8603;
2221 break;
3ba9d977
GR		 2222 case IT8620E_DEVID:
2223 sio_data->type = it8620;
2224 break;
b74f3fdd 2225 case 0xffff: /* No device at all */
2226 goto exit;
2227 default:
a8ca1037 2228 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
b74f3fdd 2229 goto exit;
2230 }
1da177e4 2231
3c2e3512
GR		 2232 superio_select(sioaddr, PME);
2233 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
a8ca1037 2234 pr_info("Device not activated, skipping\n");
1da177e4
LT		 2235 goto exit;
2236 }
2237
3c2e3512 2238 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
1da177e4 2239 if (*address == 0) {
a8ca1037 2240 pr_info("Base address not set, skipping\n");
1da177e4
LT		 2241 goto exit;
2242 }
2243
2244 err = 0;
3c2e3512 2245 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
faf392fb
GR		 2246 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2247 it87_devices[sio_data->type].suffix,
a0c1424a 2248 *address, sio_data->revision);
1da177e4 2249
f83a9cb6
GR		 2250 config = &it87_devices[sio_data->type];
2251
7f5726c3 2252 /* in7 (VSB or VCCH5V) is always internal on some chips */
f83a9cb6 2253 if (has_in7_internal(config))
48b2ae7f 2254 sio_data->internal |= BIT(1);
7f5726c3 2255
738e5e05 2256 /* in8 (Vbat) is always internal */
48b2ae7f 2257 sio_data->internal |= BIT(2);
7f5726c3 2258
73055405
GR		 2259 /* in9 (AVCC3), always internal if supported */
2260 if (has_avcc3(config))
48b2ae7f 2261 sio_data->internal |= BIT(3); /* in9 is AVCC */
73055405 2262 else
48b2ae7f 2263 sio_data->skip_in |= BIT(9);
738e5e05 2264
36c4d98a 2265 if (!has_six_pwm(config))
48b2ae7f 2266 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
36c4d98a 2267
f83a9cb6 2268 if (!has_vid(config))
895ff267 2269 sio_data->skip_vid = 1;
d9b327c3 2270
32dd7c40
GR		 2271 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2272 if (sio_data->type == it87) {
d9b327c3 2273 /* The IT8705F has a different LD number for GPIO */
3c2e3512
GR		 2274 superio_select(sioaddr, 5);
2275 sio_data->beep_pin = superio_inb(sioaddr,
2276 IT87_SIO_BEEP_PIN_REG) & 0x3f;
0531d98b 2277 } else if (sio_data->type == it8783) {
088ce2ac 2278 int reg25, reg27, reg2a, reg2c, regef;
0531d98b 2279
3c2e3512 2280 superio_select(sioaddr, GPIO);
0531d98b 2281
3c2e3512
GR		 2282 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2283 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2284 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2285 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2286 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
0531d98b 2287
0531d98b 2288 /* Check if fan3 is there or not */
48b2ae7f
GR		 2289 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2290 sio_data->skip_fan |= BIT(2);
c962024e
GR		 2291 if ((reg25 & BIT(4)) ||
2292 (!(reg2a & BIT(1)) && (regef & BIT(0))))
48b2ae7f 2293 sio_data->skip_pwm |= BIT(2);
0531d98b
GR		 2294
2295 /* Check if fan2 is there or not */
48b2ae7f
GR		 2296 if (reg27 & BIT(7))
2297 sio_data->skip_fan |= BIT(1);
2298 if (reg27 & BIT(3))
2299 sio_data->skip_pwm |= BIT(1);
0531d98b
GR		 2300
2301 /* VIN5 */
48b2ae7f
GR		 2302 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2303 sio_data->skip_in |= BIT(5); /* No VIN5 */
0531d98b
GR		 2304
2305 /* VIN6 */
48b2ae7f
GR		 2306 if (reg27 & BIT(1))
2307 sio_data->skip_in |= BIT(6); /* No VIN6 */
0531d98b
GR		 2308
2309 /*
2310 * VIN7
2311 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2312 */
48b2ae7f 2313 if (reg27 & BIT(2)) {
9172b5d1
GR		 2314 /*
2315 * The data sheet is a bit unclear regarding the
2316 * internal voltage divider for VCCH5V. It says
2317 * "This bit enables and switches VIN7 (pin 91) to the
2318 * internal voltage divider for VCCH5V".
2319 * This is different to other chips, where the internal
2320 * voltage divider would connect VIN7 to an internal
2321 * voltage source. Maybe that is the case here as well.
2322 *
2323 * Since we don't know for sure, re-route it if that is
2324 * not the case, and ask the user to report if the
2325 * resulting voltage is sane.
2326 */
48b2ae7f
GR		 2327 if (!(reg2c & BIT(1))) {
2328 reg2c |= BIT(1);
3c2e3512
GR		 2329 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2330 reg2c);
9172b5d1
GR		 2331 pr_notice("Routing internal VCCH5V to in7.\n");
2332 }
2333 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2334 pr_notice("Please report if it displays a reasonable voltage.\n");
2335 }
0531d98b 2336
48b2ae7f
GR		 2337 if (reg2c & BIT(0))
2338 sio_data->internal |= BIT(0);
2339 if (reg2c & BIT(1))
2340 sio_data->internal |= BIT(1);
0531d98b 2341
3c2e3512
GR		 2342 sio_data->beep_pin = superio_inb(sioaddr,
2343 IT87_SIO_BEEP_PIN_REG) & 0x3f;
c145d5c6
RM		 2344 } else if (sio_data->type == it8603) {
2345 int reg27, reg29;
2346
3c2e3512 2347 superio_select(sioaddr, GPIO);
0531d98b 2348
3c2e3512 2349 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
c145d5c6
RM		 2350
2351 /* Check if fan3 is there or not */
48b2ae7f
GR		 2352 if (reg27 & BIT(6))
2353 sio_data->skip_pwm |= BIT(2);
2354 if (reg27 & BIT(7))
2355 sio_data->skip_fan |= BIT(2);
c145d5c6
RM		 2356
2357 /* Check if fan2 is there or not */
3c2e3512 2358 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2359 if (reg29 & BIT(1))
2360 sio_data->skip_pwm |= BIT(1);
2361 if (reg29 & BIT(2))
2362 sio_data->skip_fan |= BIT(1);
c145d5c6 2363
48b2ae7f
GR		 2364 sio_data->skip_in |= BIT(5); /* No VIN5 */
2365 sio_data->skip_in |= BIT(6); /* No VIN6 */
c145d5c6 2366
3c2e3512
GR		 2367 sio_data->beep_pin = superio_inb(sioaddr,
2368 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3ba9d977
GR		 2369 } else if (sio_data->type == it8620) {
2370 int reg;
2371
3c2e3512 2372 superio_select(sioaddr, GPIO);
3ba9d977 2373
36c4d98a 2374 /* Check for pwm5 */
3c2e3512 2375 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
48b2ae7f
GR		 2376 if (reg & BIT(6))
2377 sio_data->skip_pwm |= BIT(4);
36c4d98a 2378
3ba9d977 2379 /* Check for fan4, fan5 */
3c2e3512 2380 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
48b2ae7f
GR		 2381 if (!(reg & BIT(5)))
2382 sio_data->skip_fan |= BIT(3);
2383 if (!(reg & BIT(4)))
2384 sio_data->skip_fan |= BIT(4);
3ba9d977
GR		 2385
2386 /* Check for pwm3, fan3 */
3c2e3512 2387 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
48b2ae7f
GR		 2388 if (reg & BIT(6))
2389 sio_data->skip_pwm |= BIT(2);
2390 if (reg & BIT(7))
2391 sio_data->skip_fan |= BIT(2);
3ba9d977 2392
36c4d98a 2393 /* Check for pwm4 */
3c2e3512 2394 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
48b2ae7f
GR		 2395 if (!(reg & BIT(2)))
2396 sio_data->skip_pwm |= BIT(3);
36c4d98a 2397
3ba9d977 2398 /* Check for pwm2, fan2 */
3c2e3512 2399 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2400 if (reg & BIT(1))
2401 sio_data->skip_pwm |= BIT(1);
2402 if (reg & BIT(2))
2403 sio_data->skip_fan |= BIT(1);
36c4d98a 2404 /* Check for pwm6, fan6 */
48b2ae7f
GR		 2405 if (!(reg & BIT(7))) {
2406 sio_data->skip_pwm |= BIT(5);
2407 sio_data->skip_fan |= BIT(5);
36c4d98a 2408 }
3ba9d977 2409
3c2e3512
GR		 2410 sio_data->beep_pin = superio_inb(sioaddr,
2411 IT87_SIO_BEEP_PIN_REG) & 0x3f;
895ff267 2412 } else {
87673dd7 2413 int reg;
9172b5d1 2414 bool uart6;
87673dd7 2415
3c2e3512 2416 superio_select(sioaddr, GPIO);
44c1bcd4 2417
a0df926d
GR		 2418 /* Check for fan4, fan5 */
2419 if (has_five_fans(config)) {
2420 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
2421 switch (sio_data->type) {
2422 case it8718:
2423 if (reg & BIT(5))
2424 sio_data->skip_fan |= BIT(3);
2425 if (reg & BIT(4))
2426 sio_data->skip_fan |= BIT(4);
2427 break;
2428 case it8720:
2429 case it8721:
2430 case it8728:
2431 if (!(reg & BIT(5)))
2432 sio_data->skip_fan |= BIT(3);
2433 if (!(reg & BIT(4)))
2434 sio_data->skip_fan |= BIT(4);
2435 break;
2436 default:
2437 break;
2438 }
2439 }
2440
3c2e3512 2441 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
32dd7c40 2442 if (!sio_data->skip_vid) {
44c1bcd4
JD		 2443 /* We need at least 4 VID pins */
2444 if (reg & 0x0f) {
a8ca1037 2445 pr_info("VID is disabled (pins used for GPIO)\n");
44c1bcd4
JD		 2446 sio_data->skip_vid = 1;
2447 }
895ff267
JD		 2448 }
2449
591ec650 2450 /* Check if fan3 is there or not */
48b2ae7f
GR		 2451 if (reg & BIT(6))
2452 sio_data->skip_pwm |= BIT(2);
2453 if (reg & BIT(7))
2454 sio_data->skip_fan |= BIT(2);
591ec650
JD		 2455
2456 /* Check if fan2 is there or not */
3c2e3512 2457 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
48b2ae7f
GR		 2458 if (reg & BIT(1))
2459 sio_data->skip_pwm |= BIT(1);
2460 if (reg & BIT(2))
2461 sio_data->skip_fan |= BIT(1);
591ec650 2462
c962024e
GR		 2463 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
2464 !(sio_data->skip_vid))
3c2e3512
GR		 2465 sio_data->vid_value = superio_inb(sioaddr,
2466 IT87_SIO_VID_REG);
87673dd7 2467
3c2e3512 2468 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
9172b5d1 2469
48b2ae7f 2470 uart6 = sio_data->type == it8782 && (reg & BIT(2));
9172b5d1 2471
436cad2a
JD		 2472 /*
2473 * The IT8720F has no VIN7 pin, so VCCH should always be
2474 * routed internally to VIN7 with an internal divider.
2475 * Curiously, there still is a configuration bit to control
2476 * this, which means it can be set incorrectly. And even
2477 * more curiously, many boards out there are improperly
2478 * configured, even though the IT8720F datasheet claims
2479 * that the internal routing of VCCH to VIN7 is the default
2480 * setting. So we force the internal routing in this case.
0531d98b
GR		 2481 *
2482 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
9172b5d1
GR		 2483 * If UART6 is enabled, re-route VIN7 to the internal divider
2484 * if that is not already the case.
436cad2a 2485 */
48b2ae7f
GR		 2486 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
2487 reg |= BIT(1);
3c2e3512 2488 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
a8ca1037 2489 pr_notice("Routing internal VCCH to in7\n");
436cad2a 2490 }
48b2ae7f
GR		 2491 if (reg & BIT(0))
2492 sio_data->internal |= BIT(0);
2493 if (reg & BIT(1))
2494 sio_data->internal |= BIT(1);
d9b327c3 2495
9172b5d1
GR		 2496 /*
2497 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
2498 * While VIN7 can be routed to the internal voltage divider,
2499 * VIN5 and VIN6 are not available if UART6 is enabled.
4573acbc
GR		 2500 *
2501 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
2502 * is the temperature source. Since we can not read the
2503 * temperature source here, skip_temp is preliminary.
9172b5d1 2504 */
4573acbc 2505 if (uart6) {
48b2ae7f
GR		 2506 sio_data->skip_in |= BIT(5) | BIT(6);
2507 sio_data->skip_temp |= BIT(2);
4573acbc 2508 }
9172b5d1 2509
3c2e3512
GR		 2510 sio_data->beep_pin = superio_inb(sioaddr,
2511 IT87_SIO_BEEP_PIN_REG) & 0x3f;
87673dd7 2512 }
d9b327c3 2513 if (sio_data->beep_pin)
a8ca1037 2514 pr_info("Beeping is supported\n");
87673dd7 2515
98dd22c3
JD		 2516 /* Disable specific features based on DMI strings */
2517 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
2518 board_name = dmi_get_system_info(DMI_BOARD_NAME);
2519 if (board_vendor && board_name) {
c962024e
GR		 2520 if (strcmp(board_vendor, "nVIDIA") == 0 &&
2521 strcmp(board_name, "FN68PT") == 0) {
4a0d71cf
GR		 2522 /*
2523 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
2524 * connected to a fan, but to something else. One user
2525 * has reported instant system power-off when changing
2526 * the PWM2 duty cycle, so we disable it.
2527 * I use the board name string as the trigger in case
2528 * the same board is ever used in other systems.
2529 */
a8ca1037 2530 pr_info("Disabling pwm2 due to hardware constraints\n");
48b2ae7f 2531 sio_data->skip_pwm = BIT(1);
98dd22c3
JD		 2532 }
2533 }
2534
1da177e4 2535exit:
3c2e3512 2536 superio_exit(sioaddr);
1da177e4
LT		 2537 return err;
2538}
2539
c1e7a4ca
GR		 2540/* Called when we have found a new IT87. */
2541static void it87_init_device(struct platform_device *pdev)
1da177e4 2542{
c1e7a4ca
GR		 2543 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
2544 struct it87_data *data = platform_get_drvdata(pdev);
2545 int tmp, i;
2546 u8 mask;
b74f3fdd 2547
c1e7a4ca
GR		 2548 /*
2549 * For each PWM channel:
2550 * - If it is in automatic mode, setting to manual mode should set
2551 * the fan to full speed by default.
2552 * - If it is in manual mode, we need a mapping to temperature
2553 * channels to use when later setting to automatic mode later.
2554 * Use a 1:1 mapping by default (we are clueless.)
2555 * In both cases, the value can (and should) be changed by the user
2556 * prior to switching to a different mode.
2557 * Note that this is no longer needed for the IT8721F and later, as
2558 * these have separate registers for the temperature mapping and the
2559 * manual duty cycle.
2560 */
2310048d 2561 for (i = 0; i < NUM_AUTO_PWM; i++) {
c1e7a4ca
GR		 2562 data->pwm_temp_map[i] = i;
2563 data->pwm_duty[i] = 0x7f; /* Full speed */
2564 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
8e9afcbb 2565 }
1da177e4 2566
483db43e 2567 /*
c1e7a4ca
GR		 2568 * Some chips seem to have default value 0xff for all limit
2569 * registers. For low voltage limits it makes no sense and triggers
2570 * alarms, so change to 0 instead. For high temperature limits, it
2571 * means -1 degree C, which surprisingly doesn't trigger an alarm,
2572 * but is still confusing, so change to 127 degrees C.
483db43e 2573 */
2310048d 2574 for (i = 0; i < NUM_VIN_LIMIT; i++) {
c1e7a4ca
GR		 2575 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
2576 if (tmp == 0xff)
2577 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
2578 }
2310048d 2579 for (i = 0; i < NUM_TEMP_LIMIT; i++) {
c1e7a4ca
GR		 2580 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
2581 if (tmp == 0xff)
2582 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
483db43e 2583 }
1da177e4 2584
c1e7a4ca
GR		 2585 /*
2586 * Temperature channels are not forcibly enabled, as they can be
2587 * set to two different sensor types and we can't guess which one
2588 * is correct for a given system. These channels can be enabled at
2589 * run-time through the temp{1-3}_type sysfs accessors if needed.
2590 */
1da177e4 2591
c1e7a4ca
GR		 2592 /* Check if voltage monitors are reset manually or by some reason */
2593 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
2594 if ((tmp & 0xff) == 0) {
2595 /* Enable all voltage monitors */
2596 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
2597 }
2598
2599 /* Check if tachometers are reset manually or by some reason */
2600 mask = 0x70 & ~(sio_data->skip_fan << 4);
2601 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
2602 if ((data->fan_main_ctrl & mask) == 0) {
2603 /* Enable all fan tachometers */
2604 data->fan_main_ctrl |= mask;
2605 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
2606 data->fan_main_ctrl);
2607 }
2608 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
2609
2610 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
2611
2612 /* Set tachometers to 16-bit mode if needed */
2613 if (has_fan16_config(data)) {
2614 if (~tmp & 0x07 & data->has_fan) {
2615 dev_dbg(&pdev->dev,
2616 "Setting fan1-3 to 16-bit mode\n");
2617 it87_write_value(data, IT87_REG_FAN_16BIT,
2618 tmp | 0x07);
2619 }
2620 }
2621
2622 /* Check for additional fans */
2623 if (has_five_fans(data)) {
48b2ae7f
GR		 2624 if (tmp & BIT(4))
2625 data->has_fan |= BIT(3); /* fan4 enabled */
2626 if (tmp & BIT(5))
2627 data->has_fan |= BIT(4); /* fan5 enabled */
2628 if (has_six_fans(data) && (tmp & BIT(2)))
2629 data->has_fan |= BIT(5); /* fan6 enabled */
c1e7a4ca
GR		 2630 }
2631
2632 /* Fan input pins may be used for alternative functions */
2633 data->has_fan &= ~sio_data->skip_fan;
2634
2635 /* Check if pwm5, pwm6 are enabled */
2636 if (has_six_pwm(data)) {
2637 /* The following code may be IT8620E specific */
2638 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
2639 if ((tmp & 0xc0) == 0xc0)
48b2ae7f
GR		 2640 sio_data->skip_pwm |= BIT(4);
2641 if (!(tmp & BIT(3)))
2642 sio_data->skip_pwm |= BIT(5);
c1e7a4ca
GR		 2643 }
2644
2645 /* Start monitoring */
2646 it87_write_value(data, IT87_REG_CONFIG,
2647 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
2648 | (update_vbat ? 0x41 : 0x01));
2649}
2650
2651/* Return 1 if and only if the PWM interface is safe to use */
2652static int it87_check_pwm(struct device *dev)
2653{
2654 struct it87_data *data = dev_get_drvdata(dev);
2655 /*
2656 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
2657 * and polarity set to active low is sign that this is the case so we
2658 * disable pwm control to protect the user.
2659 */
2660 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
2661
2662 if ((tmp & 0x87) == 0) {
2663 if (fix_pwm_polarity) {
2664 /*
2665 * The user asks us to attempt a chip reconfiguration.
2666 * This means switching to active high polarity and
2667 * inverting all fan speed values.
2668 */
2669 int i;
2670 u8 pwm[3];
2671
2310048d 2672 for (i = 0; i < ARRAY_SIZE(pwm); i++)
c1e7a4ca
GR		 2673 pwm[i] = it87_read_value(data,
2674 IT87_REG_PWM[i]);
2675
2676 /*
2677 * If any fan is in automatic pwm mode, the polarity
2678 * might be correct, as suspicious as it seems, so we
2679 * better don't change anything (but still disable the
2680 * PWM interface).
2681 */
2682 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
2683 dev_info(dev,
2684 "Reconfiguring PWM to active high polarity\n");
2685 it87_write_value(data, IT87_REG_FAN_CTL,
2686 tmp | 0x87);
2687 for (i = 0; i < 3; i++)
2688 it87_write_value(data,
2689 IT87_REG_PWM[i],
2690 0x7f & ~pwm[i]);
2691 return 1;
2692 }
2693
2694 dev_info(dev,
2695 "PWM configuration is too broken to be fixed\n");
2696 }
2697
2698 dev_info(dev,
2699 "Detected broken BIOS defaults, disabling PWM interface\n");
2700 return 0;
2701 } else if (fix_pwm_polarity) {
2702 dev_info(dev,
2703 "PWM configuration looks sane, won't touch\n");
2704 }
2705
2706 return 1;
2707}
2708
2709static int it87_probe(struct platform_device *pdev)
2710{
2711 struct it87_data *data;
2712 struct resource *res;
2713 struct device *dev = &pdev->dev;
2714 struct it87_sio_data *sio_data = dev_get_platdata(dev);
c1e7a4ca 2715 int enable_pwm_interface;
8638d0af 2716 struct device *hwmon_dev;
c1e7a4ca
GR		 2717
2718 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2719 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
2720 DRVNAME)) {
2721 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2722 (unsigned long)res->start,
2723 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
2724 return -EBUSY;
2725 }
2726
2727 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
2728 if (!data)
2729 return -ENOMEM;
2730
2731 data->addr = res->start;
2732 data->type = sio_data->type;
2733 data->features = it87_devices[sio_data->type].features;
2734 data->peci_mask = it87_devices[sio_data->type].peci_mask;
2735 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
c1e7a4ca
GR		 2736 /*
2737 * IT8705F Datasheet 0.4.1, 3h == Version G.
2738 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
2739 * These are the first revisions with 16-bit tachometer support.
2740 */
2741 switch (data->type) {
2742 case it87:
2743 if (sio_data->revision >= 0x03) {
2744 data->features &= ~FEAT_OLD_AUTOPWM;
2745 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
2746 }
2747 break;
2748 case it8712:
2749 if (sio_data->revision >= 0x08) {
2750 data->features &= ~FEAT_OLD_AUTOPWM;
2751 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
2752 FEAT_FIVE_FANS;
2753 }
2754 break;
2755 default:
2756 break;
2757 }
2758
2759 /* Now, we do the remaining detection. */
c962024e
GR		 2760 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
2761 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
c1e7a4ca
GR		 2762 return -ENODEV;
2763
2764 platform_set_drvdata(pdev, data);
1da177e4 2765
9a61bf63 2766 mutex_init(&data->update_lock);
1da177e4 2767
1da177e4 2768 /* Check PWM configuration */
b74f3fdd 2769 enable_pwm_interface = it87_check_pwm(dev);
1da177e4 2770
44c1bcd4 2771 /* Starting with IT8721F, we handle scaling of internal voltages */
16b5dda2 2772 if (has_12mv_adc(data)) {
48b2ae7f
GR		 2773 if (sio_data->internal & BIT(0))
2774 data->in_scaled |= BIT(3); /* in3 is AVCC */
2775 if (sio_data->internal & BIT(1))
2776 data->in_scaled |= BIT(7); /* in7 is VSB */
2777 if (sio_data->internal & BIT(2))
2778 data->in_scaled |= BIT(8); /* in8 is Vbat */
2779 if (sio_data->internal & BIT(3))
2780 data->in_scaled |= BIT(9); /* in9 is AVCC */
7bc32d29
GR		 2781 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
2782 sio_data->type == it8783) {
48b2ae7f
GR		 2783 if (sio_data->internal & BIT(0))
2784 data->in_scaled |= BIT(3); /* in3 is VCC5V */
2785 if (sio_data->internal & BIT(1))
2786 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
44c1bcd4
JD		 2787 }
2788
4573acbc 2789 data->has_temp = 0x07;
48b2ae7f 2790 if (sio_data->skip_temp & BIT(2)) {
c962024e
GR		 2791 if (sio_data->type == it8782 &&
2792 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
48b2ae7f 2793 data->has_temp &= ~BIT(2);
4573acbc
GR		 2794 }
2795
d3766848 2796 data->in_internal = sio_data->internal;
52929715
GR		 2797 data->has_in = 0x3ff & ~sio_data->skip_in;
2798
cc18da79
GR		 2799 if (has_six_temp(data)) {
2800 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
2801
f838aa26 2802 /* Check for additional temperature sensors */
cc18da79 2803 if ((reg & 0x03) >= 0x02)
48b2ae7f 2804 data->has_temp |= BIT(3);
cc18da79 2805 if (((reg >> 2) & 0x03) >= 0x02)
48b2ae7f 2806 data->has_temp |= BIT(4);
cc18da79 2807 if (((reg >> 4) & 0x03) >= 0x02)
48b2ae7f 2808 data->has_temp |= BIT(5);
f838aa26
GR		 2809
2810 /* Check for additional voltage sensors */
2811 if ((reg & 0x03) == 0x01)
48b2ae7f 2812 data->has_in |= BIT(10);
f838aa26 2813 if (((reg >> 2) & 0x03) == 0x01)
48b2ae7f 2814 data->has_in |= BIT(11);
f838aa26 2815 if (((reg >> 4) & 0x03) == 0x01)
48b2ae7f 2816 data->has_in |= BIT(12);
cc18da79
GR		 2817 }
2818
52929715
GR		 2819 data->has_beep = !!sio_data->beep_pin;
2820
1da177e4 2821 /* Initialize the IT87 chip */
b74f3fdd 2822 it87_init_device(pdev);
1da177e4 2823
d3766848
GR		 2824 if (!sio_data->skip_vid) {
2825 data->has_vid = true;
2826 data->vrm = vid_which_vrm();
2827 /* VID reading from Super-I/O config space if available */
2828 data->vid = sio_data->vid_value;
2829 }
2830
8638d0af
GR		 2831 /* Prepare for sysfs hooks */
2832 data->groups[0] = &it87_group;
2833 data->groups[1] = &it87_group_in;
2834 data->groups[2] = &it87_group_temp;
2835 data->groups[3] = &it87_group_fan;
17d648bf 2836
1da177e4 2837 if (enable_pwm_interface) {
48b2ae7f 2838 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
5c391261 2839 data->has_pwm &= ~sio_data->skip_pwm;
4f3f51bc 2840
8638d0af
GR		 2841 data->groups[4] = &it87_group_pwm;
2842 if (has_old_autopwm(data))
2843 data->groups[5] = &it87_group_auto_pwm;
1da177e4
LT		 2844 }
2845
8638d0af
GR		 2846 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
2847 it87_devices[sio_data->type].name,
2848 data, data->groups);
2849 return PTR_ERR_OR_ZERO(hwmon_dev);
1da177e4
LT		 2850}
2851
c1e7a4ca
GR		 2852static struct platform_driver it87_driver = {
2853 .driver = {
2854 .name = DRVNAME,
2855 },
2856 .probe = it87_probe,
c1e7a4ca 2857};
1da177e4 2858
e84bd953 2859static int __init it87_device_add(int index, unsigned short address,
b74f3fdd 2860 const struct it87_sio_data *sio_data)
2861{
8e50e3c3 2862 struct platform_device *pdev;
b74f3fdd 2863 struct resource res = {
87b4b663
BH		 2864 .start = address + IT87_EC_OFFSET,
2865 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
b74f3fdd 2866 .name = DRVNAME,
2867 .flags = IORESOURCE_IO,
2868 };
2869 int err;
2870
b9acb64a
JD		 2871 err = acpi_check_resource_conflict(&res);
2872 if (err)
5cae84a5 2873 return err;
b9acb64a 2874
b74f3fdd 2875 pdev = platform_device_alloc(DRVNAME, address);
5cae84a5
GR		 2876 if (!pdev)
2877 return -ENOMEM;
b74f3fdd 2878
2879 err = platform_device_add_resources(pdev, &res, 1);
2880 if (err) {
a8ca1037 2881 pr_err("Device resource addition failed (%d)\n", err);
b74f3fdd 2882 goto exit_device_put;
2883 }
2884
2885 err = platform_device_add_data(pdev, sio_data,
2886 sizeof(struct it87_sio_data));
2887 if (err) {
a8ca1037 2888 pr_err("Platform data allocation failed\n");
b74f3fdd 2889 goto exit_device_put;
2890 }
2891
2892 err = platform_device_add(pdev);
2893 if (err) {
a8ca1037 2894 pr_err("Device addition failed (%d)\n", err);
b74f3fdd 2895 goto exit_device_put;
2896 }
2897
e84bd953 2898 it87_pdev[index] = pdev;
b74f3fdd 2899 return 0;
2900
2901exit_device_put:
2902 platform_device_put(pdev);
b74f3fdd 2903 return err;
2904}
2905
1da177e4
LT		 2906static int __init sm_it87_init(void)
2907{
e84bd953 2908 int sioaddr[2] = { REG_2E, REG_4E };
b74f3fdd 2909 struct it87_sio_data sio_data;
e84bd953
GR		 2910 unsigned short isa_address;
2911 bool found = false;
2912 int i, err;
b74f3fdd 2913
b74f3fdd 2914 err = platform_driver_register(&it87_driver);
2915 if (err)
2916 return err;
fde09509 2917
e84bd953
GR		 2918 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
2919 memset(&sio_data, 0, sizeof(struct it87_sio_data));
2920 isa_address = 0;
2921 err = it87_find(sioaddr[i], &isa_address, &sio_data);
2922 if (err || isa_address == 0)
2923 continue;
2924
2925 err = it87_device_add(i, isa_address, &sio_data);
2926 if (err)
2927 goto exit_dev_unregister;
2928 found = true;
b74f3fdd 2929 }
2930
e84bd953
GR		 2931 if (!found) {
2932 err = -ENODEV;
2933 goto exit_unregister;
2934 }
b74f3fdd 2935 return 0;
e84bd953
GR		 2936
2937exit_dev_unregister:
2938 /* NULL check handled by platform_device_unregister */
2939 platform_device_unregister(it87_pdev[0]);
2940exit_unregister:
2941 platform_driver_unregister(&it87_driver);
2942 return err;
1da177e4
LT		 2943}
2944
2945static void __exit sm_it87_exit(void)
2946{
e84bd953
GR		 2947 /* NULL check handled by platform_device_unregister */
2948 platform_device_unregister(it87_pdev[1]);
2949 platform_device_unregister(it87_pdev[0]);
b74f3fdd 2950 platform_driver_unregister(&it87_driver);
1da177e4
LT		 2951}
2952
7c81c60f 2953MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
44c1bcd4 2954MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
1da177e4
LT		 2955module_param(update_vbat, bool, 0);
2956MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
2957module_param(fix_pwm_polarity, bool, 0);
5f2dc798
JD		 2958MODULE_PARM_DESC(fix_pwm_polarity,
2959 "Force PWM polarity to active high (DANGEROUS)");
1da177e4
LT		 2960MODULE_LICENSE("GPL");
2961
2962module_init(sm_it87_init);
2963module_exit(sm_it87_exit);
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