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Commit | Line | Data |
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1da177e4 | 1 | /* |
5f2dc798 JD |
2 | * it87.c - Part of lm_sensors, Linux kernel modules for hardware |
3 | * monitoring. | |
4 | * | |
5 | * The IT8705F is an LPC-based Super I/O part that contains UARTs, a | |
6 | * parallel port, an IR port, a MIDI port, a floppy controller, etc., in | |
7 | * addition to an Environment Controller (Enhanced Hardware Monitor and | |
8 | * Fan Controller) | |
9 | * | |
10 | * This driver supports only the Environment Controller in the IT8705F and | |
11 | * similar parts. The other devices are supported by different drivers. | |
12 | * | |
c145d5c6 | 13 | * Supports: IT8603E Super I/O chip w/LPC interface |
3ba9d977 | 14 | * IT8620E Super I/O chip w/LPC interface |
8af1abae | 15 | * IT8622E Super I/O chip w/LPC interface |
574e9bd8 | 16 | * IT8623E Super I/O chip w/LPC interface |
71a9c232 | 17 | * IT8628E Super I/O chip w/LPC interface |
c145d5c6 | 18 | * IT8705F Super I/O chip w/LPC interface |
5f2dc798 JD |
19 | * IT8712F Super I/O chip w/LPC interface |
20 | * IT8716F Super I/O chip w/LPC interface | |
21 | * IT8718F Super I/O chip w/LPC interface | |
22 | * IT8720F Super I/O chip w/LPC interface | |
44c1bcd4 | 23 | * IT8721F Super I/O chip w/LPC interface |
5f2dc798 | 24 | * IT8726F Super I/O chip w/LPC interface |
16b5dda2 | 25 | * IT8728F Super I/O chip w/LPC interface |
ead80803 | 26 | * IT8732F Super I/O chip w/LPC interface |
44c1bcd4 | 27 | * IT8758E Super I/O chip w/LPC interface |
b0636707 GR |
28 | * IT8771E Super I/O chip w/LPC interface |
29 | * IT8772E Super I/O chip w/LPC interface | |
7bc32d29 | 30 | * IT8781F Super I/O chip w/LPC interface |
0531d98b GR |
31 | * IT8782F Super I/O chip w/LPC interface |
32 | * IT8783E/F Super I/O chip w/LPC interface | |
a0c1424a | 33 | * IT8786E Super I/O chip w/LPC interface |
4ee07157 | 34 | * IT8790E Super I/O chip w/LPC interface |
5f2dc798 JD |
35 | * Sis950 A clone of the IT8705F |
36 | * | |
37 | * Copyright (C) 2001 Chris Gauthron | |
7c81c60f | 38 | * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> |
5f2dc798 JD |
39 | * |
40 | * This program is free software; you can redistribute it and/or modify | |
41 | * it under the terms of the GNU General Public License as published by | |
42 | * the Free Software Foundation; either version 2 of the License, or | |
43 | * (at your option) any later version. | |
44 | * | |
45 | * This program is distributed in the hope that it will be useful, | |
46 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
47 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
48 | * GNU General Public License for more details. | |
5f2dc798 | 49 | */ |
1da177e4 | 50 | |
a8ca1037 JP |
51 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
52 | ||
48b2ae7f | 53 | #include <linux/bitops.h> |
1da177e4 LT |
54 | #include <linux/module.h> |
55 | #include <linux/init.h> | |
56 | #include <linux/slab.h> | |
57 | #include <linux/jiffies.h> | |
b74f3fdd | 58 | #include <linux/platform_device.h> |
943b0830 | 59 | #include <linux/hwmon.h> |
303760b4 JD |
60 | #include <linux/hwmon-sysfs.h> |
61 | #include <linux/hwmon-vid.h> | |
943b0830 | 62 | #include <linux/err.h> |
9a61bf63 | 63 | #include <linux/mutex.h> |
87808be4 | 64 | #include <linux/sysfs.h> |
98dd22c3 JD |
65 | #include <linux/string.h> |
66 | #include <linux/dmi.h> | |
b9acb64a | 67 | #include <linux/acpi.h> |
6055fae8 | 68 | #include <linux/io.h> |
1da177e4 | 69 | |
b74f3fdd | 70 | #define DRVNAME "it87" |
1da177e4 | 71 | |
ead80803 JM |
72 | enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, |
73 | it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603, | |
8af1abae | 74 | it8620, it8622, it8628 }; |
1da177e4 | 75 | |
67b671bc JD |
76 | static unsigned short force_id; |
77 | module_param(force_id, ushort, 0); | |
78 | MODULE_PARM_DESC(force_id, "Override the detected device ID"); | |
79 | ||
e84bd953 | 80 | static struct platform_device *it87_pdev[2]; |
b74f3fdd | 81 | |
3c2e3512 | 82 | #define REG_2E 0x2e /* The register to read/write */ |
e84bd953 | 83 | #define REG_4E 0x4e /* Secondary register to read/write */ |
3c2e3512 | 84 | |
1da177e4 | 85 | #define DEV 0x07 /* Register: Logical device select */ |
1da177e4 | 86 | #define PME 0x04 /* The device with the fan registers in it */ |
b4da93e4 JMS |
87 | |
88 | /* The device with the IT8718F/IT8720F VID value in it */ | |
89 | #define GPIO 0x07 | |
90 | ||
1da177e4 LT |
91 | #define DEVID 0x20 /* Register: Device ID */ |
92 | #define DEVREV 0x22 /* Register: Device Revision */ | |
93 | ||
3c2e3512 | 94 | static inline int superio_inb(int ioreg, int reg) |
1da177e4 | 95 | { |
3c2e3512 GR |
96 | outb(reg, ioreg); |
97 | return inb(ioreg + 1); | |
1da177e4 LT |
98 | } |
99 | ||
3c2e3512 | 100 | static inline void superio_outb(int ioreg, int reg, int val) |
436cad2a | 101 | { |
3c2e3512 GR |
102 | outb(reg, ioreg); |
103 | outb(val, ioreg + 1); | |
436cad2a JD |
104 | } |
105 | ||
3c2e3512 | 106 | static int superio_inw(int ioreg, int reg) |
1da177e4 LT |
107 | { |
108 | int val; | |
c962024e | 109 | |
3c2e3512 GR |
110 | outb(reg++, ioreg); |
111 | val = inb(ioreg + 1) << 8; | |
112 | outb(reg, ioreg); | |
113 | val |= inb(ioreg + 1); | |
1da177e4 LT |
114 | return val; |
115 | } | |
116 | ||
3c2e3512 | 117 | static inline void superio_select(int ioreg, int ldn) |
1da177e4 | 118 | { |
3c2e3512 GR |
119 | outb(DEV, ioreg); |
120 | outb(ldn, ioreg + 1); | |
1da177e4 LT |
121 | } |
122 | ||
3c2e3512 | 123 | static inline int superio_enter(int ioreg) |
1da177e4 | 124 | { |
5b0380c9 | 125 | /* |
3c2e3512 | 126 | * Try to reserve ioreg and ioreg + 1 for exclusive access. |
5b0380c9 | 127 | */ |
3c2e3512 | 128 | if (!request_muxed_region(ioreg, 2, DRVNAME)) |
5b0380c9 NG |
129 | return -EBUSY; |
130 | ||
3c2e3512 GR |
131 | outb(0x87, ioreg); |
132 | outb(0x01, ioreg); | |
133 | outb(0x55, ioreg); | |
e84bd953 | 134 | outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); |
5b0380c9 | 135 | return 0; |
1da177e4 LT |
136 | } |
137 | ||
3c2e3512 | 138 | static inline void superio_exit(int ioreg) |
1da177e4 | 139 | { |
3c2e3512 GR |
140 | outb(0x02, ioreg); |
141 | outb(0x02, ioreg + 1); | |
142 | release_region(ioreg, 2); | |
1da177e4 LT |
143 | } |
144 | ||
87673dd7 | 145 | /* Logical device 4 registers */ |
1da177e4 LT |
146 | #define IT8712F_DEVID 0x8712 |
147 | #define IT8705F_DEVID 0x8705 | |
17d648bf | 148 | #define IT8716F_DEVID 0x8716 |
87673dd7 | 149 | #define IT8718F_DEVID 0x8718 |
b4da93e4 | 150 | #define IT8720F_DEVID 0x8720 |
44c1bcd4 | 151 | #define IT8721F_DEVID 0x8721 |
08a8f6e9 | 152 | #define IT8726F_DEVID 0x8726 |
16b5dda2 | 153 | #define IT8728F_DEVID 0x8728 |
ead80803 | 154 | #define IT8732F_DEVID 0x8732 |
b0636707 GR |
155 | #define IT8771E_DEVID 0x8771 |
156 | #define IT8772E_DEVID 0x8772 | |
7bc32d29 | 157 | #define IT8781F_DEVID 0x8781 |
0531d98b GR |
158 | #define IT8782F_DEVID 0x8782 |
159 | #define IT8783E_DEVID 0x8783 | |
a0c1424a | 160 | #define IT8786E_DEVID 0x8786 |
4ee07157 | 161 | #define IT8790E_DEVID 0x8790 |
7183ae8c | 162 | #define IT8603E_DEVID 0x8603 |
3ba9d977 | 163 | #define IT8620E_DEVID 0x8620 |
8af1abae | 164 | #define IT8622E_DEVID 0x8622 |
574e9bd8 | 165 | #define IT8623E_DEVID 0x8623 |
71a9c232 | 166 | #define IT8628E_DEVID 0x8628 |
1da177e4 LT |
167 | #define IT87_ACT_REG 0x30 |
168 | #define IT87_BASE_REG 0x60 | |
169 | ||
87673dd7 | 170 | /* Logical device 7 registers (IT8712F and later) */ |
0531d98b | 171 | #define IT87_SIO_GPIO1_REG 0x25 |
3ba9d977 | 172 | #define IT87_SIO_GPIO2_REG 0x26 |
895ff267 | 173 | #define IT87_SIO_GPIO3_REG 0x27 |
36c4d98a | 174 | #define IT87_SIO_GPIO4_REG 0x28 |
591ec650 | 175 | #define IT87_SIO_GPIO5_REG 0x29 |
0531d98b | 176 | #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ |
87673dd7 | 177 | #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ |
0531d98b | 178 | #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ |
87673dd7 | 179 | #define IT87_SIO_VID_REG 0xfc /* VID value */ |
d9b327c3 | 180 | #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ |
87673dd7 | 181 | |
1da177e4 | 182 | /* Update battery voltage after every reading if true */ |
90ab5ee9 | 183 | static bool update_vbat; |
1da177e4 LT |
184 | |
185 | /* Not all BIOSes properly configure the PWM registers */ | |
90ab5ee9 | 186 | static bool fix_pwm_polarity; |
1da177e4 | 187 | |
1da177e4 LT |
188 | /* Many IT87 constants specified below */ |
189 | ||
190 | /* Length of ISA address segment */ | |
191 | #define IT87_EXTENT 8 | |
192 | ||
87b4b663 BH |
193 | /* Length of ISA address segment for Environmental Controller */ |
194 | #define IT87_EC_EXTENT 2 | |
195 | ||
196 | /* Offset of EC registers from ISA base address */ | |
197 | #define IT87_EC_OFFSET 5 | |
198 | ||
199 | /* Where are the ISA address/data registers relative to the EC base address */ | |
200 | #define IT87_ADDR_REG_OFFSET 0 | |
201 | #define IT87_DATA_REG_OFFSET 1 | |
1da177e4 LT |
202 | |
203 | /*----- The IT87 registers -----*/ | |
204 | ||
205 | #define IT87_REG_CONFIG 0x00 | |
206 | ||
207 | #define IT87_REG_ALARM1 0x01 | |
208 | #define IT87_REG_ALARM2 0x02 | |
209 | #define IT87_REG_ALARM3 0x03 | |
210 | ||
4a0d71cf GR |
211 | /* |
212 | * The IT8718F and IT8720F have the VID value in a different register, in | |
213 | * Super-I/O configuration space. | |
214 | */ | |
1da177e4 | 215 | #define IT87_REG_VID 0x0a |
4a0d71cf GR |
216 | /* |
217 | * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b | |
218 | * for fan divisors. Later IT8712F revisions must use 16-bit tachometer | |
219 | * mode. | |
220 | */ | |
1da177e4 | 221 | #define IT87_REG_FAN_DIV 0x0b |
17d648bf | 222 | #define IT87_REG_FAN_16BIT 0x0c |
1da177e4 | 223 | |
f838aa26 GR |
224 | /* |
225 | * Monitors: | |
226 | * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) | |
227 | * - up to 6 temp (1 to 6) | |
228 | * - up to 6 fan (1 to 6) | |
229 | */ | |
1da177e4 | 230 | |
fa3f70d6 GR |
231 | static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; |
232 | static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; | |
233 | static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; | |
234 | static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; | |
235 | static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; | |
161d898a | 236 | |
1da177e4 LT |
237 | #define IT87_REG_FAN_MAIN_CTRL 0x13 |
238 | #define IT87_REG_FAN_CTL 0x14 | |
36c4d98a GR |
239 | static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; |
240 | static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; | |
1da177e4 | 241 | |
559313c4 | 242 | static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, |
f838aa26 | 243 | 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; |
1da177e4 | 244 | |
559313c4 | 245 | #define IT87_REG_TEMP(nr) (0x29 + (nr)) |
73055405 | 246 | |
1da177e4 LT |
247 | #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) |
248 | #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) | |
249 | #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) | |
250 | #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) | |
251 | ||
1da177e4 LT |
252 | #define IT87_REG_VIN_ENABLE 0x50 |
253 | #define IT87_REG_TEMP_ENABLE 0x51 | |
4573acbc | 254 | #define IT87_REG_TEMP_EXTRA 0x55 |
d9b327c3 | 255 | #define IT87_REG_BEEP_ENABLE 0x5c |
1da177e4 LT |
256 | |
257 | #define IT87_REG_CHIPID 0x58 | |
258 | ||
2cbb9c37 GR |
259 | static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; |
260 | ||
261 | #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) | |
262 | #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) | |
4f3f51bc | 263 | |
cc18da79 GR |
264 | #define IT87_REG_TEMP456_ENABLE 0x77 |
265 | ||
2310048d GR |
266 | #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) |
267 | #define NUM_VIN_LIMIT 8 | |
268 | #define NUM_TEMP 6 | |
269 | #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) | |
270 | #define NUM_TEMP_LIMIT 3 | |
271 | #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) | |
272 | #define NUM_FAN_DIV 3 | |
273 | #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) | |
274 | #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) | |
275 | ||
483db43e GR |
276 | struct it87_devices { |
277 | const char *name; | |
faf392fb | 278 | const char * const suffix; |
cc18da79 | 279 | u32 features; |
19529784 GR |
280 | u8 peci_mask; |
281 | u8 old_peci_mask; | |
483db43e GR |
282 | }; |
283 | ||
48b2ae7f GR |
284 | #define FEAT_12MV_ADC BIT(0) |
285 | #define FEAT_NEWER_AUTOPWM BIT(1) | |
286 | #define FEAT_OLD_AUTOPWM BIT(2) | |
287 | #define FEAT_16BIT_FANS BIT(3) | |
288 | #define FEAT_TEMP_OFFSET BIT(4) | |
289 | #define FEAT_TEMP_PECI BIT(5) | |
290 | #define FEAT_TEMP_OLD_PECI BIT(6) | |
291 | #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ | |
292 | #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ | |
293 | #define FEAT_VID BIT(9) /* Set if chip supports VID */ | |
294 | #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ | |
295 | #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ | |
296 | #define FEAT_10_9MV_ADC BIT(12) | |
297 | #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ | |
638c1c07 GR |
298 | #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ |
299 | #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ | |
300 | #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ | |
301 | #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ | |
302 | #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ | |
483db43e GR |
303 | |
304 | static const struct it87_devices it87_devices[] = { | |
305 | [it87] = { | |
306 | .name = "it87", | |
faf392fb | 307 | .suffix = "F", |
483db43e GR |
308 | .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */ |
309 | }, | |
310 | [it8712] = { | |
311 | .name = "it8712", | |
faf392fb | 312 | .suffix = "F", |
32dd7c40 GR |
313 | .features = FEAT_OLD_AUTOPWM | FEAT_VID, |
314 | /* may need to overwrite */ | |
483db43e GR |
315 | }, |
316 | [it8716] = { | |
317 | .name = "it8716", | |
faf392fb | 318 | .suffix = "F", |
32dd7c40 | 319 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf | 320 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2, |
483db43e GR |
321 | }, |
322 | [it8718] = { | |
323 | .name = "it8718", | |
faf392fb | 324 | .suffix = "F", |
32dd7c40 | 325 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
326 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
327 | | FEAT_PWM_FREQ2, | |
19529784 | 328 | .old_peci_mask = 0x4, |
483db43e GR |
329 | }, |
330 | [it8720] = { | |
331 | .name = "it8720", | |
faf392fb | 332 | .suffix = "F", |
32dd7c40 | 333 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID |
60878bcf GR |
334 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS |
335 | | FEAT_PWM_FREQ2, | |
19529784 | 336 | .old_peci_mask = 0x4, |
483db43e GR |
337 | }, |
338 | [it8721] = { | |
339 | .name = "it8721", | |
faf392fb | 340 | .suffix = "F", |
483db43e | 341 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
9faf28ca | 342 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI |
60878bcf GR |
343 | | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL |
344 | | FEAT_PWM_FREQ2, | |
5d8d2f2b | 345 | .peci_mask = 0x05, |
19529784 | 346 | .old_peci_mask = 0x02, /* Actually reports PCH */ |
483db43e GR |
347 | }, |
348 | [it8728] = { | |
349 | .name = "it8728", | |
faf392fb | 350 | .suffix = "F", |
483db43e | 351 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
7f5726c3 | 352 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS |
60878bcf | 353 | | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2, |
5d8d2f2b | 354 | .peci_mask = 0x07, |
483db43e | 355 | }, |
ead80803 JM |
356 | [it8732] = { |
357 | .name = "it8732", | |
358 | .suffix = "F", | |
359 | .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS | |
360 | | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | |
361 | | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, | |
362 | .peci_mask = 0x07, | |
363 | .old_peci_mask = 0x02, /* Actually reports PCH */ | |
364 | }, | |
b0636707 GR |
365 | [it8771] = { |
366 | .name = "it8771", | |
faf392fb | 367 | .suffix = "E", |
b0636707 | 368 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
369 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
370 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
371 | /* PECI: guesswork */ |
372 | /* 12mV ADC (OHM) */ | |
373 | /* 16 bit fans (OHM) */ | |
374 | /* three fans, always 16 bit (guesswork) */ | |
b0636707 GR |
375 | .peci_mask = 0x07, |
376 | }, | |
377 | [it8772] = { | |
378 | .name = "it8772", | |
faf392fb | 379 | .suffix = "E", |
b0636707 | 380 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
381 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
382 | | FEAT_PWM_FREQ2, | |
9faf28ca GR |
383 | /* PECI (coreboot) */ |
384 | /* 12mV ADC (HWSensors4, OHM) */ | |
385 | /* 16 bit fans (HWSensors4, OHM) */ | |
386 | /* three fans, always 16 bit (datasheet) */ | |
b0636707 GR |
387 | .peci_mask = 0x07, |
388 | }, | |
7bc32d29 GR |
389 | [it8781] = { |
390 | .name = "it8781", | |
faf392fb | 391 | .suffix = "F", |
7bc32d29 | 392 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 393 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
7bc32d29 GR |
394 | .old_peci_mask = 0x4, |
395 | }, | |
483db43e GR |
396 | [it8782] = { |
397 | .name = "it8782", | |
faf392fb | 398 | .suffix = "F", |
19529784 | 399 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 400 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 401 | .old_peci_mask = 0x4, |
483db43e GR |
402 | }, |
403 | [it8783] = { | |
404 | .name = "it8783", | |
faf392fb | 405 | .suffix = "E/F", |
19529784 | 406 | .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET |
60878bcf | 407 | | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, |
19529784 | 408 | .old_peci_mask = 0x4, |
483db43e | 409 | }, |
a0c1424a TL |
410 | [it8786] = { |
411 | .name = "it8786", | |
faf392fb | 412 | .suffix = "E", |
a0c1424a | 413 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
60878bcf GR |
414 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
415 | | FEAT_PWM_FREQ2, | |
a0c1424a TL |
416 | .peci_mask = 0x07, |
417 | }, | |
4ee07157 GR |
418 | [it8790] = { |
419 | .name = "it8790", | |
420 | .suffix = "E", | |
421 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
60878bcf GR |
422 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
423 | | FEAT_PWM_FREQ2, | |
4ee07157 GR |
424 | .peci_mask = 0x07, |
425 | }, | |
c145d5c6 RM |
426 | [it8603] = { |
427 | .name = "it8603", | |
faf392fb | 428 | .suffix = "E", |
c145d5c6 | 429 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS |
73055405 | 430 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL |
60878bcf | 431 | | FEAT_AVCC3 | FEAT_PWM_FREQ2, |
c145d5c6 RM |
432 | .peci_mask = 0x07, |
433 | }, | |
3ba9d977 GR |
434 | [it8620] = { |
435 | .name = "it8620", | |
436 | .suffix = "E", | |
437 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
fa3f70d6 | 438 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS |
cc18da79 | 439 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 |
a9eebd4f | 440 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
3ba9d977 GR |
441 | .peci_mask = 0x07, |
442 | }, | |
8af1abae GR |
443 | [it8622] = { |
444 | .name = "it8622", | |
445 | .suffix = "E", | |
446 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
447 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS | |
638c1c07 GR |
448 | | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 |
449 | | FEAT_AVCC3 | FEAT_VIN3_5V, | |
8af1abae GR |
450 | .peci_mask = 0x07, |
451 | }, | |
71a9c232 GR |
452 | [it8628] = { |
453 | .name = "it8628", | |
454 | .suffix = "E", | |
455 | .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS | |
456 | | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS | |
457 | | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | |
a9eebd4f | 458 | | FEAT_SIX_TEMP | FEAT_VIN3_5V, |
71a9c232 GR |
459 | .peci_mask = 0x07, |
460 | }, | |
483db43e GR |
461 | }; |
462 | ||
463 | #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) | |
464 | #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) | |
ead80803 | 465 | #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) |
483db43e GR |
466 | #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) |
467 | #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) | |
468 | #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) | |
5d8d2f2b | 469 | #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ |
48b2ae7f | 470 | ((data)->peci_mask & BIT(nr))) |
19529784 GR |
471 | #define has_temp_old_peci(data, nr) \ |
472 | (((data)->features & FEAT_TEMP_OLD_PECI) && \ | |
48b2ae7f | 473 | ((data)->old_peci_mask & BIT(nr))) |
9faf28ca | 474 | #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) |
fa3f70d6 GR |
475 | #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ |
476 | FEAT_SIX_FANS)) | |
32dd7c40 | 477 | #define has_vid(data) ((data)->features & FEAT_VID) |
7f5726c3 | 478 | #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) |
fa3f70d6 | 479 | #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) |
73055405 | 480 | #define has_avcc3(data) ((data)->features & FEAT_AVCC3) |
638c1c07 GR |
481 | #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \ |
482 | | FEAT_SIX_PWM)) | |
36c4d98a | 483 | #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) |
60878bcf | 484 | #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) |
cc18da79 | 485 | #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) |
a9eebd4f | 486 | #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) |
1da177e4 | 487 | |
b74f3fdd | 488 | struct it87_sio_data { |
489 | enum chips type; | |
490 | /* Values read from Super-I/O config space */ | |
0475169c | 491 | u8 revision; |
b74f3fdd | 492 | u8 vid_value; |
d9b327c3 | 493 | u8 beep_pin; |
738e5e05 | 494 | u8 internal; /* Internal sensors can be labeled */ |
591ec650 | 495 | /* Features skipped based on config or DMI */ |
9172b5d1 | 496 | u16 skip_in; |
895ff267 | 497 | u8 skip_vid; |
591ec650 | 498 | u8 skip_fan; |
98dd22c3 | 499 | u8 skip_pwm; |
4573acbc | 500 | u8 skip_temp; |
b74f3fdd | 501 | }; |
502 | ||
4a0d71cf GR |
503 | /* |
504 | * For each registered chip, we need to keep some data in memory. | |
505 | * The structure is dynamically allocated. | |
506 | */ | |
1da177e4 | 507 | struct it87_data { |
8638d0af | 508 | const struct attribute_group *groups[7]; |
1da177e4 | 509 | enum chips type; |
aa8b187e | 510 | u32 features; |
19529784 GR |
511 | u8 peci_mask; |
512 | u8 old_peci_mask; | |
1da177e4 | 513 | |
b74f3fdd | 514 | unsigned short addr; |
515 | const char *name; | |
9a61bf63 | 516 | struct mutex update_lock; |
1da177e4 LT |
517 | char valid; /* !=0 if following fields are valid */ |
518 | unsigned long last_updated; /* In jiffies */ | |
519 | ||
44c1bcd4 | 520 | u16 in_scaled; /* Internal voltage sensors are scaled */ |
d3766848 | 521 | u16 in_internal; /* Bitfield, internal sensors (for labels) */ |
52929715 | 522 | u16 has_in; /* Bitfield, voltage sensors enabled */ |
2310048d | 523 | u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ |
9060f8bd | 524 | u8 has_fan; /* Bitfield, fans enabled */ |
2310048d | 525 | u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ |
4573acbc | 526 | u8 has_temp; /* Bitfield, temp sensors enabled */ |
2310048d | 527 | s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ |
19529784 GR |
528 | u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ |
529 | u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ | |
2310048d | 530 | u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ |
d3766848 | 531 | bool has_vid; /* True if VID supported */ |
1da177e4 | 532 | u8 vid; /* Register encoding, combined */ |
a7be58a1 | 533 | u8 vrm; |
1da177e4 | 534 | u32 alarms; /* Register encoding, combined */ |
52929715 | 535 | bool has_beep; /* true if beep supported */ |
d9b327c3 | 536 | u8 beeps; /* Register encoding */ |
1da177e4 | 537 | u8 fan_main_ctrl; /* Register value */ |
f8d0c19a | 538 | u8 fan_ctl; /* Register value */ |
b99883dc | 539 | |
4a0d71cf GR |
540 | /* |
541 | * The following 3 arrays correspond to the same registers up to | |
6229cdb2 JD |
542 | * the IT8720F. The meaning of bits 6-0 depends on the value of bit |
543 | * 7, and we want to preserve settings on mode changes, so we have | |
544 | * to track all values separately. | |
545 | * Starting with the IT8721F, the manual PWM duty cycles are stored | |
546 | * in separate registers (8-bit values), so the separate tracking | |
547 | * is no longer needed, but it is still done to keep the driver | |
4a0d71cf GR |
548 | * simple. |
549 | */ | |
5c391261 | 550 | u8 has_pwm; /* Bitfield, pwm control enabled */ |
2310048d GR |
551 | u8 pwm_ctrl[NUM_PWM]; /* Register value */ |
552 | u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ | |
553 | u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ | |
4f3f51bc JD |
554 | |
555 | /* Automatic fan speed control registers */ | |
2310048d GR |
556 | u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ |
557 | s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ | |
1da177e4 | 558 | }; |
0df6454d | 559 | |
0531d98b | 560 | static int adc_lsb(const struct it87_data *data, int nr) |
44c1bcd4 | 561 | { |
ead80803 JM |
562 | int lsb; |
563 | ||
564 | if (has_12mv_adc(data)) | |
565 | lsb = 120; | |
566 | else if (has_10_9mv_adc(data)) | |
567 | lsb = 109; | |
568 | else | |
569 | lsb = 160; | |
48b2ae7f | 570 | if (data->in_scaled & BIT(nr)) |
0531d98b GR |
571 | lsb <<= 1; |
572 | return lsb; | |
573 | } | |
44c1bcd4 | 574 | |
0531d98b GR |
575 | static u8 in_to_reg(const struct it87_data *data, int nr, long val) |
576 | { | |
ead80803 | 577 | val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); |
2a844c14 | 578 | return clamp_val(val, 0, 255); |
44c1bcd4 JD |
579 | } |
580 | ||
581 | static int in_from_reg(const struct it87_data *data, int nr, int val) | |
582 | { | |
ead80803 | 583 | return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); |
44c1bcd4 | 584 | } |
0df6454d JD |
585 | |
586 | static inline u8 FAN_TO_REG(long rpm, int div) | |
587 | { | |
588 | if (rpm == 0) | |
589 | return 255; | |
2a844c14 GR |
590 | rpm = clamp_val(rpm, 1, 1000000); |
591 | return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); | |
0df6454d JD |
592 | } |
593 | ||
594 | static inline u16 FAN16_TO_REG(long rpm) | |
595 | { | |
596 | if (rpm == 0) | |
597 | return 0xffff; | |
2a844c14 | 598 | return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); |
0df6454d JD |
599 | } |
600 | ||
601 | #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ | |
602 | 1350000 / ((val) * (div))) | |
603 | /* The divider is fixed to 2 in 16-bit mode */ | |
604 | #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ | |
605 | 1350000 / ((val) * 2)) | |
606 | ||
2a844c14 GR |
607 | #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ |
608 | ((val) + 500) / 1000), -128, 127)) | |
0df6454d JD |
609 | #define TEMP_FROM_REG(val) ((val) * 1000) |
610 | ||
44c1bcd4 JD |
611 | static u8 pwm_to_reg(const struct it87_data *data, long val) |
612 | { | |
16b5dda2 | 613 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
614 | return val; |
615 | else | |
616 | return val >> 1; | |
617 | } | |
618 | ||
619 | static int pwm_from_reg(const struct it87_data *data, u8 reg) | |
620 | { | |
16b5dda2 | 621 | if (has_newer_autopwm(data)) |
44c1bcd4 JD |
622 | return reg; |
623 | else | |
624 | return (reg & 0x7f) << 1; | |
625 | } | |
626 | ||
0df6454d JD |
627 | static int DIV_TO_REG(int val) |
628 | { | |
629 | int answer = 0; | |
c962024e | 630 | |
0df6454d JD |
631 | while (answer < 7 && (val >>= 1)) |
632 | answer++; | |
633 | return answer; | |
634 | } | |
48b2ae7f GR |
635 | |
636 | #define DIV_FROM_REG(val) BIT(val) | |
0df6454d | 637 | |
f56c9c0a GR |
638 | /* |
639 | * PWM base frequencies. The frequency has to be divided by either 128 or 256, | |
640 | * depending on the chip type, to calculate the actual PWM frequency. | |
641 | * | |
642 | * Some of the chip datasheets suggest a base frequency of 51 kHz instead | |
643 | * of 750 kHz for the slowest base frequency, resulting in a PWM frequency | |
644 | * of 200 Hz. Sometimes both PWM frequency select registers are affected, | |
645 | * sometimes just one. It is unknown if this is a datasheet error or real, | |
646 | * so this is ignored for now. | |
647 | */ | |
0df6454d | 648 | static const unsigned int pwm_freq[8] = { |
f56c9c0a GR |
649 | 48000000, |
650 | 24000000, | |
651 | 12000000, | |
652 | 8000000, | |
653 | 6000000, | |
654 | 3000000, | |
655 | 1500000, | |
656 | 750000, | |
0df6454d | 657 | }; |
1da177e4 | 658 | |
c1e7a4ca GR |
659 | /* |
660 | * Must be called with data->update_lock held, except during initialization. | |
661 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
662 | * would slow down the IT87 access and should not be necessary. | |
663 | */ | |
664 | static int it87_read_value(struct it87_data *data, u8 reg) | |
665 | { | |
666 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
667 | return inb_p(data->addr + IT87_DATA_REG_OFFSET); | |
668 | } | |
669 | ||
670 | /* | |
671 | * Must be called with data->update_lock held, except during initialization. | |
672 | * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, | |
673 | * would slow down the IT87 access and should not be necessary. | |
674 | */ | |
675 | static void it87_write_value(struct it87_data *data, u8 reg, u8 value) | |
676 | { | |
677 | outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); | |
678 | outb_p(value, data->addr + IT87_DATA_REG_OFFSET); | |
679 | } | |
680 | ||
681 | static void it87_update_pwm_ctrl(struct it87_data *data, int nr) | |
682 | { | |
683 | data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); | |
684 | if (has_newer_autopwm(data)) { | |
0624d861 | 685 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; |
c1e7a4ca GR |
686 | data->pwm_duty[nr] = it87_read_value(data, |
687 | IT87_REG_PWM_DUTY[nr]); | |
688 | } else { | |
689 | if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ | |
690 | data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; | |
691 | else /* Manual mode */ | |
692 | data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; | |
693 | } | |
1da177e4 | 694 | |
c1e7a4ca GR |
695 | if (has_old_autopwm(data)) { |
696 | int i; | |
1da177e4 | 697 | |
c1e7a4ca GR |
698 | for (i = 0; i < 5 ; i++) |
699 | data->auto_temp[nr][i] = it87_read_value(data, | |
700 | IT87_REG_AUTO_TEMP(nr, i)); | |
701 | for (i = 0; i < 3 ; i++) | |
702 | data->auto_pwm[nr][i] = it87_read_value(data, | |
703 | IT87_REG_AUTO_PWM(nr, i)); | |
2cbb9c37 GR |
704 | } else if (has_newer_autopwm(data)) { |
705 | int i; | |
706 | ||
707 | /* | |
708 | * 0: temperature hysteresis (base + 5) | |
709 | * 1: fan off temperature (base + 0) | |
710 | * 2: fan start temperature (base + 1) | |
711 | * 3: fan max temperature (base + 2) | |
712 | */ | |
713 | data->auto_temp[nr][0] = | |
714 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); | |
715 | ||
716 | for (i = 0; i < 3 ; i++) | |
717 | data->auto_temp[nr][i + 1] = | |
718 | it87_read_value(data, | |
719 | IT87_REG_AUTO_TEMP(nr, i)); | |
720 | /* | |
721 | * 0: start pwm value (base + 3) | |
722 | * 1: pwm slope (base + 4, 1/8th pwm) | |
723 | */ | |
724 | data->auto_pwm[nr][0] = | |
725 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); | |
726 | data->auto_pwm[nr][1] = | |
727 | it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); | |
c1e7a4ca GR |
728 | } |
729 | } | |
1da177e4 | 730 | |
c1e7a4ca GR |
731 | static struct it87_data *it87_update_device(struct device *dev) |
732 | { | |
733 | struct it87_data *data = dev_get_drvdata(dev); | |
734 | int i; | |
735 | ||
736 | mutex_lock(&data->update_lock); | |
737 | ||
c962024e GR |
738 | if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || |
739 | !data->valid) { | |
c1e7a4ca GR |
740 | if (update_vbat) { |
741 | /* | |
742 | * Cleared after each update, so reenable. Value | |
743 | * returned by this read will be previous value | |
744 | */ | |
745 | it87_write_value(data, IT87_REG_CONFIG, | |
746 | it87_read_value(data, IT87_REG_CONFIG) | 0x40); | |
747 | } | |
2310048d | 748 | for (i = 0; i < NUM_VIN; i++) { |
48b2ae7f | 749 | if (!(data->has_in & BIT(i))) |
559313c4 GR |
750 | continue; |
751 | ||
c1e7a4ca | 752 | data->in[i][0] = |
559313c4 GR |
753 | it87_read_value(data, IT87_REG_VIN[i]); |
754 | ||
755 | /* VBAT and AVCC don't have limit registers */ | |
2310048d | 756 | if (i >= NUM_VIN_LIMIT) |
559313c4 GR |
757 | continue; |
758 | ||
c1e7a4ca GR |
759 | data->in[i][1] = |
760 | it87_read_value(data, IT87_REG_VIN_MIN(i)); | |
761 | data->in[i][2] = | |
762 | it87_read_value(data, IT87_REG_VIN_MAX(i)); | |
763 | } | |
c1e7a4ca | 764 | |
2310048d | 765 | for (i = 0; i < NUM_FAN; i++) { |
c1e7a4ca | 766 | /* Skip disabled fans */ |
48b2ae7f | 767 | if (!(data->has_fan & BIT(i))) |
c1e7a4ca GR |
768 | continue; |
769 | ||
770 | data->fan[i][1] = | |
771 | it87_read_value(data, IT87_REG_FAN_MIN[i]); | |
772 | data->fan[i][0] = it87_read_value(data, | |
773 | IT87_REG_FAN[i]); | |
774 | /* Add high byte if in 16-bit mode */ | |
775 | if (has_16bit_fans(data)) { | |
776 | data->fan[i][0] |= it87_read_value(data, | |
777 | IT87_REG_FANX[i]) << 8; | |
778 | data->fan[i][1] |= it87_read_value(data, | |
779 | IT87_REG_FANX_MIN[i]) << 8; | |
780 | } | |
781 | } | |
2310048d | 782 | for (i = 0; i < NUM_TEMP; i++) { |
48b2ae7f | 783 | if (!(data->has_temp & BIT(i))) |
c1e7a4ca GR |
784 | continue; |
785 | data->temp[i][0] = | |
786 | it87_read_value(data, IT87_REG_TEMP(i)); | |
cc18da79 | 787 | |
2310048d GR |
788 | if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) |
789 | data->temp[i][3] = | |
790 | it87_read_value(data, | |
791 | IT87_REG_TEMP_OFFSET[i]); | |
792 | ||
793 | if (i >= NUM_TEMP_LIMIT) | |
cc18da79 GR |
794 | continue; |
795 | ||
c1e7a4ca GR |
796 | data->temp[i][1] = |
797 | it87_read_value(data, IT87_REG_TEMP_LOW(i)); | |
798 | data->temp[i][2] = | |
799 | it87_read_value(data, IT87_REG_TEMP_HIGH(i)); | |
c1e7a4ca GR |
800 | } |
801 | ||
802 | /* Newer chips don't have clock dividers */ | |
803 | if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { | |
804 | i = it87_read_value(data, IT87_REG_FAN_DIV); | |
805 | data->fan_div[0] = i & 0x07; | |
806 | data->fan_div[1] = (i >> 3) & 0x07; | |
807 | data->fan_div[2] = (i & 0x40) ? 3 : 1; | |
808 | } | |
809 | ||
810 | data->alarms = | |
811 | it87_read_value(data, IT87_REG_ALARM1) | | |
812 | (it87_read_value(data, IT87_REG_ALARM2) << 8) | | |
813 | (it87_read_value(data, IT87_REG_ALARM3) << 16); | |
814 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
815 | ||
816 | data->fan_main_ctrl = it87_read_value(data, | |
817 | IT87_REG_FAN_MAIN_CTRL); | |
818 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); | |
0624d861 GR |
819 | for (i = 0; i < NUM_PWM; i++) { |
820 | if (!(data->has_pwm & BIT(i))) | |
821 | continue; | |
c1e7a4ca | 822 | it87_update_pwm_ctrl(data, i); |
0624d861 | 823 | } |
c1e7a4ca GR |
824 | |
825 | data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); | |
826 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); | |
827 | /* | |
828 | * The IT8705F does not have VID capability. | |
829 | * The IT8718F and later don't use IT87_REG_VID for the | |
830 | * same purpose. | |
831 | */ | |
832 | if (data->type == it8712 || data->type == it8716) { | |
833 | data->vid = it87_read_value(data, IT87_REG_VID); | |
834 | /* | |
835 | * The older IT8712F revisions had only 5 VID pins, | |
836 | * but we assume it is always safe to read 6 bits. | |
837 | */ | |
838 | data->vid &= 0x3f; | |
839 | } | |
840 | data->last_updated = jiffies; | |
841 | data->valid = 1; | |
842 | } | |
843 | ||
844 | mutex_unlock(&data->update_lock); | |
845 | ||
846 | return data; | |
847 | } | |
fde09509 | 848 | |
20ad93d4 | 849 | static ssize_t show_in(struct device *dev, struct device_attribute *attr, |
929c6a56 | 850 | char *buf) |
1da177e4 | 851 | { |
929c6a56 | 852 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
c962024e | 853 | struct it87_data *data = it87_update_device(dev); |
929c6a56 | 854 | int index = sattr->index; |
c962024e | 855 | int nr = sattr->nr; |
20ad93d4 | 856 | |
929c6a56 | 857 | return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); |
1da177e4 LT |
858 | } |
859 | ||
929c6a56 GR |
860 | static ssize_t set_in(struct device *dev, struct device_attribute *attr, |
861 | const char *buf, size_t count) | |
1da177e4 | 862 | { |
929c6a56 | 863 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
b74f3fdd | 864 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e GR |
865 | int index = sattr->index; |
866 | int nr = sattr->nr; | |
f5f64501 JD |
867 | unsigned long val; |
868 | ||
179c4fdb | 869 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 870 | return -EINVAL; |
1da177e4 | 871 | |
9a61bf63 | 872 | mutex_lock(&data->update_lock); |
929c6a56 GR |
873 | data->in[nr][index] = in_to_reg(data, nr, val); |
874 | it87_write_value(data, | |
875 | index == 1 ? IT87_REG_VIN_MIN(nr) | |
876 | : IT87_REG_VIN_MAX(nr), | |
877 | data->in[nr][index]); | |
9a61bf63 | 878 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
879 | return count; |
880 | } | |
20ad93d4 | 881 | |
929c6a56 GR |
882 | static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); |
883 | static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
884 | 0, 1); | |
885 | static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
886 | 0, 2); | |
f5f64501 | 887 | |
929c6a56 GR |
888 | static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); |
889 | static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
890 | 1, 1); | |
891 | static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
892 | 1, 2); | |
1da177e4 | 893 | |
929c6a56 GR |
894 | static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); |
895 | static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
896 | 2, 1); | |
897 | static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
898 | 2, 2); | |
1da177e4 | 899 | |
929c6a56 GR |
900 | static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); |
901 | static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
902 | 3, 1); | |
903 | static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
904 | 3, 2); | |
905 | ||
906 | static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); | |
907 | static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
908 | 4, 1); | |
909 | static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
910 | 4, 2); | |
911 | ||
912 | static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); | |
913 | static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
914 | 5, 1); | |
915 | static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
916 | 5, 2); | |
917 | ||
918 | static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); | |
919 | static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
920 | 6, 1); | |
921 | static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
922 | 6, 2); | |
923 | ||
924 | static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); | |
925 | static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, | |
926 | 7, 1); | |
927 | static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, | |
928 | 7, 2); | |
929 | ||
930 | static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); | |
c145d5c6 | 931 | static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); |
f838aa26 GR |
932 | static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); |
933 | static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); | |
934 | static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); | |
1da177e4 | 935 | |
cc18da79 | 936 | /* Up to 6 temperatures */ |
20ad93d4 | 937 | static ssize_t show_temp(struct device *dev, struct device_attribute *attr, |
60ca385a | 938 | char *buf) |
1da177e4 | 939 | { |
60ca385a GR |
940 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
941 | int nr = sattr->nr; | |
942 | int index = sattr->index; | |
1da177e4 | 943 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 944 | |
60ca385a | 945 | return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); |
1da177e4 | 946 | } |
20ad93d4 | 947 | |
60ca385a GR |
948 | static ssize_t set_temp(struct device *dev, struct device_attribute *attr, |
949 | const char *buf, size_t count) | |
1da177e4 | 950 | { |
60ca385a GR |
951 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
952 | int nr = sattr->nr; | |
953 | int index = sattr->index; | |
b74f3fdd | 954 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 955 | long val; |
161d898a | 956 | u8 reg, regval; |
f5f64501 | 957 | |
179c4fdb | 958 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 959 | return -EINVAL; |
1da177e4 | 960 | |
9a61bf63 | 961 | mutex_lock(&data->update_lock); |
161d898a GR |
962 | |
963 | switch (index) { | |
964 | default: | |
965 | case 1: | |
966 | reg = IT87_REG_TEMP_LOW(nr); | |
967 | break; | |
968 | case 2: | |
969 | reg = IT87_REG_TEMP_HIGH(nr); | |
970 | break; | |
971 | case 3: | |
972 | regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
973 | if (!(regval & 0x80)) { | |
974 | regval |= 0x80; | |
975 | it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); | |
976 | } | |
977 | data->valid = 0; | |
978 | reg = IT87_REG_TEMP_OFFSET[nr]; | |
979 | break; | |
980 | } | |
981 | ||
60ca385a | 982 | data->temp[nr][index] = TEMP_TO_REG(val); |
161d898a | 983 | it87_write_value(data, reg, data->temp[nr][index]); |
9a61bf63 | 984 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
985 | return count; |
986 | } | |
1da177e4 | 987 | |
60ca385a GR |
988 | static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); |
989 | static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
990 | 0, 1); | |
991 | static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
992 | 0, 2); | |
161d898a GR |
993 | static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, |
994 | set_temp, 0, 3); | |
60ca385a GR |
995 | static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); |
996 | static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
997 | 1, 1); | |
998 | static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
999 | 1, 2); | |
161d898a GR |
1000 | static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, |
1001 | set_temp, 1, 3); | |
60ca385a GR |
1002 | static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); |
1003 | static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1004 | 2, 1); | |
1005 | static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, | |
1006 | 2, 2); | |
161d898a GR |
1007 | static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, |
1008 | set_temp, 2, 3); | |
cc18da79 GR |
1009 | static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); |
1010 | static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); | |
1011 | static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); | |
1da177e4 | 1012 | |
2cece01f GR |
1013 | static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, |
1014 | char *buf) | |
1da177e4 | 1015 | { |
20ad93d4 JD |
1016 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1017 | int nr = sensor_attr->index; | |
1da177e4 | 1018 | struct it87_data *data = it87_update_device(dev); |
4a0d71cf | 1019 | u8 reg = data->sensor; /* In case value is updated while used */ |
19529784 | 1020 | u8 extra = data->extra; |
5f2dc798 | 1021 | |
c962024e GR |
1022 | if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || |
1023 | (has_temp_old_peci(data, nr) && (extra & 0x80))) | |
5d8d2f2b | 1024 | return sprintf(buf, "6\n"); /* Intel PECI */ |
1da177e4 LT |
1025 | if (reg & (1 << nr)) |
1026 | return sprintf(buf, "3\n"); /* thermal diode */ | |
1027 | if (reg & (8 << nr)) | |
4ed10779 | 1028 | return sprintf(buf, "4\n"); /* thermistor */ |
1da177e4 LT |
1029 | return sprintf(buf, "0\n"); /* disabled */ |
1030 | } | |
2cece01f GR |
1031 | |
1032 | static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, | |
1033 | const char *buf, size_t count) | |
1da177e4 | 1034 | { |
20ad93d4 JD |
1035 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
1036 | int nr = sensor_attr->index; | |
1037 | ||
b74f3fdd | 1038 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1039 | long val; |
19529784 | 1040 | u8 reg, extra; |
f5f64501 | 1041 | |
179c4fdb | 1042 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 | 1043 | return -EINVAL; |
1da177e4 | 1044 | |
8acf07c5 JD |
1045 | reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); |
1046 | reg &= ~(1 << nr); | |
1047 | reg &= ~(8 << nr); | |
5d8d2f2b GR |
1048 | if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) |
1049 | reg &= 0x3f; | |
19529784 GR |
1050 | extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); |
1051 | if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) | |
1052 | extra &= 0x7f; | |
4ed10779 | 1053 | if (val == 2) { /* backwards compatibility */ |
1d9bcf6a GR |
1054 | dev_warn(dev, |
1055 | "Sensor type 2 is deprecated, please use 4 instead\n"); | |
4ed10779 JD |
1056 | val = 4; |
1057 | } | |
5d8d2f2b | 1058 | /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ |
1da177e4 | 1059 | if (val == 3) |
8acf07c5 | 1060 | reg |= 1 << nr; |
4ed10779 | 1061 | else if (val == 4) |
8acf07c5 | 1062 | reg |= 8 << nr; |
5d8d2f2b GR |
1063 | else if (has_temp_peci(data, nr) && val == 6) |
1064 | reg |= (nr + 1) << 6; | |
19529784 GR |
1065 | else if (has_temp_old_peci(data, nr) && val == 6) |
1066 | extra |= 0x80; | |
8acf07c5 | 1067 | else if (val != 0) |
1da177e4 | 1068 | return -EINVAL; |
8acf07c5 JD |
1069 | |
1070 | mutex_lock(&data->update_lock); | |
1071 | data->sensor = reg; | |
19529784 | 1072 | data->extra = extra; |
b74f3fdd | 1073 | it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); |
19529784 GR |
1074 | if (has_temp_old_peci(data, nr)) |
1075 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
2b3d1d87 | 1076 | data->valid = 0; /* Force cache refresh */ |
9a61bf63 | 1077 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1078 | return count; |
1079 | } | |
1da177e4 | 1080 | |
2cece01f GR |
1081 | static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, |
1082 | set_temp_type, 0); | |
1083 | static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1084 | set_temp_type, 1); | |
1085 | static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, | |
1086 | set_temp_type, 2); | |
1da177e4 | 1087 | |
f1bbe618 | 1088 | /* 6 Fans */ |
b99883dc JD |
1089 | |
1090 | static int pwm_mode(const struct it87_data *data, int nr) | |
1091 | { | |
f1bbe618 GR |
1092 | if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) |
1093 | return 0; /* Full speed */ | |
1094 | if (data->pwm_ctrl[nr] & 0x80) | |
1095 | return 2; /* Automatic mode */ | |
1096 | if ((data->type == it8603 || nr >= 3) && | |
1097 | data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) | |
1098 | return 0; /* Full speed */ | |
1099 | ||
1100 | return 1; /* Manual mode */ | |
b99883dc JD |
1101 | } |
1102 | ||
20ad93d4 | 1103 | static ssize_t show_fan(struct device *dev, struct device_attribute *attr, |
e1169ba0 | 1104 | char *buf) |
1da177e4 | 1105 | { |
e1169ba0 GR |
1106 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1107 | int nr = sattr->nr; | |
1108 | int index = sattr->index; | |
1109 | int speed; | |
1da177e4 | 1110 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 | 1111 | |
e1169ba0 GR |
1112 | speed = has_16bit_fans(data) ? |
1113 | FAN16_FROM_REG(data->fan[nr][index]) : | |
1114 | FAN_FROM_REG(data->fan[nr][index], | |
1115 | DIV_FROM_REG(data->fan_div[nr])); | |
1116 | return sprintf(buf, "%d\n", speed); | |
1da177e4 | 1117 | } |
e1169ba0 | 1118 | |
20ad93d4 | 1119 | static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1120 | char *buf) |
1da177e4 | 1121 | { |
20ad93d4 | 1122 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1123 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1124 | int nr = sensor_attr->index; |
1125 | ||
48b2ae7f | 1126 | return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 | 1127 | } |
c962024e | 1128 | |
5f2dc798 | 1129 | static ssize_t show_pwm_enable(struct device *dev, |
c962024e | 1130 | struct device_attribute *attr, char *buf) |
1da177e4 | 1131 | { |
20ad93d4 | 1132 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1133 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1134 | int nr = sensor_attr->index; |
1135 | ||
b99883dc | 1136 | return sprintf(buf, "%d\n", pwm_mode(data, nr)); |
1da177e4 | 1137 | } |
c962024e | 1138 | |
20ad93d4 | 1139 | static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1140 | char *buf) |
1da177e4 | 1141 | { |
20ad93d4 | 1142 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
c962024e | 1143 | struct it87_data *data = it87_update_device(dev); |
20ad93d4 JD |
1144 | int nr = sensor_attr->index; |
1145 | ||
44c1bcd4 JD |
1146 | return sprintf(buf, "%d\n", |
1147 | pwm_from_reg(data, data->pwm_duty[nr])); | |
1da177e4 | 1148 | } |
c962024e | 1149 | |
f8d0c19a | 1150 | static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, |
c962024e | 1151 | char *buf) |
f8d0c19a | 1152 | { |
60878bcf | 1153 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
f8d0c19a | 1154 | struct it87_data *data = it87_update_device(dev); |
60878bcf | 1155 | int nr = sensor_attr->index; |
f56c9c0a | 1156 | unsigned int freq; |
60878bcf GR |
1157 | int index; |
1158 | ||
1159 | if (has_pwm_freq2(data) && nr == 1) | |
1160 | index = (data->extra >> 4) & 0x07; | |
1161 | else | |
1162 | index = (data->fan_ctl >> 4) & 0x07; | |
f8d0c19a | 1163 | |
f56c9c0a GR |
1164 | freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); |
1165 | ||
1166 | return sprintf(buf, "%u\n", freq); | |
f8d0c19a | 1167 | } |
e1169ba0 GR |
1168 | |
1169 | static ssize_t set_fan(struct device *dev, struct device_attribute *attr, | |
1170 | const char *buf, size_t count) | |
1da177e4 | 1171 | { |
e1169ba0 GR |
1172 | struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); |
1173 | int nr = sattr->nr; | |
1174 | int index = sattr->index; | |
20ad93d4 | 1175 | |
b74f3fdd | 1176 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 | 1177 | long val; |
7f999aa7 | 1178 | u8 reg; |
1da177e4 | 1179 | |
179c4fdb | 1180 | if (kstrtol(buf, 10, &val) < 0) |
f5f64501 JD |
1181 | return -EINVAL; |
1182 | ||
9a61bf63 | 1183 | mutex_lock(&data->update_lock); |
e1169ba0 GR |
1184 | |
1185 | if (has_16bit_fans(data)) { | |
1186 | data->fan[nr][index] = FAN16_TO_REG(val); | |
1187 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1188 | data->fan[nr][index] & 0xff); | |
1189 | it87_write_value(data, IT87_REG_FANX_MIN[nr], | |
1190 | data->fan[nr][index] >> 8); | |
1191 | } else { | |
1192 | reg = it87_read_value(data, IT87_REG_FAN_DIV); | |
1193 | switch (nr) { | |
1194 | case 0: | |
1195 | data->fan_div[nr] = reg & 0x07; | |
1196 | break; | |
1197 | case 1: | |
1198 | data->fan_div[nr] = (reg >> 3) & 0x07; | |
1199 | break; | |
1200 | case 2: | |
1201 | data->fan_div[nr] = (reg & 0x40) ? 3 : 1; | |
1202 | break; | |
1203 | } | |
1204 | data->fan[nr][index] = | |
1205 | FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); | |
1206 | it87_write_value(data, IT87_REG_FAN_MIN[nr], | |
1207 | data->fan[nr][index]); | |
07eab46d JD |
1208 | } |
1209 | ||
9a61bf63 | 1210 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1211 | return count; |
1212 | } | |
e1169ba0 | 1213 | |
20ad93d4 | 1214 | static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, |
c962024e | 1215 | const char *buf, size_t count) |
1da177e4 | 1216 | { |
20ad93d4 | 1217 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1218 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1219 | int nr = sensor_attr->index; |
f5f64501 | 1220 | unsigned long val; |
8ab4ec3e | 1221 | int min; |
1da177e4 LT |
1222 | u8 old; |
1223 | ||
179c4fdb | 1224 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 JD |
1225 | return -EINVAL; |
1226 | ||
9a61bf63 | 1227 | mutex_lock(&data->update_lock); |
b74f3fdd | 1228 | old = it87_read_value(data, IT87_REG_FAN_DIV); |
1da177e4 | 1229 | |
8ab4ec3e | 1230 | /* Save fan min limit */ |
e1169ba0 | 1231 | min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); |
1da177e4 LT |
1232 | |
1233 | switch (nr) { | |
1234 | case 0: | |
1235 | case 1: | |
1236 | data->fan_div[nr] = DIV_TO_REG(val); | |
1237 | break; | |
1238 | case 2: | |
1239 | if (val < 8) | |
1240 | data->fan_div[nr] = 1; | |
1241 | else | |
1242 | data->fan_div[nr] = 3; | |
1243 | } | |
1244 | val = old & 0x80; | |
1245 | val |= (data->fan_div[0] & 0x07); | |
1246 | val |= (data->fan_div[1] & 0x07) << 3; | |
1247 | if (data->fan_div[2] == 3) | |
1248 | val |= 0x1 << 6; | |
b74f3fdd | 1249 | it87_write_value(data, IT87_REG_FAN_DIV, val); |
1da177e4 | 1250 | |
8ab4ec3e | 1251 | /* Restore fan min limit */ |
e1169ba0 GR |
1252 | data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); |
1253 | it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); | |
8ab4ec3e | 1254 | |
9a61bf63 | 1255 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1256 | return count; |
1257 | } | |
cccfc9c4 JD |
1258 | |
1259 | /* Returns 0 if OK, -EINVAL otherwise */ | |
1260 | static int check_trip_points(struct device *dev, int nr) | |
1261 | { | |
1262 | const struct it87_data *data = dev_get_drvdata(dev); | |
1263 | int i, err = 0; | |
1264 | ||
1265 | if (has_old_autopwm(data)) { | |
1266 | for (i = 0; i < 3; i++) { | |
1267 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1268 | err = -EINVAL; | |
1269 | } | |
1270 | for (i = 0; i < 2; i++) { | |
1271 | if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) | |
1272 | err = -EINVAL; | |
1273 | } | |
2cbb9c37 GR |
1274 | } else if (has_newer_autopwm(data)) { |
1275 | for (i = 1; i < 3; i++) { | |
1276 | if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) | |
1277 | err = -EINVAL; | |
1278 | } | |
cccfc9c4 JD |
1279 | } |
1280 | ||
1281 | if (err) { | |
1d9bcf6a GR |
1282 | dev_err(dev, |
1283 | "Inconsistent trip points, not switching to automatic mode\n"); | |
cccfc9c4 JD |
1284 | dev_err(dev, "Adjust the trip points and try again\n"); |
1285 | } | |
1286 | return err; | |
1287 | } | |
1288 | ||
c962024e GR |
1289 | static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, |
1290 | const char *buf, size_t count) | |
1da177e4 | 1291 | { |
20ad93d4 | 1292 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1293 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1294 | int nr = sensor_attr->index; |
f5f64501 | 1295 | long val; |
1da177e4 | 1296 | |
179c4fdb | 1297 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) |
b99883dc JD |
1298 | return -EINVAL; |
1299 | ||
cccfc9c4 JD |
1300 | /* Check trip points before switching to automatic mode */ |
1301 | if (val == 2) { | |
1302 | if (check_trip_points(dev, nr) < 0) | |
1303 | return -EINVAL; | |
1304 | } | |
1305 | ||
9a61bf63 | 1306 | mutex_lock(&data->update_lock); |
1da177e4 LT |
1307 | |
1308 | if (val == 0) { | |
f1bbe618 GR |
1309 | if (nr < 3 && data->type != it8603) { |
1310 | int tmp; | |
1311 | /* make sure the fan is on when in on/off mode */ | |
1312 | tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
1313 | it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); | |
1314 | /* set on/off mode */ | |
1315 | data->fan_main_ctrl &= ~BIT(nr); | |
1316 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
1317 | data->fan_main_ctrl); | |
1318 | } else { | |
1319 | /* No on/off mode, set maximum pwm value */ | |
1320 | data->pwm_duty[nr] = pwm_to_reg(data, 0xff); | |
1321 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], | |
1322 | data->pwm_duty[nr]); | |
1323 | /* and set manual mode */ | |
1324 | data->pwm_ctrl[nr] = has_newer_autopwm(data) ? | |
1325 | data->pwm_temp_map[nr] : | |
1326 | data->pwm_duty[nr]; | |
1327 | it87_write_value(data, IT87_REG_PWM[nr], | |
1328 | data->pwm_ctrl[nr]); | |
1329 | } | |
b99883dc JD |
1330 | } else { |
1331 | if (val == 1) /* Manual mode */ | |
16b5dda2 | 1332 | data->pwm_ctrl[nr] = has_newer_autopwm(data) ? |
6229cdb2 JD |
1333 | data->pwm_temp_map[nr] : |
1334 | data->pwm_duty[nr]; | |
b99883dc JD |
1335 | else /* Automatic mode */ |
1336 | data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; | |
36c4d98a | 1337 | it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); |
c145d5c6 | 1338 | |
f1bbe618 | 1339 | if (data->type != it8603 && nr < 3) { |
c145d5c6 | 1340 | /* set SmartGuardian mode */ |
48b2ae7f | 1341 | data->fan_main_ctrl |= BIT(nr); |
c145d5c6 RM |
1342 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, |
1343 | data->fan_main_ctrl); | |
1344 | } | |
1da177e4 LT |
1345 | } |
1346 | ||
9a61bf63 | 1347 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1348 | return count; |
1349 | } | |
c962024e | 1350 | |
20ad93d4 | 1351 | static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, |
c962024e | 1352 | const char *buf, size_t count) |
1da177e4 | 1353 | { |
20ad93d4 | 1354 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1355 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1356 | int nr = sensor_attr->index; |
f5f64501 | 1357 | long val; |
1da177e4 | 1358 | |
179c4fdb | 1359 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
1da177e4 LT |
1360 | return -EINVAL; |
1361 | ||
9a61bf63 | 1362 | mutex_lock(&data->update_lock); |
82dbe987 | 1363 | it87_update_pwm_ctrl(data, nr); |
16b5dda2 | 1364 | if (has_newer_autopwm(data)) { |
4a0d71cf GR |
1365 | /* |
1366 | * If we are in automatic mode, the PWM duty cycle register | |
1367 | * is read-only so we can't write the value. | |
1368 | */ | |
6229cdb2 JD |
1369 | if (data->pwm_ctrl[nr] & 0x80) { |
1370 | mutex_unlock(&data->update_lock); | |
1371 | return -EBUSY; | |
1372 | } | |
1373 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
36c4d98a | 1374 | it87_write_value(data, IT87_REG_PWM_DUTY[nr], |
6229cdb2 JD |
1375 | data->pwm_duty[nr]); |
1376 | } else { | |
1377 | data->pwm_duty[nr] = pwm_to_reg(data, val); | |
4a0d71cf GR |
1378 | /* |
1379 | * If we are in manual mode, write the duty cycle immediately; | |
1380 | * otherwise, just store it for later use. | |
1381 | */ | |
6229cdb2 JD |
1382 | if (!(data->pwm_ctrl[nr] & 0x80)) { |
1383 | data->pwm_ctrl[nr] = data->pwm_duty[nr]; | |
36c4d98a | 1384 | it87_write_value(data, IT87_REG_PWM[nr], |
6229cdb2 JD |
1385 | data->pwm_ctrl[nr]); |
1386 | } | |
b99883dc | 1387 | } |
9a61bf63 | 1388 | mutex_unlock(&data->update_lock); |
1da177e4 LT |
1389 | return count; |
1390 | } | |
c962024e GR |
1391 | |
1392 | static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, | |
1393 | const char *buf, size_t count) | |
f8d0c19a | 1394 | { |
60878bcf | 1395 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); |
b74f3fdd | 1396 | struct it87_data *data = dev_get_drvdata(dev); |
60878bcf | 1397 | int nr = sensor_attr->index; |
f5f64501 | 1398 | unsigned long val; |
f8d0c19a JD |
1399 | int i; |
1400 | ||
179c4fdb | 1401 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1402 | return -EINVAL; |
f56c9c0a GR |
1403 | |
1404 | val = clamp_val(val, 0, 1000000); | |
1405 | val *= has_newer_autopwm(data) ? 256 : 128; | |
f5f64501 | 1406 | |
f8d0c19a JD |
1407 | /* Search for the nearest available frequency */ |
1408 | for (i = 0; i < 7; i++) { | |
c962024e | 1409 | if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) |
f8d0c19a JD |
1410 | break; |
1411 | } | |
1412 | ||
1413 | mutex_lock(&data->update_lock); | |
60878bcf GR |
1414 | if (nr == 0) { |
1415 | data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; | |
1416 | data->fan_ctl |= i << 4; | |
1417 | it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); | |
1418 | } else { | |
1419 | data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; | |
1420 | data->extra |= i << 4; | |
1421 | it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); | |
1422 | } | |
f8d0c19a JD |
1423 | mutex_unlock(&data->update_lock); |
1424 | ||
1425 | return count; | |
1426 | } | |
c962024e | 1427 | |
94ac7ee6 | 1428 | static ssize_t show_pwm_temp_map(struct device *dev, |
c962024e | 1429 | struct device_attribute *attr, char *buf) |
94ac7ee6 JD |
1430 | { |
1431 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1432 | struct it87_data *data = it87_update_device(dev); |
c962024e | 1433 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1434 | int map; |
1435 | ||
0624d861 GR |
1436 | map = data->pwm_temp_map[nr]; |
1437 | if (map >= 3) | |
1438 | map = 0; /* Should never happen */ | |
1439 | if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ | |
1440 | map += 3; | |
1441 | ||
1442 | return sprintf(buf, "%d\n", (int)BIT(map)); | |
94ac7ee6 | 1443 | } |
c962024e | 1444 | |
94ac7ee6 | 1445 | static ssize_t set_pwm_temp_map(struct device *dev, |
c962024e GR |
1446 | struct device_attribute *attr, const char *buf, |
1447 | size_t count) | |
94ac7ee6 JD |
1448 | { |
1449 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
94ac7ee6 | 1450 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1451 | int nr = sensor_attr->index; |
94ac7ee6 JD |
1452 | long val; |
1453 | u8 reg; | |
1454 | ||
179c4fdb | 1455 | if (kstrtol(buf, 10, &val) < 0) |
94ac7ee6 JD |
1456 | return -EINVAL; |
1457 | ||
0624d861 GR |
1458 | if (nr >= 3) |
1459 | val -= 3; | |
1460 | ||
94ac7ee6 | 1461 | switch (val) { |
48b2ae7f | 1462 | case BIT(0): |
94ac7ee6 JD |
1463 | reg = 0x00; |
1464 | break; | |
48b2ae7f | 1465 | case BIT(1): |
94ac7ee6 JD |
1466 | reg = 0x01; |
1467 | break; | |
48b2ae7f | 1468 | case BIT(2): |
94ac7ee6 JD |
1469 | reg = 0x02; |
1470 | break; | |
1471 | default: | |
1472 | return -EINVAL; | |
1473 | } | |
1474 | ||
1475 | mutex_lock(&data->update_lock); | |
82dbe987 | 1476 | it87_update_pwm_ctrl(data, nr); |
94ac7ee6 | 1477 | data->pwm_temp_map[nr] = reg; |
4a0d71cf GR |
1478 | /* |
1479 | * If we are in automatic mode, write the temp mapping immediately; | |
1480 | * otherwise, just store it for later use. | |
1481 | */ | |
94ac7ee6 JD |
1482 | if (data->pwm_ctrl[nr] & 0x80) { |
1483 | data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; | |
36c4d98a | 1484 | it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); |
94ac7ee6 JD |
1485 | } |
1486 | mutex_unlock(&data->update_lock); | |
1487 | return count; | |
1488 | } | |
1da177e4 | 1489 | |
c962024e GR |
1490 | static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, |
1491 | char *buf) | |
4f3f51bc JD |
1492 | { |
1493 | struct it87_data *data = it87_update_device(dev); | |
1494 | struct sensor_device_attribute_2 *sensor_attr = | |
1495 | to_sensor_dev_attr_2(attr); | |
1496 | int nr = sensor_attr->nr; | |
1497 | int point = sensor_attr->index; | |
1498 | ||
44c1bcd4 JD |
1499 | return sprintf(buf, "%d\n", |
1500 | pwm_from_reg(data, data->auto_pwm[nr][point])); | |
4f3f51bc JD |
1501 | } |
1502 | ||
c962024e GR |
1503 | static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, |
1504 | const char *buf, size_t count) | |
4f3f51bc JD |
1505 | { |
1506 | struct it87_data *data = dev_get_drvdata(dev); | |
1507 | struct sensor_device_attribute_2 *sensor_attr = | |
1508 | to_sensor_dev_attr_2(attr); | |
1509 | int nr = sensor_attr->nr; | |
1510 | int point = sensor_attr->index; | |
2cbb9c37 | 1511 | int regaddr; |
4f3f51bc JD |
1512 | long val; |
1513 | ||
179c4fdb | 1514 | if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) |
4f3f51bc JD |
1515 | return -EINVAL; |
1516 | ||
1517 | mutex_lock(&data->update_lock); | |
44c1bcd4 | 1518 | data->auto_pwm[nr][point] = pwm_to_reg(data, val); |
2cbb9c37 GR |
1519 | if (has_newer_autopwm(data)) |
1520 | regaddr = IT87_REG_AUTO_TEMP(nr, 3); | |
1521 | else | |
1522 | regaddr = IT87_REG_AUTO_PWM(nr, point); | |
1523 | it87_write_value(data, regaddr, data->auto_pwm[nr][point]); | |
1524 | mutex_unlock(&data->update_lock); | |
1525 | return count; | |
1526 | } | |
1527 | ||
1528 | static ssize_t show_auto_pwm_slope(struct device *dev, | |
1529 | struct device_attribute *attr, char *buf) | |
1530 | { | |
1531 | struct it87_data *data = it87_update_device(dev); | |
1532 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1533 | int nr = sensor_attr->index; | |
1534 | ||
1535 | return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); | |
1536 | } | |
1537 | ||
1538 | static ssize_t set_auto_pwm_slope(struct device *dev, | |
1539 | struct device_attribute *attr, | |
1540 | const char *buf, size_t count) | |
1541 | { | |
1542 | struct it87_data *data = dev_get_drvdata(dev); | |
1543 | struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); | |
1544 | int nr = sensor_attr->index; | |
1545 | unsigned long val; | |
1546 | ||
1547 | if (kstrtoul(buf, 10, &val) < 0 || val > 127) | |
1548 | return -EINVAL; | |
1549 | ||
1550 | mutex_lock(&data->update_lock); | |
1551 | data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; | |
1552 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), | |
1553 | data->auto_pwm[nr][1]); | |
4f3f51bc JD |
1554 | mutex_unlock(&data->update_lock); |
1555 | return count; | |
1556 | } | |
1557 | ||
c962024e GR |
1558 | static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, |
1559 | char *buf) | |
4f3f51bc JD |
1560 | { |
1561 | struct it87_data *data = it87_update_device(dev); | |
1562 | struct sensor_device_attribute_2 *sensor_attr = | |
1563 | to_sensor_dev_attr_2(attr); | |
1564 | int nr = sensor_attr->nr; | |
1565 | int point = sensor_attr->index; | |
2cbb9c37 GR |
1566 | int reg; |
1567 | ||
1568 | if (has_old_autopwm(data) || point) | |
1569 | reg = data->auto_temp[nr][point]; | |
1570 | else | |
1571 | reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); | |
4f3f51bc | 1572 | |
2cbb9c37 | 1573 | return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); |
4f3f51bc JD |
1574 | } |
1575 | ||
c962024e GR |
1576 | static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, |
1577 | const char *buf, size_t count) | |
4f3f51bc JD |
1578 | { |
1579 | struct it87_data *data = dev_get_drvdata(dev); | |
1580 | struct sensor_device_attribute_2 *sensor_attr = | |
1581 | to_sensor_dev_attr_2(attr); | |
1582 | int nr = sensor_attr->nr; | |
1583 | int point = sensor_attr->index; | |
1584 | long val; | |
2cbb9c37 | 1585 | int reg; |
4f3f51bc | 1586 | |
179c4fdb | 1587 | if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) |
4f3f51bc JD |
1588 | return -EINVAL; |
1589 | ||
1590 | mutex_lock(&data->update_lock); | |
2cbb9c37 GR |
1591 | if (has_newer_autopwm(data) && !point) { |
1592 | reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); | |
1593 | reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); | |
1594 | data->auto_temp[nr][0] = reg; | |
1595 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); | |
1596 | } else { | |
1597 | reg = TEMP_TO_REG(val); | |
1598 | data->auto_temp[nr][point] = reg; | |
1599 | if (has_newer_autopwm(data)) | |
1600 | point--; | |
1601 | it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); | |
1602 | } | |
4f3f51bc JD |
1603 | mutex_unlock(&data->update_lock); |
1604 | return count; | |
1605 | } | |
1606 | ||
e1169ba0 GR |
1607 | static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); |
1608 | static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1609 | 0, 1); | |
1610 | static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1611 | set_fan_div, 0); | |
1612 | ||
1613 | static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); | |
1614 | static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1615 | 1, 1); | |
1616 | static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1617 | set_fan_div, 1); | |
1618 | ||
1619 | static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); | |
1620 | static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1621 | 2, 1); | |
1622 | static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, | |
1623 | set_fan_div, 2); | |
1624 | ||
1625 | static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); | |
1626 | static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1627 | 3, 1); | |
1da177e4 | 1628 | |
e1169ba0 GR |
1629 | static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); |
1630 | static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1631 | 4, 1); | |
1da177e4 | 1632 | |
fa3f70d6 GR |
1633 | static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); |
1634 | static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, | |
1635 | 5, 1); | |
1636 | ||
c4458db3 GR |
1637 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, |
1638 | show_pwm_enable, set_pwm_enable, 0); | |
1639 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); | |
60878bcf GR |
1640 | static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, |
1641 | set_pwm_freq, 0); | |
5c391261 | 1642 | static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1643 | show_pwm_temp_map, set_pwm_temp_map, 0); |
1644 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1645 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1646 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1647 | show_auto_pwm, set_auto_pwm, 0, 1); | |
1648 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1649 | show_auto_pwm, set_auto_pwm, 0, 2); | |
1650 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, | |
1651 | show_auto_pwm, NULL, 0, 3); | |
1652 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1653 | show_auto_temp, set_auto_temp, 0, 1); | |
1654 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1655 | show_auto_temp, set_auto_temp, 0, 0); | |
1656 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1657 | show_auto_temp, set_auto_temp, 0, 2); | |
1658 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1659 | show_auto_temp, set_auto_temp, 0, 3); | |
1660 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1661 | show_auto_temp, set_auto_temp, 0, 4); | |
2cbb9c37 GR |
1662 | static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, |
1663 | show_auto_pwm, set_auto_pwm, 0, 0); | |
1664 | static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, | |
1665 | show_auto_pwm_slope, set_auto_pwm_slope, 0); | |
c4458db3 GR |
1666 | |
1667 | static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, | |
1668 | show_pwm_enable, set_pwm_enable, 1); | |
1669 | static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); | |
60878bcf | 1670 | static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); |
5c391261 | 1671 | static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1672 | show_pwm_temp_map, set_pwm_temp_map, 1); |
1673 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1674 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1675 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1676 | show_auto_pwm, set_auto_pwm, 1, 1); | |
1677 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1678 | show_auto_pwm, set_auto_pwm, 1, 2); | |
1679 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, | |
1680 | show_auto_pwm, NULL, 1, 3); | |
1681 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1682 | show_auto_temp, set_auto_temp, 1, 1); | |
1683 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1684 | show_auto_temp, set_auto_temp, 1, 0); | |
1685 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1686 | show_auto_temp, set_auto_temp, 1, 2); | |
1687 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1688 | show_auto_temp, set_auto_temp, 1, 3); | |
1689 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1690 | show_auto_temp, set_auto_temp, 1, 4); | |
2cbb9c37 GR |
1691 | static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, |
1692 | show_auto_pwm, set_auto_pwm, 1, 0); | |
1693 | static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, | |
1694 | show_auto_pwm_slope, set_auto_pwm_slope, 1); | |
c4458db3 GR |
1695 | |
1696 | static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, | |
1697 | show_pwm_enable, set_pwm_enable, 2); | |
1698 | static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); | |
60878bcf | 1699 | static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); |
5c391261 | 1700 | static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, |
c4458db3 GR |
1701 | show_pwm_temp_map, set_pwm_temp_map, 2); |
1702 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, | |
1703 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1704 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, | |
1705 | show_auto_pwm, set_auto_pwm, 2, 1); | |
1706 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, | |
1707 | show_auto_pwm, set_auto_pwm, 2, 2); | |
1708 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, | |
1709 | show_auto_pwm, NULL, 2, 3); | |
1710 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, | |
1711 | show_auto_temp, set_auto_temp, 2, 1); | |
1712 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1713 | show_auto_temp, set_auto_temp, 2, 0); | |
1714 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1715 | show_auto_temp, set_auto_temp, 2, 2); | |
1716 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1717 | show_auto_temp, set_auto_temp, 2, 3); | |
1718 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, | |
1719 | show_auto_temp, set_auto_temp, 2, 4); | |
2cbb9c37 GR |
1720 | static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, |
1721 | show_auto_pwm, set_auto_pwm, 2, 0); | |
1722 | static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, | |
1723 | show_auto_pwm_slope, set_auto_pwm_slope, 2); | |
1da177e4 | 1724 | |
36c4d98a GR |
1725 | static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, |
1726 | show_pwm_enable, set_pwm_enable, 3); | |
1727 | static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); | |
60878bcf | 1728 | static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); |
5c391261 | 1729 | static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, |
36c4d98a | 1730 | show_pwm_temp_map, set_pwm_temp_map, 3); |
2cbb9c37 GR |
1731 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, |
1732 | show_auto_temp, set_auto_temp, 2, 1); | |
1733 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1734 | show_auto_temp, set_auto_temp, 2, 0); | |
1735 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1736 | show_auto_temp, set_auto_temp, 2, 2); | |
1737 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1738 | show_auto_temp, set_auto_temp, 2, 3); | |
1739 | static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, | |
1740 | show_auto_pwm, set_auto_pwm, 3, 0); | |
1741 | static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, | |
1742 | show_auto_pwm_slope, set_auto_pwm_slope, 3); | |
36c4d98a GR |
1743 | |
1744 | static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, | |
1745 | show_pwm_enable, set_pwm_enable, 4); | |
1746 | static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); | |
60878bcf | 1747 | static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); |
5c391261 | 1748 | static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, |
36c4d98a | 1749 | show_pwm_temp_map, set_pwm_temp_map, 4); |
2cbb9c37 GR |
1750 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, |
1751 | show_auto_temp, set_auto_temp, 2, 1); | |
1752 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1753 | show_auto_temp, set_auto_temp, 2, 0); | |
1754 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1755 | show_auto_temp, set_auto_temp, 2, 2); | |
1756 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1757 | show_auto_temp, set_auto_temp, 2, 3); | |
1758 | static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, | |
1759 | show_auto_pwm, set_auto_pwm, 4, 0); | |
1760 | static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, | |
1761 | show_auto_pwm_slope, set_auto_pwm_slope, 4); | |
36c4d98a GR |
1762 | |
1763 | static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, | |
1764 | show_pwm_enable, set_pwm_enable, 5); | |
1765 | static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); | |
60878bcf | 1766 | static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); |
5c391261 | 1767 | static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, |
36c4d98a | 1768 | show_pwm_temp_map, set_pwm_temp_map, 5); |
2cbb9c37 GR |
1769 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, |
1770 | show_auto_temp, set_auto_temp, 2, 1); | |
1771 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, | |
1772 | show_auto_temp, set_auto_temp, 2, 0); | |
1773 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, | |
1774 | show_auto_temp, set_auto_temp, 2, 2); | |
1775 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, | |
1776 | show_auto_temp, set_auto_temp, 2, 3); | |
1777 | static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, | |
1778 | show_auto_pwm, set_auto_pwm, 5, 0); | |
1779 | static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, | |
1780 | show_auto_pwm_slope, set_auto_pwm_slope, 5); | |
36c4d98a | 1781 | |
1da177e4 | 1782 | /* Alarms */ |
ddc64ae8 | 1783 | static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, |
c962024e | 1784 | char *buf) |
1da177e4 LT |
1785 | { |
1786 | struct it87_data *data = it87_update_device(dev); | |
c962024e | 1787 | |
68188ba7 | 1788 | return sprintf(buf, "%u\n", data->alarms); |
1da177e4 | 1789 | } |
ddc64ae8 | 1790 | static DEVICE_ATTR_RO(alarms); |
1da177e4 | 1791 | |
0124dd78 | 1792 | static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, |
c962024e | 1793 | char *buf) |
0124dd78 | 1794 | { |
0124dd78 | 1795 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1796 | int bitnr = to_sensor_dev_attr(attr)->index; |
1797 | ||
0124dd78 JD |
1798 | return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); |
1799 | } | |
3d30f9e6 | 1800 | |
c962024e GR |
1801 | static ssize_t clear_intrusion(struct device *dev, |
1802 | struct device_attribute *attr, const char *buf, | |
1803 | size_t count) | |
3d30f9e6 JD |
1804 | { |
1805 | struct it87_data *data = dev_get_drvdata(dev); | |
3d30f9e6 | 1806 | int config; |
c962024e | 1807 | long val; |
3d30f9e6 | 1808 | |
179c4fdb | 1809 | if (kstrtol(buf, 10, &val) < 0 || val != 0) |
3d30f9e6 JD |
1810 | return -EINVAL; |
1811 | ||
1812 | mutex_lock(&data->update_lock); | |
1813 | config = it87_read_value(data, IT87_REG_CONFIG); | |
1814 | if (config < 0) { | |
1815 | count = config; | |
1816 | } else { | |
48b2ae7f | 1817 | config |= BIT(5); |
3d30f9e6 JD |
1818 | it87_write_value(data, IT87_REG_CONFIG, config); |
1819 | /* Invalidate cache to force re-read */ | |
1820 | data->valid = 0; | |
1821 | } | |
1822 | mutex_unlock(&data->update_lock); | |
1823 | ||
1824 | return count; | |
1825 | } | |
1826 | ||
0124dd78 JD |
1827 | static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); |
1828 | static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); | |
1829 | static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); | |
1830 | static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); | |
1831 | static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); | |
1832 | static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); | |
1833 | static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); | |
1834 | static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); | |
1835 | static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); | |
1836 | static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); | |
1837 | static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); | |
1838 | static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); | |
1839 | static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); | |
fa3f70d6 | 1840 | static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); |
0124dd78 JD |
1841 | static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); |
1842 | static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); | |
1843 | static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); | |
3d30f9e6 JD |
1844 | static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, |
1845 | show_alarm, clear_intrusion, 4); | |
0124dd78 | 1846 | |
d9b327c3 | 1847 | static ssize_t show_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1848 | char *buf) |
d9b327c3 | 1849 | { |
d9b327c3 | 1850 | struct it87_data *data = it87_update_device(dev); |
c962024e GR |
1851 | int bitnr = to_sensor_dev_attr(attr)->index; |
1852 | ||
d9b327c3 JD |
1853 | return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); |
1854 | } | |
c962024e | 1855 | |
d9b327c3 | 1856 | static ssize_t set_beep(struct device *dev, struct device_attribute *attr, |
c962024e | 1857 | const char *buf, size_t count) |
d9b327c3 JD |
1858 | { |
1859 | int bitnr = to_sensor_dev_attr(attr)->index; | |
1860 | struct it87_data *data = dev_get_drvdata(dev); | |
1861 | long val; | |
1862 | ||
c962024e | 1863 | if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) |
d9b327c3 JD |
1864 | return -EINVAL; |
1865 | ||
1866 | mutex_lock(&data->update_lock); | |
1867 | data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); | |
1868 | if (val) | |
48b2ae7f | 1869 | data->beeps |= BIT(bitnr); |
d9b327c3 | 1870 | else |
48b2ae7f | 1871 | data->beeps &= ~BIT(bitnr); |
d9b327c3 JD |
1872 | it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); |
1873 | mutex_unlock(&data->update_lock); | |
1874 | return count; | |
1875 | } | |
1876 | ||
1877 | static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, | |
1878 | show_beep, set_beep, 1); | |
1879 | static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); | |
1880 | static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); | |
1881 | static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); | |
1882 | static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); | |
1883 | static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); | |
1884 | static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); | |
1885 | static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); | |
1886 | /* fanX_beep writability is set later */ | |
1887 | static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); | |
1888 | static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); | |
1889 | static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); | |
1890 | static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); | |
1891 | static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); | |
fa3f70d6 | 1892 | static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); |
d9b327c3 JD |
1893 | static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, |
1894 | show_beep, set_beep, 2); | |
1895 | static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); | |
1896 | static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); | |
1897 | ||
ddc64ae8 JL |
1898 | static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, |
1899 | char *buf) | |
1da177e4 | 1900 | { |
90d6619a | 1901 | struct it87_data *data = dev_get_drvdata(dev); |
c962024e | 1902 | |
a7be58a1 | 1903 | return sprintf(buf, "%u\n", data->vrm); |
1da177e4 | 1904 | } |
c962024e | 1905 | |
ddc64ae8 JL |
1906 | static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, |
1907 | const char *buf, size_t count) | |
1da177e4 | 1908 | { |
b74f3fdd | 1909 | struct it87_data *data = dev_get_drvdata(dev); |
f5f64501 JD |
1910 | unsigned long val; |
1911 | ||
179c4fdb | 1912 | if (kstrtoul(buf, 10, &val) < 0) |
f5f64501 | 1913 | return -EINVAL; |
1da177e4 | 1914 | |
1da177e4 LT |
1915 | data->vrm = val; |
1916 | ||
1917 | return count; | |
1918 | } | |
ddc64ae8 | 1919 | static DEVICE_ATTR_RW(vrm); |
1da177e4 | 1920 | |
ddc64ae8 JL |
1921 | static ssize_t cpu0_vid_show(struct device *dev, |
1922 | struct device_attribute *attr, char *buf) | |
1da177e4 LT |
1923 | { |
1924 | struct it87_data *data = it87_update_device(dev); | |
c962024e GR |
1925 | |
1926 | return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); | |
1da177e4 | 1927 | } |
ddc64ae8 | 1928 | static DEVICE_ATTR_RO(cpu0_vid); |
87808be4 | 1929 | |
738e5e05 | 1930 | static ssize_t show_label(struct device *dev, struct device_attribute *attr, |
c962024e | 1931 | char *buf) |
738e5e05 | 1932 | { |
3c4c4971 | 1933 | static const char * const labels[] = { |
738e5e05 JD |
1934 | "+5V", |
1935 | "5VSB", | |
1936 | "Vbat", | |
638c1c07 | 1937 | "AVCC", |
738e5e05 | 1938 | }; |
3c4c4971 | 1939 | static const char * const labels_it8721[] = { |
44c1bcd4 JD |
1940 | "+3.3V", |
1941 | "3VSB", | |
1942 | "Vbat", | |
638c1c07 | 1943 | "+3.3V", |
44c1bcd4 JD |
1944 | }; |
1945 | struct it87_data *data = dev_get_drvdata(dev); | |
738e5e05 | 1946 | int nr = to_sensor_dev_attr(attr)->index; |
ead80803 | 1947 | const char *label; |
738e5e05 | 1948 | |
a9eebd4f GR |
1949 | if (has_vin3_5v(data) && nr == 0) |
1950 | label = labels[0]; | |
1951 | else if (has_12mv_adc(data) || has_10_9mv_adc(data)) | |
ead80803 JM |
1952 | label = labels_it8721[nr]; |
1953 | else | |
1954 | label = labels[nr]; | |
1955 | ||
1956 | return sprintf(buf, "%s\n", label); | |
738e5e05 JD |
1957 | } |
1958 | static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); | |
1959 | static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); | |
1960 | static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); | |
73055405 | 1961 | /* AVCC3 */ |
638c1c07 | 1962 | static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); |
738e5e05 | 1963 | |
52929715 GR |
1964 | static umode_t it87_in_is_visible(struct kobject *kobj, |
1965 | struct attribute *attr, int index) | |
9172b5d1 | 1966 | { |
52929715 GR |
1967 | struct device *dev = container_of(kobj, struct device, kobj); |
1968 | struct it87_data *data = dev_get_drvdata(dev); | |
1969 | int i = index / 5; /* voltage index */ | |
1970 | int a = index % 5; /* attribute index */ | |
1971 | ||
f838aa26 | 1972 | if (index >= 40) { /* in8 and higher only have input attributes */ |
52929715 GR |
1973 | i = index - 40 + 8; |
1974 | a = 0; | |
1975 | } | |
1976 | ||
48b2ae7f | 1977 | if (!(data->has_in & BIT(i))) |
52929715 GR |
1978 | return 0; |
1979 | ||
1980 | if (a == 4 && !data->has_beep) | |
1981 | return 0; | |
1982 | ||
1983 | return attr->mode; | |
1984 | } | |
1985 | ||
1986 | static struct attribute *it87_attributes_in[] = { | |
87808be4 | 1987 | &sensor_dev_attr_in0_input.dev_attr.attr, |
87808be4 | 1988 | &sensor_dev_attr_in0_min.dev_attr.attr, |
87808be4 | 1989 | &sensor_dev_attr_in0_max.dev_attr.attr, |
0124dd78 | 1990 | &sensor_dev_attr_in0_alarm.dev_attr.attr, |
52929715 GR |
1991 | &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ |
1992 | ||
9172b5d1 GR |
1993 | &sensor_dev_attr_in1_input.dev_attr.attr, |
1994 | &sensor_dev_attr_in1_min.dev_attr.attr, | |
1995 | &sensor_dev_attr_in1_max.dev_attr.attr, | |
0124dd78 | 1996 | &sensor_dev_attr_in1_alarm.dev_attr.attr, |
52929715 GR |
1997 | &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ |
1998 | ||
9172b5d1 GR |
1999 | &sensor_dev_attr_in2_input.dev_attr.attr, |
2000 | &sensor_dev_attr_in2_min.dev_attr.attr, | |
2001 | &sensor_dev_attr_in2_max.dev_attr.attr, | |
0124dd78 | 2002 | &sensor_dev_attr_in2_alarm.dev_attr.attr, |
52929715 GR |
2003 | &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ |
2004 | ||
9172b5d1 GR |
2005 | &sensor_dev_attr_in3_input.dev_attr.attr, |
2006 | &sensor_dev_attr_in3_min.dev_attr.attr, | |
2007 | &sensor_dev_attr_in3_max.dev_attr.attr, | |
0124dd78 | 2008 | &sensor_dev_attr_in3_alarm.dev_attr.attr, |
52929715 GR |
2009 | &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ |
2010 | ||
9172b5d1 GR |
2011 | &sensor_dev_attr_in4_input.dev_attr.attr, |
2012 | &sensor_dev_attr_in4_min.dev_attr.attr, | |
2013 | &sensor_dev_attr_in4_max.dev_attr.attr, | |
0124dd78 | 2014 | &sensor_dev_attr_in4_alarm.dev_attr.attr, |
52929715 GR |
2015 | &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ |
2016 | ||
9172b5d1 GR |
2017 | &sensor_dev_attr_in5_input.dev_attr.attr, |
2018 | &sensor_dev_attr_in5_min.dev_attr.attr, | |
2019 | &sensor_dev_attr_in5_max.dev_attr.attr, | |
0124dd78 | 2020 | &sensor_dev_attr_in5_alarm.dev_attr.attr, |
52929715 GR |
2021 | &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ |
2022 | ||
9172b5d1 GR |
2023 | &sensor_dev_attr_in6_input.dev_attr.attr, |
2024 | &sensor_dev_attr_in6_min.dev_attr.attr, | |
2025 | &sensor_dev_attr_in6_max.dev_attr.attr, | |
0124dd78 | 2026 | &sensor_dev_attr_in6_alarm.dev_attr.attr, |
52929715 GR |
2027 | &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ |
2028 | ||
9172b5d1 GR |
2029 | &sensor_dev_attr_in7_input.dev_attr.attr, |
2030 | &sensor_dev_attr_in7_min.dev_attr.attr, | |
2031 | &sensor_dev_attr_in7_max.dev_attr.attr, | |
0124dd78 | 2032 | &sensor_dev_attr_in7_alarm.dev_attr.attr, |
52929715 GR |
2033 | &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ |
2034 | ||
2035 | &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ | |
d5f3f6c8 JD |
2036 | &sensor_dev_attr_in9_input.dev_attr.attr, |
2037 | &sensor_dev_attr_in10_input.dev_attr.attr, | |
2038 | &sensor_dev_attr_in11_input.dev_attr.attr, | |
2039 | &sensor_dev_attr_in12_input.dev_attr.attr, | |
3c329263 | 2040 | NULL |
52929715 GR |
2041 | }; |
2042 | ||
2043 | static const struct attribute_group it87_group_in = { | |
2044 | .attrs = it87_attributes_in, | |
2045 | .is_visible = it87_in_is_visible, | |
9172b5d1 GR |
2046 | }; |
2047 | ||
87533770 GR |
2048 | static umode_t it87_temp_is_visible(struct kobject *kobj, |
2049 | struct attribute *attr, int index) | |
4573acbc | 2050 | { |
87533770 GR |
2051 | struct device *dev = container_of(kobj, struct device, kobj); |
2052 | struct it87_data *data = dev_get_drvdata(dev); | |
2053 | int i = index / 7; /* temperature index */ | |
2054 | int a = index % 7; /* attribute index */ | |
2055 | ||
cc18da79 GR |
2056 | if (index >= 21) { |
2057 | i = index - 21 + 3; | |
2058 | a = 0; | |
2059 | } | |
2060 | ||
48b2ae7f | 2061 | if (!(data->has_temp & BIT(i))) |
87533770 GR |
2062 | return 0; |
2063 | ||
2064 | if (a == 5 && !has_temp_offset(data)) | |
2065 | return 0; | |
2066 | ||
2067 | if (a == 6 && !data->has_beep) | |
2068 | return 0; | |
2069 | ||
2070 | return attr->mode; | |
2071 | } | |
2072 | ||
2073 | static struct attribute *it87_attributes_temp[] = { | |
87808be4 | 2074 | &sensor_dev_attr_temp1_input.dev_attr.attr, |
87808be4 | 2075 | &sensor_dev_attr_temp1_max.dev_attr.attr, |
87808be4 | 2076 | &sensor_dev_attr_temp1_min.dev_attr.attr, |
87808be4 | 2077 | &sensor_dev_attr_temp1_type.dev_attr.attr, |
0124dd78 | 2078 | &sensor_dev_attr_temp1_alarm.dev_attr.attr, |
87533770 GR |
2079 | &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ |
2080 | &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ | |
2081 | ||
cc18da79 | 2082 | &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ |
4573acbc GR |
2083 | &sensor_dev_attr_temp2_max.dev_attr.attr, |
2084 | &sensor_dev_attr_temp2_min.dev_attr.attr, | |
2085 | &sensor_dev_attr_temp2_type.dev_attr.attr, | |
0124dd78 | 2086 | &sensor_dev_attr_temp2_alarm.dev_attr.attr, |
87533770 GR |
2087 | &sensor_dev_attr_temp2_offset.dev_attr.attr, |
2088 | &sensor_dev_attr_temp2_beep.dev_attr.attr, | |
2089 | ||
cc18da79 | 2090 | &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ |
4573acbc GR |
2091 | &sensor_dev_attr_temp3_max.dev_attr.attr, |
2092 | &sensor_dev_attr_temp3_min.dev_attr.attr, | |
2093 | &sensor_dev_attr_temp3_type.dev_attr.attr, | |
0124dd78 | 2094 | &sensor_dev_attr_temp3_alarm.dev_attr.attr, |
87533770 GR |
2095 | &sensor_dev_attr_temp3_offset.dev_attr.attr, |
2096 | &sensor_dev_attr_temp3_beep.dev_attr.attr, | |
4573acbc | 2097 | |
cc18da79 GR |
2098 | &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ |
2099 | &sensor_dev_attr_temp5_input.dev_attr.attr, | |
2100 | &sensor_dev_attr_temp6_input.dev_attr.attr, | |
87533770 | 2101 | NULL |
4573acbc | 2102 | }; |
87808be4 | 2103 | |
87533770 GR |
2104 | static const struct attribute_group it87_group_temp = { |
2105 | .attrs = it87_attributes_temp, | |
2106 | .is_visible = it87_temp_is_visible, | |
161d898a GR |
2107 | }; |
2108 | ||
d3766848 GR |
2109 | static umode_t it87_is_visible(struct kobject *kobj, |
2110 | struct attribute *attr, int index) | |
2111 | { | |
2112 | struct device *dev = container_of(kobj, struct device, kobj); | |
2113 | struct it87_data *data = dev_get_drvdata(dev); | |
2114 | ||
8638d0af | 2115 | if ((index == 2 || index == 3) && !data->has_vid) |
d3766848 GR |
2116 | return 0; |
2117 | ||
48b2ae7f | 2118 | if (index > 3 && !(data->in_internal & BIT(index - 4))) |
d3766848 GR |
2119 | return 0; |
2120 | ||
2121 | return attr->mode; | |
2122 | } | |
2123 | ||
4573acbc | 2124 | static struct attribute *it87_attributes[] = { |
87808be4 | 2125 | &dev_attr_alarms.attr, |
3d30f9e6 | 2126 | &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, |
8638d0af GR |
2127 | &dev_attr_vrm.attr, /* 2 */ |
2128 | &dev_attr_cpu0_vid.attr, /* 3 */ | |
2129 | &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ | |
d3766848 GR |
2130 | &sensor_dev_attr_in7_label.dev_attr.attr, |
2131 | &sensor_dev_attr_in8_label.dev_attr.attr, | |
2132 | &sensor_dev_attr_in9_label.dev_attr.attr, | |
87808be4 JD |
2133 | NULL |
2134 | }; | |
2135 | ||
2136 | static const struct attribute_group it87_group = { | |
2137 | .attrs = it87_attributes, | |
d3766848 | 2138 | .is_visible = it87_is_visible, |
87808be4 JD |
2139 | }; |
2140 | ||
9a70ee81 GR |
2141 | static umode_t it87_fan_is_visible(struct kobject *kobj, |
2142 | struct attribute *attr, int index) | |
2143 | { | |
2144 | struct device *dev = container_of(kobj, struct device, kobj); | |
2145 | struct it87_data *data = dev_get_drvdata(dev); | |
2146 | int i = index / 5; /* fan index */ | |
2147 | int a = index % 5; /* attribute index */ | |
2148 | ||
2149 | if (index >= 15) { /* fan 4..6 don't have divisor attributes */ | |
2150 | i = (index - 15) / 4 + 3; | |
2151 | a = (index - 15) % 4; | |
2152 | } | |
2153 | ||
48b2ae7f | 2154 | if (!(data->has_fan & BIT(i))) |
9a70ee81 GR |
2155 | return 0; |
2156 | ||
2157 | if (a == 3) { /* beep */ | |
2158 | if (!data->has_beep) | |
2159 | return 0; | |
2160 | /* first fan beep attribute is writable */ | |
2161 | if (i == __ffs(data->has_fan)) | |
2162 | return attr->mode | S_IWUSR; | |
2163 | } | |
2164 | ||
2165 | if (a == 4 && has_16bit_fans(data)) /* divisor */ | |
2166 | return 0; | |
2167 | ||
2168 | return attr->mode; | |
2169 | } | |
2170 | ||
2171 | static struct attribute *it87_attributes_fan[] = { | |
e1169ba0 GR |
2172 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
2173 | &sensor_dev_attr_fan1_min.dev_attr.attr, | |
723a0aa0 | 2174 | &sensor_dev_attr_fan1_alarm.dev_attr.attr, |
9a70ee81 GR |
2175 | &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ |
2176 | &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ | |
2177 | ||
e1169ba0 GR |
2178 | &sensor_dev_attr_fan2_input.dev_attr.attr, |
2179 | &sensor_dev_attr_fan2_min.dev_attr.attr, | |
723a0aa0 | 2180 | &sensor_dev_attr_fan2_alarm.dev_attr.attr, |
9a70ee81 GR |
2181 | &sensor_dev_attr_fan2_beep.dev_attr.attr, |
2182 | &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ | |
2183 | ||
e1169ba0 GR |
2184 | &sensor_dev_attr_fan3_input.dev_attr.attr, |
2185 | &sensor_dev_attr_fan3_min.dev_attr.attr, | |
723a0aa0 | 2186 | &sensor_dev_attr_fan3_alarm.dev_attr.attr, |
9a70ee81 GR |
2187 | &sensor_dev_attr_fan3_beep.dev_attr.attr, |
2188 | &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ | |
2189 | ||
2190 | &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ | |
e1169ba0 | 2191 | &sensor_dev_attr_fan4_min.dev_attr.attr, |
723a0aa0 | 2192 | &sensor_dev_attr_fan4_alarm.dev_attr.attr, |
9a70ee81 GR |
2193 | &sensor_dev_attr_fan4_beep.dev_attr.attr, |
2194 | ||
2195 | &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ | |
e1169ba0 | 2196 | &sensor_dev_attr_fan5_min.dev_attr.attr, |
723a0aa0 | 2197 | &sensor_dev_attr_fan5_alarm.dev_attr.attr, |
9a70ee81 GR |
2198 | &sensor_dev_attr_fan5_beep.dev_attr.attr, |
2199 | ||
2200 | &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ | |
fa3f70d6 GR |
2201 | &sensor_dev_attr_fan6_min.dev_attr.attr, |
2202 | &sensor_dev_attr_fan6_alarm.dev_attr.attr, | |
9a70ee81 | 2203 | &sensor_dev_attr_fan6_beep.dev_attr.attr, |
fa3f70d6 | 2204 | NULL |
723a0aa0 | 2205 | }; |
87808be4 | 2206 | |
9a70ee81 GR |
2207 | static const struct attribute_group it87_group_fan = { |
2208 | .attrs = it87_attributes_fan, | |
2209 | .is_visible = it87_fan_is_visible, | |
723a0aa0 JD |
2210 | }; |
2211 | ||
5c391261 GR |
2212 | static umode_t it87_pwm_is_visible(struct kobject *kobj, |
2213 | struct attribute *attr, int index) | |
2214 | { | |
2215 | struct device *dev = container_of(kobj, struct device, kobj); | |
2216 | struct it87_data *data = dev_get_drvdata(dev); | |
2217 | int i = index / 4; /* pwm index */ | |
2218 | int a = index % 4; /* attribute index */ | |
2219 | ||
48b2ae7f | 2220 | if (!(data->has_pwm & BIT(i))) |
5c391261 GR |
2221 | return 0; |
2222 | ||
2cbb9c37 GR |
2223 | /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ |
2224 | if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) | |
5c391261 GR |
2225 | return attr->mode | S_IWUSR; |
2226 | ||
2227 | /* pwm2_freq is writable if there are two pwm frequency selects */ | |
2228 | if (has_pwm_freq2(data) && i == 1 && a == 2) | |
2229 | return attr->mode | S_IWUSR; | |
2230 | ||
2231 | return attr->mode; | |
2232 | } | |
2233 | ||
2234 | static struct attribute *it87_attributes_pwm[] = { | |
87808be4 | 2235 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, |
87808be4 | 2236 | &sensor_dev_attr_pwm1.dev_attr.attr, |
60878bcf | 2237 | &sensor_dev_attr_pwm1_freq.dev_attr.attr, |
94ac7ee6 | 2238 | &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, |
5c391261 | 2239 | |
723a0aa0 JD |
2240 | &sensor_dev_attr_pwm2_enable.dev_attr.attr, |
2241 | &sensor_dev_attr_pwm2.dev_attr.attr, | |
60878bcf | 2242 | &sensor_dev_attr_pwm2_freq.dev_attr.attr, |
94ac7ee6 | 2243 | &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, |
5c391261 | 2244 | |
723a0aa0 JD |
2245 | &sensor_dev_attr_pwm3_enable.dev_attr.attr, |
2246 | &sensor_dev_attr_pwm3.dev_attr.attr, | |
60878bcf | 2247 | &sensor_dev_attr_pwm3_freq.dev_attr.attr, |
94ac7ee6 | 2248 | &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, |
5c391261 | 2249 | |
36c4d98a GR |
2250 | &sensor_dev_attr_pwm4_enable.dev_attr.attr, |
2251 | &sensor_dev_attr_pwm4.dev_attr.attr, | |
60878bcf | 2252 | &sensor_dev_attr_pwm4_freq.dev_attr.attr, |
36c4d98a | 2253 | &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, |
5c391261 | 2254 | |
36c4d98a GR |
2255 | &sensor_dev_attr_pwm5_enable.dev_attr.attr, |
2256 | &sensor_dev_attr_pwm5.dev_attr.attr, | |
60878bcf | 2257 | &sensor_dev_attr_pwm5_freq.dev_attr.attr, |
36c4d98a | 2258 | &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, |
5c391261 | 2259 | |
36c4d98a GR |
2260 | &sensor_dev_attr_pwm6_enable.dev_attr.attr, |
2261 | &sensor_dev_attr_pwm6.dev_attr.attr, | |
60878bcf | 2262 | &sensor_dev_attr_pwm6_freq.dev_attr.attr, |
36c4d98a | 2263 | &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, |
5c391261 | 2264 | |
36c4d98a | 2265 | NULL |
5c391261 | 2266 | }; |
87808be4 | 2267 | |
5c391261 GR |
2268 | static const struct attribute_group it87_group_pwm = { |
2269 | .attrs = it87_attributes_pwm, | |
2270 | .is_visible = it87_pwm_is_visible, | |
2271 | }; | |
2272 | ||
2273 | static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, | |
2274 | struct attribute *attr, int index) | |
60878bcf GR |
2275 | { |
2276 | struct device *dev = container_of(kobj, struct device, kobj); | |
2277 | struct it87_data *data = dev_get_drvdata(dev); | |
2cbb9c37 GR |
2278 | int i = index / 11; /* pwm index */ |
2279 | int a = index % 11; /* attribute index */ | |
2280 | ||
2281 | if (index >= 33) { /* pwm 4..6 */ | |
2282 | i = (index - 33) / 6 + 3; | |
2283 | a = (index - 33) % 6 + 4; | |
2284 | } | |
60878bcf | 2285 | |
48b2ae7f | 2286 | if (!(data->has_pwm & BIT(i))) |
5c391261 | 2287 | return 0; |
60878bcf | 2288 | |
2cbb9c37 GR |
2289 | if (has_newer_autopwm(data)) { |
2290 | if (a < 4) /* no auto point pwm */ | |
2291 | return 0; | |
2292 | if (a == 8) /* no auto_point4 */ | |
2293 | return 0; | |
2294 | } | |
2295 | if (has_old_autopwm(data)) { | |
2296 | if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ | |
2297 | return 0; | |
2298 | } | |
2299 | ||
60878bcf GR |
2300 | return attr->mode; |
2301 | } | |
2302 | ||
5c391261 | 2303 | static struct attribute *it87_attributes_auto_pwm[] = { |
4f3f51bc JD |
2304 | &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, |
2305 | &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, | |
2306 | &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, | |
2307 | &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, | |
2308 | &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, | |
2309 | &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, | |
2310 | &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, | |
2311 | &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, | |
2312 | &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2313 | &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, |
2314 | &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, | |
5c391261 | 2315 | |
2cbb9c37 | 2316 | &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ |
4f3f51bc JD |
2317 | &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, |
2318 | &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, | |
2319 | &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, | |
2320 | &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, | |
2321 | &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, | |
2322 | &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, | |
2323 | &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, | |
2324 | &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2325 | &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, |
2326 | &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, | |
5c391261 | 2327 | |
2cbb9c37 | 2328 | &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ |
4f3f51bc JD |
2329 | &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, |
2330 | &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, | |
2331 | &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, | |
2332 | &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, | |
2333 | &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, | |
2334 | &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, | |
2335 | &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, | |
2336 | &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, | |
2cbb9c37 GR |
2337 | &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, |
2338 | &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, | |
2339 | ||
2340 | &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ | |
2341 | &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, | |
2342 | &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, | |
2343 | &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, | |
2344 | &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, | |
2345 | &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, | |
2346 | ||
2347 | &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, | |
2348 | &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, | |
2349 | &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, | |
2350 | &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, | |
2351 | &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, | |
2352 | &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, | |
2353 | ||
2354 | &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, | |
2355 | &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, | |
2356 | &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, | |
2357 | &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, | |
2358 | &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, | |
2359 | &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, | |
4f3f51bc | 2360 | |
5c391261 GR |
2361 | NULL, |
2362 | }; | |
2363 | ||
2364 | static const struct attribute_group it87_group_auto_pwm = { | |
2365 | .attrs = it87_attributes_auto_pwm, | |
2366 | .is_visible = it87_auto_pwm_is_visible, | |
4f3f51bc JD |
2367 | }; |
2368 | ||
2d8672c5 | 2369 | /* SuperIO detection - will change isa_address if a chip is found */ |
3c2e3512 GR |
2370 | static int __init it87_find(int sioaddr, unsigned short *address, |
2371 | struct it87_sio_data *sio_data) | |
1da177e4 | 2372 | { |
5b0380c9 | 2373 | int err; |
b74f3fdd | 2374 | u16 chip_type; |
98dd22c3 | 2375 | const char *board_vendor, *board_name; |
f83a9cb6 | 2376 | const struct it87_devices *config; |
1da177e4 | 2377 | |
3c2e3512 | 2378 | err = superio_enter(sioaddr); |
5b0380c9 NG |
2379 | if (err) |
2380 | return err; | |
2381 | ||
2382 | err = -ENODEV; | |
3c2e3512 | 2383 | chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID); |
b74f3fdd | 2384 | |
2385 | switch (chip_type) { | |
2386 | case IT8705F_DEVID: | |
2387 | sio_data->type = it87; | |
2388 | break; | |
2389 | case IT8712F_DEVID: | |
2390 | sio_data->type = it8712; | |
2391 | break; | |
2392 | case IT8716F_DEVID: | |
2393 | case IT8726F_DEVID: | |
2394 | sio_data->type = it8716; | |
2395 | break; | |
2396 | case IT8718F_DEVID: | |
2397 | sio_data->type = it8718; | |
2398 | break; | |
b4da93e4 JMS |
2399 | case IT8720F_DEVID: |
2400 | sio_data->type = it8720; | |
2401 | break; | |
44c1bcd4 JD |
2402 | case IT8721F_DEVID: |
2403 | sio_data->type = it8721; | |
2404 | break; | |
16b5dda2 JD |
2405 | case IT8728F_DEVID: |
2406 | sio_data->type = it8728; | |
2407 | break; | |
ead80803 JM |
2408 | case IT8732F_DEVID: |
2409 | sio_data->type = it8732; | |
2410 | break; | |
b0636707 GR |
2411 | case IT8771E_DEVID: |
2412 | sio_data->type = it8771; | |
2413 | break; | |
2414 | case IT8772E_DEVID: | |
2415 | sio_data->type = it8772; | |
2416 | break; | |
7bc32d29 GR |
2417 | case IT8781F_DEVID: |
2418 | sio_data->type = it8781; | |
2419 | break; | |
0531d98b GR |
2420 | case IT8782F_DEVID: |
2421 | sio_data->type = it8782; | |
2422 | break; | |
2423 | case IT8783E_DEVID: | |
2424 | sio_data->type = it8783; | |
2425 | break; | |
a0c1424a TL |
2426 | case IT8786E_DEVID: |
2427 | sio_data->type = it8786; | |
2428 | break; | |
4ee07157 GR |
2429 | case IT8790E_DEVID: |
2430 | sio_data->type = it8790; | |
2431 | break; | |
7183ae8c | 2432 | case IT8603E_DEVID: |
574e9bd8 | 2433 | case IT8623E_DEVID: |
c145d5c6 RM |
2434 | sio_data->type = it8603; |
2435 | break; | |
3ba9d977 GR |
2436 | case IT8620E_DEVID: |
2437 | sio_data->type = it8620; | |
2438 | break; | |
8af1abae GR |
2439 | case IT8622E_DEVID: |
2440 | sio_data->type = it8622; | |
2441 | break; | |
71a9c232 GR |
2442 | case IT8628E_DEVID: |
2443 | sio_data->type = it8628; | |
2444 | break; | |
b74f3fdd | 2445 | case 0xffff: /* No device at all */ |
2446 | goto exit; | |
2447 | default: | |
a8ca1037 | 2448 | pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); |
b74f3fdd | 2449 | goto exit; |
2450 | } | |
1da177e4 | 2451 | |
3c2e3512 GR |
2452 | superio_select(sioaddr, PME); |
2453 | if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { | |
a8ca1037 | 2454 | pr_info("Device not activated, skipping\n"); |
1da177e4 LT |
2455 | goto exit; |
2456 | } | |
2457 | ||
3c2e3512 | 2458 | *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); |
1da177e4 | 2459 | if (*address == 0) { |
a8ca1037 | 2460 | pr_info("Base address not set, skipping\n"); |
1da177e4 LT |
2461 | goto exit; |
2462 | } | |
2463 | ||
2464 | err = 0; | |
3c2e3512 | 2465 | sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; |
faf392fb GR |
2466 | pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type, |
2467 | it87_devices[sio_data->type].suffix, | |
a0c1424a | 2468 | *address, sio_data->revision); |
1da177e4 | 2469 | |
f83a9cb6 GR |
2470 | config = &it87_devices[sio_data->type]; |
2471 | ||
7f5726c3 | 2472 | /* in7 (VSB or VCCH5V) is always internal on some chips */ |
f83a9cb6 | 2473 | if (has_in7_internal(config)) |
48b2ae7f | 2474 | sio_data->internal |= BIT(1); |
7f5726c3 | 2475 | |
738e5e05 | 2476 | /* in8 (Vbat) is always internal */ |
48b2ae7f | 2477 | sio_data->internal |= BIT(2); |
7f5726c3 | 2478 | |
73055405 GR |
2479 | /* in9 (AVCC3), always internal if supported */ |
2480 | if (has_avcc3(config)) | |
48b2ae7f | 2481 | sio_data->internal |= BIT(3); /* in9 is AVCC */ |
73055405 | 2482 | else |
48b2ae7f | 2483 | sio_data->skip_in |= BIT(9); |
738e5e05 | 2484 | |
638c1c07 | 2485 | if (!has_five_pwm(config)) |
48b2ae7f | 2486 | sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); |
638c1c07 GR |
2487 | else if (!has_six_pwm(config)) |
2488 | sio_data->skip_pwm |= BIT(5); | |
36c4d98a | 2489 | |
f83a9cb6 | 2490 | if (!has_vid(config)) |
895ff267 | 2491 | sio_data->skip_vid = 1; |
d9b327c3 | 2492 | |
32dd7c40 GR |
2493 | /* Read GPIO config and VID value from LDN 7 (GPIO) */ |
2494 | if (sio_data->type == it87) { | |
d9b327c3 | 2495 | /* The IT8705F has a different LD number for GPIO */ |
3c2e3512 GR |
2496 | superio_select(sioaddr, 5); |
2497 | sio_data->beep_pin = superio_inb(sioaddr, | |
2498 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
0531d98b | 2499 | } else if (sio_data->type == it8783) { |
088ce2ac | 2500 | int reg25, reg27, reg2a, reg2c, regef; |
0531d98b | 2501 | |
3c2e3512 | 2502 | superio_select(sioaddr, GPIO); |
0531d98b | 2503 | |
3c2e3512 GR |
2504 | reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
2505 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2506 | reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); | |
2507 | reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2508 | regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); | |
0531d98b | 2509 | |
0531d98b | 2510 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2511 | if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) |
2512 | sio_data->skip_fan |= BIT(2); | |
c962024e GR |
2513 | if ((reg25 & BIT(4)) || |
2514 | (!(reg2a & BIT(1)) && (regef & BIT(0)))) | |
48b2ae7f | 2515 | sio_data->skip_pwm |= BIT(2); |
0531d98b GR |
2516 | |
2517 | /* Check if fan2 is there or not */ | |
48b2ae7f GR |
2518 | if (reg27 & BIT(7)) |
2519 | sio_data->skip_fan |= BIT(1); | |
2520 | if (reg27 & BIT(3)) | |
2521 | sio_data->skip_pwm |= BIT(1); | |
0531d98b GR |
2522 | |
2523 | /* VIN5 */ | |
48b2ae7f GR |
2524 | if ((reg27 & BIT(0)) || (reg2c & BIT(2))) |
2525 | sio_data->skip_in |= BIT(5); /* No VIN5 */ | |
0531d98b GR |
2526 | |
2527 | /* VIN6 */ | |
48b2ae7f GR |
2528 | if (reg27 & BIT(1)) |
2529 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
0531d98b GR |
2530 | |
2531 | /* | |
2532 | * VIN7 | |
2533 | * Does not depend on bit 2 of Reg2C, contrary to datasheet. | |
2534 | */ | |
48b2ae7f | 2535 | if (reg27 & BIT(2)) { |
9172b5d1 GR |
2536 | /* |
2537 | * The data sheet is a bit unclear regarding the | |
2538 | * internal voltage divider for VCCH5V. It says | |
2539 | * "This bit enables and switches VIN7 (pin 91) to the | |
2540 | * internal voltage divider for VCCH5V". | |
2541 | * This is different to other chips, where the internal | |
2542 | * voltage divider would connect VIN7 to an internal | |
2543 | * voltage source. Maybe that is the case here as well. | |
2544 | * | |
2545 | * Since we don't know for sure, re-route it if that is | |
2546 | * not the case, and ask the user to report if the | |
2547 | * resulting voltage is sane. | |
2548 | */ | |
48b2ae7f GR |
2549 | if (!(reg2c & BIT(1))) { |
2550 | reg2c |= BIT(1); | |
3c2e3512 GR |
2551 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, |
2552 | reg2c); | |
9172b5d1 GR |
2553 | pr_notice("Routing internal VCCH5V to in7.\n"); |
2554 | } | |
2555 | pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); | |
2556 | pr_notice("Please report if it displays a reasonable voltage.\n"); | |
2557 | } | |
0531d98b | 2558 | |
48b2ae7f GR |
2559 | if (reg2c & BIT(0)) |
2560 | sio_data->internal |= BIT(0); | |
2561 | if (reg2c & BIT(1)) | |
2562 | sio_data->internal |= BIT(1); | |
0531d98b | 2563 | |
3c2e3512 GR |
2564 | sio_data->beep_pin = superio_inb(sioaddr, |
2565 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
c145d5c6 RM |
2566 | } else if (sio_data->type == it8603) { |
2567 | int reg27, reg29; | |
2568 | ||
3c2e3512 | 2569 | superio_select(sioaddr, GPIO); |
0531d98b | 2570 | |
3c2e3512 | 2571 | reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
c145d5c6 RM |
2572 | |
2573 | /* Check if fan3 is there or not */ | |
48b2ae7f GR |
2574 | if (reg27 & BIT(6)) |
2575 | sio_data->skip_pwm |= BIT(2); | |
2576 | if (reg27 & BIT(7)) | |
2577 | sio_data->skip_fan |= BIT(2); | |
c145d5c6 RM |
2578 | |
2579 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2580 | reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2581 | if (reg29 & BIT(1)) |
2582 | sio_data->skip_pwm |= BIT(1); | |
2583 | if (reg29 & BIT(2)) | |
2584 | sio_data->skip_fan |= BIT(1); | |
c145d5c6 | 2585 | |
48b2ae7f GR |
2586 | sio_data->skip_in |= BIT(5); /* No VIN5 */ |
2587 | sio_data->skip_in |= BIT(6); /* No VIN6 */ | |
c145d5c6 | 2588 | |
3c2e3512 GR |
2589 | sio_data->beep_pin = superio_inb(sioaddr, |
2590 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
71a9c232 | 2591 | } else if (sio_data->type == it8620 || sio_data->type == it8628) { |
3ba9d977 GR |
2592 | int reg; |
2593 | ||
3c2e3512 | 2594 | superio_select(sioaddr, GPIO); |
3ba9d977 | 2595 | |
36c4d98a | 2596 | /* Check for pwm5 */ |
3c2e3512 | 2597 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); |
48b2ae7f GR |
2598 | if (reg & BIT(6)) |
2599 | sio_data->skip_pwm |= BIT(4); | |
36c4d98a | 2600 | |
3ba9d977 | 2601 | /* Check for fan4, fan5 */ |
3c2e3512 | 2602 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); |
48b2ae7f GR |
2603 | if (!(reg & BIT(5))) |
2604 | sio_data->skip_fan |= BIT(3); | |
2605 | if (!(reg & BIT(4))) | |
2606 | sio_data->skip_fan |= BIT(4); | |
3ba9d977 GR |
2607 | |
2608 | /* Check for pwm3, fan3 */ | |
3c2e3512 | 2609 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
48b2ae7f GR |
2610 | if (reg & BIT(6)) |
2611 | sio_data->skip_pwm |= BIT(2); | |
2612 | if (reg & BIT(7)) | |
2613 | sio_data->skip_fan |= BIT(2); | |
3ba9d977 | 2614 | |
36c4d98a | 2615 | /* Check for pwm4 */ |
3c2e3512 | 2616 | reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); |
d66777ca | 2617 | if (reg & BIT(2)) |
48b2ae7f | 2618 | sio_data->skip_pwm |= BIT(3); |
36c4d98a | 2619 | |
3ba9d977 | 2620 | /* Check for pwm2, fan2 */ |
3c2e3512 | 2621 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2622 | if (reg & BIT(1)) |
2623 | sio_data->skip_pwm |= BIT(1); | |
2624 | if (reg & BIT(2)) | |
2625 | sio_data->skip_fan |= BIT(1); | |
36c4d98a | 2626 | /* Check for pwm6, fan6 */ |
48b2ae7f GR |
2627 | if (!(reg & BIT(7))) { |
2628 | sio_data->skip_pwm |= BIT(5); | |
2629 | sio_data->skip_fan |= BIT(5); | |
36c4d98a | 2630 | } |
3ba9d977 | 2631 | |
638c1c07 GR |
2632 | /* Check if AVCC is on VIN3 */ |
2633 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2634 | if (reg & BIT(0)) | |
2635 | sio_data->internal |= BIT(0); | |
2636 | else | |
2637 | sio_data->skip_in |= BIT(9); | |
2638 | ||
2639 | sio_data->beep_pin = superio_inb(sioaddr, | |
2640 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
2641 | } else if (sio_data->type == it8622) { | |
2642 | int reg; | |
2643 | ||
2644 | superio_select(sioaddr, GPIO); | |
2645 | ||
2646 | /* Check for pwm4, fan4 */ | |
2647 | reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); | |
2648 | if (reg & BIT(6)) | |
2649 | sio_data->skip_fan |= BIT(3); | |
2650 | if (reg & BIT(5)) | |
2651 | sio_data->skip_pwm |= BIT(3); | |
2652 | ||
2653 | /* Check for pwm3, fan3, pwm5, fan5 */ | |
2654 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); | |
2655 | if (reg & BIT(6)) | |
2656 | sio_data->skip_pwm |= BIT(2); | |
2657 | if (reg & BIT(7)) | |
2658 | sio_data->skip_fan |= BIT(2); | |
2659 | if (reg & BIT(3)) | |
2660 | sio_data->skip_pwm |= BIT(4); | |
2661 | if (reg & BIT(1)) | |
2662 | sio_data->skip_fan |= BIT(4); | |
2663 | ||
2664 | /* Check for pwm2, fan2 */ | |
2665 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); | |
2666 | if (reg & BIT(1)) | |
2667 | sio_data->skip_pwm |= BIT(1); | |
2668 | if (reg & BIT(2)) | |
2669 | sio_data->skip_fan |= BIT(1); | |
2670 | ||
2671 | /* Check for AVCC */ | |
2672 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); | |
2673 | if (!(reg & BIT(0))) | |
2674 | sio_data->skip_in |= BIT(9); | |
2675 | ||
3c2e3512 GR |
2676 | sio_data->beep_pin = superio_inb(sioaddr, |
2677 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
895ff267 | 2678 | } else { |
87673dd7 | 2679 | int reg; |
9172b5d1 | 2680 | bool uart6; |
87673dd7 | 2681 | |
3c2e3512 | 2682 | superio_select(sioaddr, GPIO); |
44c1bcd4 | 2683 | |
a0df926d GR |
2684 | /* Check for fan4, fan5 */ |
2685 | if (has_five_fans(config)) { | |
2686 | reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); | |
2687 | switch (sio_data->type) { | |
2688 | case it8718: | |
2689 | if (reg & BIT(5)) | |
2690 | sio_data->skip_fan |= BIT(3); | |
2691 | if (reg & BIT(4)) | |
2692 | sio_data->skip_fan |= BIT(4); | |
2693 | break; | |
2694 | case it8720: | |
2695 | case it8721: | |
2696 | case it8728: | |
2697 | if (!(reg & BIT(5))) | |
2698 | sio_data->skip_fan |= BIT(3); | |
2699 | if (!(reg & BIT(4))) | |
2700 | sio_data->skip_fan |= BIT(4); | |
2701 | break; | |
2702 | default: | |
2703 | break; | |
2704 | } | |
2705 | } | |
2706 | ||
3c2e3512 | 2707 | reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); |
32dd7c40 | 2708 | if (!sio_data->skip_vid) { |
44c1bcd4 JD |
2709 | /* We need at least 4 VID pins */ |
2710 | if (reg & 0x0f) { | |
a8ca1037 | 2711 | pr_info("VID is disabled (pins used for GPIO)\n"); |
44c1bcd4 JD |
2712 | sio_data->skip_vid = 1; |
2713 | } | |
895ff267 JD |
2714 | } |
2715 | ||
591ec650 | 2716 | /* Check if fan3 is there or not */ |
48b2ae7f GR |
2717 | if (reg & BIT(6)) |
2718 | sio_data->skip_pwm |= BIT(2); | |
2719 | if (reg & BIT(7)) | |
2720 | sio_data->skip_fan |= BIT(2); | |
591ec650 JD |
2721 | |
2722 | /* Check if fan2 is there or not */ | |
3c2e3512 | 2723 | reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); |
48b2ae7f GR |
2724 | if (reg & BIT(1)) |
2725 | sio_data->skip_pwm |= BIT(1); | |
2726 | if (reg & BIT(2)) | |
2727 | sio_data->skip_fan |= BIT(1); | |
591ec650 | 2728 | |
c962024e GR |
2729 | if ((sio_data->type == it8718 || sio_data->type == it8720) && |
2730 | !(sio_data->skip_vid)) | |
3c2e3512 GR |
2731 | sio_data->vid_value = superio_inb(sioaddr, |
2732 | IT87_SIO_VID_REG); | |
87673dd7 | 2733 | |
3c2e3512 | 2734 | reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); |
9172b5d1 | 2735 | |
48b2ae7f | 2736 | uart6 = sio_data->type == it8782 && (reg & BIT(2)); |
9172b5d1 | 2737 | |
436cad2a JD |
2738 | /* |
2739 | * The IT8720F has no VIN7 pin, so VCCH should always be | |
2740 | * routed internally to VIN7 with an internal divider. | |
2741 | * Curiously, there still is a configuration bit to control | |
2742 | * this, which means it can be set incorrectly. And even | |
2743 | * more curiously, many boards out there are improperly | |
2744 | * configured, even though the IT8720F datasheet claims | |
2745 | * that the internal routing of VCCH to VIN7 is the default | |
2746 | * setting. So we force the internal routing in this case. | |
0531d98b GR |
2747 | * |
2748 | * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. | |
9172b5d1 GR |
2749 | * If UART6 is enabled, re-route VIN7 to the internal divider |
2750 | * if that is not already the case. | |
436cad2a | 2751 | */ |
48b2ae7f GR |
2752 | if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { |
2753 | reg |= BIT(1); | |
3c2e3512 | 2754 | superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); |
a8ca1037 | 2755 | pr_notice("Routing internal VCCH to in7\n"); |
436cad2a | 2756 | } |
48b2ae7f GR |
2757 | if (reg & BIT(0)) |
2758 | sio_data->internal |= BIT(0); | |
2759 | if (reg & BIT(1)) | |
2760 | sio_data->internal |= BIT(1); | |
d9b327c3 | 2761 | |
9172b5d1 GR |
2762 | /* |
2763 | * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. | |
2764 | * While VIN7 can be routed to the internal voltage divider, | |
2765 | * VIN5 and VIN6 are not available if UART6 is enabled. | |
4573acbc GR |
2766 | * |
2767 | * Also, temp3 is not available if UART6 is enabled and TEMPIN3 | |
2768 | * is the temperature source. Since we can not read the | |
2769 | * temperature source here, skip_temp is preliminary. | |
9172b5d1 | 2770 | */ |
4573acbc | 2771 | if (uart6) { |
48b2ae7f GR |
2772 | sio_data->skip_in |= BIT(5) | BIT(6); |
2773 | sio_data->skip_temp |= BIT(2); | |
4573acbc | 2774 | } |
9172b5d1 | 2775 | |
3c2e3512 GR |
2776 | sio_data->beep_pin = superio_inb(sioaddr, |
2777 | IT87_SIO_BEEP_PIN_REG) & 0x3f; | |
87673dd7 | 2778 | } |
d9b327c3 | 2779 | if (sio_data->beep_pin) |
a8ca1037 | 2780 | pr_info("Beeping is supported\n"); |
87673dd7 | 2781 | |
98dd22c3 JD |
2782 | /* Disable specific features based on DMI strings */ |
2783 | board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); | |
2784 | board_name = dmi_get_system_info(DMI_BOARD_NAME); | |
2785 | if (board_vendor && board_name) { | |
c962024e GR |
2786 | if (strcmp(board_vendor, "nVIDIA") == 0 && |
2787 | strcmp(board_name, "FN68PT") == 0) { | |
4a0d71cf GR |
2788 | /* |
2789 | * On the Shuttle SN68PT, FAN_CTL2 is apparently not | |
2790 | * connected to a fan, but to something else. One user | |
2791 | * has reported instant system power-off when changing | |
2792 | * the PWM2 duty cycle, so we disable it. | |
2793 | * I use the board name string as the trigger in case | |
2794 | * the same board is ever used in other systems. | |
2795 | */ | |
a8ca1037 | 2796 | pr_info("Disabling pwm2 due to hardware constraints\n"); |
48b2ae7f | 2797 | sio_data->skip_pwm = BIT(1); |
98dd22c3 JD |
2798 | } |
2799 | } | |
2800 | ||
1da177e4 | 2801 | exit: |
3c2e3512 | 2802 | superio_exit(sioaddr); |
1da177e4 LT |
2803 | return err; |
2804 | } | |
2805 | ||
c1e7a4ca GR |
2806 | /* Called when we have found a new IT87. */ |
2807 | static void it87_init_device(struct platform_device *pdev) | |
1da177e4 | 2808 | { |
c1e7a4ca GR |
2809 | struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); |
2810 | struct it87_data *data = platform_get_drvdata(pdev); | |
2811 | int tmp, i; | |
2812 | u8 mask; | |
b74f3fdd | 2813 | |
c1e7a4ca GR |
2814 | /* |
2815 | * For each PWM channel: | |
2816 | * - If it is in automatic mode, setting to manual mode should set | |
2817 | * the fan to full speed by default. | |
2818 | * - If it is in manual mode, we need a mapping to temperature | |
2819 | * channels to use when later setting to automatic mode later. | |
2820 | * Use a 1:1 mapping by default (we are clueless.) | |
2821 | * In both cases, the value can (and should) be changed by the user | |
2822 | * prior to switching to a different mode. | |
2823 | * Note that this is no longer needed for the IT8721F and later, as | |
2824 | * these have separate registers for the temperature mapping and the | |
2825 | * manual duty cycle. | |
2826 | */ | |
2310048d | 2827 | for (i = 0; i < NUM_AUTO_PWM; i++) { |
c1e7a4ca GR |
2828 | data->pwm_temp_map[i] = i; |
2829 | data->pwm_duty[i] = 0x7f; /* Full speed */ | |
2830 | data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ | |
8e9afcbb | 2831 | } |
1da177e4 | 2832 | |
483db43e | 2833 | /* |
c1e7a4ca GR |
2834 | * Some chips seem to have default value 0xff for all limit |
2835 | * registers. For low voltage limits it makes no sense and triggers | |
2836 | * alarms, so change to 0 instead. For high temperature limits, it | |
2837 | * means -1 degree C, which surprisingly doesn't trigger an alarm, | |
2838 | * but is still confusing, so change to 127 degrees C. | |
483db43e | 2839 | */ |
2310048d | 2840 | for (i = 0; i < NUM_VIN_LIMIT; i++) { |
c1e7a4ca GR |
2841 | tmp = it87_read_value(data, IT87_REG_VIN_MIN(i)); |
2842 | if (tmp == 0xff) | |
2843 | it87_write_value(data, IT87_REG_VIN_MIN(i), 0); | |
2844 | } | |
2310048d | 2845 | for (i = 0; i < NUM_TEMP_LIMIT; i++) { |
c1e7a4ca GR |
2846 | tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); |
2847 | if (tmp == 0xff) | |
2848 | it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); | |
483db43e | 2849 | } |
1da177e4 | 2850 | |
c1e7a4ca GR |
2851 | /* |
2852 | * Temperature channels are not forcibly enabled, as they can be | |
2853 | * set to two different sensor types and we can't guess which one | |
2854 | * is correct for a given system. These channels can be enabled at | |
2855 | * run-time through the temp{1-3}_type sysfs accessors if needed. | |
2856 | */ | |
1da177e4 | 2857 | |
c1e7a4ca GR |
2858 | /* Check if voltage monitors are reset manually or by some reason */ |
2859 | tmp = it87_read_value(data, IT87_REG_VIN_ENABLE); | |
2860 | if ((tmp & 0xff) == 0) { | |
2861 | /* Enable all voltage monitors */ | |
2862 | it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); | |
2863 | } | |
2864 | ||
2865 | /* Check if tachometers are reset manually or by some reason */ | |
2866 | mask = 0x70 & ~(sio_data->skip_fan << 4); | |
2867 | data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); | |
2868 | if ((data->fan_main_ctrl & mask) == 0) { | |
2869 | /* Enable all fan tachometers */ | |
2870 | data->fan_main_ctrl |= mask; | |
2871 | it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, | |
2872 | data->fan_main_ctrl); | |
2873 | } | |
2874 | data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; | |
2875 | ||
2876 | tmp = it87_read_value(data, IT87_REG_FAN_16BIT); | |
2877 | ||
2878 | /* Set tachometers to 16-bit mode if needed */ | |
2879 | if (has_fan16_config(data)) { | |
2880 | if (~tmp & 0x07 & data->has_fan) { | |
2881 | dev_dbg(&pdev->dev, | |
2882 | "Setting fan1-3 to 16-bit mode\n"); | |
2883 | it87_write_value(data, IT87_REG_FAN_16BIT, | |
2884 | tmp | 0x07); | |
2885 | } | |
2886 | } | |
2887 | ||
2888 | /* Check for additional fans */ | |
2889 | if (has_five_fans(data)) { | |
48b2ae7f GR |
2890 | if (tmp & BIT(4)) |
2891 | data->has_fan |= BIT(3); /* fan4 enabled */ | |
2892 | if (tmp & BIT(5)) | |
2893 | data->has_fan |= BIT(4); /* fan5 enabled */ | |
2894 | if (has_six_fans(data) && (tmp & BIT(2))) | |
2895 | data->has_fan |= BIT(5); /* fan6 enabled */ | |
c1e7a4ca GR |
2896 | } |
2897 | ||
2898 | /* Fan input pins may be used for alternative functions */ | |
2899 | data->has_fan &= ~sio_data->skip_fan; | |
2900 | ||
2901 | /* Check if pwm5, pwm6 are enabled */ | |
2902 | if (has_six_pwm(data)) { | |
2903 | /* The following code may be IT8620E specific */ | |
2904 | tmp = it87_read_value(data, IT87_REG_FAN_DIV); | |
2905 | if ((tmp & 0xc0) == 0xc0) | |
48b2ae7f GR |
2906 | sio_data->skip_pwm |= BIT(4); |
2907 | if (!(tmp & BIT(3))) | |
2908 | sio_data->skip_pwm |= BIT(5); | |
c1e7a4ca GR |
2909 | } |
2910 | ||
2911 | /* Start monitoring */ | |
2912 | it87_write_value(data, IT87_REG_CONFIG, | |
2913 | (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) | |
2914 | | (update_vbat ? 0x41 : 0x01)); | |
2915 | } | |
2916 | ||
2917 | /* Return 1 if and only if the PWM interface is safe to use */ | |
2918 | static int it87_check_pwm(struct device *dev) | |
2919 | { | |
2920 | struct it87_data *data = dev_get_drvdata(dev); | |
2921 | /* | |
2922 | * Some BIOSes fail to correctly configure the IT87 fans. All fans off | |
2923 | * and polarity set to active low is sign that this is the case so we | |
2924 | * disable pwm control to protect the user. | |
2925 | */ | |
2926 | int tmp = it87_read_value(data, IT87_REG_FAN_CTL); | |
2927 | ||
2928 | if ((tmp & 0x87) == 0) { | |
2929 | if (fix_pwm_polarity) { | |
2930 | /* | |
2931 | * The user asks us to attempt a chip reconfiguration. | |
2932 | * This means switching to active high polarity and | |
2933 | * inverting all fan speed values. | |
2934 | */ | |
2935 | int i; | |
2936 | u8 pwm[3]; | |
2937 | ||
2310048d | 2938 | for (i = 0; i < ARRAY_SIZE(pwm); i++) |
c1e7a4ca GR |
2939 | pwm[i] = it87_read_value(data, |
2940 | IT87_REG_PWM[i]); | |
2941 | ||
2942 | /* | |
2943 | * If any fan is in automatic pwm mode, the polarity | |
2944 | * might be correct, as suspicious as it seems, so we | |
2945 | * better don't change anything (but still disable the | |
2946 | * PWM interface). | |
2947 | */ | |
2948 | if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { | |
2949 | dev_info(dev, | |
2950 | "Reconfiguring PWM to active high polarity\n"); | |
2951 | it87_write_value(data, IT87_REG_FAN_CTL, | |
2952 | tmp | 0x87); | |
2953 | for (i = 0; i < 3; i++) | |
2954 | it87_write_value(data, | |
2955 | IT87_REG_PWM[i], | |
2956 | 0x7f & ~pwm[i]); | |
2957 | return 1; | |
2958 | } | |
2959 | ||
2960 | dev_info(dev, | |
2961 | "PWM configuration is too broken to be fixed\n"); | |
2962 | } | |
2963 | ||
2964 | dev_info(dev, | |
2965 | "Detected broken BIOS defaults, disabling PWM interface\n"); | |
2966 | return 0; | |
2967 | } else if (fix_pwm_polarity) { | |
2968 | dev_info(dev, | |
2969 | "PWM configuration looks sane, won't touch\n"); | |
2970 | } | |
2971 | ||
2972 | return 1; | |
2973 | } | |
2974 | ||
2975 | static int it87_probe(struct platform_device *pdev) | |
2976 | { | |
2977 | struct it87_data *data; | |
2978 | struct resource *res; | |
2979 | struct device *dev = &pdev->dev; | |
2980 | struct it87_sio_data *sio_data = dev_get_platdata(dev); | |
c1e7a4ca | 2981 | int enable_pwm_interface; |
8638d0af | 2982 | struct device *hwmon_dev; |
c1e7a4ca GR |
2983 | |
2984 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
2985 | if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, | |
2986 | DRVNAME)) { | |
2987 | dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", | |
2988 | (unsigned long)res->start, | |
2989 | (unsigned long)(res->start + IT87_EC_EXTENT - 1)); | |
2990 | return -EBUSY; | |
2991 | } | |
2992 | ||
2993 | data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); | |
2994 | if (!data) | |
2995 | return -ENOMEM; | |
2996 | ||
2997 | data->addr = res->start; | |
2998 | data->type = sio_data->type; | |
2999 | data->features = it87_devices[sio_data->type].features; | |
3000 | data->peci_mask = it87_devices[sio_data->type].peci_mask; | |
3001 | data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; | |
c1e7a4ca GR |
3002 | /* |
3003 | * IT8705F Datasheet 0.4.1, 3h == Version G. | |
3004 | * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. | |
3005 | * These are the first revisions with 16-bit tachometer support. | |
3006 | */ | |
3007 | switch (data->type) { | |
3008 | case it87: | |
3009 | if (sio_data->revision >= 0x03) { | |
3010 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3011 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; | |
3012 | } | |
3013 | break; | |
3014 | case it8712: | |
3015 | if (sio_data->revision >= 0x08) { | |
3016 | data->features &= ~FEAT_OLD_AUTOPWM; | |
3017 | data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | | |
3018 | FEAT_FIVE_FANS; | |
3019 | } | |
3020 | break; | |
3021 | default: | |
3022 | break; | |
3023 | } | |
3024 | ||
3025 | /* Now, we do the remaining detection. */ | |
c962024e GR |
3026 | if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || |
3027 | it87_read_value(data, IT87_REG_CHIPID) != 0x90) | |
c1e7a4ca GR |
3028 | return -ENODEV; |
3029 | ||
3030 | platform_set_drvdata(pdev, data); | |
1da177e4 | 3031 | |
9a61bf63 | 3032 | mutex_init(&data->update_lock); |
1da177e4 | 3033 | |
1da177e4 | 3034 | /* Check PWM configuration */ |
b74f3fdd | 3035 | enable_pwm_interface = it87_check_pwm(dev); |
1da177e4 | 3036 | |
44c1bcd4 | 3037 | /* Starting with IT8721F, we handle scaling of internal voltages */ |
16b5dda2 | 3038 | if (has_12mv_adc(data)) { |
48b2ae7f GR |
3039 | if (sio_data->internal & BIT(0)) |
3040 | data->in_scaled |= BIT(3); /* in3 is AVCC */ | |
3041 | if (sio_data->internal & BIT(1)) | |
3042 | data->in_scaled |= BIT(7); /* in7 is VSB */ | |
3043 | if (sio_data->internal & BIT(2)) | |
3044 | data->in_scaled |= BIT(8); /* in8 is Vbat */ | |
3045 | if (sio_data->internal & BIT(3)) | |
3046 | data->in_scaled |= BIT(9); /* in9 is AVCC */ | |
7bc32d29 GR |
3047 | } else if (sio_data->type == it8781 || sio_data->type == it8782 || |
3048 | sio_data->type == it8783) { | |
48b2ae7f GR |
3049 | if (sio_data->internal & BIT(0)) |
3050 | data->in_scaled |= BIT(3); /* in3 is VCC5V */ | |
3051 | if (sio_data->internal & BIT(1)) | |
3052 | data->in_scaled |= BIT(7); /* in7 is VCCH5V */ | |
44c1bcd4 JD |
3053 | } |
3054 | ||
4573acbc | 3055 | data->has_temp = 0x07; |
48b2ae7f | 3056 | if (sio_data->skip_temp & BIT(2)) { |
c962024e GR |
3057 | if (sio_data->type == it8782 && |
3058 | !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) | |
48b2ae7f | 3059 | data->has_temp &= ~BIT(2); |
4573acbc GR |
3060 | } |
3061 | ||
d3766848 | 3062 | data->in_internal = sio_data->internal; |
52929715 GR |
3063 | data->has_in = 0x3ff & ~sio_data->skip_in; |
3064 | ||
cc18da79 GR |
3065 | if (has_six_temp(data)) { |
3066 | u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); | |
3067 | ||
f838aa26 | 3068 | /* Check for additional temperature sensors */ |
cc18da79 | 3069 | if ((reg & 0x03) >= 0x02) |
48b2ae7f | 3070 | data->has_temp |= BIT(3); |
cc18da79 | 3071 | if (((reg >> 2) & 0x03) >= 0x02) |
48b2ae7f | 3072 | data->has_temp |= BIT(4); |
cc18da79 | 3073 | if (((reg >> 4) & 0x03) >= 0x02) |
48b2ae7f | 3074 | data->has_temp |= BIT(5); |
f838aa26 GR |
3075 | |
3076 | /* Check for additional voltage sensors */ | |
3077 | if ((reg & 0x03) == 0x01) | |
48b2ae7f | 3078 | data->has_in |= BIT(10); |
f838aa26 | 3079 | if (((reg >> 2) & 0x03) == 0x01) |
48b2ae7f | 3080 | data->has_in |= BIT(11); |
f838aa26 | 3081 | if (((reg >> 4) & 0x03) == 0x01) |
48b2ae7f | 3082 | data->has_in |= BIT(12); |
cc18da79 GR |
3083 | } |
3084 | ||
52929715 GR |
3085 | data->has_beep = !!sio_data->beep_pin; |
3086 | ||
1da177e4 | 3087 | /* Initialize the IT87 chip */ |
b74f3fdd | 3088 | it87_init_device(pdev); |
1da177e4 | 3089 | |
d3766848 GR |
3090 | if (!sio_data->skip_vid) { |
3091 | data->has_vid = true; | |
3092 | data->vrm = vid_which_vrm(); | |
3093 | /* VID reading from Super-I/O config space if available */ | |
3094 | data->vid = sio_data->vid_value; | |
3095 | } | |
3096 | ||
8638d0af GR |
3097 | /* Prepare for sysfs hooks */ |
3098 | data->groups[0] = &it87_group; | |
3099 | data->groups[1] = &it87_group_in; | |
3100 | data->groups[2] = &it87_group_temp; | |
3101 | data->groups[3] = &it87_group_fan; | |
17d648bf | 3102 | |
1da177e4 | 3103 | if (enable_pwm_interface) { |
48b2ae7f | 3104 | data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; |
5c391261 | 3105 | data->has_pwm &= ~sio_data->skip_pwm; |
4f3f51bc | 3106 | |
8638d0af | 3107 | data->groups[4] = &it87_group_pwm; |
2cbb9c37 | 3108 | if (has_old_autopwm(data) || has_newer_autopwm(data)) |
8638d0af | 3109 | data->groups[5] = &it87_group_auto_pwm; |
1da177e4 LT |
3110 | } |
3111 | ||
8638d0af GR |
3112 | hwmon_dev = devm_hwmon_device_register_with_groups(dev, |
3113 | it87_devices[sio_data->type].name, | |
3114 | data, data->groups); | |
3115 | return PTR_ERR_OR_ZERO(hwmon_dev); | |
1da177e4 LT |
3116 | } |
3117 | ||
c1e7a4ca GR |
3118 | static struct platform_driver it87_driver = { |
3119 | .driver = { | |
3120 | .name = DRVNAME, | |
3121 | }, | |
3122 | .probe = it87_probe, | |
c1e7a4ca | 3123 | }; |
1da177e4 | 3124 | |
e84bd953 | 3125 | static int __init it87_device_add(int index, unsigned short address, |
b74f3fdd | 3126 | const struct it87_sio_data *sio_data) |
3127 | { | |
8e50e3c3 | 3128 | struct platform_device *pdev; |
b74f3fdd | 3129 | struct resource res = { |
87b4b663 BH |
3130 | .start = address + IT87_EC_OFFSET, |
3131 | .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, | |
b74f3fdd | 3132 | .name = DRVNAME, |
3133 | .flags = IORESOURCE_IO, | |
3134 | }; | |
3135 | int err; | |
3136 | ||
b9acb64a JD |
3137 | err = acpi_check_resource_conflict(&res); |
3138 | if (err) | |
5cae84a5 | 3139 | return err; |
b9acb64a | 3140 | |
b74f3fdd | 3141 | pdev = platform_device_alloc(DRVNAME, address); |
5cae84a5 GR |
3142 | if (!pdev) |
3143 | return -ENOMEM; | |
b74f3fdd | 3144 | |
3145 | err = platform_device_add_resources(pdev, &res, 1); | |
3146 | if (err) { | |
a8ca1037 | 3147 | pr_err("Device resource addition failed (%d)\n", err); |
b74f3fdd | 3148 | goto exit_device_put; |
3149 | } | |
3150 | ||
3151 | err = platform_device_add_data(pdev, sio_data, | |
3152 | sizeof(struct it87_sio_data)); | |
3153 | if (err) { | |
a8ca1037 | 3154 | pr_err("Platform data allocation failed\n"); |
b74f3fdd | 3155 | goto exit_device_put; |
3156 | } | |
3157 | ||
3158 | err = platform_device_add(pdev); | |
3159 | if (err) { | |
a8ca1037 | 3160 | pr_err("Device addition failed (%d)\n", err); |
b74f3fdd | 3161 | goto exit_device_put; |
3162 | } | |
3163 | ||
e84bd953 | 3164 | it87_pdev[index] = pdev; |
b74f3fdd | 3165 | return 0; |
3166 | ||
3167 | exit_device_put: | |
3168 | platform_device_put(pdev); | |
b74f3fdd | 3169 | return err; |
3170 | } | |
3171 | ||
1da177e4 LT |
3172 | static int __init sm_it87_init(void) |
3173 | { | |
e84bd953 | 3174 | int sioaddr[2] = { REG_2E, REG_4E }; |
b74f3fdd | 3175 | struct it87_sio_data sio_data; |
e84bd953 GR |
3176 | unsigned short isa_address; |
3177 | bool found = false; | |
3178 | int i, err; | |
b74f3fdd | 3179 | |
b74f3fdd | 3180 | err = platform_driver_register(&it87_driver); |
3181 | if (err) | |
3182 | return err; | |
fde09509 | 3183 | |
e84bd953 GR |
3184 | for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { |
3185 | memset(&sio_data, 0, sizeof(struct it87_sio_data)); | |
3186 | isa_address = 0; | |
3187 | err = it87_find(sioaddr[i], &isa_address, &sio_data); | |
3188 | if (err || isa_address == 0) | |
3189 | continue; | |
3190 | ||
3191 | err = it87_device_add(i, isa_address, &sio_data); | |
3192 | if (err) | |
3193 | goto exit_dev_unregister; | |
3194 | found = true; | |
b74f3fdd | 3195 | } |
3196 | ||
e84bd953 GR |
3197 | if (!found) { |
3198 | err = -ENODEV; | |
3199 | goto exit_unregister; | |
3200 | } | |
b74f3fdd | 3201 | return 0; |
e84bd953 GR |
3202 | |
3203 | exit_dev_unregister: | |
3204 | /* NULL check handled by platform_device_unregister */ | |
3205 | platform_device_unregister(it87_pdev[0]); | |
3206 | exit_unregister: | |
3207 | platform_driver_unregister(&it87_driver); | |
3208 | return err; | |
1da177e4 LT |
3209 | } |
3210 | ||
3211 | static void __exit sm_it87_exit(void) | |
3212 | { | |
e84bd953 GR |
3213 | /* NULL check handled by platform_device_unregister */ |
3214 | platform_device_unregister(it87_pdev[1]); | |
3215 | platform_device_unregister(it87_pdev[0]); | |
b74f3fdd | 3216 | platform_driver_unregister(&it87_driver); |
1da177e4 LT |
3217 | } |
3218 | ||
7c81c60f | 3219 | MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); |
44c1bcd4 | 3220 | MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); |
1da177e4 LT |
3221 | module_param(update_vbat, bool, 0); |
3222 | MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); | |
3223 | module_param(fix_pwm_polarity, bool, 0); | |
5f2dc798 JD |
3224 | MODULE_PARM_DESC(fix_pwm_polarity, |
3225 | "Force PWM polarity to active high (DANGEROUS)"); | |
1da177e4 LT |
3226 | MODULE_LICENSE("GPL"); |
3227 | ||
3228 | module_init(sm_it87_init); | |
3229 | module_exit(sm_it87_exit); |