[mirror_ubuntu-jammy-kernel.git] / drivers / hwmon / k10temp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
 *		processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
 *
 * Implementation notes:
 * - CCD register address information as well as the calculation to
 *   convert raw register values is from https://github.com/ocerman/zenpower.
 *   The information is not confirmed from chip datasheets, but experiments
 *   suggest that it provides reasonable temperature values.
 */

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3	0x15b3
#endif

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	GENMASK(31, 28)
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			BIT(8)

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			BIT(0)

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			BIT(10)

/*
 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
 * and REG_REPORTED_TEMPERATURE have been moved to
 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
 */
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET	0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

/* Common for Zen CPU families (Family 17h and 18h) */
#define ZEN_REPORTED_TEMP_CTRL_OFFSET		0x00059800

#define ZEN_CCD_TEMP(x)				(0x00059954 + ((x) * 4))
#define ZEN_CCD_TEMP_VALID			BIT(11)
#define ZEN_CCD_TEMP_MASK			GENMASK(10, 0)

#define ZEN_CUR_TEMP_SHIFT			21
#define ZEN_CUR_TEMP_RANGE_SEL_MASK		BIT(19)

#define ZEN_SVI_BASE				0x0005A000

/* F17h thermal registers through SMN */
#define F17H_M01H_SVI_TEL_PLANE0		(ZEN_SVI_BASE + 0xc)
#define F17H_M01H_SVI_TEL_PLANE1		(ZEN_SVI_BASE + 0x10)
#define F17H_M31H_SVI_TEL_PLANE0		(ZEN_SVI_BASE + 0x14)
#define F17H_M31H_SVI_TEL_PLANE1		(ZEN_SVI_BASE + 0x10)

#define F17H_M01H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F17H_M01H_CFACTOR_ISOC			250000	/* 0.25A / LSB	*/
#define F17H_M31H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F17H_M31H_CFACTOR_ISOC			310000	/* 0.31A / LSB	*/

/* F19h thermal registers through SMN */
#define F19H_M01_SVI_TEL_PLANE0			(ZEN_SVI_BASE + 0x14)
#define F19H_M01_SVI_TEL_PLANE1			(ZEN_SVI_BASE + 0x10)

#define F19H_M01H_CFACTOR_ICORE			1000000	/* 1A / LSB	*/
#define F19H_M01H_CFACTOR_ISOC			310000	/* 0.31A / LSB	*/

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
	int temp_offset;
	u32 temp_adjust_mask;
	u32 show_temp;
	bool is_zen;
};

#define TCTL_BIT	0
#define TDIE_BIT	1
#define TCCD_BIT(x)	((x) + 2)

#define HAVE_TEMP(d, channel)	((d)->show_temp & BIT(channel))
#define HAVE_TDIE(d)		HAVE_TEMP(d, TDIE_BIT)

struct tctl_offset {
	u8 model;
	char const *id;
	int offset;
};

static const struct tctl_offset tctl_offset_table[] = {
	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
};

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
{
	amd_smn_read(amd_pci_dev_to_node_id(pdev),
		     ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static long get_raw_temp(struct k10temp_data *data)
{
	u32 regval;
	long temp;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
	if (regval & data->temp_adjust_mask)
		temp -= 49000;
	return temp;
}

static const char *k10temp_temp_label[] = {
	"Tctl",
	"Tdie",
	"Tccd1",
	"Tccd2",
	"Tccd3",
	"Tccd4",
	"Tccd5",
	"Tccd6",
	"Tccd7",
	"Tccd8",
};

static int k10temp_read_labels(struct device *dev,
			       enum hwmon_sensor_types type,
			       u32 attr, int channel, const char **str)
{
	switch (type) {
	case hwmon_temp:
		*str = k10temp_temp_label[channel];
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
			     long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_temp_input:
		switch (channel) {
		case 0:		/* Tctl */
			*val = get_raw_temp(data);
			if (*val < 0)
				*val = 0;
			break;
		case 1:		/* Tdie */
			*val = get_raw_temp(data) - data->temp_offset;
			if (*val < 0)
				*val = 0;
			break;
		case 2 ... 9:		/* Tccd{1-8} */
			amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
				     ZEN_CCD_TEMP(channel - 2), &regval);
			*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
			break;
		default:
			return -EOPNOTSUPP;
		}
		break;
	case hwmon_temp_max:
		*val = 70 * 1000;
		break;
	case hwmon_temp_crit:
		data->read_htcreg(data->pdev, &regval);
		*val = ((regval >> 16) & 0x7f) * 500 + 52000;
		break;
	case hwmon_temp_crit_hyst:
		data->read_htcreg(data->pdev, &regval);
		*val = (((regval >> 16) & 0x7f)
			- ((regval >> 24) & 0xf)) * 500 + 52000;
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
			u32 attr, int channel, long *val)
{
	switch (type) {
	case hwmon_temp:
		return k10temp_read_temp(dev, attr, channel, val);
	default:
		return -EOPNOTSUPP;
	}
}

static umode_t k10temp_is_visible(const void *_data,
				  enum hwmon_sensor_types type,
				  u32 attr, int channel)
{
	const struct k10temp_data *data = _data;
	struct pci_dev *pdev = data->pdev;
	u32 reg;

	switch (type) {
	case hwmon_temp:
		switch (attr) {
		case hwmon_temp_input:
			if (!HAVE_TEMP(data, channel))
				return 0;
			break;
		case hwmon_temp_max:
			if (channel || data->is_zen)
				return 0;
			break;
		case hwmon_temp_crit:
		case hwmon_temp_crit_hyst:
			if (channel || !data->read_htcreg)
				return 0;

			pci_read_config_dword(pdev,
					      REG_NORTHBRIDGE_CAPABILITIES,
					      &reg);
			if (!(reg & NB_CAP_HTC))
				return 0;

			data->read_htcreg(data->pdev, &reg);
			if (!(reg & HTC_ENABLE))
				return 0;
			break;
		case hwmon_temp_label:
			/* Show temperature labels only on Zen CPUs */
			if (!data->is_zen || !HAVE_TEMP(data, channel))
				return 0;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}
	return 0444;
}

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}

static const struct hwmon_channel_info *k10temp_info[] = {
	HWMON_CHANNEL_INFO(temp,
			   HWMON_T_INPUT | HWMON_T_MAX |
			   HWMON_T_CRIT | HWMON_T_CRIT_HYST |
			   HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL),
	HWMON_CHANNEL_INFO(in,
			   HWMON_I_INPUT | HWMON_I_LABEL,
			   HWMON_I_INPUT | HWMON_I_LABEL),
	HWMON_CHANNEL_INFO(curr,
			   HWMON_C_INPUT | HWMON_C_LABEL,
			   HWMON_C_INPUT | HWMON_C_LABEL),
	NULL
};

static const struct hwmon_ops k10temp_hwmon_ops = {
	.is_visible = k10temp_is_visible,
	.read = k10temp_read,
	.read_string = k10temp_read_labels,
};

static const struct hwmon_chip_info k10temp_chip_info = {
	.ops = &k10temp_hwmon_ops,
	.info = k10temp_info,
};

static void k10temp_get_ccd_support(struct pci_dev *pdev,
				    struct k10temp_data *data, int limit)
{
	u32 regval;
	int i;

	for (i = 0; i < limit; i++) {
		amd_smn_read(amd_pci_dev_to_node_id(pdev),
			     ZEN_CCD_TEMP(i), &regval);
		if (regval & ZEN_CCD_TEMP_VALID)
			data->show_temp |= BIT(TCCD_BIT(i));
	}
}

static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;
	int i;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;
	data->show_temp |= BIT(TCTL_BIT);	/* Always show Tctl */

	if (boot_cpu_data.x86 == 0x15 &&
	    ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
	     (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
		data->read_htcreg = read_htcreg_nb_f15;
		data->read_tempreg = read_tempreg_nb_f15;
	} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
		data->read_tempreg = read_tempreg_nb_zen;
		data->show_temp |= BIT(TDIE_BIT);	/* show Tdie */
		data->is_zen = true;

		switch (boot_cpu_data.x86_model) {
		case 0x1:	/* Zen */
		case 0x8:	/* Zen+ */
		case 0x11:	/* Zen APU */
		case 0x18:	/* Zen+ APU */
			k10temp_get_ccd_support(pdev, data, 4);
			break;
		case 0x31:	/* Zen2 Threadripper */
		case 0x71:	/* Zen2 */
			k10temp_get_ccd_support(pdev, data, 8);
			break;
		}
	} else if (boot_cpu_data.x86 == 0x19) {
		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
		data->read_tempreg = read_tempreg_nb_zen;
		data->show_temp |= BIT(TDIE_BIT);
		data->is_zen = true;

		switch (boot_cpu_data.x86_model) {
		case 0x0 ... 0x1:	/* Zen3 SP3/TR */
		case 0x21:		/* Zen3 Ryzen Desktop */
			k10temp_get_ccd_support(pdev, data, 8);
			break;
		}
	} else {
		data->read_htcreg = read_htcreg_pci;
		data->read_tempreg = read_tempreg_pci;
	}

	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
		const struct tctl_offset *entry = &tctl_offset_table[i];

		if (boot_cpu_data.x86 == entry->model &&
		    strstr(boot_cpu_data.x86_model_id, entry->id)) {
			data->temp_offset = entry->offset;
			break;
		}
	}

	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
							 &k10temp_chip_info,
							 NULL);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
6e7c1094	1	// SPDX-License-Identifier: GPL-2.0-or-later
3c57e89b	2	/*
d547552a GR	3	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
d547552a GR	4	* processor hardware monitoring
3c57e89b CL	5	*
3c57e89b CL	6	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
d547552a	7	* Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
c7579389 GR	8	*
c7579389 GR	9	* Implementation notes:
fd8bdb23	10	* - CCD register address information as well as the calculation to
c7579389 GR	11	* convert raw register values is from https://github.com/ocerman/zenpower.
	12	* The information is not confirmed from chip datasheets, but experiments
	13	* suggest that it provides reasonable temperature values.
3c57e89b CL	14	*/
3c57e89b CL	15
a6d210da	16	#include <linux/bitops.h>
3c57e89b CL	17	#include <linux/err.h>
3c57e89b CL	18	#include <linux/hwmon.h>
3c57e89b CL	19	#include <linux/init.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
dedf7dce	22	#include <linux/pci_ids.h>
3b031622	23	#include <asm/amd_nb.h>
3c57e89b CL	24	#include <asm/processor.h>
3c57e89b CL	25
9e581311	26	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	27	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	28	MODULE_LICENSE("GPL");
	29
	30	static bool force;
	31	module_param(force, bool, 0444);
	32	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	33
f89ce270 AG	34	/* Provide lock for writing to NB_SMU_IND_ADDR */
	35	static DEFINE_MUTEX(nb_smu_ind_mutex);
	36
ccaf63b4 GR	37	#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
	38	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
	39	#endif
	40
c5114a1c	41	/* CPUID function 0x80000001, ebx */
a6d210da	42	#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
c5114a1c CL	43	#define CPUID_PKGTYPE_F 0x00000000
	44	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	45
	46	/* DRAM controller (PCI function 2) */
	47	#define REG_DCT0_CONFIG_HIGH 0x094
a6d210da	48	#define DDR3_MODE BIT(8)
c5114a1c CL	49
c5114a1c CL	50	/* miscellaneous (PCI function 3) */
3c57e89b	51	#define REG_HARDWARE_THERMAL_CONTROL 0x64
a6d210da	52	#define HTC_ENABLE BIT(0)
3c57e89b CL	53
	54	#define REG_REPORTED_TEMPERATURE 0xa4
	55
	56	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
a6d210da	57	#define NB_CAP_HTC BIT(10)
3c57e89b	58
f89ce270	59	/*
40626a1b GR	60	* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
	61	* and REG_REPORTED_TEMPERATURE have been moved to
	62	* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
	63	* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
f89ce270	64	*/
40626a1b	65	#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
f89ce270	66	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	67
17822417 WH	68	/* Common for Zen CPU families (Family 17h and 18h) */
17822417 WH	69	#define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800
fd8bdb23	70
17822417 WH	71	#define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4))
	72	#define ZEN_CCD_TEMP_VALID BIT(11)
	73	#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
9af0a9ae	74
17822417 WH	75	#define ZEN_CUR_TEMP_SHIFT 21
17822417 WH	76	#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
b00647c4	77
17822417	78	#define ZEN_SVI_BASE 0x0005A000
a6d210da	79
17822417 WH	80	/* F17h thermal registers through SMN */
	81	#define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
	82	#define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
d6144a40 WH	83	#define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
d6144a40 WH	84	#define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
17822417	85
d6144a40 WH	86	#define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	87	#define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */
	88	#define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	89	#define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
b00647c4	90
55163a1c WH	91	/* F19h thermal registers through SMN */
	92	#define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
	93	#define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
	94
	95	#define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */
	96	#define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */
	97
68546abf GR	98	struct k10temp_data {
68546abf GR	99	struct pci_dev *pdev;
40626a1b	100	void (read_htcreg)(struct pci_dev pdev, u32 *regval);
68546abf	101	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
1b50b776	102	int temp_offset;
1b597889	103	u32 temp_adjust_mask;
60465245	104	u32 show_temp;
60465245	105	bool is_zen;
1b50b776 GR	106	};
1b50b776 GR	107
60465245 GR	108	#define TCTL_BIT 0
	109	#define TDIE_BIT 1
	110	#define TCCD_BIT(x) ((x) + 2)
	111
	112	#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
	113	#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
	114
1b50b776 GR	115	struct tctl_offset {
	116	u8 model;
	117	char const *id;
	118	int offset;
	119	};
	120
	121	static const struct tctl_offset tctl_offset_table[] = {
ab5ee246	122	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
1b50b776 GR	123	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
1b50b776 GR	124	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
1b597889	125	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
cd6a2064 GR	126	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
cd6a2064 GR	127	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
68546abf GR	128	};
68546abf GR	129
40626a1b GR	130	static void read_htcreg_pci(struct pci_dev pdev, u32 regval)
	131	{
	132	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
	133	}
	134
68546abf GR	135	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	136	{
	137	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	138	}
	139
	140	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	141	unsigned int base, int offset, u32 *val)
f89ce270 AG	142	{
	143	mutex_lock(&nb_smu_ind_mutex);
	144	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	145	base, offset);
f89ce270	146	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	147	base + 4, val);
f89ce270 AG	148	mutex_unlock(&nb_smu_ind_mutex);
	149	}
	150
40626a1b GR	151	static void read_htcreg_nb_f15(struct pci_dev pdev, u32 regval)
	152	{
	153	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	154	F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
	155	}
	156
68546abf GR	157	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	158	{
	159	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	160	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	161	}
	162
17822417	163	static void read_tempreg_nb_zen(struct pci_dev pdev, u32 regval)
9af0a9ae	164	{
3b031622	165	amd_smn_read(amd_pci_dev_to_node_id(pdev),
17822417	166	ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
9af0a9ae GR	167	}
9af0a9ae GR	168
d547552a	169	static long get_raw_temp(struct k10temp_data *data)
3c57e89b	170	{
f934c059	171	u32 regval;
d547552a	172	long temp;
68546abf GR	173
68546abf GR	174	data->read_tempreg(data->pdev, &regval);
17822417	175	temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
1b597889 GR	176	if (regval & data->temp_adjust_mask)
1b597889 GR	177	temp -= 49000;
f934c059 GR	178	return temp;
	179	}
	180
0e786f32	181	static const char *k10temp_temp_label[] = {
d547552a	182	"Tctl",
b02c6857	183	"Tdie",
c7579389 GR	184	"Tccd1",
c7579389 GR	185	"Tccd2",
fd8bdb23 GR	186	"Tccd3",
	187	"Tccd4",
	188	"Tccd5",
	189	"Tccd6",
	190	"Tccd7",
	191	"Tccd8",
d547552a	192	};
f934c059	193
d547552a GR	194	static int k10temp_read_labels(struct device *dev,
	195	enum hwmon_sensor_types type,
	196	u32 attr, int channel, const char **str)
3c57e89b	197	{
b00647c4 GR	198	switch (type) {
	199	case hwmon_temp:
	200	*str = k10temp_temp_label[channel];
	201	break;
b00647c4 GR	202	default:
	203	return -EOPNOTSUPP;
	204	}
	205	return 0;
	206	}
	207
	208	static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
	209	long *val)
3c57e89b	210	{
68546abf	211	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b	212	u32 regval;
3c57e89b	213
d547552a GR	214	switch (attr) {
	215	case hwmon_temp_input:
	216	switch (channel) {
b02c6857 GR	217	case 0: /* Tctl */
b02c6857 GR	218	*val = get_raw_temp(data);
d547552a GR	219	if (*val < 0)
	220	*val = 0;
	221	break;
b02c6857 GR	222	case 1: /* Tdie */
b02c6857 GR	223	*val = get_raw_temp(data) - data->temp_offset;
d547552a GR	224	if (*val < 0)
	225	*val = 0;
	226	break;
fd8bdb23	227	case 2 ... 9: /* Tccd{1-8} */
c7579389	228	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
17822417 WH	229	ZEN_CCD_TEMP(channel - 2), &regval);
17822417 WH	230	val = (regval & ZEN_CCD_TEMP_MASK) 125 - 49000;
c7579389	231	break;
d547552a GR	232	default:
	233	return -EOPNOTSUPP;
	234	}
	235	break;
	236	case hwmon_temp_max:
	237	val = 70 1000;
	238	break;
	239	case hwmon_temp_crit:
	240	data->read_htcreg(data->pdev, &regval);
	241	val = ((regval >> 16) & 0x7f) 500 + 52000;
	242	break;
	243	case hwmon_temp_crit_hyst:
	244	data->read_htcreg(data->pdev, &regval);
	245	*val = (((regval >> 16) & 0x7f)
	246	- ((regval >> 24) & 0xf)) * 500 + 52000;
	247	break;
	248	default:
	249	return -EOPNOTSUPP;
	250	}
	251	return 0;
3c57e89b CL	252	}
3c57e89b CL	253
b00647c4 GR	254	static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
	255	u32 attr, int channel, long *val)
	256	{
	257	switch (type) {
	258	case hwmon_temp:
	259	return k10temp_read_temp(dev, attr, channel, val);
b00647c4 GR	260	default:
	261	return -EOPNOTSUPP;
	262	}
	263	}
	264
d547552a GR	265	static umode_t k10temp_is_visible(const void *_data,
	266	enum hwmon_sensor_types type,
	267	u32 attr, int channel)
3e3e1022	268	{
d547552a	269	const struct k10temp_data *data = _data;
68546abf	270	struct pci_dev *pdev = data->pdev;
f934c059	271	u32 reg;
3e3e1022	272
d547552a GR	273	switch (type) {
	274	case hwmon_temp:
	275	switch (attr) {
	276	case hwmon_temp_input:
60465245	277	if (!HAVE_TEMP(data, channel))
d547552a GR	278	return 0;
	279	break;
	280	case hwmon_temp_max:
60465245	281	if (channel \|\| data->is_zen)
d547552a GR	282	return 0;
	283	break;
	284	case hwmon_temp_crit:
	285	case hwmon_temp_crit_hyst:
	286	if (channel \|\| !data->read_htcreg)
	287	return 0;
	288
	289	pci_read_config_dword(pdev,
	290	REG_NORTHBRIDGE_CAPABILITIES,
	291	&reg);
	292	if (!(reg & NB_CAP_HTC))
	293	return 0;
	294
	295	data->read_htcreg(data->pdev, &reg);
	296	if (!(reg & HTC_ENABLE))
	297	return 0;
	298	break;
	299	case hwmon_temp_label:
60465245 GR	300	/* Show temperature labels only on Zen CPUs */
60465245 GR	301	if (!data->is_zen \|\| !HAVE_TEMP(data, channel))
c7579389	302	return 0;
d547552a GR	303	break;
d547552a GR	304	default:
f934c059	305	return 0;
d547552a	306	}
f934c059	307	break;
d547552a GR	308	default:
d547552a GR	309	return 0;
3e3e1022	310	}
d547552a	311	return 0444;
3e3e1022 GR	312	}
3e3e1022 GR	313
6c931ae1	314	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	315	{
c5114a1c CL	316	u32 pkg_type, reg_dram_cfg;
	317
	318	if (boot_cpu_data.x86 != 0x10)
	319	return false;
	320
3c57e89b	321	/*
c5114a1c CL	322	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	323	* may be unreliable.
3c57e89b	324	*/
c5114a1c CL	325	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	326	if (pkg_type == CPUID_PKGTYPE_F)
	327	return true;
	328	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	329	return false;
	330
eefc2d9e	331	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	332	pci_bus_read_config_dword(pdev->bus,
	333	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	334	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	335	if (reg_dram_cfg & DDR3_MODE)
	336	return false;
	337
	338	/*
	339	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	340	* memory. We blacklist all the cores which do exist in socket AM2+
	341	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	342	* and AM3 formats, but that's the best we can do.
	343	*/
	344	return boot_cpu_data.x86_model < 4 \|\|
b399151c	345	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
3c57e89b CL	346	}
3c57e89b CL	347
d547552a GR	348	static const struct hwmon_channel_info *k10temp_info[] = {
	349	HWMON_CHANNEL_INFO(temp,
	350	HWMON_T_INPUT \| HWMON_T_MAX \|
	351	HWMON_T_CRIT \| HWMON_T_CRIT_HYST \|
	352	HWMON_T_LABEL,
c7579389 GR	353	HWMON_T_INPUT \| HWMON_T_LABEL,
c7579389 GR	354	HWMON_T_INPUT \| HWMON_T_LABEL,
fd8bdb23 GR	355	HWMON_T_INPUT \| HWMON_T_LABEL,
	356	HWMON_T_INPUT \| HWMON_T_LABEL,
	357	HWMON_T_INPUT \| HWMON_T_LABEL,
	358	HWMON_T_INPUT \| HWMON_T_LABEL,
	359	HWMON_T_INPUT \| HWMON_T_LABEL,
	360	HWMON_T_INPUT \| HWMON_T_LABEL,
d547552a	361	HWMON_T_INPUT \| HWMON_T_LABEL),
b00647c4 GR	362	HWMON_CHANNEL_INFO(in,
	363	HWMON_I_INPUT \| HWMON_I_LABEL,
	364	HWMON_I_INPUT \| HWMON_I_LABEL),
	365	HWMON_CHANNEL_INFO(curr,
	366	HWMON_C_INPUT \| HWMON_C_LABEL,
	367	HWMON_C_INPUT \| HWMON_C_LABEL),
d547552a GR	368	NULL
	369	};
	370
	371	static const struct hwmon_ops k10temp_hwmon_ops = {
	372	.is_visible = k10temp_is_visible,
	373	.read = k10temp_read,
	374	.read_string = k10temp_read_labels,
	375	};
	376
	377	static const struct hwmon_chip_info k10temp_chip_info = {
	378	.ops = &k10temp_hwmon_ops,
	379	.info = k10temp_info,
	380	};
	381
fd8bdb23 GR	382	static void k10temp_get_ccd_support(struct pci_dev *pdev,
	383	struct k10temp_data *data, int limit)
	384	{
	385	u32 regval;
	386	int i;
	387
	388	for (i = 0; i < limit; i++) {
	389	amd_smn_read(amd_pci_dev_to_node_id(pdev),
17822417 WH	390	ZEN_CCD_TEMP(i), &regval);
17822417 WH	391	if (regval & ZEN_CCD_TEMP_VALID)
60465245	392	data->show_temp \|= BIT(TCCD_BIT(i));
fd8bdb23 GR	393	}
	394	}
	395
d547552a	396	static int k10temp_probe(struct pci_dev pdev, const struct pci_device_id id)
3c57e89b	397	{
c5114a1c	398	int unreliable = has_erratum_319(pdev);
3e3e1022	399	struct device *dev = &pdev->dev;
68546abf	400	struct k10temp_data *data;
3e3e1022	401	struct device *hwmon_dev;
1b50b776	402	int i;
3c57e89b	403
3e3e1022 GR	404	if (unreliable) {
	405	if (!force) {
	406	dev_err(dev,
	407	"unreliable CPU thermal sensor; monitoring disabled\n");
	408	return -ENODEV;
	409	}
	410	dev_warn(dev,
3c57e89b	411	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	412	}
3c57e89b	413
68546abf GR	414	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	415	if (!data)
	416	return -ENOMEM;
	417
	418	data->pdev = pdev;
60465245	419	data->show_temp \|= BIT(TCTL_BIT); /* Always show Tctl */
68546abf	420
53dfa008 GR	421	if (boot_cpu_data.x86 == 0x15 &&
	422	((boot_cpu_data.x86_model & 0xf0) == 0x60 \|\|
	423	(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
40626a1b	424	data->read_htcreg = read_htcreg_nb_f15;
68546abf	425	data->read_tempreg = read_tempreg_nb_f15;
d93217d8	426	} else if (boot_cpu_data.x86 == 0x17 \|\| boot_cpu_data.x86 == 0x18) {
17822417 WH	427	data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
17822417 WH	428	data->read_tempreg = read_tempreg_nb_zen;
60465245 GR	429	data->show_temp \|= BIT(TDIE_BIT); /* show Tdie */
60465245 GR	430	data->is_zen = true;
c7579389 GR	431
	432	switch (boot_cpu_data.x86_model) {
	433	case 0x1: /* Zen */
	434	case 0x8: /* Zen+ */
	435	case 0x11: /* Zen APU */
	436	case 0x18: /* Zen+ APU */
fd8bdb23	437	k10temp_get_ccd_support(pdev, data, 4);
c7579389 GR	438	break;
	439	case 0x31: /* Zen2 Threadripper */
	440	case 0x71: /* Zen2 */
fd8bdb23	441	k10temp_get_ccd_support(pdev, data, 8);
c7579389 GR	442	break;
c7579389 GR	443	}
55163a1c WH	444	} else if (boot_cpu_data.x86 == 0x19) {
	445	data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
	446	data->read_tempreg = read_tempreg_nb_zen;
	447	data->show_temp \|= BIT(TDIE_BIT);
	448	data->is_zen = true;
	449
	450	switch (boot_cpu_data.x86_model) {
c8d0d3fa GC	451	case 0x0 ... 0x1: /* Zen3 SP3/TR */
c8d0d3fa GC	452	case 0x21: /* Zen3 Ryzen Desktop */
55163a1c WH	453	k10temp_get_ccd_support(pdev, data, 8);
	454	break;
	455	}
1b597889	456	} else {
40626a1b	457	data->read_htcreg = read_htcreg_pci;
68546abf	458	data->read_tempreg = read_tempreg_pci;
1b597889	459	}
68546abf	460
1b50b776 GR	461	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
	462	const struct tctl_offset *entry = &tctl_offset_table[i];
	463
	464	if (boot_cpu_data.x86 == entry->model &&
	465	strstr(boot_cpu_data.x86_model_id, entry->id)) {
	466	data->temp_offset = entry->offset;
	467	break;
	468	}
	469	}
	470
d547552a GR	471	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
	472	&k10temp_chip_info,
	473	NULL);
8999eabf	474	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	475	}
3c57e89b CL	476
cd9bb056	477	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	478	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	479	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	480	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	481	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	482	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	483	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	484	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
ccaf63b4	485	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
30b146d1	486	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	487	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
9af0a9ae	488	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3b031622	489	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
210ba120	490	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
279f0b3a	491	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
12163cfb	492	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
55163a1c	493	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
d93217d8	494	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3c57e89b CL	495	{}
	496	};
	497	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	498
	499	static struct pci_driver k10temp_driver = {
	500	.name = "k10temp",
	501	.id_table = k10temp_id_table,
	502	.probe = k10temp_probe,
3c57e89b CL	503	};
3c57e89b CL	504
f71f5a55	505	module_pci_driver(k10temp_driver);