[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / k10temp.c

/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3	0x15b3
#endif

#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
#define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463
#endif

#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3	0x15eb
#endif

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	0xf0000000
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			0x00000100

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			0x00000001

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			0x00000400

/*
 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
 * and REG_REPORTED_TEMPERATURE have been moved to
 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
 */
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET	0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

/* F17h M01h Access througn SMN */
#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET	0x00059800

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
	int temp_offset;
	u32 temp_adjust_mask;
};

struct tctl_offset {
	u8 model;
	char const *id;
	int offset;
};

static const struct tctl_offset tctl_offset_table[] = {
	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
	{ 0x17, "AMD Ryzen Threadripper 1950", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1920", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
};

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
{
	amd_smn_read(amd_pci_dev_to_node_id(pdev),
		     F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static ssize_t temp1_input_show(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;
	unsigned int temp;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> 21) * 125;
	if (regval & data->temp_adjust_mask)
		temp -= 49000;
	if (temp > data->temp_offset)
		temp -= data->temp_offset;
	else
		temp = 0;

	return sprintf(buf, "%u\n", temp);
}

static ssize_t temp1_max_show(struct device *dev,
			      struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "%d\n", 70 * 1000);
}

static ssize_t show_temp_crit(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct k10temp_data *data = dev_get_drvdata(dev);
	int show_hyst = attr->index;
	u32 regval;
	int value;

	data->read_htcreg(data->pdev, &regval);
	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	if (show_hyst)
		value -= ((regval >> 24) & 0xf) * 500;
	return sprintf(buf, "%d\n", value);
}

static DEVICE_ATTR_RO(temp1_input);
static DEVICE_ATTR_RO(temp1_max);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);

static umode_t k10temp_is_visible(struct kobject *kobj,
				  struct attribute *attr, int index)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct k10temp_data *data = dev_get_drvdata(dev);
	struct pci_dev *pdev = data->pdev;

	if (index >= 2) {
		u32 reg;

		if (!data->read_htcreg)
			return 0;

		pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
				      &reg);
		if (!(reg & NB_CAP_HTC))
			return 0;

		data->read_htcreg(data->pdev, &reg);
		if (!(reg & HTC_ENABLE))
			return 0;
	}
	return attr->mode;
}

static struct attribute *k10temp_attrs[] = {
	&dev_attr_temp1_input.attr,
	&dev_attr_temp1_max.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	NULL
};

static const struct attribute_group k10temp_group = {
	.attrs = k10temp_attrs,
	.is_visible = k10temp_is_visible,
};
__ATTRIBUTE_GROUPS(k10temp);

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}

static int k10temp_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;
	int i;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;

	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
					  boot_cpu_data.x86_model == 0x70)) {
		data->read_htcreg = read_htcreg_nb_f15;
		data->read_tempreg = read_tempreg_nb_f15;
	} else if (boot_cpu_data.x86 == 0x17) {
		data->temp_adjust_mask = 0x80000;
		data->read_tempreg = read_tempreg_nb_f17;
	} else {
		data->read_htcreg = read_htcreg_pci;
		data->read_tempreg = read_tempreg_pci;
	}

	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
		const struct tctl_offset *entry = &tctl_offset_table[i];

		if (boot_cpu_data.x86 == entry->model &&
		    strstr(boot_cpu_data.x86_model_id, entry->id)) {
			data->temp_offset = entry->offset;
			break;
		}
	}

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
							   k10temp_groups);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
3c57e89b	1	/*
30b146d1	2	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3c57e89b CL	3	*
	4	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This driver is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	14	* See the GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/hwmon.h>
	22	#include <linux/hwmon-sysfs.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
e0743212	26	#include <asm/amd_nb.h>
3c57e89b CL	27	#include <asm/processor.h>
3c57e89b CL	28
9e581311	29	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	30	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	31	MODULE_LICENSE("GPL");
	32
	33	static bool force;
	34	module_param(force, bool, 0444);
	35	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	36
f89ce270 AG	37	/* Provide lock for writing to NB_SMU_IND_ADDR */
	38	static DEFINE_MUTEX(nb_smu_ind_mutex);
	39
f34812be GR	40	#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
	41	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
	42	#endif
	43
9af0a9ae GR	44	#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
	45	#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
	46	#endif
	47
e0743212 GR	48	#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
e0743212 GR	49	#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
b64f743c GR	50	#endif
b64f743c GR	51
c5114a1c CL	52	/* CPUID function 0x80000001, ebx */
	53	#define CPUID_PKGTYPE_MASK 0xf0000000
	54	#define CPUID_PKGTYPE_F 0x00000000
	55	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	56
	57	/* DRAM controller (PCI function 2) */
	58	#define REG_DCT0_CONFIG_HIGH 0x094
	59	#define DDR3_MODE 0x00000100
	60
	61	/* miscellaneous (PCI function 3) */
3c57e89b CL	62	#define REG_HARDWARE_THERMAL_CONTROL 0x64
	63	#define HTC_ENABLE 0x00000001
	64
	65	#define REG_REPORTED_TEMPERATURE 0xa4
	66
	67	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
	68	#define NB_CAP_HTC 0x00000400
	69
f89ce270	70	/*
b8af4dea GR	71	* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
	72	* and REG_REPORTED_TEMPERATURE have been moved to
	73	* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
	74	* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
f89ce270	75	*/
b8af4dea	76	#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
f89ce270	77	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	78
9af0a9ae GR	79	/* F17h M01h Access througn SMN */
	80	#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
	81
68546abf GR	82	struct k10temp_data {
68546abf GR	83	struct pci_dev *pdev;
b8af4dea	84	void (read_htcreg)(struct pci_dev pdev, u32 *regval);
68546abf	85	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
1b50b776	86	int temp_offset;
7f4bedab	87	u32 temp_adjust_mask;
1b50b776 GR	88	};
	89
	90	struct tctl_offset {
	91	u8 model;
	92	char const *id;
	93	int offset;
	94	};
	95
	96	static const struct tctl_offset tctl_offset_table[] = {
ab5ee246	97	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
1b50b776 GR	98	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
1b50b776 GR	99	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
7f4bedab	100	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
1b50b776 GR	101	{ 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
1b50b776 GR	102	{ 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
fc400604	103	{ 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
1b50b776 GR	104	{ 0x17, "AMD Ryzen Threadripper 1950", 10000 },
	105	{ 0x17, "AMD Ryzen Threadripper 1920", 10000 },
	106	{ 0x17, "AMD Ryzen Threadripper 1910", 10000 },
68546abf GR	107	};
68546abf GR	108
b8af4dea GR	109	static void read_htcreg_pci(struct pci_dev pdev, u32 regval)
	110	{
	111	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
	112	}
	113
68546abf GR	114	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	115	{
	116	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	117	}
	118
	119	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	120	unsigned int base, int offset, u32 *val)
f89ce270 AG	121	{
	122	mutex_lock(&nb_smu_ind_mutex);
	123	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	124	base, offset);
f89ce270	125	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	126	base + 4, val);
f89ce270 AG	127	mutex_unlock(&nb_smu_ind_mutex);
	128	}
	129
b8af4dea GR	130	static void read_htcreg_nb_f15(struct pci_dev pdev, u32 regval)
	131	{
	132	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	133	F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
	134	}
	135
68546abf GR	136	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	137	{
	138	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	139	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	140	}
	141
9af0a9ae GR	142	static void read_tempreg_nb_f17(struct pci_dev pdev, u32 regval)
9af0a9ae GR	143	{
e0743212 GR	144	amd_smn_read(amd_pci_dev_to_node_id(pdev),
e0743212 GR	145	F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
9af0a9ae GR	146	}
9af0a9ae GR	147
0c36d72e JL	148	static ssize_t temp1_input_show(struct device *dev,
0c36d72e JL	149	struct device_attribute attr, char buf)
3c57e89b	150	{
68546abf	151	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b	152	u32 regval;
68546abf GR	153	unsigned int temp;
	154
	155	data->read_tempreg(data->pdev, &regval);
	156	temp = (regval >> 21) * 125;
7f4bedab GR	157	if (regval & data->temp_adjust_mask)
7f4bedab GR	158	temp -= 49000;
f07a3d41 GR	159	if (temp > data->temp_offset)
	160	temp -= data->temp_offset;
	161	else
	162	temp = 0;
68546abf GR	163
68546abf GR	164	return sprintf(buf, "%u\n", temp);
3c57e89b CL	165	}
3c57e89b CL	166
0c36d72e JL	167	static ssize_t temp1_max_show(struct device *dev,
0c36d72e JL	168	struct device_attribute attr, char buf)
3c57e89b CL	169	{
	170	return sprintf(buf, "%d\n", 70 * 1000);
	171	}
	172
	173	static ssize_t show_temp_crit(struct device *dev,
	174	struct device_attribute devattr, char buf)
	175	{
	176	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
68546abf	177	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b CL	178	int show_hyst = attr->index;
	179	u32 regval;
	180	int value;
	181
b8af4dea	182	data->read_htcreg(data->pdev, &regval);
3c57e89b CL	183	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	184	if (show_hyst)
	185	value -= ((regval >> 24) & 0xf) * 500;
	186	return sprintf(buf, "%d\n", value);
	187	}
	188
0c36d72e JL	189	static DEVICE_ATTR_RO(temp1_input);
0c36d72e JL	190	static DEVICE_ATTR_RO(temp1_max);
3c57e89b CL	191	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
3c57e89b CL	192	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
3e3e1022 GR	193
	194	static umode_t k10temp_is_visible(struct kobject *kobj,
	195	struct attribute *attr, int index)
	196	{
	197	struct device *dev = container_of(kobj, struct device, kobj);
68546abf GR	198	struct k10temp_data *data = dev_get_drvdata(dev);
68546abf GR	199	struct pci_dev *pdev = data->pdev;
3e3e1022 GR	200
3e3e1022 GR	201	if (index >= 2) {
b8af4dea GR	202	u32 reg;
	203
	204	if (!data->read_htcreg)
	205	return 0;
3e3e1022 GR	206
3e3e1022 GR	207	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
b8af4dea GR	208	&reg);
	209	if (!(reg & NB_CAP_HTC))
	210	return 0;
	211
	212	data->read_htcreg(data->pdev, &reg);
	213	if (!(reg & HTC_ENABLE))
3e3e1022 GR	214	return 0;
	215	}
	216	return attr->mode;
	217	}
	218
	219	static struct attribute *k10temp_attrs[] = {
	220	&dev_attr_temp1_input.attr,
	221	&dev_attr_temp1_max.attr,
	222	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	223	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	224	NULL
	225	};
	226
	227	static const struct attribute_group k10temp_group = {
	228	.attrs = k10temp_attrs,
	229	.is_visible = k10temp_is_visible,
	230	};
	231	__ATTRIBUTE_GROUPS(k10temp);
3c57e89b	232
6c931ae1	233	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	234	{
c5114a1c CL	235	u32 pkg_type, reg_dram_cfg;
	236
	237	if (boot_cpu_data.x86 != 0x10)
	238	return false;
	239
3c57e89b	240	/*
c5114a1c CL	241	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	242	* may be unreliable.
3c57e89b	243	*/
c5114a1c CL	244	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	245	if (pkg_type == CPUID_PKGTYPE_F)
	246	return true;
	247	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	248	return false;
	249
eefc2d9e	250	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	251	pci_bus_read_config_dword(pdev->bus,
	252	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	253	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	254	if (reg_dram_cfg & DDR3_MODE)
	255	return false;
	256
	257	/*
	258	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	259	* memory. We blacklist all the cores which do exist in socket AM2+
	260	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	261	* and AM3 formats, but that's the best we can do.
	262	*/
	263	return boot_cpu_data.x86_model < 4 \|\|
dd7cc466	264	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
3c57e89b CL	265	}
3c57e89b CL	266
6c931ae1	267	static int k10temp_probe(struct pci_dev *pdev,
3c57e89b CL	268	const struct pci_device_id *id)
3c57e89b CL	269	{
c5114a1c	270	int unreliable = has_erratum_319(pdev);
3e3e1022	271	struct device *dev = &pdev->dev;
68546abf	272	struct k10temp_data *data;
3e3e1022	273	struct device *hwmon_dev;
1b50b776	274	int i;
3c57e89b	275
3e3e1022 GR	276	if (unreliable) {
	277	if (!force) {
	278	dev_err(dev,
	279	"unreliable CPU thermal sensor; monitoring disabled\n");
	280	return -ENODEV;
	281	}
	282	dev_warn(dev,
3c57e89b	283	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	284	}
3c57e89b	285
68546abf GR	286	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	287	if (!data)
	288	return -ENOMEM;
	289
	290	data->pdev = pdev;
	291
	292	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 \|\|
7f4bedab	293	boot_cpu_data.x86_model == 0x70)) {
b8af4dea	294	data->read_htcreg = read_htcreg_nb_f15;
68546abf	295	data->read_tempreg = read_tempreg_nb_f15;
7f4bedab GR	296	} else if (boot_cpu_data.x86 == 0x17) {
7f4bedab GR	297	data->temp_adjust_mask = 0x80000;
9af0a9ae	298	data->read_tempreg = read_tempreg_nb_f17;
7f4bedab	299	} else {
b8af4dea	300	data->read_htcreg = read_htcreg_pci;
68546abf	301	data->read_tempreg = read_tempreg_pci;
7f4bedab	302	}
68546abf	303
1b50b776 GR	304	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
	305	const struct tctl_offset *entry = &tctl_offset_table[i];
	306
	307	if (boot_cpu_data.x86 == entry->model &&
	308	strstr(boot_cpu_data.x86_model_id, entry->id)) {
	309	data->temp_offset = entry->offset;
	310	break;
	311	}
	312	}
	313
68546abf	314	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
3e3e1022 GR	315	k10temp_groups);
3e3e1022 GR	316	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	317	}
3c57e89b CL	318
cd9bb056	319	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	320	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	321	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	322	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	323	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	324	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	325	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	326	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
f34812be	327	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
30b146d1	328	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	329	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
9af0a9ae	330	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
e0743212	331	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
3c57e89b CL	332	{}
	333	};
	334	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	335
	336	static struct pci_driver k10temp_driver = {
	337	.name = "k10temp",
	338	.id_table = k10temp_id_table,
	339	.probe = k10temp_probe,
3c57e89b CL	340	};
3c57e89b CL	341
f71f5a55	342	module_pci_driver(k10temp_driver);