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Commit | Line | Data |
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3c57e89b | 1 | /* |
9e581311 | 2 | * k10temp.c - AMD Family 10h/11h/12h/14h/15h processor hardware monitoring |
3c57e89b CL |
3 | * |
4 | * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> | |
5 | * | |
6 | * | |
7 | * This driver is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This driver is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
14 | * See the GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this driver; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/err.h> | |
21 | #include <linux/hwmon.h> | |
22 | #include <linux/hwmon-sysfs.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <asm/processor.h> | |
27 | ||
9e581311 | 28 | MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); |
3c57e89b CL |
29 | MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | static bool force; | |
33 | module_param(force, bool, 0444); | |
34 | MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); | |
35 | ||
fbc729a4 AP |
36 | /* PCI-IDs for Northbridge devices not used anywhere else */ |
37 | #define PCI_DEVICE_ID_AMD_15H_M10H_NB_F3 0x1403 | |
38 | ||
c5114a1c CL |
39 | /* CPUID function 0x80000001, ebx */ |
40 | #define CPUID_PKGTYPE_MASK 0xf0000000 | |
41 | #define CPUID_PKGTYPE_F 0x00000000 | |
42 | #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 | |
43 | ||
44 | /* DRAM controller (PCI function 2) */ | |
45 | #define REG_DCT0_CONFIG_HIGH 0x094 | |
46 | #define DDR3_MODE 0x00000100 | |
47 | ||
48 | /* miscellaneous (PCI function 3) */ | |
3c57e89b CL |
49 | #define REG_HARDWARE_THERMAL_CONTROL 0x64 |
50 | #define HTC_ENABLE 0x00000001 | |
51 | ||
52 | #define REG_REPORTED_TEMPERATURE 0xa4 | |
53 | ||
54 | #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 | |
55 | #define NB_CAP_HTC 0x00000400 | |
56 | ||
57 | static ssize_t show_temp(struct device *dev, | |
58 | struct device_attribute *attr, char *buf) | |
59 | { | |
60 | u32 regval; | |
61 | ||
62 | pci_read_config_dword(to_pci_dev(dev), | |
63 | REG_REPORTED_TEMPERATURE, ®val); | |
64 | return sprintf(buf, "%u\n", (regval >> 21) * 125); | |
65 | } | |
66 | ||
67 | static ssize_t show_temp_max(struct device *dev, | |
68 | struct device_attribute *attr, char *buf) | |
69 | { | |
70 | return sprintf(buf, "%d\n", 70 * 1000); | |
71 | } | |
72 | ||
73 | static ssize_t show_temp_crit(struct device *dev, | |
74 | struct device_attribute *devattr, char *buf) | |
75 | { | |
76 | struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); | |
77 | int show_hyst = attr->index; | |
78 | u32 regval; | |
79 | int value; | |
80 | ||
81 | pci_read_config_dword(to_pci_dev(dev), | |
82 | REG_HARDWARE_THERMAL_CONTROL, ®val); | |
83 | value = ((regval >> 16) & 0x7f) * 500 + 52000; | |
84 | if (show_hyst) | |
85 | value -= ((regval >> 24) & 0xf) * 500; | |
86 | return sprintf(buf, "%d\n", value); | |
87 | } | |
88 | ||
89 | static ssize_t show_name(struct device *dev, | |
90 | struct device_attribute *attr, char *buf) | |
91 | { | |
92 | return sprintf(buf, "k10temp\n"); | |
93 | } | |
94 | ||
95 | static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL); | |
96 | static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL); | |
97 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0); | |
98 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1); | |
99 | static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); | |
100 | ||
c5114a1c | 101 | static bool __devinit has_erratum_319(struct pci_dev *pdev) |
3c57e89b | 102 | { |
c5114a1c CL |
103 | u32 pkg_type, reg_dram_cfg; |
104 | ||
105 | if (boot_cpu_data.x86 != 0x10) | |
106 | return false; | |
107 | ||
3c57e89b | 108 | /* |
c5114a1c CL |
109 | * Erratum 319: The thermal sensor of Socket F/AM2+ processors |
110 | * may be unreliable. | |
3c57e89b | 111 | */ |
c5114a1c CL |
112 | pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; |
113 | if (pkg_type == CPUID_PKGTYPE_F) | |
114 | return true; | |
115 | if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) | |
116 | return false; | |
117 | ||
eefc2d9e | 118 | /* DDR3 memory implies socket AM3, which is good */ |
c5114a1c CL |
119 | pci_bus_read_config_dword(pdev->bus, |
120 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), | |
121 | REG_DCT0_CONFIG_HIGH, ®_dram_cfg); | |
eefc2d9e JD |
122 | if (reg_dram_cfg & DDR3_MODE) |
123 | return false; | |
124 | ||
125 | /* | |
126 | * Unfortunately it is possible to run a socket AM3 CPU with DDR2 | |
127 | * memory. We blacklist all the cores which do exist in socket AM2+ | |
128 | * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ | |
129 | * and AM3 formats, but that's the best we can do. | |
130 | */ | |
131 | return boot_cpu_data.x86_model < 4 || | |
132 | (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2); | |
3c57e89b CL |
133 | } |
134 | ||
135 | static int __devinit k10temp_probe(struct pci_dev *pdev, | |
136 | const struct pci_device_id *id) | |
137 | { | |
138 | struct device *hwmon_dev; | |
139 | u32 reg_caps, reg_htc; | |
c5114a1c | 140 | int unreliable = has_erratum_319(pdev); |
3c57e89b CL |
141 | int err; |
142 | ||
c5114a1c | 143 | if (unreliable && !force) { |
3c57e89b CL |
144 | dev_err(&pdev->dev, |
145 | "unreliable CPU thermal sensor; monitoring disabled\n"); | |
146 | err = -ENODEV; | |
147 | goto exit; | |
148 | } | |
149 | ||
150 | err = device_create_file(&pdev->dev, &dev_attr_temp1_input); | |
151 | if (err) | |
152 | goto exit; | |
153 | err = device_create_file(&pdev->dev, &dev_attr_temp1_max); | |
154 | if (err) | |
155 | goto exit_remove; | |
156 | ||
157 | pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, ®_caps); | |
158 | pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, ®_htc); | |
159 | if ((reg_caps & NB_CAP_HTC) && (reg_htc & HTC_ENABLE)) { | |
160 | err = device_create_file(&pdev->dev, | |
161 | &sensor_dev_attr_temp1_crit.dev_attr); | |
162 | if (err) | |
163 | goto exit_remove; | |
164 | err = device_create_file(&pdev->dev, | |
165 | &sensor_dev_attr_temp1_crit_hyst.dev_attr); | |
166 | if (err) | |
167 | goto exit_remove; | |
168 | } | |
169 | ||
170 | err = device_create_file(&pdev->dev, &dev_attr_name); | |
171 | if (err) | |
172 | goto exit_remove; | |
173 | ||
174 | hwmon_dev = hwmon_device_register(&pdev->dev); | |
175 | if (IS_ERR(hwmon_dev)) { | |
176 | err = PTR_ERR(hwmon_dev); | |
177 | goto exit_remove; | |
178 | } | |
95de3b25 | 179 | pci_set_drvdata(pdev, hwmon_dev); |
3c57e89b | 180 | |
c5114a1c | 181 | if (unreliable && force) |
3c57e89b CL |
182 | dev_warn(&pdev->dev, |
183 | "unreliable CPU thermal sensor; check erratum 319\n"); | |
184 | return 0; | |
185 | ||
186 | exit_remove: | |
187 | device_remove_file(&pdev->dev, &dev_attr_name); | |
188 | device_remove_file(&pdev->dev, &dev_attr_temp1_input); | |
189 | device_remove_file(&pdev->dev, &dev_attr_temp1_max); | |
190 | device_remove_file(&pdev->dev, | |
191 | &sensor_dev_attr_temp1_crit.dev_attr); | |
192 | device_remove_file(&pdev->dev, | |
193 | &sensor_dev_attr_temp1_crit_hyst.dev_attr); | |
194 | exit: | |
195 | return err; | |
196 | } | |
197 | ||
198 | static void __devexit k10temp_remove(struct pci_dev *pdev) | |
199 | { | |
95de3b25 | 200 | hwmon_device_unregister(pci_get_drvdata(pdev)); |
3c57e89b CL |
201 | device_remove_file(&pdev->dev, &dev_attr_name); |
202 | device_remove_file(&pdev->dev, &dev_attr_temp1_input); | |
203 | device_remove_file(&pdev->dev, &dev_attr_temp1_max); | |
204 | device_remove_file(&pdev->dev, | |
205 | &sensor_dev_attr_temp1_crit.dev_attr); | |
206 | device_remove_file(&pdev->dev, | |
207 | &sensor_dev_attr_temp1_crit_hyst.dev_attr); | |
95de3b25 | 208 | pci_set_drvdata(pdev, NULL); |
3c57e89b CL |
209 | } |
210 | ||
600151b9 | 211 | static DEFINE_PCI_DEVICE_TABLE(k10temp_id_table) = { |
3c57e89b CL |
212 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
213 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, | |
aa4790a6 | 214 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, |
9e581311 | 215 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
fbc729a4 | 216 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_NB_F3) }, |
3c57e89b CL |
217 | {} |
218 | }; | |
219 | MODULE_DEVICE_TABLE(pci, k10temp_id_table); | |
220 | ||
221 | static struct pci_driver k10temp_driver = { | |
222 | .name = "k10temp", | |
223 | .id_table = k10temp_id_table, | |
224 | .probe = k10temp_probe, | |
225 | .remove = __devexit_p(k10temp_remove), | |
226 | }; | |
227 | ||
228 | static int __init k10temp_init(void) | |
229 | { | |
230 | return pci_register_driver(&k10temp_driver); | |
231 | } | |
232 | ||
233 | static void __exit k10temp_exit(void) | |
234 | { | |
235 | pci_unregister_driver(&k10temp_driver); | |
236 | } | |
237 | ||
238 | module_init(k10temp_init) | |
239 | module_exit(k10temp_exit) |