[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / k10temp.c

/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
 *
 *
 * This driver is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This driver is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	0xf0000000
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			0x00000100

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			0x00000001

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			0x00000400

/*
 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
 * Control]
 */
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
};

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static ssize_t temp1_input_show(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;
	unsigned int temp;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> 21) * 125;

	return sprintf(buf, "%u\n", temp);
}

static ssize_t temp1_max_show(struct device *dev,
			      struct device_attribute *attr, char *buf)
{
	return sprintf(buf, "%d\n", 70 * 1000);
}

static ssize_t show_temp_crit(struct device *dev,
			      struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct k10temp_data *data = dev_get_drvdata(dev);
	int show_hyst = attr->index;
	u32 regval;
	int value;

	pci_read_config_dword(data->pdev,
			      REG_HARDWARE_THERMAL_CONTROL, &regval);
	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	if (show_hyst)
		value -= ((regval >> 24) & 0xf) * 500;
	return sprintf(buf, "%d\n", value);
}

static DEVICE_ATTR_RO(temp1_input);
static DEVICE_ATTR_RO(temp1_max);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);

static umode_t k10temp_is_visible(struct kobject *kobj,
				  struct attribute *attr, int index)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct k10temp_data *data = dev_get_drvdata(dev);
	struct pci_dev *pdev = data->pdev;

	if (index >= 2) {
		u32 reg_caps, reg_htc;

		pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
				      &reg_caps);
		pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
				      &reg_htc);
		if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
			return 0;
	}
	return attr->mode;
}

static struct attribute *k10temp_attrs[] = {
	&dev_attr_temp1_input.attr,
	&dev_attr_temp1_max.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	NULL
};

static const struct attribute_group k10temp_group = {
	.attrs = k10temp_attrs,
	.is_visible = k10temp_is_visible,
};
__ATTRIBUTE_GROUPS(k10temp);

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
}

static int k10temp_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;

	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
					  boot_cpu_data.x86_model == 0x70))
		data->read_tempreg = read_tempreg_nb_f15;
	else
		data->read_tempreg = read_tempreg_pci;

	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
							   k10temp_groups);
	return PTR_ERR_OR_ZERO(hwmon_dev);
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
3c57e89b	1	/*
30b146d1	2	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
3c57e89b CL	3	*
	4	* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This driver is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	14	* See the GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/hwmon.h>
	22	#include <linux/hwmon-sysfs.h>
	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
	26	#include <asm/processor.h>
	27
9e581311	28	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	29	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	30	MODULE_LICENSE("GPL");
	31
	32	static bool force;
	33	module_param(force, bool, 0444);
	34	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	35
f89ce270 AG	36	/* Provide lock for writing to NB_SMU_IND_ADDR */
	37	static DEFINE_MUTEX(nb_smu_ind_mutex);
	38
c5114a1c CL	39	/* CPUID function 0x80000001, ebx */
	40	#define CPUID_PKGTYPE_MASK 0xf0000000
	41	#define CPUID_PKGTYPE_F 0x00000000
	42	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	43
	44	/* DRAM controller (PCI function 2) */
	45	#define REG_DCT0_CONFIG_HIGH 0x094
	46	#define DDR3_MODE 0x00000100
	47
	48	/* miscellaneous (PCI function 3) */
3c57e89b CL	49	#define REG_HARDWARE_THERMAL_CONTROL 0x64
	50	#define HTC_ENABLE 0x00000001
	51
	52	#define REG_REPORTED_TEMPERATURE 0xa4
	53
	54	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
	55	#define NB_CAP_HTC 0x00000400
	56
f89ce270 AG	57	/*
	58	* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
	59	* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
	60	* Control]
	61	*/
	62	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	63
68546abf GR	64	struct k10temp_data {
	65	struct pci_dev *pdev;
	66	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
	67	};
	68
	69	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	70	{
	71	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	72	}
	73
	74	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	75	unsigned int base, int offset, u32 *val)
f89ce270 AG	76	{
	77	mutex_lock(&nb_smu_ind_mutex);
	78	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	79	base, offset);
f89ce270	80	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	81	base + 4, val);
f89ce270 AG	82	mutex_unlock(&nb_smu_ind_mutex);
	83	}
	84
68546abf GR	85	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	86	{
	87	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	88	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	89	}
	90
0c36d72e JL	91	static ssize_t temp1_input_show(struct device *dev,
0c36d72e JL	92	struct device_attribute attr, char buf)
3c57e89b	93	{
68546abf	94	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b	95	u32 regval;
68546abf GR	96	unsigned int temp;
	97
	98	data->read_tempreg(data->pdev, &regval);
	99	temp = (regval >> 21) * 125;
	100
	101	return sprintf(buf, "%u\n", temp);
3c57e89b CL	102	}
3c57e89b CL	103
0c36d72e JL	104	static ssize_t temp1_max_show(struct device *dev,
0c36d72e JL	105	struct device_attribute attr, char buf)
3c57e89b CL	106	{
	107	return sprintf(buf, "%d\n", 70 * 1000);
	108	}
	109
	110	static ssize_t show_temp_crit(struct device *dev,
	111	struct device_attribute devattr, char buf)
	112	{
	113	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
68546abf	114	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b CL	115	int show_hyst = attr->index;
	116	u32 regval;
	117	int value;
	118
68546abf	119	pci_read_config_dword(data->pdev,
3c57e89b CL	120	REG_HARDWARE_THERMAL_CONTROL, &regval);
	121	value = ((regval >> 16) & 0x7f) * 500 + 52000;
	122	if (show_hyst)
	123	value -= ((regval >> 24) & 0xf) * 500;
	124	return sprintf(buf, "%d\n", value);
	125	}
	126
0c36d72e JL	127	static DEVICE_ATTR_RO(temp1_input);
0c36d72e JL	128	static DEVICE_ATTR_RO(temp1_max);
3c57e89b CL	129	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
3c57e89b CL	130	static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
3e3e1022 GR	131
	132	static umode_t k10temp_is_visible(struct kobject *kobj,
	133	struct attribute *attr, int index)
	134	{
	135	struct device *dev = container_of(kobj, struct device, kobj);
68546abf GR	136	struct k10temp_data *data = dev_get_drvdata(dev);
68546abf GR	137	struct pci_dev *pdev = data->pdev;
3e3e1022 GR	138
	139	if (index >= 2) {
	140	u32 reg_caps, reg_htc;
	141
	142	pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
	143	&reg_caps);
	144	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
	145	&reg_htc);
	146	if (!(reg_caps & NB_CAP_HTC) \|\| !(reg_htc & HTC_ENABLE))
	147	return 0;
	148	}
	149	return attr->mode;
	150	}
	151
	152	static struct attribute *k10temp_attrs[] = {
	153	&dev_attr_temp1_input.attr,
	154	&dev_attr_temp1_max.attr,
	155	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	156	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
	157	NULL
	158	};
	159
	160	static const struct attribute_group k10temp_group = {
	161	.attrs = k10temp_attrs,
	162	.is_visible = k10temp_is_visible,
	163	};
	164	__ATTRIBUTE_GROUPS(k10temp);
3c57e89b	165
6c931ae1	166	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	167	{
c5114a1c CL	168	u32 pkg_type, reg_dram_cfg;
	169
	170	if (boot_cpu_data.x86 != 0x10)
	171	return false;
	172
3c57e89b	173	/*
c5114a1c CL	174	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	175	* may be unreliable.
3c57e89b	176	*/
c5114a1c CL	177	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	178	if (pkg_type == CPUID_PKGTYPE_F)
	179	return true;
	180	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	181	return false;
	182
eefc2d9e	183	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	184	pci_bus_read_config_dword(pdev->bus,
	185	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	186	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	187	if (reg_dram_cfg & DDR3_MODE)
	188	return false;
	189
	190	/*
	191	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	192	* memory. We blacklist all the cores which do exist in socket AM2+
	193	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	194	* and AM3 formats, but that's the best we can do.
	195	*/
	196	return boot_cpu_data.x86_model < 4 \|\|
	197	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
3c57e89b CL	198	}
3c57e89b CL	199
6c931ae1	200	static int k10temp_probe(struct pci_dev *pdev,
3c57e89b CL	201	const struct pci_device_id *id)
3c57e89b CL	202	{
c5114a1c	203	int unreliable = has_erratum_319(pdev);
3e3e1022	204	struct device *dev = &pdev->dev;
68546abf	205	struct k10temp_data *data;
3e3e1022	206	struct device *hwmon_dev;
3c57e89b	207
3e3e1022 GR	208	if (unreliable) {
	209	if (!force) {
	210	dev_err(dev,
	211	"unreliable CPU thermal sensor; monitoring disabled\n");
	212	return -ENODEV;
	213	}
	214	dev_warn(dev,
3c57e89b	215	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	216	}
3c57e89b	217
68546abf GR	218	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	219	if (!data)
	220	return -ENOMEM;
	221
	222	data->pdev = pdev;
	223
	224	if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 \|\|
	225	boot_cpu_data.x86_model == 0x70))
	226	data->read_tempreg = read_tempreg_nb_f15;
	227	else
	228	data->read_tempreg = read_tempreg_pci;
	229
	230	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
3e3e1022 GR	231	k10temp_groups);
3e3e1022 GR	232	return PTR_ERR_OR_ZERO(hwmon_dev);
3c57e89b CL	233	}
3c57e89b CL	234
cd9bb056	235	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	236	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	237	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	238	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	239	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	240	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	241	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	242	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
30b146d1	243	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	244	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
3c57e89b CL	245	{}
	246	};
	247	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	248
	249	static struct pci_driver k10temp_driver = {
	250	.name = "k10temp",
	251	.id_table = k10temp_id_table,
	252	.probe = k10temp_probe,
3c57e89b CL	253	};
3c57e89b CL	254
f71f5a55	255	module_pci_driver(k10temp_driver);