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x86/msr-index: Cleanup bit defines
[mirror_ubuntu-bionic-kernel.git] / drivers / hwmon / nct6775.c
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9de2e2e8
GR		 1/*
2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
4 *
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
6 *
7 * Derived from w83627ehf driver
7c81c60f 8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9de2e2e8
GR		 9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
14 *
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 *
33 * Supports the following chips:
34 *
35 * Chip #vin #fan #pwm #temp chip IDs man ID
6c009501 36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
9de2e2e8
GR		 37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
578ab5f0 40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
8aefb93f 41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
cd1faefa 42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
419220dc
GR		 43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 *
9de2e2e8
GR		 45 *
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
48 */
49
50#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
52#include <linux/module.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <linux/jiffies.h>
56#include <linux/platform_device.h>
57#include <linux/hwmon.h>
58#include <linux/hwmon-sysfs.h>
59#include <linux/hwmon-vid.h>
60#include <linux/err.h>
61#include <linux/mutex.h>
62#include <linux/acpi.h>
d1bb2186 63#include <linux/bitops.h>
25cdd99d 64#include <linux/dmi.h>
9de2e2e8 65#include <linux/io.h>
f3834b85 66#include <linux/nospec.h>
9de2e2e8
GR		 67#include "lm75.h"
68
aa136e5d
GR		 69#define USE_ALTERNATE
70
419220dc
GR		 71enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
72 nct6795 };
9de2e2e8
GR		 73
74/* used to set data->name = nct6775_device_names[data->sio_kind] */
75static const char * const nct6775_device_names[] = {
6c009501 76 "nct6106",
9de2e2e8
GR		 77 "nct6775",
78 "nct6776",
79 "nct6779",
578ab5f0 80 "nct6791",
8aefb93f 81 "nct6792",
cd1faefa 82 "nct6793",
419220dc 83 "nct6795",
cd1faefa
GR		 84};
85
86static const char * const nct6775_sio_names[] __initconst = {
87 "NCT6106D",
88 "NCT6775F",
89 "NCT6776D/F",
90 "NCT6779D",
91 "NCT6791D",
92 "NCT6792D",
93 "NCT6793D",
419220dc 94 "NCT6795D",
9de2e2e8
GR		 95};
96
97static unsigned short force_id;
98module_param(force_id, ushort, 0);
99MODULE_PARM_DESC(force_id, "Override the detected device ID");
100
47ece964
GR		 101static unsigned short fan_debounce;
102module_param(fan_debounce, ushort, 0);
103MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
104
9de2e2e8
GR		 105#define DRVNAME "nct6775"
106
107/*
108 * Super-I/O constants and functions
109 */
110
a6bd5878 111#define NCT6775_LD_ACPI 0x0a
9de2e2e8
GR		 112#define NCT6775_LD_HWM 0x0b
113#define NCT6775_LD_VID 0x0d
e5c85221 114#define NCT6775_LD_12 0x12
9de2e2e8
GR		 115
116#define SIO_REG_LDSEL 0x07 /* Logical device select */
117#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
118#define SIO_REG_ENABLE 0x30 /* Logical device enable */
119#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
120
6c009501 121#define SIO_NCT6106_ID 0xc450
9de2e2e8
GR		 122#define SIO_NCT6775_ID 0xb470
123#define SIO_NCT6776_ID 0xc330
124#define SIO_NCT6779_ID 0xc560
578ab5f0 125#define SIO_NCT6791_ID 0xc800
8aefb93f 126#define SIO_NCT6792_ID 0xc910
cd1faefa 127#define SIO_NCT6793_ID 0xd120
419220dc 128#define SIO_NCT6795_ID 0xd350
9de2e2e8
GR		 129#define SIO_ID_MASK 0xFFF0
130
77eb5b37
GR		 131enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
132
9de2e2e8
GR		 133static inline void
134superio_outb(int ioreg, int reg, int val)
135{
136 outb(reg, ioreg);
137 outb(val, ioreg + 1);
138}
139
140static inline int
141superio_inb(int ioreg, int reg)
142{
143 outb(reg, ioreg);
144 return inb(ioreg + 1);
145}
146
147static inline void
148superio_select(int ioreg, int ld)
149{
150 outb(SIO_REG_LDSEL, ioreg);
151 outb(ld, ioreg + 1);
152}
153
154static inline int
155superio_enter(int ioreg)
156{
157 /*
158 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
159 */
160 if (!request_muxed_region(ioreg, 2, DRVNAME))
161 return -EBUSY;
162
163 outb(0x87, ioreg);
164 outb(0x87, ioreg);
165
166 return 0;
167}
168
169static inline void
170superio_exit(int ioreg)
171{
172 outb(0xaa, ioreg);
173 outb(0x02, ioreg);
174 outb(0x02, ioreg + 1);
175 release_region(ioreg, 2);
176}
177
178/*
179 * ISA constants
180 */
181
182#define IOREGION_ALIGNMENT (~7)
183#define IOREGION_OFFSET 5
184#define IOREGION_LENGTH 2
185#define ADDR_REG_OFFSET 0
186#define DATA_REG_OFFSET 1
187
188#define NCT6775_REG_BANK 0x4E
189#define NCT6775_REG_CONFIG 0x40
190
191/*
192 * Not currently used:
193 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
194 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
195 * REG_MAN_ID is at port 0x4f
196 * REG_CHIP_ID is at port 0x58
197 */
198
aa136e5d
GR		 199#define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
200#define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
201
6c009501 202#define NUM_REG_ALARM 7 /* Max number of alarm registers */
30846993 203#define NUM_REG_BEEP 5 /* Max number of beep registers */
9de2e2e8 204
578ab5f0
DB		 205#define NUM_FAN 6
206
7ce4190c
GR		 207#define TEMP_SOURCE_VIRTUAL 0x1f
208
9de2e2e8
GR		 209/* Common and NCT6775 specific data */
210
211/* Voltage min/max registers for nr=7..14 are in bank 5 */
212
213static const u16 NCT6775_REG_IN_MAX[] = {
214 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
215 0x55c, 0x55e, 0x560, 0x562 };
216static const u16 NCT6775_REG_IN_MIN[] = {
217 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
218 0x55d, 0x55f, 0x561, 0x563 };
219static const u16 NCT6775_REG_IN[] = {
220 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
221};
222
223#define NCT6775_REG_VBAT 0x5D
aa136e5d 224#define NCT6775_REG_DIODE 0x5E
6c009501 225#define NCT6775_DIODE_MASK 0x02
9de2e2e8 226
1c65dc36
GR		 227#define NCT6775_REG_FANDIV1 0x506
228#define NCT6775_REG_FANDIV2 0x507
229
47ece964
GR		 230#define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
231
9de2e2e8
GR		 232static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
233
30846993 234/* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
9de2e2e8
GR		 235
236static const s8 NCT6775_ALARM_BITS[] = {
237 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
238 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
239 -1, /* unused */
41fa9a94 240 6, 7, 11, -1, -1, /* fan1..fan5 */
9de2e2e8
GR		 241 -1, -1, -1, /* unused */
242 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
243 12, -1 }; /* intrusion0, intrusion1 */
244
1c65dc36 245#define FAN_ALARM_BASE 16
aa136e5d 246#define TEMP_ALARM_BASE 24
a6bd5878
GR		 247#define INTRUSION_ALARM_BASE 30
248
30846993
GR		 249static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
250
251/*
252 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
253 * 30..31 intrusion
254 */
255static const s8 NCT6775_BEEP_BITS[] = {
256 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
257 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
258 21, /* global beep enable */
259 6, 7, 11, 28, -1, /* fan1..fan5 */
260 -1, -1, -1, /* unused */
261 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
262 12, -1 }; /* intrusion0, intrusion1 */
263
264#define BEEP_ENABLE_BASE 15
265
a6bd5878
GR		 266static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
267static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
268
77eb5b37
GR		 269/* DC or PWM output fan configuration */
270static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
271static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
272
cdcaeceb 273/* Advanced Fan control, some values are common for all fans */
77eb5b37 274
578ab5f0
DB		 275static const u16 NCT6775_REG_TARGET[] = {
276 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01 };
277static const u16 NCT6775_REG_FAN_MODE[] = {
278 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02 };
cdcaeceb 279static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
578ab5f0 280 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03 };
cdcaeceb 281static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
578ab5f0 282 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04 };
cdcaeceb 283static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
578ab5f0
DB		 284 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05 };
285static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
286 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06 };
cdcaeceb
GR		 287static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
288static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
289
290static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
578ab5f0
DB		 291 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07 };
292static const u16 NCT6775_REG_PWM[] = {
293 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09 };
294static const u16 NCT6775_REG_PWM_READ[] = {
295 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09 };
77eb5b37 296
1c65dc36
GR		 297static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
298static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
5c25d954 299static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
578ab5f0 300static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
1c65dc36 301
aa136e5d
GR		 302static const u16 NCT6775_REG_TEMP[] = {
303 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
304
d1a284b7
GR		 305static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
306
aa136e5d
GR		 307static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
308 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
309static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
310 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
311static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
312 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
313
314static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
315 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
316
cdcaeceb 317static const u16 NCT6775_REG_TEMP_SEL[] = {
578ab5f0 318 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00 };
cdcaeceb 319
bbd8decd 320static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
578ab5f0 321 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
bbd8decd 322static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
578ab5f0 323 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
bbd8decd 324static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
578ab5f0 325 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
bbd8decd 326static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
578ab5f0 327 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
bbd8decd 328static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
578ab5f0 329 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
bbd8decd 330
aa136e5d
GR		 331static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
332
cdcaeceb 333static const u16 NCT6775_REG_AUTO_TEMP[] = {
578ab5f0 334 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21 };
cdcaeceb 335static const u16 NCT6775_REG_AUTO_PWM[] = {
578ab5f0 336 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27 };
cdcaeceb
GR		 337
338#define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
339#define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
340
341static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
342
343static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
578ab5f0 344 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35 };
cdcaeceb 345static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
578ab5f0 346 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38 };
cdcaeceb 347
aa136e5d
GR		 348static const char *const nct6775_temp_label[] = {
349 "",
350 "SYSTIN",
351 "CPUTIN",
352 "AUXTIN",
353 "AMD SB-TSI",
354 "PECI Agent 0",
355 "PECI Agent 1",
356 "PECI Agent 2",
357 "PECI Agent 3",
358 "PECI Agent 4",
359 "PECI Agent 5",
360 "PECI Agent 6",
361 "PECI Agent 7",
362 "PCH_CHIP_CPU_MAX_TEMP",
363 "PCH_CHIP_TEMP",
364 "PCH_CPU_TEMP",
365 "PCH_MCH_TEMP",
366 "PCH_DIM0_TEMP",
367 "PCH_DIM1_TEMP",
368 "PCH_DIM2_TEMP",
369 "PCH_DIM3_TEMP"
370};
371
cc66b303 372#define NCT6775_TEMP_MASK 0x001ffffe
aa136e5d 373
cc66b303
GR		 374static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
375 [13] = 0x661,
376 [14] = 0x662,
377 [15] = 0x664,
378};
379
380static const u16 NCT6775_REG_TEMP_CRIT[32] = {
381 [4] = 0xa00,
382 [5] = 0xa01,
383 [6] = 0xa02,
384 [7] = 0xa03,
385 [8] = 0xa04,
386 [9] = 0xa05,
387 [10] = 0xa06,
388 [11] = 0xa07
389};
aa136e5d 390
9de2e2e8
GR		 391/* NCT6776 specific data */
392
728d2940
GR		 393/* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
394#define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
395#define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
396
9de2e2e8
GR		 397static const s8 NCT6776_ALARM_BITS[] = {
398 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
399 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
400 -1, /* unused */
401 6, 7, 11, 10, 23, /* fan1..fan5 */
402 -1, -1, -1, /* unused */
403 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
404 12, 9 }; /* intrusion0, intrusion1 */
405
30846993
GR		 406static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
407
408static const s8 NCT6776_BEEP_BITS[] = {
409 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
410 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
411 24, /* global beep enable */
412 25, 26, 27, 28, 29, /* fan1..fan5 */
413 -1, -1, -1, /* unused */
414 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
415 30, 31 }; /* intrusion0, intrusion1 */
416
cdcaeceb 417static const u16 NCT6776_REG_TOLERANCE_H[] = {
578ab5f0 418 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c };
cdcaeceb 419
578ab5f0
DB		 420static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
421static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
77eb5b37 422
1c65dc36 423static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642 };
5c25d954 424static const u16 NCT6776_REG_FAN_PULSES[] = { 0x644, 0x645, 0x646, 0, 0 };
1c65dc36 425
bbd8decd 426static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
578ab5f0 427 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
bbd8decd 428
aa136e5d
GR		 429static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
430 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
431
432static const char *const nct6776_temp_label[] = {
433 "",
434 "SYSTIN",
435 "CPUTIN",
436 "AUXTIN",
437 "SMBUSMASTER 0",
438 "SMBUSMASTER 1",
439 "SMBUSMASTER 2",
440 "SMBUSMASTER 3",
441 "SMBUSMASTER 4",
442 "SMBUSMASTER 5",
443 "SMBUSMASTER 6",
444 "SMBUSMASTER 7",
445 "PECI Agent 0",
446 "PECI Agent 1",
447 "PCH_CHIP_CPU_MAX_TEMP",
448 "PCH_CHIP_TEMP",
449 "PCH_CPU_TEMP",
450 "PCH_MCH_TEMP",
451 "PCH_DIM0_TEMP",
452 "PCH_DIM1_TEMP",
453 "PCH_DIM2_TEMP",
454 "PCH_DIM3_TEMP",
455 "BYTE_TEMP"
456};
457
cc66b303 458#define NCT6776_TEMP_MASK 0x007ffffe
aa136e5d 459
cc66b303
GR		 460static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
461 [14] = 0x401,
462 [15] = 0x402,
463 [16] = 0x404,
464};
465
466static const u16 NCT6776_REG_TEMP_CRIT[32] = {
467 [11] = 0x709,
468 [12] = 0x70a,
469};
aa136e5d 470
9de2e2e8
GR		 471/* NCT6779 specific data */
472
473static const u16 NCT6779_REG_IN[] = {
474 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
475 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
476
477static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
478 0x459, 0x45A, 0x45B, 0x568 };
479
480static const s8 NCT6779_ALARM_BITS[] = {
481 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
482 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
483 -1, /* unused */
484 6, 7, 11, 10, 23, /* fan1..fan5 */
485 -1, -1, -1, /* unused */
486 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
487 12, 9 }; /* intrusion0, intrusion1 */
488
30846993
GR		 489static const s8 NCT6779_BEEP_BITS[] = {
490 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
491 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
492 24, /* global beep enable */
493 25, 26, 27, 28, 29, /* fan1..fan5 */
494 -1, -1, -1, /* unused */
495 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
496 30, 31 }; /* intrusion0, intrusion1 */
497
578ab5f0
DB		 498static const u16 NCT6779_REG_FAN[] = {
499 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba };
5c25d954 500static const u16 NCT6779_REG_FAN_PULSES[] = {
578ab5f0 501 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
1c65dc36 502
cdcaeceb 503static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
578ab5f0 504 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36 };
6c009501 505#define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
cdcaeceb 506static const u16 NCT6779_REG_CRITICAL_PWM[] = {
578ab5f0 507 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37 };
cdcaeceb 508
aa136e5d 509static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
d1a284b7 510static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
aa136e5d
GR		 511static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
512 0x18, 0x152 };
513static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
514 0x3a, 0x153 };
515static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
516 0x39, 0x155 };
517
518static const u16 NCT6779_REG_TEMP_OFFSET[] = {
519 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
520
521static const char *const nct6779_temp_label[] = {
522 "",
523 "SYSTIN",
524 "CPUTIN",
525 "AUXTIN0",
526 "AUXTIN1",
527 "AUXTIN2",
528 "AUXTIN3",
529 "",
530 "SMBUSMASTER 0",
531 "SMBUSMASTER 1",
532 "SMBUSMASTER 2",
533 "SMBUSMASTER 3",
534 "SMBUSMASTER 4",
535 "SMBUSMASTER 5",
536 "SMBUSMASTER 6",
537 "SMBUSMASTER 7",
538 "PECI Agent 0",
539 "PECI Agent 1",
540 "PCH_CHIP_CPU_MAX_TEMP",
541 "PCH_CHIP_TEMP",
542 "PCH_CPU_TEMP",
543 "PCH_MCH_TEMP",
544 "PCH_DIM0_TEMP",
545 "PCH_DIM1_TEMP",
546 "PCH_DIM2_TEMP",
547 "PCH_DIM3_TEMP",
9a38371a
GR		 548 "BYTE_TEMP",
549 "",
550 "",
551 "",
552 "",
553 "Virtual_TEMP"
aa136e5d
GR		 554};
555
cc66b303
GR		 556#define NCT6779_TEMP_MASK 0x07ffff7e
557#define NCT6791_TEMP_MASK 0x87ffff7e
9a38371a 558
cc66b303 559static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
aa136e5d
GR		 560 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
561 0, 0, 0, 0, 0, 0, 0, 0,
562 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
563 0x408, 0 };
564
cc66b303
GR		 565static const u16 NCT6779_REG_TEMP_CRIT[32] = {
566 [15] = 0x709,
567 [16] = 0x70a,
568};
aa136e5d 569
578ab5f0
DB		 570/* NCT6791 specific data */
571
572#define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
573
cc76dee1
GR		 574static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[6] = { 0, 0x239 };
575static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[6] = { 0, 0x23a };
576static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[6] = { 0, 0x23b };
577static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[6] = { 0, 0x23c };
578static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[6] = { 0, 0x23d };
579static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[6] = { 0, 0x23e };
580
578ab5f0
DB		 581static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
582 0x459, 0x45A, 0x45B, 0x568, 0x45D };
583
584static const s8 NCT6791_ALARM_BITS[] = {
585 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
586 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
587 -1, /* unused */
588 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
589 -1, -1, /* unused */
590 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
591 12, 9 }; /* intrusion0, intrusion1 */
592
cd1faefa 593/* NCT6792/NCT6793 specific data */
8aefb93f
GR		 594
595static const u16 NCT6792_REG_TEMP_MON[] = {
596 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
597static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
598 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
578ab5f0 599
50224f4d
GR		 600static const char *const nct6792_temp_label[] = {
601 "",
602 "SYSTIN",
603 "CPUTIN",
604 "AUXTIN0",
605 "AUXTIN1",
606 "AUXTIN2",
607 "AUXTIN3",
608 "",
609 "SMBUSMASTER 0",
610 "SMBUSMASTER 1",
611 "SMBUSMASTER 2",
612 "SMBUSMASTER 3",
613 "SMBUSMASTER 4",
614 "SMBUSMASTER 5",
615 "SMBUSMASTER 6",
616 "SMBUSMASTER 7",
617 "PECI Agent 0",
618 "PECI Agent 1",
619 "PCH_CHIP_CPU_MAX_TEMP",
620 "PCH_CHIP_TEMP",
621 "PCH_CPU_TEMP",
622 "PCH_MCH_TEMP",
623 "PCH_DIM0_TEMP",
624 "PCH_DIM1_TEMP",
625 "PCH_DIM2_TEMP",
626 "PCH_DIM3_TEMP",
627 "BYTE_TEMP",
628 "PECI Agent 0 Calibration",
629 "PECI Agent 1 Calibration",
630 "",
631 "",
632 "Virtual_TEMP"
633};
634
cc66b303
GR		 635#define NCT6792_TEMP_MASK 0x9fffff7e
636
50224f4d
GR		 637static const char *const nct6793_temp_label[] = {
638 "",
639 "SYSTIN",
640 "CPUTIN",
641 "AUXTIN0",
642 "AUXTIN1",
643 "AUXTIN2",
644 "AUXTIN3",
645 "",
646 "SMBUSMASTER 0",
647 "SMBUSMASTER 1",
648 "",
649 "",
650 "",
651 "",
652 "",
653 "",
654 "PECI Agent 0",
655 "PECI Agent 1",
656 "PCH_CHIP_CPU_MAX_TEMP",
657 "PCH_CHIP_TEMP",
658 "PCH_CPU_TEMP",
659 "PCH_MCH_TEMP",
660 "Agent0 Dimm0 ",
661 "Agent0 Dimm1",
662 "Agent1 Dimm0",
663 "Agent1 Dimm1",
664 "BYTE_TEMP0",
665 "BYTE_TEMP1",
666 "PECI Agent 0 Calibration",
667 "PECI Agent 1 Calibration",
668 "",
669 "Virtual_TEMP"
670};
671
cc66b303
GR		 672#define NCT6793_TEMP_MASK 0xbfff037e
673
419220dc
GR		 674static const char *const nct6795_temp_label[] = {
675 "",
676 "SYSTIN",
677 "CPUTIN",
678 "AUXTIN0",
679 "AUXTIN1",
680 "AUXTIN2",
681 "AUXTIN3",
682 "",
683 "SMBUSMASTER 0",
684 "SMBUSMASTER 1",
685 "SMBUSMASTER 2",
686 "SMBUSMASTER 3",
687 "SMBUSMASTER 4",
688 "SMBUSMASTER 5",
689 "SMBUSMASTER 6",
690 "SMBUSMASTER 7",
691 "PECI Agent 0",
692 "PECI Agent 1",
693 "PCH_CHIP_CPU_MAX_TEMP",
694 "PCH_CHIP_TEMP",
695 "PCH_CPU_TEMP",
696 "PCH_MCH_TEMP",
697 "PCH_DIM0_TEMP",
698 "PCH_DIM1_TEMP",
699 "PCH_DIM2_TEMP",
700 "PCH_DIM3_TEMP",
701 "BYTE_TEMP0",
702 "BYTE_TEMP1",
703 "PECI Agent 0 Calibration",
704 "PECI Agent 1 Calibration",
705 "",
706 "Virtual_TEMP"
707};
708
709#define NCT6795_TEMP_MASK 0xbfffff7e
710
6c009501
GR		 711/* NCT6102D/NCT6106D specific data */
712
713#define NCT6106_REG_VBAT 0x318
714#define NCT6106_REG_DIODE 0x319
715#define NCT6106_DIODE_MASK 0x01
716
717static const u16 NCT6106_REG_IN_MAX[] = {
718 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
719static const u16 NCT6106_REG_IN_MIN[] = {
720 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
721static const u16 NCT6106_REG_IN[] = {
722 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
723
724static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
d1a284b7 725static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
6c009501
GR		 726static const u16 NCT6106_REG_TEMP_HYST[] = {
727 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
728static const u16 NCT6106_REG_TEMP_OVER[] = {
b7a61353
GR		 729 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
730static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
731 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
732static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
733 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
6c009501
GR		 734static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
735static const u16 NCT6106_REG_TEMP_CONFIG[] = {
736 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
737
738static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
739static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
740static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
741static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
742
743static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
744static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
745static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
746static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
747static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
748static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
749static const u16 NCT6106_REG_TEMP_SOURCE[] = {
750 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
751
752static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
753static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
754 0x11b, 0x12b, 0x13b };
755
756static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
757#define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
758static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
759
760static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
761static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
762static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
763static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
764static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
765static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
766
767static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
768
769static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
770static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
771static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
772static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
773static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
774static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
775
776static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
777static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
778
779static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
780 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
781
782static const s8 NCT6106_ALARM_BITS[] = {
783 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
784 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
785 -1, /* unused */
786 32, 33, 34, -1, -1, /* fan1..fan5 */
787 -1, -1, -1, /* unused */
788 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
789 48, -1 /* intrusion0, intrusion1 */
790};
791
30846993
GR		 792static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
793 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
794
795static const s8 NCT6106_BEEP_BITS[] = {
796 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
797 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
798 32, /* global beep enable */
799 24, 25, 26, 27, 28, /* fan1..fan5 */
800 -1, -1, -1, /* unused */
801 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
802 34, -1 /* intrusion0, intrusion1 */
803};
804
cc66b303
GR		 805static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
806 [14] = 0x51,
807 [15] = 0x52,
808 [16] = 0x54,
809};
6c009501 810
cc66b303
GR		 811static const u16 NCT6106_REG_TEMP_CRIT[32] = {
812 [11] = 0x204,
813 [12] = 0x205,
814};
6c009501 815
77eb5b37
GR		 816static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
817{
818 if (mode == 0 && pwm == 255)
819 return off;
820 return mode + 1;
821}
822
823static int pwm_enable_to_reg(enum pwm_enable mode)
824{
825 if (mode == off)
826 return 0;
827 return mode - 1;
828}
829
9de2e2e8
GR		 830/*
831 * Conversions
832 */
833
cdcaeceb
GR		 834/* 1 is DC mode, output in ms */
835static unsigned int step_time_from_reg(u8 reg, u8 mode)
836{
837 return mode ? 400 * reg : 100 * reg;
838}
839
840static u8 step_time_to_reg(unsigned int msec, u8 mode)
841{
842 return clamp_val((mode ? (msec + 200) / 400 :
843 (msec + 50) / 100), 1, 255);
844}
845
1c65dc36
GR		 846static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
847{
848 if (reg == 0 || reg == 255)
849 return 0;
850 return 1350000U / (reg << divreg);
851}
852
853static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
854{
855 if ((reg & 0xff1f) == 0xff1f)
856 return 0;
857
858 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
859
860 if (reg == 0)
861 return 0;
862
863 return 1350000U / reg;
864}
865
866static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
867{
868 if (reg == 0 || reg == 0xffff)
869 return 0;
870
871 /*
872 * Even though the registers are 16 bit wide, the fan divisor
873 * still applies.
874 */
875 return 1350000U / (reg << divreg);
876}
877
cdcaeceb
GR		 878static u16 fan_to_reg(u32 fan, unsigned int divreg)
879{
880 if (!fan)
881 return 0;
882
883 return (1350000U / fan) >> divreg;
884}
885
1c65dc36
GR		 886static inline unsigned int
887div_from_reg(u8 reg)
888{
d1bb2186 889 return BIT(reg);
1c65dc36
GR		 890}
891
9de2e2e8
GR		 892/*
893 * Some of the voltage inputs have internal scaling, the tables below
894 * contain 8 (the ADC LSB in mV) * scaling factor * 100
895 */
896static const u16 scale_in[15] = {
897 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
898 800, 800
899};
900
901static inline long in_from_reg(u8 reg, u8 nr)
902{
903 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
904}
905
906static inline u8 in_to_reg(u32 val, u8 nr)
907{
908 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
909}
910
911/*
912 * Data structures and manipulation thereof
913 */
914
915struct nct6775_data {
916 int addr; /* IO base of hw monitor block */
df612d5f 917 int sioreg; /* SIO register address */
9de2e2e8
GR		 918 enum kinds kind;
919 const char *name;
920
615fc8cb 921 const struct attribute_group *groups[6];
9de2e2e8 922
b7a61353
GR		 923 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
924 * 3=temp_crit, 4=temp_lcrit
aa136e5d
GR		 925 */
926 u8 temp_src[NUM_TEMP];
927 u16 reg_temp_config[NUM_TEMP];
928 const char * const *temp_label;
cc66b303 929 u32 temp_mask;
aa136e5d 930
9de2e2e8
GR		 931 u16 REG_CONFIG;
932 u16 REG_VBAT;
aa136e5d 933 u16 REG_DIODE;
6c009501 934 u8 DIODE_MASK;
9de2e2e8
GR		 935
936 const s8 *ALARM_BITS;
30846993 937 const s8 *BEEP_BITS;
9de2e2e8
GR		 938
939 const u16 *REG_VIN;
940 const u16 *REG_IN_MINMAX[2];
941
cdcaeceb 942 const u16 *REG_TARGET;
1c65dc36 943 const u16 *REG_FAN;
77eb5b37 944 const u16 *REG_FAN_MODE;
1c65dc36 945 const u16 *REG_FAN_MIN;
5c25d954 946 const u16 *REG_FAN_PULSES;
6c009501 947 const u16 *FAN_PULSE_SHIFT;
cdcaeceb
GR		 948 const u16 *REG_FAN_TIME[3];
949
950 const u16 *REG_TOLERANCE_H;
aa136e5d 951
77eb5b37
GR		 952 const u8 *REG_PWM_MODE;
953 const u8 *PWM_MODE_MASK;
954
bbd8decd
GR		 955 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
956 * [3]=pwm_max, [4]=pwm_step,
957 * [5]=weight_duty_step, [6]=weight_duty_base
cdcaeceb 958 */
77eb5b37
GR		 959 const u16 *REG_PWM_READ;
960
6c009501
GR		 961 const u16 *REG_CRITICAL_PWM_ENABLE;
962 u8 CRITICAL_PWM_ENABLE_MASK;
963 const u16 *REG_CRITICAL_PWM;
964
cdcaeceb
GR		 965 const u16 *REG_AUTO_TEMP;
966 const u16 *REG_AUTO_PWM;
967
968 const u16 *REG_CRITICAL_TEMP;
969 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
970
1c65dc36 971 const u16 *REG_TEMP_SOURCE; /* temp register sources */
cdcaeceb 972 const u16 *REG_TEMP_SEL;
bbd8decd
GR		 973 const u16 *REG_WEIGHT_TEMP_SEL;
974 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
975
aa136e5d
GR		 976 const u16 *REG_TEMP_OFFSET;
977
9de2e2e8 978 const u16 *REG_ALARM;
30846993 979 const u16 *REG_BEEP;
9de2e2e8 980
1c65dc36
GR		 981 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
982 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
983
9de2e2e8
GR		 984 struct mutex update_lock;
985 bool valid; /* true if following fields are valid */
986 unsigned long last_updated; /* In jiffies */
987
988 /* Register values */
989 u8 bank; /* current register bank */
990 u8 in_num; /* number of in inputs we have */
991 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
578ab5f0
DB		 992 unsigned int rpm[NUM_FAN];
993 u16 fan_min[NUM_FAN];
994 u8 fan_pulses[NUM_FAN];
995 u8 fan_div[NUM_FAN];
77eb5b37 996 u8 has_pwm;
1c65dc36
GR		 997 u8 has_fan; /* some fan inputs can be disabled */
998 u8 has_fan_min; /* some fans don't have min register */
999 bool has_fan_div;
9de2e2e8 1000
6c009501 1001 u8 num_temp_alarms; /* 2, 3, or 6 */
30846993 1002 u8 num_temp_beeps; /* 2, 3, or 6 */
aa136e5d
GR		 1003 u8 temp_fixed_num; /* 3 or 6 */
1004 u8 temp_type[NUM_TEMP_FIXED];
1005 s8 temp_offset[NUM_TEMP_FIXED];
f58876ac
DC		 1006 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1007 * 3=temp_crit, 4=temp_lcrit */
9de2e2e8 1008 u64 alarms;
30846993 1009 u64 beeps;
9de2e2e8 1010
77eb5b37 1011 u8 pwm_num; /* number of pwm */
578ab5f0
DB		 1012 u8 pwm_mode[NUM_FAN]; /* 1->DC variable voltage,
1013 * 0->PWM variable duty cycle
1014 */
1015 enum pwm_enable pwm_enable[NUM_FAN];
77eb5b37
GR		 1016 /* 0->off
1017 * 1->manual
1018 * 2->thermal cruise mode (also called SmartFan I)
1019 * 3->fan speed cruise mode
1020 * 4->SmartFan III
1021 * 5->enhanced variable thermal cruise (SmartFan IV)
1022 */
578ab5f0
DB		 1023 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1024 * [3]=pwm_max, [4]=pwm_step,
1025 * [5]=weight_duty_step, [6]=weight_duty_base
1026 */
cdcaeceb 1027
578ab5f0 1028 u8 target_temp[NUM_FAN];
cdcaeceb 1029 u8 target_temp_mask;
578ab5f0
DB		 1030 u32 target_speed[NUM_FAN];
1031 u32 target_speed_tolerance[NUM_FAN];
cdcaeceb
GR		 1032 u8 speed_tolerance_limit;
1033
578ab5f0 1034 u8 temp_tolerance[2][NUM_FAN];
cdcaeceb
GR		 1035 u8 tolerance_mask;
1036
578ab5f0 1037 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
cdcaeceb
GR		 1038
1039 /* Automatic fan speed control registers */
1040 int auto_pwm_num;
578ab5f0
DB		 1041 u8 auto_pwm[NUM_FAN][7];
1042 u8 auto_temp[NUM_FAN][7];
1043 u8 pwm_temp_sel[NUM_FAN];
1044 u8 pwm_weight_temp_sel[NUM_FAN];
1045 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1046 * 2->temp_base
1047 */
77eb5b37 1048
9de2e2e8
GR		 1049 u8 vid;
1050 u8 vrm;
1051
f73cf632
GR		 1052 bool have_vid;
1053
aa136e5d
GR		 1054 u16 have_temp;
1055 u16 have_temp_fixed;
9de2e2e8 1056 u16 have_in;
48e93182 1057
84d19d92
GR		 1058 /* Remember extra register values over suspend/resume */
1059 u8 vbat;
1060 u8 fandiv1;
1061 u8 fandiv2;
d2a14ea5 1062 u8 sio_reg_enable;
9de2e2e8
GR		 1063};
1064
1065struct nct6775_sio_data {
1066 int sioreg;
1067 enum kinds kind;
1068};
1069
f73cf632
GR		 1070struct sensor_device_template {
1071 struct device_attribute dev_attr;
1072 union {
1073 struct {
1074 u8 nr;
1075 u8 index;
1076 } s;
1077 int index;
1078 } u;
1079 bool s2; /* true if both index and nr are used */
1080};
1081
1082struct sensor_device_attr_u {
1083 union {
1084 struct sensor_device_attribute a1;
1085 struct sensor_device_attribute_2 a2;
1086 } u;
1087 char name[32];
1088};
1089
1090#define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1091 .attr = {.name = _template, .mode = _mode }, \
1092 .show = _show, \
1093 .store = _store, \
1094}
1095
1096#define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1097 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1098 .u.index = _index, \
1099 .s2 = false }
1100
1101#define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1102 _nr, _index) \
1103 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1104 .u.s.index = _index, \
1105 .u.s.nr = _nr, \
1106 .s2 = true }
1107
1108#define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1109static struct sensor_device_template sensor_dev_template_##_name \
1110 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1111 _index)
1112
1113#define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1114 _nr, _index) \
1115static struct sensor_device_template sensor_dev_template_##_name \
1116 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1117 _nr, _index)
1118
1119struct sensor_template_group {
1120 struct sensor_device_template **templates;
1121 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1122 int base;
1123};
1124
1125static struct attribute_group *
c60fdf85
JL		 1126nct6775_create_attr_group(struct device *dev,
1127 const struct sensor_template_group *tg,
f73cf632
GR		 1128 int repeat)
1129{
1130 struct attribute_group *group;
1131 struct sensor_device_attr_u *su;
1132 struct sensor_device_attribute *a;
1133 struct sensor_device_attribute_2 *a2;
1134 struct attribute **attrs;
1135 struct sensor_device_template **t;
1e687e80 1136 int i, count;
f73cf632
GR		 1137
1138 if (repeat <= 0)
1139 return ERR_PTR(-EINVAL);
1140
1141 t = tg->templates;
1142 for (count = 0; *t; t++, count++)
1143 ;
1144
1145 if (count == 0)
1146 return ERR_PTR(-EINVAL);
1147
1148 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1149 if (group == NULL)
1150 return ERR_PTR(-ENOMEM);
1151
1152 attrs = devm_kzalloc(dev, sizeof(*attrs) * (repeat * count + 1),
1153 GFP_KERNEL);
1154 if (attrs == NULL)
1155 return ERR_PTR(-ENOMEM);
1156
1157 su = devm_kzalloc(dev, sizeof(*su) * repeat * count,
1158 GFP_KERNEL);
1159 if (su == NULL)
1160 return ERR_PTR(-ENOMEM);
1161
1162 group->attrs = attrs;
1163 group->is_visible = tg->is_visible;
1164
1165 for (i = 0; i < repeat; i++) {
1166 t = tg->templates;
1e687e80 1167 while (*t != NULL) {
f73cf632
GR		 1168 snprintf(su->name, sizeof(su->name),
1169 (*t)->dev_attr.attr.name, tg->base + i);
1170 if ((*t)->s2) {
1171 a2 = &su->u.a2;
1b63bf61 1172 sysfs_attr_init(&a2->dev_attr.attr);
f73cf632
GR		 1173 a2->dev_attr.attr.name = su->name;
1174 a2->nr = (*t)->u.s.nr + i;
1175 a2->index = (*t)->u.s.index;
1176 a2->dev_attr.attr.mode =
1177 (*t)->dev_attr.attr.mode;
1178 a2->dev_attr.show = (*t)->dev_attr.show;
1179 a2->dev_attr.store = (*t)->dev_attr.store;
1180 *attrs = &a2->dev_attr.attr;
1181 } else {
1182 a = &su->u.a1;
1b63bf61 1183 sysfs_attr_init(&a->dev_attr.attr);
f73cf632
GR		 1184 a->dev_attr.attr.name = su->name;
1185 a->index = (*t)->u.index + i;
1186 a->dev_attr.attr.mode =
1187 (*t)->dev_attr.attr.mode;
1188 a->dev_attr.show = (*t)->dev_attr.show;
1189 a->dev_attr.store = (*t)->dev_attr.store;
1190 *attrs = &a->dev_attr.attr;
1191 }
1192 attrs++;
1193 su++;
1194 t++;
1195 }
1196 }
1197
f73cf632
GR		 1198 return group;
1199}
1200
9de2e2e8
GR		 1201static bool is_word_sized(struct nct6775_data *data, u16 reg)
1202{
1203 switch (data->kind) {
6c009501
GR		 1204 case nct6106:
1205 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1206 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1207 reg == 0x111 || reg == 0x121 || reg == 0x131;
9de2e2e8
GR		 1208 case nct6775:
1209 return (((reg & 0xff00) == 0x100 ||
1210 (reg & 0xff00) == 0x200) &&
1211 ((reg & 0x00ff) == 0x50 ||
1212 (reg & 0x00ff) == 0x53 ||
1213 (reg & 0x00ff) == 0x55)) ||
1214 (reg & 0xfff0) == 0x630 ||
1215 reg == 0x640 || reg == 0x642 ||
1216 reg == 0x662 ||
1217 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1218 reg == 0x73 || reg == 0x75 || reg == 0x77;
1219 case nct6776:
1220 return (((reg & 0xff00) == 0x100 ||
1221 (reg & 0xff00) == 0x200) &&
1222 ((reg & 0x00ff) == 0x50 ||
1223 (reg & 0x00ff) == 0x53 ||
1224 (reg & 0x00ff) == 0x55)) ||
1225 (reg & 0xfff0) == 0x630 ||
1226 reg == 0x402 ||
1227 reg == 0x640 || reg == 0x642 ||
1228 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1229 reg == 0x73 || reg == 0x75 || reg == 0x77;
1230 case nct6779:
578ab5f0 1231 case nct6791:
8aefb93f 1232 case nct6792:
cd1faefa 1233 case nct6793:
419220dc 1234 case nct6795:
9de2e2e8 1235 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
578ab5f0 1236 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
9de2e2e8
GR		 1237 reg == 0x402 ||
1238 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1239 reg == 0x640 || reg == 0x642 ||
1240 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
8aefb93f 1241 reg == 0x7b || reg == 0x7d;
9de2e2e8
GR		 1242 }
1243 return false;
1244}
1245
1246/*
1247 * On older chips, only registers 0x50-0x5f are banked.
1248 * On more recent chips, all registers are banked.
1249 * Assume that is the case and set the bank number for each access.
1250 * Cache the bank number so it only needs to be set if it changes.
1251 */
1252static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1253{
1254 u8 bank = reg >> 8;
9cd892bc 1255
9de2e2e8
GR		 1256 if (data->bank != bank) {
1257 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1258 outb_p(bank, data->addr + DATA_REG_OFFSET);
1259 data->bank = bank;
1260 }
1261}
1262
1263static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1264{
1265 int res, word_sized = is_word_sized(data, reg);
1266
9de2e2e8
GR		 1267 nct6775_set_bank(data, reg);
1268 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1269 res = inb_p(data->addr + DATA_REG_OFFSET);
1270 if (word_sized) {
1271 outb_p((reg & 0xff) + 1,
1272 data->addr + ADDR_REG_OFFSET);
1273 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1274 }
9de2e2e8
GR		 1275 return res;
1276}
1277
1278static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1279{
1280 int word_sized = is_word_sized(data, reg);
1281
9de2e2e8
GR		 1282 nct6775_set_bank(data, reg);
1283 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1284 if (word_sized) {
1285 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1286 outb_p((reg & 0xff) + 1,
1287 data->addr + ADDR_REG_OFFSET);
1288 }
1289 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
9de2e2e8
GR		 1290 return 0;
1291}
1292
aa136e5d
GR		 1293/* We left-align 8-bit temperature values to make the code simpler */
1294static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1295{
1296 u16 res;
1297
1298 res = nct6775_read_value(data, reg);
1299 if (!is_word_sized(data, reg))
1300 res <<= 8;
1301
1302 return res;
1303}
1304
1305static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1306{
1307 if (!is_word_sized(data, reg))
1308 value >>= 8;
1309 return nct6775_write_value(data, reg, value);
1310}
1311
1c65dc36
GR		 1312/* This function assumes that the caller holds data->update_lock */
1313static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1314{
1315 u8 reg;
1316
1317 switch (nr) {
1318 case 0:
1319 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1320 | (data->fan_div[0] & 0x7);
1321 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1322 break;
1323 case 1:
1324 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1325 | ((data->fan_div[1] << 4) & 0x70);
1326 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1327 break;
1328 case 2:
1329 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1330 | (data->fan_div[2] & 0x7);
1331 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1332 break;
1333 case 3:
1334 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1335 | ((data->fan_div[3] << 4) & 0x70);
1336 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1337 break;
1338 }
1339}
1340
1341static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1342{
1343 if (data->kind == nct6775)
1344 nct6775_write_fan_div(data, nr);
1345}
1346
1347static void nct6775_update_fan_div(struct nct6775_data *data)
1348{
1349 u8 i;
1350
1351 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1352 data->fan_div[0] = i & 0x7;
1353 data->fan_div[1] = (i & 0x70) >> 4;
1354 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1355 data->fan_div[2] = i & 0x7;
d1bb2186 1356 if (data->has_fan & BIT(3))
1c65dc36
GR		 1357 data->fan_div[3] = (i & 0x70) >> 4;
1358}
1359
1360static void nct6775_update_fan_div_common(struct nct6775_data *data)
1361{
1362 if (data->kind == nct6775)
1363 nct6775_update_fan_div(data);
1364}
1365
1366static void nct6775_init_fan_div(struct nct6775_data *data)
1367{
1368 int i;
1369
1370 nct6775_update_fan_div_common(data);
1371 /*
1372 * For all fans, start with highest divider value if the divider
1373 * register is not initialized. This ensures that we get a
1374 * reading from the fan count register, even if it is not optimal.
1375 * We'll compute a better divider later on.
1376 */
c409fd43 1377 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
d1bb2186 1378 if (!(data->has_fan & BIT(i)))
1c65dc36
GR		 1379 continue;
1380 if (data->fan_div[i] == 0) {
1381 data->fan_div[i] = 7;
1382 nct6775_write_fan_div_common(data, i);
1383 }
1384 }
1385}
1386
1387static void nct6775_init_fan_common(struct device *dev,
1388 struct nct6775_data *data)
1389{
1390 int i;
1391 u8 reg;
1392
1393 if (data->has_fan_div)
1394 nct6775_init_fan_div(data);
1395
1396 /*
1397 * If fan_min is not set (0), set it to 0xff to disable it. This
1398 * prevents the unnecessary warning when fanX_min is reported as 0.
1399 */
c409fd43 1400 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
d1bb2186 1401 if (data->has_fan_min & BIT(i)) {
1c65dc36
GR		 1402 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1403 if (!reg)
1404 nct6775_write_value(data, data->REG_FAN_MIN[i],
1405 data->has_fan_div ? 0xff
1406 : 0xff1f);
1407 }
1408 }
1409}
1410
1411static void nct6775_select_fan_div(struct device *dev,
1412 struct nct6775_data *data, int nr, u16 reg)
1413{
1414 u8 fan_div = data->fan_div[nr];
1415 u16 fan_min;
1416
1417 if (!data->has_fan_div)
1418 return;
1419
1420 /*
1421 * If we failed to measure the fan speed, or the reported value is not
1422 * in the optimal range, and the clock divider can be modified,
1423 * let's try that for next time.
1424 */
1425 if (reg == 0x00 && fan_div < 0x07)
1426 fan_div++;
1427 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1428 fan_div--;
1429
1430 if (fan_div != data->fan_div[nr]) {
1431 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1432 nr + 1, div_from_reg(data->fan_div[nr]),
1433 div_from_reg(fan_div));
1434
1435 /* Preserve min limit if possible */
d1bb2186 1436 if (data->has_fan_min & BIT(nr)) {
1c65dc36
GR		 1437 fan_min = data->fan_min[nr];
1438 if (fan_div > data->fan_div[nr]) {
1439 if (fan_min != 255 && fan_min > 1)
1440 fan_min >>= 1;
1441 } else {
1442 if (fan_min != 255) {
1443 fan_min <<= 1;
1444 if (fan_min > 254)
1445 fan_min = 254;
1446 }
1447 }
1448 if (fan_min != data->fan_min[nr]) {
1449 data->fan_min[nr] = fan_min;
1450 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1451 fan_min);
1452 }
1453 }
1454 data->fan_div[nr] = fan_div;
1455 nct6775_write_fan_div_common(data, nr);
1456 }
1457}
1458
77eb5b37
GR		 1459static void nct6775_update_pwm(struct device *dev)
1460{
1461 struct nct6775_data *data = dev_get_drvdata(dev);
1462 int i, j;
cdcaeceb 1463 int fanmodecfg, reg;
77eb5b37
GR		 1464 bool duty_is_dc;
1465
1466 for (i = 0; i < data->pwm_num; i++) {
d1bb2186 1467 if (!(data->has_pwm & BIT(i)))
77eb5b37
GR		 1468 continue;
1469
1470 duty_is_dc = data->REG_PWM_MODE[i] &&
1471 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1472 & data->PWM_MODE_MASK[i]);
1743704a 1473 data->pwm_mode[i] = !duty_is_dc;
77eb5b37
GR		 1474
1475 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1476 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1477 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1478 data->pwm[j][i]
1479 = nct6775_read_value(data,
1480 data->REG_PWM[j][i]);
1481 }
1482 }
1483
1484 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1485 (fanmodecfg >> 4) & 7);
cdcaeceb
GR		 1486
1487 if (!data->temp_tolerance[0][i] ||
1488 data->pwm_enable[i] != speed_cruise)
1489 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1490 if (!data->target_speed_tolerance[i] ||
1491 data->pwm_enable[i] == speed_cruise) {
1492 u8 t = fanmodecfg & 0x0f;
9cd892bc 1493
cdcaeceb
GR		 1494 if (data->REG_TOLERANCE_H) {
1495 t |= (nct6775_read_value(data,
1496 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1497 }
1498 data->target_speed_tolerance[i] = t;
1499 }
1500
1501 data->temp_tolerance[1][i] =
1502 nct6775_read_value(data,
1503 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1504
1505 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1506 data->pwm_temp_sel[i] = reg & 0x1f;
1507 /* If fan can stop, report floor as 0 */
1508 if (reg & 0x80)
1509 data->pwm[2][i] = 0;
bbd8decd 1510
cc76dee1
GR		 1511 if (!data->REG_WEIGHT_TEMP_SEL[i])
1512 continue;
1513
bbd8decd
GR		 1514 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1515 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1516 /* If weight is disabled, report weight source as 0 */
1517 if (j == 1 && !(reg & 0x80))
1518 data->pwm_weight_temp_sel[i] = 0;
1519
1520 /* Weight temp data */
c409fd43 1521 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
bbd8decd
GR		 1522 data->weight_temp[j][i]
1523 = nct6775_read_value(data,
1524 data->REG_WEIGHT_TEMP[j][i]);
1525 }
cdcaeceb
GR		 1526 }
1527}
1528
1529static void nct6775_update_pwm_limits(struct device *dev)
1530{
1531 struct nct6775_data *data = dev_get_drvdata(dev);
1532 int i, j;
1533 u8 reg;
1534 u16 reg_t;
1535
1536 for (i = 0; i < data->pwm_num; i++) {
d1bb2186 1537 if (!(data->has_pwm & BIT(i)))
cdcaeceb
GR		 1538 continue;
1539
c409fd43 1540 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
cdcaeceb
GR		 1541 data->fan_time[j][i] =
1542 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1543 }
1544
1545 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1546 /* Update only in matching mode or if never updated */
1547 if (!data->target_temp[i] ||
1548 data->pwm_enable[i] == thermal_cruise)
1549 data->target_temp[i] = reg_t & data->target_temp_mask;
1550 if (!data->target_speed[i] ||
1551 data->pwm_enable[i] == speed_cruise) {
1552 if (data->REG_TOLERANCE_H) {
1553 reg_t |= (nct6775_read_value(data,
1554 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1555 }
1556 data->target_speed[i] = reg_t;
1557 }
1558
1559 for (j = 0; j < data->auto_pwm_num; j++) {
1560 data->auto_pwm[i][j] =
1561 nct6775_read_value(data,
1562 NCT6775_AUTO_PWM(data, i, j));
1563 data->auto_temp[i][j] =
1564 nct6775_read_value(data,
1565 NCT6775_AUTO_TEMP(data, i, j));
1566 }
1567
1568 /* critical auto_pwm temperature data */
1569 data->auto_temp[i][data->auto_pwm_num] =
1570 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1571
1572 switch (data->kind) {
1573 case nct6775:
1574 reg = nct6775_read_value(data,
1575 NCT6775_REG_CRITICAL_ENAB[i]);
1576 data->auto_pwm[i][data->auto_pwm_num] =
1577 (reg & 0x02) ? 0xff : 0x00;
1578 break;
1579 case nct6776:
1580 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1581 break;
6c009501 1582 case nct6106:
cdcaeceb 1583 case nct6779:
578ab5f0 1584 case nct6791:
8aefb93f 1585 case nct6792:
cd1faefa 1586 case nct6793:
419220dc 1587 case nct6795:
cdcaeceb 1588 reg = nct6775_read_value(data,
6c009501
GR		 1589 data->REG_CRITICAL_PWM_ENABLE[i]);
1590 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1591 reg = nct6775_read_value(data,
1592 data->REG_CRITICAL_PWM[i]);
cdcaeceb 1593 else
6c009501
GR		 1594 reg = 0xff;
1595 data->auto_pwm[i][data->auto_pwm_num] = reg;
cdcaeceb
GR		 1596 break;
1597 }
77eb5b37
GR		 1598 }
1599}
1600
9de2e2e8
GR		 1601static struct nct6775_data *nct6775_update_device(struct device *dev)
1602{
1603 struct nct6775_data *data = dev_get_drvdata(dev);
aa136e5d 1604 int i, j;
9de2e2e8
GR		 1605
1606 mutex_lock(&data->update_lock);
1607
6445e660 1608 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
9de2e2e8 1609 || !data->valid) {
1c65dc36
GR		 1610 /* Fan clock dividers */
1611 nct6775_update_fan_div_common(data);
1612
9de2e2e8
GR		 1613 /* Measured voltages and limits */
1614 for (i = 0; i < data->in_num; i++) {
d1bb2186 1615 if (!(data->have_in & BIT(i)))
9de2e2e8
GR		 1616 continue;
1617
1618 data->in[i][0] = nct6775_read_value(data,
1619 data->REG_VIN[i]);
1620 data->in[i][1] = nct6775_read_value(data,
1621 data->REG_IN_MINMAX[0][i]);
1622 data->in[i][2] = nct6775_read_value(data,
1623 data->REG_IN_MINMAX[1][i]);
1624 }
1625
1c65dc36 1626 /* Measured fan speeds and limits */
c409fd43 1627 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1c65dc36
GR		 1628 u16 reg;
1629
d1bb2186 1630 if (!(data->has_fan & BIT(i)))
1c65dc36
GR		 1631 continue;
1632
1633 reg = nct6775_read_value(data, data->REG_FAN[i]);
1634 data->rpm[i] = data->fan_from_reg(reg,
1635 data->fan_div[i]);
1636
d1bb2186 1637 if (data->has_fan_min & BIT(i))
1c65dc36
GR		 1638 data->fan_min[i] = nct6775_read_value(data,
1639 data->REG_FAN_MIN[i]);
5c25d954 1640 data->fan_pulses[i] =
6c009501
GR		 1641 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1642 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1c65dc36
GR		 1643
1644 nct6775_select_fan_div(dev, data, i, reg);
1645 }
1646
77eb5b37 1647 nct6775_update_pwm(dev);
cdcaeceb 1648 nct6775_update_pwm_limits(dev);
77eb5b37 1649
aa136e5d
GR		 1650 /* Measured temperatures and limits */
1651 for (i = 0; i < NUM_TEMP; i++) {
d1bb2186 1652 if (!(data->have_temp & BIT(i)))
aa136e5d 1653 continue;
c409fd43 1654 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
aa136e5d
GR		 1655 if (data->reg_temp[j][i])
1656 data->temp[j][i]
1657 = nct6775_read_temp(data,
1658 data->reg_temp[j][i]);
1659 }
45a5b3a1 1660 if (i >= NUM_TEMP_FIXED ||
d1bb2186 1661 !(data->have_temp_fixed & BIT(i)))
aa136e5d
GR		 1662 continue;
1663 data->temp_offset[i]
1664 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1665 }
1666
9de2e2e8
GR		 1667 data->alarms = 0;
1668 for (i = 0; i < NUM_REG_ALARM; i++) {
1669 u8 alarm;
9cd892bc 1670
9de2e2e8
GR		 1671 if (!data->REG_ALARM[i])
1672 continue;
1673 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1674 data->alarms |= ((u64)alarm) << (i << 3);
1675 }
1676
30846993
GR		 1677 data->beeps = 0;
1678 for (i = 0; i < NUM_REG_BEEP; i++) {
1679 u8 beep;
9cd892bc 1680
30846993
GR		 1681 if (!data->REG_BEEP[i])
1682 continue;
1683 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1684 data->beeps |= ((u64)beep) << (i << 3);
1685 }
1686
9de2e2e8
GR		 1687 data->last_updated = jiffies;
1688 data->valid = true;
1689 }
1690
1691 mutex_unlock(&data->update_lock);
1692 return data;
1693}
1694
1695/*
1696 * Sysfs callback functions
1697 */
1698static ssize_t
1699show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1700{
1701 struct nct6775_data *data = nct6775_update_device(dev);
1702 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
9de2e2e8 1703 int index = sattr->index;
9cd892bc
GR		 1704 int nr = sattr->nr;
1705
9de2e2e8
GR		 1706 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1707}
1708
1709static ssize_t
1710store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1711 size_t count)
1712{
1713 struct nct6775_data *data = dev_get_drvdata(dev);
1714 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
9de2e2e8 1715 int index = sattr->index;
9cd892bc 1716 int nr = sattr->nr;
9de2e2e8 1717 unsigned long val;
9cd892bc
GR		 1718 int err;
1719
1720 err = kstrtoul(buf, 10, &val);
9de2e2e8
GR		 1721 if (err < 0)
1722 return err;
1723 mutex_lock(&data->update_lock);
1724 data->in[nr][index] = in_to_reg(val, nr);
6445e660 1725 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
9de2e2e8
GR		 1726 data->in[nr][index]);
1727 mutex_unlock(&data->update_lock);
1728 return count;
1729}
1730
1731static ssize_t
1732show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1733{
1734 struct nct6775_data *data = nct6775_update_device(dev);
1735 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1736 int nr = data->ALARM_BITS[sattr->index];
9cd892bc 1737
9de2e2e8
GR		 1738 return sprintf(buf, "%u\n",
1739 (unsigned int)((data->alarms >> nr) & 0x01));
1740}
1741
b1d2bff6
GR		 1742static int find_temp_source(struct nct6775_data *data, int index, int count)
1743{
1744 int source = data->temp_src[index];
1745 int nr;
1746
1747 for (nr = 0; nr < count; nr++) {
1748 int src;
1749
1750 src = nct6775_read_value(data,
1751 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1752 if (src == source)
1753 return nr;
1754 }
e8ab508c 1755 return -ENODEV;
b1d2bff6
GR		 1756}
1757
1758static ssize_t
1759show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1760{
1761 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1762 struct nct6775_data *data = nct6775_update_device(dev);
1763 unsigned int alarm = 0;
1764 int nr;
1765
1766 /*
1767 * For temperatures, there is no fixed mapping from registers to alarm
1768 * bits. Alarm bits are determined by the temperature source mapping.
1769 */
1770 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1771 if (nr >= 0) {
1772 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
9cd892bc 1773
b1d2bff6
GR		 1774 alarm = (data->alarms >> bit) & 0x01;
1775 }
1776 return sprintf(buf, "%u\n", alarm);
1777}
1778
30846993
GR		 1779static ssize_t
1780show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1781{
1782 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1783 struct nct6775_data *data = nct6775_update_device(dev);
1784 int nr = data->BEEP_BITS[sattr->index];
1785
1786 return sprintf(buf, "%u\n",
1787 (unsigned int)((data->beeps >> nr) & 0x01));
1788}
1789
1790static ssize_t
1791store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1792 size_t count)
1793{
1794 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1795 struct nct6775_data *data = dev_get_drvdata(dev);
1796 int nr = data->BEEP_BITS[sattr->index];
1797 int regindex = nr >> 3;
1798 unsigned long val;
9cd892bc 1799 int err;
30846993 1800
9cd892bc 1801 err = kstrtoul(buf, 10, &val);
30846993
GR		 1802 if (err < 0)
1803 return err;
1804 if (val > 1)
1805 return -EINVAL;
1806
1807 mutex_lock(&data->update_lock);
1808 if (val)
1809 data->beeps |= (1ULL << nr);
1810 else
1811 data->beeps &= ~(1ULL << nr);
1812 nct6775_write_value(data, data->REG_BEEP[regindex],
1813 (data->beeps >> (regindex << 3)) & 0xff);
1814 mutex_unlock(&data->update_lock);
1815 return count;
1816}
1817
1818static ssize_t
1819show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1820{
1821 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1822 struct nct6775_data *data = nct6775_update_device(dev);
1823 unsigned int beep = 0;
1824 int nr;
1825
1826 /*
1827 * For temperatures, there is no fixed mapping from registers to beep
1828 * enable bits. Beep enable bits are determined by the temperature
1829 * source mapping.
1830 */
1831 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1832 if (nr >= 0) {
1833 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
9cd892bc 1834
30846993
GR		 1835 beep = (data->beeps >> bit) & 0x01;
1836 }
1837 return sprintf(buf, "%u\n", beep);
1838}
1839
1840static ssize_t
1841store_temp_beep(struct device *dev, struct device_attribute *attr,
1842 const char *buf, size_t count)
1843{
1844 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1845 struct nct6775_data *data = dev_get_drvdata(dev);
1846 int nr, bit, regindex;
1847 unsigned long val;
9cd892bc 1848 int err;
30846993 1849
9cd892bc 1850 err = kstrtoul(buf, 10, &val);
30846993
GR		 1851 if (err < 0)
1852 return err;
1853 if (val > 1)
1854 return -EINVAL;
1855
1856 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1857 if (nr < 0)
e8ab508c 1858 return nr;
30846993
GR		 1859
1860 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1861 regindex = bit >> 3;
1862
1863 mutex_lock(&data->update_lock);
1864 if (val)
1865 data->beeps |= (1ULL << bit);
1866 else
1867 data->beeps &= ~(1ULL << bit);
1868 nct6775_write_value(data, data->REG_BEEP[regindex],
1869 (data->beeps >> (regindex << 3)) & 0xff);
1870 mutex_unlock(&data->update_lock);
1871
1872 return count;
1873}
1874
f73cf632
GR		 1875static umode_t nct6775_in_is_visible(struct kobject *kobj,
1876 struct attribute *attr, int index)
1877{
1878 struct device *dev = container_of(kobj, struct device, kobj);
1879 struct nct6775_data *data = dev_get_drvdata(dev);
30846993 1880 int in = index / 5; /* voltage index */
f73cf632 1881
d1bb2186 1882 if (!(data->have_in & BIT(in)))
f73cf632
GR		 1883 return 0;
1884
1885 return attr->mode;
1886}
1887
1888SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1889SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
30846993
GR		 1890SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1891 0);
f73cf632
GR		 1892SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1893 store_in_reg, 0, 1);
1894SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1895 store_in_reg, 0, 2);
1896
1897/*
1898 * nct6775_in_is_visible uses the index into the following array
1899 * to determine if attributes should be created or not.
1900 * Any change in order or content must be matched.
1901 */
1902static struct sensor_device_template *nct6775_attributes_in_template[] = {
1903 &sensor_dev_template_in_input,
1904 &sensor_dev_template_in_alarm,
30846993 1905 &sensor_dev_template_in_beep,
f73cf632
GR		 1906 &sensor_dev_template_in_min,
1907 &sensor_dev_template_in_max,
1908 NULL
9de2e2e8
GR		 1909};
1910
c60fdf85 1911static const struct sensor_template_group nct6775_in_template_group = {
f73cf632
GR		 1912 .templates = nct6775_attributes_in_template,
1913 .is_visible = nct6775_in_is_visible,
9de2e2e8
GR		 1914};
1915
1c65dc36
GR		 1916static ssize_t
1917show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1918{
1919 struct nct6775_data *data = nct6775_update_device(dev);
1920 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1921 int nr = sattr->index;
9cd892bc 1922
1c65dc36
GR		 1923 return sprintf(buf, "%d\n", data->rpm[nr]);
1924}
1925
1926static ssize_t
1927show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1928{
1929 struct nct6775_data *data = nct6775_update_device(dev);
1930 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1931 int nr = sattr->index;
9cd892bc 1932
1c65dc36
GR		 1933 return sprintf(buf, "%d\n",
1934 data->fan_from_reg_min(data->fan_min[nr],
1935 data->fan_div[nr]));
1936}
1937
1938static ssize_t
1939show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
1940{
1941 struct nct6775_data *data = nct6775_update_device(dev);
1942 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1943 int nr = sattr->index;
9cd892bc 1944
1c65dc36
GR		 1945 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1946}
1947
1948static ssize_t
1949store_fan_min(struct device *dev, struct device_attribute *attr,
1950 const char *buf, size_t count)
1951{
1952 struct nct6775_data *data = dev_get_drvdata(dev);
1953 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1954 int nr = sattr->index;
1955 unsigned long val;
1c65dc36
GR		 1956 unsigned int reg;
1957 u8 new_div;
9cd892bc 1958 int err;
1c65dc36
GR		 1959
1960 err = kstrtoul(buf, 10, &val);
1961 if (err < 0)
1962 return err;
1963
1964 mutex_lock(&data->update_lock);
1965 if (!data->has_fan_div) {
1966 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
1967 if (!val) {
1968 val = 0xff1f;
1969 } else {
1970 if (val > 1350000U)
1971 val = 135000U;
1972 val = 1350000U / val;
1973 val = (val & 0x1f) | ((val << 3) & 0xff00);
1974 }
1975 data->fan_min[nr] = val;
1976 goto write_min; /* Leave fan divider alone */
1977 }
1978 if (!val) {
1979 /* No min limit, alarm disabled */
1980 data->fan_min[nr] = 255;
1981 new_div = data->fan_div[nr]; /* No change */
1982 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1983 goto write_div;
1984 }
1985 reg = 1350000U / val;
1986 if (reg >= 128 * 255) {
1987 /*
1988 * Speed below this value cannot possibly be represented,
1989 * even with the highest divider (128)
1990 */
1991 data->fan_min[nr] = 254;
d1bb2186 1992 new_div = 7; /* 128 == BIT(7) */
1c65dc36
GR		 1993 dev_warn(dev,
1994 "fan%u low limit %lu below minimum %u, set to minimum\n",
1995 nr + 1, val, data->fan_from_reg_min(254, 7));
1996 } else if (!reg) {
1997 /*
1998 * Speed above this value cannot possibly be represented,
1999 * even with the lowest divider (1)
2000 */
2001 data->fan_min[nr] = 1;
d1bb2186 2002 new_div = 0; /* 1 == BIT(0) */
1c65dc36
GR		 2003 dev_warn(dev,
2004 "fan%u low limit %lu above maximum %u, set to maximum\n",
2005 nr + 1, val, data->fan_from_reg_min(1, 0));
2006 } else {
2007 /*
2008 * Automatically pick the best divider, i.e. the one such
2009 * that the min limit will correspond to a register value
2010 * in the 96..192 range
2011 */
2012 new_div = 0;
2013 while (reg > 192 && new_div < 7) {
2014 reg >>= 1;
2015 new_div++;
2016 }
2017 data->fan_min[nr] = reg;
2018 }
2019
2020write_div:
2021 /*
2022 * Write both the fan clock divider (if it changed) and the new
2023 * fan min (unconditionally)
2024 */
2025 if (new_div != data->fan_div[nr]) {
2026 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2027 nr + 1, div_from_reg(data->fan_div[nr]),
2028 div_from_reg(new_div));
2029 data->fan_div[nr] = new_div;
2030 nct6775_write_fan_div_common(data, nr);
2031 /* Give the chip time to sample a new speed value */
2032 data->last_updated = jiffies;
2033 }
2034
2035write_min:
2036 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2037 mutex_unlock(&data->update_lock);
2038
2039 return count;
2040}
2041
5c25d954
GR		 2042static ssize_t
2043show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2044{
2045 struct nct6775_data *data = nct6775_update_device(dev);
2046 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2047 int p = data->fan_pulses[sattr->index];
2048
2049 return sprintf(buf, "%d\n", p ? : 4);
2050}
2051
2052static ssize_t
2053store_fan_pulses(struct device *dev, struct device_attribute *attr,
2054 const char *buf, size_t count)
2055{
2056 struct nct6775_data *data = dev_get_drvdata(dev);
2057 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2058 int nr = sattr->index;
2059 unsigned long val;
2060 int err;
6c009501 2061 u8 reg;
5c25d954
GR		 2062
2063 err = kstrtoul(buf, 10, &val);
2064 if (err < 0)
2065 return err;
2066
2067 if (val > 4)
2068 return -EINVAL;
2069
2070 mutex_lock(&data->update_lock);
2071 data->fan_pulses[nr] = val & 3;
6c009501
GR		 2072 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2073 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2074 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2075 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
5c25d954
GR		 2076 mutex_unlock(&data->update_lock);
2077
2078 return count;
2079}
2080
f73cf632
GR		 2081static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2082 struct attribute *attr, int index)
2083{
2084 struct device *dev = container_of(kobj, struct device, kobj);
2085 struct nct6775_data *data = dev_get_drvdata(dev);
30846993
GR		 2086 int fan = index / 6; /* fan index */
2087 int nr = index % 6; /* attribute index */
1c65dc36 2088
d1bb2186 2089 if (!(data->has_fan & BIT(fan)))
f73cf632 2090 return 0;
1c65dc36 2091
f73cf632
GR		 2092 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2093 return 0;
30846993 2094 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
f73cf632 2095 return 0;
d1bb2186 2096 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
30846993
GR		 2097 return 0;
2098 if (nr == 5 && data->kind != nct6775)
f73cf632
GR		 2099 return 0;
2100
2101 return attr->mode;
2102}
1c65dc36 2103
f73cf632
GR		 2104SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2105SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2106 FAN_ALARM_BASE);
30846993
GR		 2107SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2108 store_beep, FAN_ALARM_BASE);
f73cf632
GR		 2109SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2110 store_fan_pulses, 0);
2111SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2112 store_fan_min, 0);
2113SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2114
2115/*
2116 * nct6775_fan_is_visible uses the index into the following array
2117 * to determine if attributes should be created or not.
2118 * Any change in order or content must be matched.
2119 */
2120static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2121 &sensor_dev_template_fan_input,
2122 &sensor_dev_template_fan_alarm, /* 1 */
30846993 2123 &sensor_dev_template_fan_beep, /* 2 */
f73cf632 2124 &sensor_dev_template_fan_pulses,
30846993
GR		 2125 &sensor_dev_template_fan_min, /* 4 */
2126 &sensor_dev_template_fan_div, /* 5 */
f73cf632 2127 NULL
5c25d954
GR		 2128};
2129
c60fdf85 2130static const struct sensor_template_group nct6775_fan_template_group = {
f73cf632
GR		 2131 .templates = nct6775_attributes_fan_template,
2132 .is_visible = nct6775_fan_is_visible,
2133 .base = 1,
1c65dc36
GR		 2134};
2135
aa136e5d
GR		 2136static ssize_t
2137show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2138{
2139 struct nct6775_data *data = nct6775_update_device(dev);
2140 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2141 int nr = sattr->index;
9cd892bc 2142
aa136e5d
GR		 2143 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2144}
2145
2146static ssize_t
2147show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2148{
2149 struct nct6775_data *data = nct6775_update_device(dev);
2150 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2151 int nr = sattr->nr;
2152 int index = sattr->index;
2153
2154 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2155}
2156
2157static ssize_t
2158store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2159 size_t count)
2160{
2161 struct nct6775_data *data = dev_get_drvdata(dev);
2162 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2163 int nr = sattr->nr;
2164 int index = sattr->index;
2165 int err;
2166 long val;
2167
2168 err = kstrtol(buf, 10, &val);
2169 if (err < 0)
2170 return err;
2171
2172 mutex_lock(&data->update_lock);
2173 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2174 nct6775_write_temp(data, data->reg_temp[index][nr],
2175 data->temp[index][nr]);
2176 mutex_unlock(&data->update_lock);
2177 return count;
2178}
2179
2180static ssize_t
2181show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2182{
2183 struct nct6775_data *data = nct6775_update_device(dev);
2184 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2185
2186 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2187}
2188
2189static ssize_t
2190store_temp_offset(struct device *dev, struct device_attribute *attr,
2191 const char *buf, size_t count)
2192{
2193 struct nct6775_data *data = dev_get_drvdata(dev);
2194 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2195 int nr = sattr->index;
2196 long val;
2197 int err;
2198
2199 err = kstrtol(buf, 10, &val);
2200 if (err < 0)
2201 return err;
2202
2203 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2204
2205 mutex_lock(&data->update_lock);
2206 data->temp_offset[nr] = val;
2207 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2208 mutex_unlock(&data->update_lock);
2209
2210 return count;
2211}
2212
2213static ssize_t
2214show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2215{
2216 struct nct6775_data *data = nct6775_update_device(dev);
2217 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2218 int nr = sattr->index;
9cd892bc 2219
aa136e5d
GR		 2220 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2221}
2222
2223static ssize_t
2224store_temp_type(struct device *dev, struct device_attribute *attr,
2225 const char *buf, size_t count)
2226{
2227 struct nct6775_data *data = nct6775_update_device(dev);
2228 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2229 int nr = sattr->index;
2230 unsigned long val;
2231 int err;
6c009501 2232 u8 vbat, diode, vbit, dbit;
aa136e5d
GR		 2233
2234 err = kstrtoul(buf, 10, &val);
2235 if (err < 0)
2236 return err;
2237
2238 if (val != 1 && val != 3 && val != 4)
2239 return -EINVAL;
2240
2241 mutex_lock(&data->update_lock);
2242
2243 data->temp_type[nr] = val;
6c009501
GR		 2244 vbit = 0x02 << nr;
2245 dbit = data->DIODE_MASK << nr;
2246 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2247 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
aa136e5d
GR		 2248 switch (val) {
2249 case 1: /* CPU diode (diode, current mode) */
6c009501
GR		 2250 vbat |= vbit;
2251 diode |= dbit;
aa136e5d
GR		 2252 break;
2253 case 3: /* diode, voltage mode */
6c009501 2254 vbat |= dbit;
aa136e5d
GR		 2255 break;
2256 case 4: /* thermistor */
2257 break;
2258 }
2259 nct6775_write_value(data, data->REG_VBAT, vbat);
2260 nct6775_write_value(data, data->REG_DIODE, diode);
2261
2262 mutex_unlock(&data->update_lock);
2263 return count;
2264}
2265
f73cf632
GR		 2266static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2267 struct attribute *attr, int index)
2268{
2269 struct device *dev = container_of(kobj, struct device, kobj);
2270 struct nct6775_data *data = dev_get_drvdata(dev);
30846993
GR		 2271 int temp = index / 10; /* temp index */
2272 int nr = index % 10; /* attribute index */
aa136e5d 2273
d1bb2186 2274 if (!(data->have_temp & BIT(temp)))
f73cf632 2275 return 0;
aa136e5d 2276
cc66b303
GR		 2277 if (nr == 1 && !data->temp_label)
2278 return 0;
2279
f73cf632
GR		 2280 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2281 return 0; /* alarm */
aa136e5d 2282
30846993
GR		 2283 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2284 return 0; /* beep */
2285
2286 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
f73cf632 2287 return 0;
aa136e5d 2288
30846993 2289 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
f73cf632 2290 return 0;
aa136e5d 2291
30846993 2292 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
f73cf632
GR		 2293 return 0;
2294
30846993 2295 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
b7a61353
GR		 2296 return 0;
2297
2298 /* offset and type only apply to fixed sensors */
d1bb2186 2299 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
f73cf632 2300 return 0;
aa136e5d 2301
f73cf632
GR		 2302 return attr->mode;
2303}
2304
2305SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2306SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2307SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2308 store_temp, 0, 1);
2309SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2310 show_temp, store_temp, 0, 2);
2311SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2312 store_temp, 0, 3);
b7a61353
GR		 2313SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2314 store_temp, 0, 4);
f73cf632
GR		 2315SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2316 show_temp_offset, store_temp_offset, 0);
2317SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2318 store_temp_type, 0);
2319SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
30846993
GR		 2320SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2321 store_temp_beep, 0);
f73cf632
GR		 2322
2323/*
2324 * nct6775_temp_is_visible uses the index into the following array
2325 * to determine if attributes should be created or not.
2326 * Any change in order or content must be matched.
2327 */
2328static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2329 &sensor_dev_template_temp_input,
2330 &sensor_dev_template_temp_label,
2331 &sensor_dev_template_temp_alarm, /* 2 */
30846993
GR		 2332 &sensor_dev_template_temp_beep, /* 3 */
2333 &sensor_dev_template_temp_max, /* 4 */
2334 &sensor_dev_template_temp_max_hyst, /* 5 */
2335 &sensor_dev_template_temp_crit, /* 6 */
2336 &sensor_dev_template_temp_lcrit, /* 7 */
2337 &sensor_dev_template_temp_offset, /* 8 */
2338 &sensor_dev_template_temp_type, /* 9 */
f73cf632 2339 NULL
aa136e5d
GR		 2340};
2341
c60fdf85 2342static const struct sensor_template_group nct6775_temp_template_group = {
f73cf632
GR		 2343 .templates = nct6775_attributes_temp_template,
2344 .is_visible = nct6775_temp_is_visible,
2345 .base = 1,
aa136e5d
GR		 2346};
2347
77eb5b37
GR		 2348static ssize_t
2349show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2350{
2351 struct nct6775_data *data = nct6775_update_device(dev);
2352 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2353
1743704a 2354 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
77eb5b37
GR		 2355}
2356
2357static ssize_t
2358store_pwm_mode(struct device *dev, struct device_attribute *attr,
2359 const char *buf, size_t count)
2360{
2361 struct nct6775_data *data = dev_get_drvdata(dev);
2362 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2363 int nr = sattr->index;
2364 unsigned long val;
2365 int err;
2366 u8 reg;
2367
2368 err = kstrtoul(buf, 10, &val);
2369 if (err < 0)
2370 return err;
2371
2372 if (val > 1)
2373 return -EINVAL;
2374
1743704a 2375 /* Setting DC mode (0) is not supported for all chips/channels */
77eb5b37 2376 if (data->REG_PWM_MODE[nr] == 0) {
1743704a 2377 if (!val)
77eb5b37
GR		 2378 return -EINVAL;
2379 return count;
2380 }
2381
2382 mutex_lock(&data->update_lock);
2383 data->pwm_mode[nr] = val;
2384 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2385 reg &= ~data->PWM_MODE_MASK[nr];
1743704a 2386 if (!val)
77eb5b37
GR		 2387 reg |= data->PWM_MODE_MASK[nr];
2388 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2389 mutex_unlock(&data->update_lock);
2390 return count;
2391}
2392
2393static ssize_t
2394show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2395{
2396 struct nct6775_data *data = nct6775_update_device(dev);
2397 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2398 int nr = sattr->nr;
2399 int index = sattr->index;
2400 int pwm;
2401
2402 /*
2403 * For automatic fan control modes, show current pwm readings.
2404 * Otherwise, show the configured value.
2405 */
2406 if (index == 0 && data->pwm_enable[nr] > manual)
2407 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2408 else
2409 pwm = data->pwm[index][nr];
2410
2411 return sprintf(buf, "%d\n", pwm);
2412}
2413
2414static ssize_t
2415store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2416 size_t count)
2417{
2418 struct nct6775_data *data = dev_get_drvdata(dev);
2419 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2420 int nr = sattr->nr;
2421 int index = sattr->index;
2422 unsigned long val;
bbd8decd
GR		 2423 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2424 int maxval[7]
2425 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
77eb5b37 2426 int err;
cdcaeceb 2427 u8 reg;
77eb5b37
GR		 2428
2429 err = kstrtoul(buf, 10, &val);
2430 if (err < 0)
2431 return err;
cdcaeceb 2432 val = clamp_val(val, minval[index], maxval[index]);
77eb5b37
GR		 2433
2434 mutex_lock(&data->update_lock);
2435 data->pwm[index][nr] = val;
2436 nct6775_write_value(data, data->REG_PWM[index][nr], val);
cdcaeceb
GR		 2437 if (index == 2) { /* floor: disable if val == 0 */
2438 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2439 reg &= 0x7f;
2440 if (val)
2441 reg |= 0x80;
2442 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2443 }
77eb5b37
GR		 2444 mutex_unlock(&data->update_lock);
2445 return count;
2446}
2447
cdcaeceb
GR		 2448/* Returns 0 if OK, -EINVAL otherwise */
2449static int check_trip_points(struct nct6775_data *data, int nr)
2450{
2451 int i;
2452
2453 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2454 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2455 return -EINVAL;
2456 }
2457 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2458 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2459 return -EINVAL;
2460 }
2461 /* validate critical temperature and pwm if enabled (pwm > 0) */
2462 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2463 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2464 data->auto_temp[nr][data->auto_pwm_num] ||
2465 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2466 data->auto_pwm[nr][data->auto_pwm_num])
2467 return -EINVAL;
2468 }
2469 return 0;
2470}
2471
2472static void pwm_update_registers(struct nct6775_data *data, int nr)
2473{
2474 u8 reg;
2475
2476 switch (data->pwm_enable[nr]) {
2477 case off:
2478 case manual:
2479 break;
2480 case speed_cruise:
2481 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2482 reg = (reg & ~data->tolerance_mask) |
2483 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2484 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2485 nct6775_write_value(data, data->REG_TARGET[nr],
2486 data->target_speed[nr] & 0xff);
2487 if (data->REG_TOLERANCE_H) {
2488 reg = (data->target_speed[nr] >> 8) & 0x0f;
2489 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2490 nct6775_write_value(data,
2491 data->REG_TOLERANCE_H[nr],
2492 reg);
2493 }
2494 break;
2495 case thermal_cruise:
2496 nct6775_write_value(data, data->REG_TARGET[nr],
2497 data->target_temp[nr]);
2498 /* intentional */
2499 default:
2500 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2501 reg = (reg & ~data->tolerance_mask) |
2502 data->temp_tolerance[0][nr];
2503 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2504 break;
2505 }
2506}
2507
77eb5b37
GR		 2508static ssize_t
2509show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2510{
2511 struct nct6775_data *data = nct6775_update_device(dev);
2512 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2513
2514 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2515}
2516
2517static ssize_t
2518store_pwm_enable(struct device *dev, struct device_attribute *attr,
2519 const char *buf, size_t count)
2520{
2521 struct nct6775_data *data = dev_get_drvdata(dev);
2522 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2523 int nr = sattr->index;
2524 unsigned long val;
2525 int err;
2526 u16 reg;
2527
2528 err = kstrtoul(buf, 10, &val);
2529 if (err < 0)
2530 return err;
2531
2532 if (val > sf4)
2533 return -EINVAL;
2534
2535 if (val == sf3 && data->kind != nct6775)
2536 return -EINVAL;
2537
cdcaeceb
GR		 2538 if (val == sf4 && check_trip_points(data, nr)) {
2539 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2540 dev_err(dev, "Adjust trip points and try again\n");
2541 return -EINVAL;
2542 }
2543
77eb5b37
GR		 2544 mutex_lock(&data->update_lock);
2545 data->pwm_enable[nr] = val;
2546 if (val == off) {
2547 /*
2548 * turn off pwm control: select manual mode, set pwm to maximum
2549 */
2550 data->pwm[0][nr] = 255;
2551 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2552 }
cdcaeceb 2553 pwm_update_registers(data, nr);
77eb5b37
GR		 2554 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2555 reg &= 0x0f;
2556 reg |= pwm_enable_to_reg(val) << 4;
2557 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2558 mutex_unlock(&data->update_lock);
2559 return count;
2560}
2561
cdcaeceb 2562static ssize_t
bbd8decd 2563show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
cdcaeceb 2564{
bbd8decd 2565 int i, sel = 0;
cdcaeceb
GR		 2566
2567 for (i = 0; i < NUM_TEMP; i++) {
d1bb2186 2568 if (!(data->have_temp & BIT(i)))
cdcaeceb
GR		 2569 continue;
2570 if (src == data->temp_src[i]) {
2571 sel = i + 1;
2572 break;
2573 }
2574 }
2575
2576 return sprintf(buf, "%d\n", sel);
2577}
2578
bbd8decd
GR		 2579static ssize_t
2580show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2581{
2582 struct nct6775_data *data = nct6775_update_device(dev);
2583 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2584 int index = sattr->index;
2585
2586 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2587}
2588
cdcaeceb
GR		 2589static ssize_t
2590store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2591 const char *buf, size_t count)
2592{
2593 struct nct6775_data *data = nct6775_update_device(dev);
2594 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2595 int nr = sattr->index;
2596 unsigned long val;
2597 int err, reg, src;
2598
2599 err = kstrtoul(buf, 10, &val);
2600 if (err < 0)
2601 return err;
2602 if (val == 0 || val > NUM_TEMP)
2603 return -EINVAL;
d1bb2186 2604 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
cdcaeceb
GR		 2605 return -EINVAL;
2606
2607 mutex_lock(&data->update_lock);
2608 src = data->temp_src[val - 1];
2609 data->pwm_temp_sel[nr] = src;
2610 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2611 reg &= 0xe0;
2612 reg |= src;
2613 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2614 mutex_unlock(&data->update_lock);
2615
2616 return count;
2617}
2618
bbd8decd
GR		 2619static ssize_t
2620show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2621 char *buf)
2622{
2623 struct nct6775_data *data = nct6775_update_device(dev);
2624 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2625 int index = sattr->index;
2626
2627 return show_pwm_temp_sel_common(data, buf,
2628 data->pwm_weight_temp_sel[index]);
2629}
2630
2631static ssize_t
2632store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2633 const char *buf, size_t count)
2634{
2635 struct nct6775_data *data = nct6775_update_device(dev);
2636 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2637 int nr = sattr->index;
2638 unsigned long val;
2639 int err, reg, src;
2640
2641 err = kstrtoul(buf, 10, &val);
2642 if (err < 0)
2643 return err;
2644 if (val > NUM_TEMP)
2645 return -EINVAL;
f3834b85 2646 val = array_index_nospec(val, NUM_TEMP + 1);
d1bb2186 2647 if (val && (!(data->have_temp & BIT(val - 1)) ||
bbd8decd
GR		 2648 !data->temp_src[val - 1]))
2649 return -EINVAL;
2650
2651 mutex_lock(&data->update_lock);
2652 if (val) {
2653 src = data->temp_src[val - 1];
2654 data->pwm_weight_temp_sel[nr] = src;
2655 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2656 reg &= 0xe0;
2657 reg |= (src | 0x80);
2658 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2659 } else {
2660 data->pwm_weight_temp_sel[nr] = 0;
2661 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2662 reg &= 0x7f;
2663 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2664 }
2665 mutex_unlock(&data->update_lock);
2666
2667 return count;
2668}
2669
cdcaeceb
GR		 2670static ssize_t
2671show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2672{
2673 struct nct6775_data *data = nct6775_update_device(dev);
2674 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2675
2676 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2677}
2678
2679static ssize_t
2680store_target_temp(struct device *dev, struct device_attribute *attr,
2681 const char *buf, size_t count)
2682{
2683 struct nct6775_data *data = dev_get_drvdata(dev);
2684 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2685 int nr = sattr->index;
2686 unsigned long val;
2687 int err;
2688
2689 err = kstrtoul(buf, 10, &val);
2690 if (err < 0)
2691 return err;
2692
2693 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2694 data->target_temp_mask);
2695
2696 mutex_lock(&data->update_lock);
2697 data->target_temp[nr] = val;
2698 pwm_update_registers(data, nr);
2699 mutex_unlock(&data->update_lock);
2700 return count;
2701}
2702
2703static ssize_t
2704show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2705{
2706 struct nct6775_data *data = nct6775_update_device(dev);
2707 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2708 int nr = sattr->index;
2709
2710 return sprintf(buf, "%d\n",
2711 fan_from_reg16(data->target_speed[nr],
2712 data->fan_div[nr]));
2713}
2714
2715static ssize_t
2716store_target_speed(struct device *dev, struct device_attribute *attr,
2717 const char *buf, size_t count)
2718{
2719 struct nct6775_data *data = dev_get_drvdata(dev);
2720 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2721 int nr = sattr->index;
2722 unsigned long val;
2723 int err;
2724 u16 speed;
2725
2726 err = kstrtoul(buf, 10, &val);
2727 if (err < 0)
2728 return err;
2729
2730 val = clamp_val(val, 0, 1350000U);
2731 speed = fan_to_reg(val, data->fan_div[nr]);
2732
2733 mutex_lock(&data->update_lock);
2734 data->target_speed[nr] = speed;
2735 pwm_update_registers(data, nr);
2736 mutex_unlock(&data->update_lock);
2737 return count;
2738}
2739
2740static ssize_t
2741show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2742 char *buf)
2743{
2744 struct nct6775_data *data = nct6775_update_device(dev);
2745 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2746 int nr = sattr->nr;
2747 int index = sattr->index;
2748
2749 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2750}
2751
2752static ssize_t
2753store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2754 const char *buf, size_t count)
2755{
2756 struct nct6775_data *data = dev_get_drvdata(dev);
2757 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2758 int nr = sattr->nr;
2759 int index = sattr->index;
2760 unsigned long val;
2761 int err;
2762
2763 err = kstrtoul(buf, 10, &val);
2764 if (err < 0)
2765 return err;
2766
2767 /* Limit tolerance as needed */
2768 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2769
2770 mutex_lock(&data->update_lock);
2771 data->temp_tolerance[index][nr] = val;
2772 if (index)
2773 pwm_update_registers(data, nr);
2774 else
2775 nct6775_write_value(data,
2776 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2777 val);
2778 mutex_unlock(&data->update_lock);
2779 return count;
2780}
2781
2782/*
2783 * Fan speed tolerance is a tricky beast, since the associated register is
2784 * a tick counter, but the value is reported and configured as rpm.
2785 * Compute resulting low and high rpm values and report the difference.
2786 */
2787static ssize_t
2788show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2789 char *buf)
2790{
2791 struct nct6775_data *data = nct6775_update_device(dev);
2792 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2793 int nr = sattr->index;
2794 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2795 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2796 int tolerance;
2797
2798 if (low <= 0)
2799 low = 1;
2800 if (high > 0xffff)
2801 high = 0xffff;
2802 if (high < low)
2803 high = low;
2804
2805 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2806 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2807
2808 return sprintf(buf, "%d\n", tolerance);
2809}
2810
2811static ssize_t
2812store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2813 const char *buf, size_t count)
2814{
2815 struct nct6775_data *data = dev_get_drvdata(dev);
2816 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2817 int nr = sattr->index;
2818 unsigned long val;
2819 int err;
2820 int low, high;
2821
2822 err = kstrtoul(buf, 10, &val);
2823 if (err < 0)
2824 return err;
2825
2826 high = fan_from_reg16(data->target_speed[nr],
2827 data->fan_div[nr]) + val;
2828 low = fan_from_reg16(data->target_speed[nr],
2829 data->fan_div[nr]) - val;
2830 if (low <= 0)
2831 low = 1;
2832 if (high < low)
2833 high = low;
2834
2835 val = (fan_to_reg(low, data->fan_div[nr]) -
2836 fan_to_reg(high, data->fan_div[nr])) / 2;
2837
2838 /* Limit tolerance as needed */
2839 val = clamp_val(val, 0, data->speed_tolerance_limit);
2840
2841 mutex_lock(&data->update_lock);
2842 data->target_speed_tolerance[nr] = val;
2843 pwm_update_registers(data, nr);
2844 mutex_unlock(&data->update_lock);
2845 return count;
2846}
2847
f73cf632
GR		 2848SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2849SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2850 store_pwm_mode, 0);
2851SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2852 store_pwm_enable, 0);
2853SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2854 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2855SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2856 show_target_temp, store_target_temp, 0);
2857SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2858 show_target_speed, store_target_speed, 0);
2859SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2860 show_speed_tolerance, store_speed_tolerance, 0);
cdcaeceb
GR		 2861
2862/* Smart Fan registers */
2863
bbd8decd
GR		 2864static ssize_t
2865show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2866{
2867 struct nct6775_data *data = nct6775_update_device(dev);
2868 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2869 int nr = sattr->nr;
2870 int index = sattr->index;
2871
2872 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2873}
2874
2875static ssize_t
2876store_weight_temp(struct device *dev, struct device_attribute *attr,
2877 const char *buf, size_t count)
2878{
2879 struct nct6775_data *data = dev_get_drvdata(dev);
2880 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2881 int nr = sattr->nr;
2882 int index = sattr->index;
2883 unsigned long val;
2884 int err;
2885
2886 err = kstrtoul(buf, 10, &val);
2887 if (err < 0)
2888 return err;
2889
2890 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2891
2892 mutex_lock(&data->update_lock);
2893 data->weight_temp[index][nr] = val;
2894 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2895 mutex_unlock(&data->update_lock);
2896 return count;
2897}
2898
f73cf632
GR		 2899SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2900 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2901SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2902 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2903SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2904 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2905SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2906 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2907SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2908 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2909SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2910 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
bbd8decd 2911
cdcaeceb
GR		 2912static ssize_t
2913show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2914{
2915 struct nct6775_data *data = nct6775_update_device(dev);
2916 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2917 int nr = sattr->nr;
2918 int index = sattr->index;
2919
2920 return sprintf(buf, "%d\n",
2921 step_time_from_reg(data->fan_time[index][nr],
2922 data->pwm_mode[nr]));
2923}
2924
2925static ssize_t
2926store_fan_time(struct device *dev, struct device_attribute *attr,
2927 const char *buf, size_t count)
2928{
2929 struct nct6775_data *data = dev_get_drvdata(dev);
2930 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2931 int nr = sattr->nr;
2932 int index = sattr->index;
2933 unsigned long val;
2934 int err;
2935
2936 err = kstrtoul(buf, 10, &val);
2937 if (err < 0)
2938 return err;
2939
2940 val = step_time_to_reg(val, data->pwm_mode[nr]);
2941 mutex_lock(&data->update_lock);
2942 data->fan_time[index][nr] = val;
2943 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
2944 mutex_unlock(&data->update_lock);
2945 return count;
2946}
2947
cdcaeceb
GR		 2948static ssize_t
2949show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2950{
2951 struct nct6775_data *data = nct6775_update_device(dev);
2952 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2953
2954 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
2955}
2956
2957static ssize_t
2958store_auto_pwm(struct device *dev, struct device_attribute *attr,
2959 const char *buf, size_t count)
2960{
2961 struct nct6775_data *data = dev_get_drvdata(dev);
2962 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2963 int nr = sattr->nr;
2964 int point = sattr->index;
2965 unsigned long val;
2966 int err;
2967 u8 reg;
2968
2969 err = kstrtoul(buf, 10, &val);
2970 if (err < 0)
2971 return err;
2972 if (val > 255)
2973 return -EINVAL;
2974
2975 if (point == data->auto_pwm_num) {
2976 if (data->kind != nct6775 && !val)
2977 return -EINVAL;
2978 if (data->kind != nct6779 && val)
2979 val = 0xff;
2980 }
2981
2982 mutex_lock(&data->update_lock);
2983 data->auto_pwm[nr][point] = val;
2984 if (point < data->auto_pwm_num) {
2985 nct6775_write_value(data,
2986 NCT6775_AUTO_PWM(data, nr, point),
2987 data->auto_pwm[nr][point]);
2988 } else {
2989 switch (data->kind) {
2990 case nct6775:
2991 /* disable if needed (pwm == 0) */
2992 reg = nct6775_read_value(data,
2993 NCT6775_REG_CRITICAL_ENAB[nr]);
2994 if (val)
2995 reg |= 0x02;
2996 else
2997 reg &= ~0x02;
2998 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
2999 reg);
3000 break;
3001 case nct6776:
3002 break; /* always enabled, nothing to do */
6c009501 3003 case nct6106:
cdcaeceb 3004 case nct6779:
578ab5f0 3005 case nct6791:
8aefb93f 3006 case nct6792:
cd1faefa 3007 case nct6793:
419220dc 3008 case nct6795:
6c009501 3009 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
cdcaeceb
GR		 3010 val);
3011 reg = nct6775_read_value(data,
6c009501 3012 data->REG_CRITICAL_PWM_ENABLE[nr]);
cdcaeceb 3013 if (val == 255)
6c009501 3014 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
cdcaeceb 3015 else
6c009501 3016 reg |= data->CRITICAL_PWM_ENABLE_MASK;
cdcaeceb 3017 nct6775_write_value(data,
6c009501 3018 data->REG_CRITICAL_PWM_ENABLE[nr],
cdcaeceb
GR		 3019 reg);
3020 break;
3021 }
3022 }
3023 mutex_unlock(&data->update_lock);
3024 return count;
3025}
3026
3027static ssize_t
3028show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3029{
3030 struct nct6775_data *data = nct6775_update_device(dev);
3031 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3032 int nr = sattr->nr;
3033 int point = sattr->index;
3034
3035 /*
3036 * We don't know for sure if the temperature is signed or unsigned.
3037 * Assume it is unsigned.
3038 */
3039 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3040}
3041
3042static ssize_t
3043store_auto_temp(struct device *dev, struct device_attribute *attr,
3044 const char *buf, size_t count)
3045{
3046 struct nct6775_data *data = dev_get_drvdata(dev);
3047 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3048 int nr = sattr->nr;
3049 int point = sattr->index;
3050 unsigned long val;
3051 int err;
3052
3053 err = kstrtoul(buf, 10, &val);
3054 if (err)
3055 return err;
3056 if (val > 255000)
3057 return -EINVAL;
3058
3059 mutex_lock(&data->update_lock);
3060 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3061 if (point < data->auto_pwm_num) {
3062 nct6775_write_value(data,
3063 NCT6775_AUTO_TEMP(data, nr, point),
3064 data->auto_temp[nr][point]);
3065 } else {
3066 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3067 data->auto_temp[nr][point]);
3068 }
3069 mutex_unlock(&data->update_lock);
3070 return count;
3071}
3072
f73cf632
GR		 3073static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3074 struct attribute *attr, int index)
3075{
3076 struct device *dev = container_of(kobj, struct device, kobj);
3077 struct nct6775_data *data = dev_get_drvdata(dev);
3078 int pwm = index / 36; /* pwm index */
3079 int nr = index % 36; /* attribute index */
3080
d1bb2186 3081 if (!(data->has_pwm & BIT(pwm)))
f73cf632
GR		 3082 return 0;
3083
cc76dee1
GR		 3084 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3085 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3086 return 0;
f73cf632
GR		 3087 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3088 return 0;
3089 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3090 return 0;
3091 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3092 return 0;
3093
3094 if (nr >= 22 && nr <= 35) { /* auto point */
3095 int api = (nr - 22) / 2; /* auto point index */
3096
3097 if (api > data->auto_pwm_num)
3098 return 0;
3099 }
3100 return attr->mode;
3101}
3102
3103SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3104 show_fan_time, store_fan_time, 0, 0);
3105SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3106 show_fan_time, store_fan_time, 0, 1);
3107SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3108 show_fan_time, store_fan_time, 0, 2);
3109SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3110 store_pwm, 0, 1);
3111SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3112 store_pwm, 0, 2);
3113SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3114 show_temp_tolerance, store_temp_tolerance, 0, 0);
3115SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3116 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3117 0, 1);
3118
3119SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3120 0, 3);
3121
3122SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3123 store_pwm, 0, 4);
3124
3125SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3126 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3127SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3128 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3129
3130SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3131 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3132SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3133 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3134
3135SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3136 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3137SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3138 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3139
3140SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3141 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3142SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3143 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3144
3145SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3146 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3147SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3148 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3149
3150SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3151 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3152SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3153 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3154
3155SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3156 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3157SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3158 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3159
cdcaeceb 3160/*
f73cf632
GR		 3161 * nct6775_pwm_is_visible uses the index into the following array
3162 * to determine if attributes should be created or not.
3163 * Any change in order or content must be matched.
cdcaeceb 3164 */
f73cf632
GR		 3165static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3166 &sensor_dev_template_pwm,
3167 &sensor_dev_template_pwm_mode,
3168 &sensor_dev_template_pwm_enable,
3169 &sensor_dev_template_pwm_temp_sel,
3170 &sensor_dev_template_pwm_temp_tolerance,
3171 &sensor_dev_template_pwm_crit_temp_tolerance,
3172 &sensor_dev_template_pwm_target_temp,
3173 &sensor_dev_template_fan_target,
3174 &sensor_dev_template_fan_tolerance,
3175 &sensor_dev_template_pwm_stop_time,
3176 &sensor_dev_template_pwm_step_up_time,
3177 &sensor_dev_template_pwm_step_down_time,
3178 &sensor_dev_template_pwm_start,
3179 &sensor_dev_template_pwm_floor,
cc76dee1 3180 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
f73cf632
GR		 3181 &sensor_dev_template_pwm_weight_temp_step,
3182 &sensor_dev_template_pwm_weight_temp_step_tol,
3183 &sensor_dev_template_pwm_weight_temp_step_base,
cc76dee1 3184 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
f73cf632
GR		 3185 &sensor_dev_template_pwm_max, /* 19 */
3186 &sensor_dev_template_pwm_step, /* 20 */
3187 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3188 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3189 &sensor_dev_template_pwm_auto_point1_temp,
3190 &sensor_dev_template_pwm_auto_point2_pwm,
3191 &sensor_dev_template_pwm_auto_point2_temp,
3192 &sensor_dev_template_pwm_auto_point3_pwm,
3193 &sensor_dev_template_pwm_auto_point3_temp,
3194 &sensor_dev_template_pwm_auto_point4_pwm,
3195 &sensor_dev_template_pwm_auto_point4_temp,
3196 &sensor_dev_template_pwm_auto_point5_pwm,
3197 &sensor_dev_template_pwm_auto_point5_temp,
3198 &sensor_dev_template_pwm_auto_point6_pwm,
3199 &sensor_dev_template_pwm_auto_point6_temp,
3200 &sensor_dev_template_pwm_auto_point7_pwm,
3201 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3202
3203 NULL
3204};
3205
c60fdf85 3206static const struct sensor_template_group nct6775_pwm_template_group = {
f73cf632
GR		 3207 .templates = nct6775_attributes_pwm_template,
3208 .is_visible = nct6775_pwm_is_visible,
3209 .base = 1,
cdcaeceb
GR		 3210};
3211
9de2e2e8 3212static ssize_t
93d72ac3 3213cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
9de2e2e8
GR		 3214{
3215 struct nct6775_data *data = dev_get_drvdata(dev);
9cd892bc 3216
9de2e2e8
GR		 3217 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3218}
3219
93d72ac3 3220static DEVICE_ATTR_RO(cpu0_vid);
9de2e2e8 3221
a6bd5878
GR		 3222/* Case open detection */
3223
3224static ssize_t
3225clear_caseopen(struct device *dev, struct device_attribute *attr,
3226 const char *buf, size_t count)
3227{
3228 struct nct6775_data *data = dev_get_drvdata(dev);
a6bd5878
GR		 3229 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3230 unsigned long val;
3231 u8 reg;
3232 int ret;
3233
3234 if (kstrtoul(buf, 10, &val) || val != 0)
3235 return -EINVAL;
3236
3237 mutex_lock(&data->update_lock);
3238
3239 /*
3240 * Use CR registers to clear caseopen status.
3241 * The CR registers are the same for all chips, and not all chips
3242 * support clearing the caseopen status through "regular" registers.
3243 */
df612d5f 3244 ret = superio_enter(data->sioreg);
a6bd5878
GR		 3245 if (ret) {
3246 count = ret;
3247 goto error;
3248 }
3249
df612d5f
GR		 3250 superio_select(data->sioreg, NCT6775_LD_ACPI);
3251 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
a6bd5878 3252 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
df612d5f 3253 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
a6bd5878 3254 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
df612d5f
GR		 3255 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3256 superio_exit(data->sioreg);
a6bd5878
GR		 3257
3258 data->valid = false; /* Force cache refresh */
3259error:
3260 mutex_unlock(&data->update_lock);
3261 return count;
3262}
3263
f73cf632
GR		 3264static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3265 clear_caseopen, INTRUSION_ALARM_BASE);
3266static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3267 clear_caseopen, INTRUSION_ALARM_BASE + 1);
30846993
GR		 3268static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3269 store_beep, INTRUSION_ALARM_BASE);
3270static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3271 store_beep, INTRUSION_ALARM_BASE + 1);
3272static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3273 store_beep, BEEP_ENABLE_BASE);
9de2e2e8 3274
f73cf632
GR		 3275static umode_t nct6775_other_is_visible(struct kobject *kobj,
3276 struct attribute *attr, int index)
9de2e2e8 3277{
f73cf632 3278 struct device *dev = container_of(kobj, struct device, kobj);
9de2e2e8
GR		 3279 struct nct6775_data *data = dev_get_drvdata(dev);
3280
615fc8cb 3281 if (index == 0 && !data->have_vid)
f73cf632 3282 return 0;
77eb5b37 3283
615fc8cb
GR		 3284 if (index == 1 || index == 2) {
3285 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
f73cf632
GR		 3286 return 0;
3287 }
cdcaeceb 3288
615fc8cb
GR		 3289 if (index == 3 || index == 4) {
3290 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
30846993
GR		 3291 return 0;
3292 }
3293
f73cf632
GR		 3294 return attr->mode;
3295}
cdcaeceb 3296
f73cf632
GR		 3297/*
3298 * nct6775_other_is_visible uses the index into the following array
3299 * to determine if attributes should be created or not.
3300 * Any change in order or content must be matched.
3301 */
3302static struct attribute *nct6775_attributes_other[] = {
615fc8cb
GR		 3303 &dev_attr_cpu0_vid.attr, /* 0 */
3304 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3305 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3306 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3307 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3308 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
bbd8decd 3309
f73cf632
GR		 3310 NULL
3311};
cdcaeceb 3312
f73cf632
GR		 3313static const struct attribute_group nct6775_group_other = {
3314 .attrs = nct6775_attributes_other,
3315 .is_visible = nct6775_other_is_visible,
3316};
9de2e2e8 3317
9de2e2e8
GR		 3318static inline void nct6775_init_device(struct nct6775_data *data)
3319{
aa136e5d
GR		 3320 int i;
3321 u8 tmp, diode;
9de2e2e8
GR		 3322
3323 /* Start monitoring if needed */
3324 if (data->REG_CONFIG) {
3325 tmp = nct6775_read_value(data, data->REG_CONFIG);
3326 if (!(tmp & 0x01))
3327 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3328 }
3329
aa136e5d
GR		 3330 /* Enable temperature sensors if needed */
3331 for (i = 0; i < NUM_TEMP; i++) {
d1bb2186 3332 if (!(data->have_temp & BIT(i)))
aa136e5d
GR		 3333 continue;
3334 if (!data->reg_temp_config[i])
3335 continue;
3336 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3337 if (tmp & 0x01)
3338 nct6775_write_value(data, data->reg_temp_config[i],
3339 tmp & 0xfe);
3340 }
3341
9de2e2e8
GR		 3342 /* Enable VBAT monitoring if needed */
3343 tmp = nct6775_read_value(data, data->REG_VBAT);
3344 if (!(tmp & 0x01))
3345 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
aa136e5d
GR		 3346
3347 diode = nct6775_read_value(data, data->REG_DIODE);
3348
3349 for (i = 0; i < data->temp_fixed_num; i++) {
d1bb2186 3350 if (!(data->have_temp_fixed & BIT(i)))
aa136e5d 3351 continue;
6c009501
GR		 3352 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3353 data->temp_type[i]
3354 = 3 - ((diode >> i) & data->DIODE_MASK);
aa136e5d
GR		 3355 else /* thermistor */
3356 data->temp_type[i] = 4;
3357 }
9de2e2e8
GR		 3358}
3359
f73cf632 3360static void
df612d5f 3361nct6775_check_fan_inputs(struct nct6775_data *data)
1c65dc36 3362{
578ab5f0
DB		 3363 bool fan3pin, fan4pin, fan4min, fan5pin, fan6pin;
3364 bool pwm3pin, pwm4pin, pwm5pin, pwm6pin;
df612d5f
GR		 3365 int sioreg = data->sioreg;
3366 int regval;
1c65dc36 3367
d2a14ea5
GR		 3368 /* Store SIO_REG_ENABLE for use during resume */
3369 superio_select(sioreg, NCT6775_LD_HWM);
3370 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3371
1c65dc36
GR		 3372 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3373 if (data->kind == nct6775) {
df612d5f 3374 regval = superio_inb(sioreg, 0x2c);
1c65dc36 3375
d1bb2186
GR		 3376 fan3pin = regval & BIT(6);
3377 pwm3pin = regval & BIT(7);
1c65dc36
GR		 3378
3379 /* On NCT6775, fan4 shares pins with the fdc interface */
df612d5f 3380 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
578ab5f0
DB		 3381 fan4min = false;
3382 fan5pin = false;
3383 fan6pin = false;
3384 pwm4pin = false;
3385 pwm5pin = false;
3386 pwm6pin = false;
1c65dc36 3387 } else if (data->kind == nct6776) {
df612d5f 3388 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
25cdd99d
GR		 3389 const char *board_vendor, *board_name;
3390
3391 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3392 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3393
3394 if (board_name && board_vendor &&
3395 !strcmp(board_vendor, "ASRock")) {
3396 /*
3397 * Auxiliary fan monitoring is not enabled on ASRock
3398 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3399 * Observed with BIOS version 2.00.
3400 */
3401 if (!strcmp(board_name, "Z77 Pro4-M")) {
3402 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3403 data->sio_reg_enable |= 0xe0;
3404 superio_outb(sioreg, SIO_REG_ENABLE,
3405 data->sio_reg_enable);
3406 }
3407 }
3408 }
1c65dc36 3409
d2a14ea5 3410 if (data->sio_reg_enable & 0x80)
1c65dc36
GR		 3411 fan3pin = gpok;
3412 else
df612d5f 3413 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
1c65dc36 3414
d2a14ea5 3415 if (data->sio_reg_enable & 0x40)
1c65dc36
GR		 3416 fan4pin = gpok;
3417 else
df612d5f 3418 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
1c65dc36 3419
d2a14ea5 3420 if (data->sio_reg_enable & 0x20)
1c65dc36
GR		 3421 fan5pin = gpok;
3422 else
df612d5f 3423 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
1c65dc36
GR		 3424
3425 fan4min = fan4pin;
578ab5f0 3426 fan6pin = false;
77eb5b37 3427 pwm3pin = fan3pin;
578ab5f0
DB		 3428 pwm4pin = false;
3429 pwm5pin = false;
3430 pwm6pin = false;
6c009501 3431 } else if (data->kind == nct6106) {
df612d5f 3432 regval = superio_inb(sioreg, 0x24);
6c009501
GR		 3433 fan3pin = !(regval & 0x80);
3434 pwm3pin = regval & 0x08;
6c009501
GR		 3435
3436 fan4pin = false;
3437 fan4min = false;
3438 fan5pin = false;
578ab5f0 3439 fan6pin = false;
6c009501
GR		 3440 pwm4pin = false;
3441 pwm5pin = false;
578ab5f0 3442 pwm6pin = false;
419220dc 3443 } else { /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, or NCT6795D */
e5c85221
GR		 3444 int regval_1b, regval_2a, regval_eb;
3445
df612d5f 3446 regval = superio_inb(sioreg, 0x1c);
1c65dc36 3447
d1bb2186
GR		 3448 fan3pin = !(regval & BIT(5));
3449 fan4pin = !(regval & BIT(6));
3450 fan5pin = !(regval & BIT(7));
1c65dc36 3451
d1bb2186
GR		 3452 pwm3pin = !(regval & BIT(0));
3453 pwm4pin = !(regval & BIT(1));
3454 pwm5pin = !(regval & BIT(2));
77eb5b37 3455
e5c85221
GR		 3456 regval = superio_inb(sioreg, 0x2d);
3457 switch (data->kind) {
3458 case nct6791:
3459 case nct6792:
3460 fan6pin = regval & BIT(1);
3461 pwm6pin = regval & BIT(0);
3462 break;
3463 case nct6793:
419220dc 3464 case nct6795:
e5c85221
GR		 3465 regval_1b = superio_inb(sioreg, 0x1b);
3466 regval_2a = superio_inb(sioreg, 0x2a);
3467
3468 if (!pwm5pin)
3469 pwm5pin = regval & BIT(7);
3470 fan6pin = regval & BIT(1);
3471 pwm6pin = regval & BIT(0);
3472 if (!fan5pin)
3473 fan5pin = regval_1b & BIT(5);
3474
3475 superio_select(sioreg, NCT6775_LD_12);
3476 regval_eb = superio_inb(sioreg, 0xeb);
3477 if (!fan5pin)
3478 fan5pin = regval_eb & BIT(5);
3479 if (!pwm5pin)
3480 pwm5pin = (regval_eb & BIT(4)) &&
3481 !(regval_2a & BIT(0));
3482 if (!fan6pin)
3483 fan6pin = regval_eb & BIT(3);
3484 if (!pwm6pin)
3485 pwm6pin = regval_eb & BIT(2);
3486 break;
3487 default: /* NCT6779D */
578ab5f0
DB		 3488 fan6pin = false;
3489 pwm6pin = false;
e5c85221 3490 break;
578ab5f0 3491 }
e5c85221
GR		 3492
3493 fan4min = fan4pin;
578ab5f0 3494 }
1c65dc36 3495
578ab5f0
DB		 3496 /* fan 1 and 2 (0x03) are always present */
3497 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3498 (fan5pin << 4) | (fan6pin << 5);
3499 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3500 (fan5pin << 4);
3501 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3502 (pwm5pin << 4) | (pwm6pin << 5);
1c65dc36
GR		 3503}
3504
8e9285b0
GR		 3505static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3506 int *available, int *mask)
3507{
3508 int i;
3509 u8 src;
3510
3511 for (i = 0; i < data->pwm_num && *available; i++) {
3512 int index;
3513
3514 if (!regp[i])
3515 continue;
3516 src = nct6775_read_value(data, regp[i]);
3517 src &= 0x1f;
d1bb2186 3518 if (!src || (*mask & BIT(src)))
8e9285b0 3519 continue;
cc66b303 3520 if (!(data->temp_mask & BIT(src)))
8e9285b0
GR		 3521 continue;
3522
3523 index = __ffs(*available);
3524 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
d1bb2186
GR		 3525 *available &= ~BIT(index);
3526 *mask |= BIT(src);
8e9285b0
GR		 3527 }
3528}
3529
9de2e2e8
GR		 3530static int nct6775_probe(struct platform_device *pdev)
3531{
3532 struct device *dev = &pdev->dev;
a8b3a3a5 3533 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
9de2e2e8
GR		 3534 struct nct6775_data *data;
3535 struct resource *res;
aa136e5d
GR		 3536 int i, s, err = 0;
3537 int src, mask, available;
3538 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
d1a284b7 3539 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
b7a61353 3540 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
d1a284b7 3541 int num_reg_temp, num_reg_temp_mon;
0fc1f8fc 3542 u8 cr2a;
f73cf632 3543 struct attribute_group *group;
a150d95b 3544 struct device *hwmon_dev;
55bdee69 3545 int num_attr_groups = 0;
9de2e2e8
GR		 3546
3547 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3548 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3549 DRVNAME))
3550 return -EBUSY;
3551
3552 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3553 GFP_KERNEL);
3554 if (!data)
3555 return -ENOMEM;
3556
3557 data->kind = sio_data->kind;
df612d5f 3558 data->sioreg = sio_data->sioreg;
9de2e2e8 3559 data->addr = res->start;
9de2e2e8
GR		 3560 mutex_init(&data->update_lock);
3561 data->name = nct6775_device_names[data->kind];
3562 data->bank = 0xff; /* Force initial bank selection */
3563 platform_set_drvdata(pdev, data);
3564
3565 switch (data->kind) {
6c009501
GR		 3566 case nct6106:
3567 data->in_num = 9;
3568 data->pwm_num = 3;
3569 data->auto_pwm_num = 4;
3570 data->temp_fixed_num = 3;
3571 data->num_temp_alarms = 6;
30846993 3572 data->num_temp_beeps = 6;
6c009501
GR		 3573
3574 data->fan_from_reg = fan_from_reg13;
3575 data->fan_from_reg_min = fan_from_reg13;
3576
3577 data->temp_label = nct6776_temp_label;
cc66b303 3578 data->temp_mask = NCT6776_TEMP_MASK;
6c009501
GR		 3579
3580 data->REG_VBAT = NCT6106_REG_VBAT;
3581 data->REG_DIODE = NCT6106_REG_DIODE;
3582 data->DIODE_MASK = NCT6106_DIODE_MASK;
3583 data->REG_VIN = NCT6106_REG_IN;
3584 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3585 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3586 data->REG_TARGET = NCT6106_REG_TARGET;
3587 data->REG_FAN = NCT6106_REG_FAN;
3588 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3589 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3590 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3591 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3592 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3593 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3594 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3595 data->REG_PWM[0] = NCT6106_REG_PWM;
3596 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3597 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3598 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3599 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3600 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3601 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3602 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3603 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3604 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3605 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3606 data->REG_CRITICAL_TEMP_TOLERANCE
3607 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3608 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3609 data->CRITICAL_PWM_ENABLE_MASK
3610 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3611 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3612 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3613 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3614 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3615 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3616 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3617 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3618 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3619 data->REG_ALARM = NCT6106_REG_ALARM;
3620 data->ALARM_BITS = NCT6106_ALARM_BITS;
30846993
GR		 3621 data->REG_BEEP = NCT6106_REG_BEEP;
3622 data->BEEP_BITS = NCT6106_BEEP_BITS;
6c009501
GR		 3623
3624 reg_temp = NCT6106_REG_TEMP;
d1a284b7 3625 reg_temp_mon = NCT6106_REG_TEMP_MON;
6c009501 3626 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
d1a284b7 3627 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
6c009501
GR		 3628 reg_temp_over = NCT6106_REG_TEMP_OVER;
3629 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3630 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3631 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3632 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
b7a61353
GR		 3633 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3634 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
6c009501
GR		 3635
3636 break;
9de2e2e8
GR		 3637 case nct6775:
3638 data->in_num = 9;
77eb5b37 3639 data->pwm_num = 3;
cdcaeceb 3640 data->auto_pwm_num = 6;
1c65dc36 3641 data->has_fan_div = true;
aa136e5d 3642 data->temp_fixed_num = 3;
b1d2bff6 3643 data->num_temp_alarms = 3;
30846993 3644 data->num_temp_beeps = 3;
9de2e2e8
GR		 3645
3646 data->ALARM_BITS = NCT6775_ALARM_BITS;
30846993 3647 data->BEEP_BITS = NCT6775_BEEP_BITS;
9de2e2e8 3648
1c65dc36
GR		 3649 data->fan_from_reg = fan_from_reg16;
3650 data->fan_from_reg_min = fan_from_reg8;
cdcaeceb
GR		 3651 data->target_temp_mask = 0x7f;
3652 data->tolerance_mask = 0x0f;
3653 data->speed_tolerance_limit = 15;
1c65dc36 3654
aa136e5d 3655 data->temp_label = nct6775_temp_label;
cc66b303 3656 data->temp_mask = NCT6775_TEMP_MASK;
aa136e5d 3657
9de2e2e8
GR		 3658 data->REG_CONFIG = NCT6775_REG_CONFIG;
3659 data->REG_VBAT = NCT6775_REG_VBAT;
aa136e5d 3660 data->REG_DIODE = NCT6775_REG_DIODE;
6c009501 3661 data->DIODE_MASK = NCT6775_DIODE_MASK;
9de2e2e8
GR		 3662 data->REG_VIN = NCT6775_REG_IN;
3663 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3664 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
cdcaeceb 3665 data->REG_TARGET = NCT6775_REG_TARGET;
1c65dc36 3666 data->REG_FAN = NCT6775_REG_FAN;
77eb5b37 3667 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
1c65dc36 3668 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
5c25d954 3669 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
6c009501 3670 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
cdcaeceb
GR		 3671 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3672 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3673 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
77eb5b37 3674 data->REG_PWM[0] = NCT6775_REG_PWM;
cdcaeceb
GR		 3675 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3676 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3677 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3678 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
bbd8decd 3679 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
77eb5b37
GR		 3680 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3681 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3682 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
cdcaeceb
GR		 3683 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3684 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3685 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3686 data->REG_CRITICAL_TEMP_TOLERANCE
3687 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
aa136e5d
GR		 3688 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3689 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
cdcaeceb 3690 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
bbd8decd
GR		 3691 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3692 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3693 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3694 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
9de2e2e8 3695 data->REG_ALARM = NCT6775_REG_ALARM;
30846993 3696 data->REG_BEEP = NCT6775_REG_BEEP;
aa136e5d
GR		 3697
3698 reg_temp = NCT6775_REG_TEMP;
d1a284b7 3699 reg_temp_mon = NCT6775_REG_TEMP_MON;
aa136e5d 3700 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
d1a284b7 3701 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
aa136e5d
GR		 3702 reg_temp_over = NCT6775_REG_TEMP_OVER;
3703 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3704 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3705 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3706 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3707
9de2e2e8
GR		 3708 break;
3709 case nct6776:
3710 data->in_num = 9;
77eb5b37 3711 data->pwm_num = 3;
cdcaeceb 3712 data->auto_pwm_num = 4;
1c65dc36 3713 data->has_fan_div = false;
aa136e5d 3714 data->temp_fixed_num = 3;
b1d2bff6 3715 data->num_temp_alarms = 3;
30846993 3716 data->num_temp_beeps = 6;
9de2e2e8
GR		 3717
3718 data->ALARM_BITS = NCT6776_ALARM_BITS;
30846993 3719 data->BEEP_BITS = NCT6776_BEEP_BITS;
9de2e2e8 3720
1c65dc36
GR		 3721 data->fan_from_reg = fan_from_reg13;
3722 data->fan_from_reg_min = fan_from_reg13;
cdcaeceb
GR		 3723 data->target_temp_mask = 0xff;
3724 data->tolerance_mask = 0x07;
3725 data->speed_tolerance_limit = 63;
1c65dc36 3726
aa136e5d 3727 data->temp_label = nct6776_temp_label;
cc66b303 3728 data->temp_mask = NCT6776_TEMP_MASK;
aa136e5d 3729
9de2e2e8
GR		 3730 data->REG_CONFIG = NCT6775_REG_CONFIG;
3731 data->REG_VBAT = NCT6775_REG_VBAT;
aa136e5d 3732 data->REG_DIODE = NCT6775_REG_DIODE;
6c009501 3733 data->DIODE_MASK = NCT6775_DIODE_MASK;
9de2e2e8
GR		 3734 data->REG_VIN = NCT6775_REG_IN;
3735 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3736 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
cdcaeceb 3737 data->REG_TARGET = NCT6775_REG_TARGET;
1c65dc36 3738 data->REG_FAN = NCT6775_REG_FAN;
77eb5b37 3739 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
1c65dc36 3740 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
5c25d954 3741 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
6c009501 3742 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
cdcaeceb 3743 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
728d2940
GR		 3744 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3745 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
cdcaeceb 3746 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
77eb5b37 3747 data->REG_PWM[0] = NCT6775_REG_PWM;
cdcaeceb
GR		 3748 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3749 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
bbd8decd
GR		 3750 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3751 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
77eb5b37
GR		 3752 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3753 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3754 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
cdcaeceb
GR		 3755 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3756 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3757 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3758 data->REG_CRITICAL_TEMP_TOLERANCE
3759 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
aa136e5d
GR		 3760 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3761 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
cdcaeceb 3762 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
bbd8decd
GR		 3763 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3764 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3765 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3766 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
9de2e2e8 3767 data->REG_ALARM = NCT6775_REG_ALARM;
30846993 3768 data->REG_BEEP = NCT6776_REG_BEEP;
aa136e5d
GR		 3769
3770 reg_temp = NCT6775_REG_TEMP;
d1a284b7 3771 reg_temp_mon = NCT6775_REG_TEMP_MON;
aa136e5d 3772 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
d1a284b7 3773 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
aa136e5d
GR		 3774 reg_temp_over = NCT6775_REG_TEMP_OVER;
3775 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3776 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3777 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3778 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3779
9de2e2e8
GR		 3780 break;
3781 case nct6779:
3782 data->in_num = 15;
77eb5b37 3783 data->pwm_num = 5;
cdcaeceb 3784 data->auto_pwm_num = 4;
1c65dc36 3785 data->has_fan_div = false;
aa136e5d 3786 data->temp_fixed_num = 6;
b1d2bff6 3787 data->num_temp_alarms = 2;
30846993 3788 data->num_temp_beeps = 2;
9de2e2e8
GR		 3789
3790 data->ALARM_BITS = NCT6779_ALARM_BITS;
30846993 3791 data->BEEP_BITS = NCT6779_BEEP_BITS;
9de2e2e8 3792
1c65dc36
GR		 3793 data->fan_from_reg = fan_from_reg13;
3794 data->fan_from_reg_min = fan_from_reg13;
cdcaeceb
GR		 3795 data->target_temp_mask = 0xff;
3796 data->tolerance_mask = 0x07;
3797 data->speed_tolerance_limit = 63;
1c65dc36 3798
aa136e5d 3799 data->temp_label = nct6779_temp_label;
cc66b303 3800 data->temp_mask = NCT6779_TEMP_MASK;
aa136e5d 3801
9de2e2e8
GR		 3802 data->REG_CONFIG = NCT6775_REG_CONFIG;
3803 data->REG_VBAT = NCT6775_REG_VBAT;
aa136e5d 3804 data->REG_DIODE = NCT6775_REG_DIODE;
6c009501 3805 data->DIODE_MASK = NCT6775_DIODE_MASK;
9de2e2e8
GR		 3806 data->REG_VIN = NCT6779_REG_IN;
3807 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3808 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
cdcaeceb 3809 data->REG_TARGET = NCT6775_REG_TARGET;
1c65dc36 3810 data->REG_FAN = NCT6779_REG_FAN;
77eb5b37 3811 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
1c65dc36 3812 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
5c25d954 3813 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
6c009501 3814 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
cdcaeceb 3815 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
728d2940
GR		 3816 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3817 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
cdcaeceb 3818 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
77eb5b37 3819 data->REG_PWM[0] = NCT6775_REG_PWM;
cdcaeceb
GR		 3820 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3821 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
bbd8decd
GR		 3822 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3823 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
77eb5b37
GR		 3824 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3825 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3826 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
cdcaeceb
GR		 3827 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3828 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3829 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3830 data->REG_CRITICAL_TEMP_TOLERANCE
3831 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
6c009501
GR		 3832 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3833 data->CRITICAL_PWM_ENABLE_MASK
3834 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3835 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
aa136e5d
GR		 3836 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3837 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
cdcaeceb 3838 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
bbd8decd
GR		 3839 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3840 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3841 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3842 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
9de2e2e8 3843 data->REG_ALARM = NCT6779_REG_ALARM;
30846993 3844 data->REG_BEEP = NCT6776_REG_BEEP;
aa136e5d
GR		 3845
3846 reg_temp = NCT6779_REG_TEMP;
d1a284b7 3847 reg_temp_mon = NCT6779_REG_TEMP_MON;
aa136e5d 3848 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
d1a284b7 3849 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
aa136e5d
GR		 3850 reg_temp_over = NCT6779_REG_TEMP_OVER;
3851 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3852 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3853 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3854 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3855
578ab5f0
DB		 3856 break;
3857 case nct6791:
8aefb93f 3858 case nct6792:
cd1faefa 3859 case nct6793:
419220dc 3860 case nct6795:
578ab5f0
DB		 3861 data->in_num = 15;
3862 data->pwm_num = 6;
3863 data->auto_pwm_num = 4;
3864 data->has_fan_div = false;
3865 data->temp_fixed_num = 6;
3866 data->num_temp_alarms = 2;
3867 data->num_temp_beeps = 2;
3868
3869 data->ALARM_BITS = NCT6791_ALARM_BITS;
3870 data->BEEP_BITS = NCT6779_BEEP_BITS;
3871
3872 data->fan_from_reg = fan_from_reg13;
3873 data->fan_from_reg_min = fan_from_reg13;
3874 data->target_temp_mask = 0xff;
3875 data->tolerance_mask = 0x07;
3876 data->speed_tolerance_limit = 63;
3877
50224f4d
GR		 3878 switch (data->kind) {
3879 default:
3880 case nct6791:
3881 data->temp_label = nct6779_temp_label;
cc66b303 3882 data->temp_mask = NCT6791_TEMP_MASK;
50224f4d
GR		 3883 break;
3884 case nct6792:
3885 data->temp_label = nct6792_temp_label;
cc66b303 3886 data->temp_mask = NCT6792_TEMP_MASK;
50224f4d
GR		 3887 break;
3888 case nct6793:
3889 data->temp_label = nct6793_temp_label;
cc66b303 3890 data->temp_mask = NCT6793_TEMP_MASK;
50224f4d 3891 break;
419220dc
GR		 3892 case nct6795:
3893 data->temp_label = nct6795_temp_label;
3894 data->temp_mask = NCT6795_TEMP_MASK;
3895 break;
50224f4d 3896 }
578ab5f0
DB		 3897
3898 data->REG_CONFIG = NCT6775_REG_CONFIG;
3899 data->REG_VBAT = NCT6775_REG_VBAT;
3900 data->REG_DIODE = NCT6775_REG_DIODE;
3901 data->DIODE_MASK = NCT6775_DIODE_MASK;
3902 data->REG_VIN = NCT6779_REG_IN;
3903 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3904 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3905 data->REG_TARGET = NCT6775_REG_TARGET;
3906 data->REG_FAN = NCT6779_REG_FAN;
3907 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3908 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3909 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3910 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3911 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
728d2940
GR		 3912 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3913 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
578ab5f0
DB		 3914 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3915 data->REG_PWM[0] = NCT6775_REG_PWM;
3916 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3917 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
cc76dee1
GR		 3918 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
3919 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
578ab5f0
DB		 3920 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3921 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3922 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3923 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3924 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3925 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3926 data->REG_CRITICAL_TEMP_TOLERANCE
3927 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3928 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3929 data->CRITICAL_PWM_ENABLE_MASK
3930 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3931 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3932 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3933 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3934 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
cc76dee1
GR		 3935 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
3936 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
3937 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
3938 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
578ab5f0 3939 data->REG_ALARM = NCT6791_REG_ALARM;
8aefb93f
GR		 3940 if (data->kind == nct6791)
3941 data->REG_BEEP = NCT6776_REG_BEEP;
3942 else
3943 data->REG_BEEP = NCT6792_REG_BEEP;
578ab5f0
DB		 3944
3945 reg_temp = NCT6779_REG_TEMP;
3946 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
8aefb93f
GR		 3947 if (data->kind == nct6791) {
3948 reg_temp_mon = NCT6779_REG_TEMP_MON;
3949 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3950 } else {
3951 reg_temp_mon = NCT6792_REG_TEMP_MON;
3952 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
3953 }
578ab5f0
DB		 3954 reg_temp_over = NCT6779_REG_TEMP_OVER;
3955 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3956 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3957 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3958 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3959
9de2e2e8
GR		 3960 break;
3961 default:
3962 return -ENODEV;
3963 }
d1bb2186 3964 data->have_in = BIT(data->in_num) - 1;
aa136e5d
GR		 3965 data->have_temp = 0;
3966
3967 /*
3968 * On some boards, not all available temperature sources are monitored,
3969 * even though some of the monitoring registers are unused.
3970 * Get list of unused monitoring registers, then detect if any fan
3971 * controls are configured to use unmonitored temperature sources.
3972 * If so, assign the unmonitored temperature sources to available
3973 * monitoring registers.
3974 */
3975 mask = 0;
3976 available = 0;
3977 for (i = 0; i < num_reg_temp; i++) {
3978 if (reg_temp[i] == 0)
3979 continue;
3980
3981 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
d1bb2186
GR		 3982 if (!src || (mask & BIT(src)))
3983 available |= BIT(i);
aa136e5d 3984
d1bb2186 3985 mask |= BIT(src);
aa136e5d
GR		 3986 }
3987
8e9285b0
GR		 3988 /*
3989 * Now find unmonitored temperature registers and enable monitoring
3990 * if additional monitoring registers are available.
3991 */
3992 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
3993 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
3994
aa136e5d
GR		 3995 mask = 0;
3996 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
3997 for (i = 0; i < num_reg_temp; i++) {
3998 if (reg_temp[i] == 0)
3999 continue;
4000
4001 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
d1bb2186 4002 if (!src || (mask & BIT(src)))
aa136e5d
GR		 4003 continue;
4004
cc66b303 4005 if (!(data->temp_mask & BIT(src))) {
aa136e5d
GR		 4006 dev_info(dev,
4007 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4008 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4009 continue;
4010 }
4011
d1bb2186 4012 mask |= BIT(src);
aa136e5d
GR		 4013
4014 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4015 if (src <= data->temp_fixed_num) {
d1bb2186
GR		 4016 data->have_temp |= BIT(src - 1);
4017 data->have_temp_fixed |= BIT(src - 1);
aa136e5d
GR		 4018 data->reg_temp[0][src - 1] = reg_temp[i];
4019 data->reg_temp[1][src - 1] = reg_temp_over[i];
4020 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
b7a61353
GR		 4021 if (reg_temp_crit_h && reg_temp_crit_h[i])
4022 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4023 else if (reg_temp_crit[src - 1])
4024 data->reg_temp[3][src - 1]
4025 = reg_temp_crit[src - 1];
4026 if (reg_temp_crit_l && reg_temp_crit_l[i])
4027 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
aa136e5d
GR		 4028 data->reg_temp_config[src - 1] = reg_temp_config[i];
4029 data->temp_src[src - 1] = src;
4030 continue;
4031 }
4032
4033 if (s >= NUM_TEMP)
4034 continue;
4035
4036 /* Use dynamic index for other sources */
d1bb2186 4037 data->have_temp |= BIT(s);
aa136e5d
GR		 4038 data->reg_temp[0][s] = reg_temp[i];
4039 data->reg_temp[1][s] = reg_temp_over[i];
4040 data->reg_temp[2][s] = reg_temp_hyst[i];
4041 data->reg_temp_config[s] = reg_temp_config[i];
b7a61353
GR		 4042 if (reg_temp_crit_h && reg_temp_crit_h[i])
4043 data->reg_temp[3][s] = reg_temp_crit_h[i];
4044 else if (reg_temp_crit[src - 1])
aa136e5d 4045 data->reg_temp[3][s] = reg_temp_crit[src - 1];
b7a61353
GR		 4046 if (reg_temp_crit_l && reg_temp_crit_l[i])
4047 data->reg_temp[4][s] = reg_temp_crit_l[i];
aa136e5d
GR		 4048
4049 data->temp_src[s] = src;
4050 s++;
4051 }
4052
d1a284b7
GR		 4053 /*
4054 * Repeat with temperatures used for fan control.
4055 * This set of registers does not support limits.
4056 */
4057 for (i = 0; i < num_reg_temp_mon; i++) {
4058 if (reg_temp_mon[i] == 0)
4059 continue;
4060
4061 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
7ce4190c 4062 if (!src)
d1a284b7
GR		 4063 continue;
4064
cc66b303 4065 if (!(data->temp_mask & BIT(src))) {
d1a284b7
GR		 4066 dev_info(dev,
4067 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4068 src, i, data->REG_TEMP_SEL[i],
4069 reg_temp_mon[i]);
4070 continue;
4071 }
4072
7ce4190c
GR		 4073 /*
4074 * For virtual temperature sources, the 'virtual' temperature
4075 * for each fan reflects a different temperature, and there
4076 * are no duplicates.
4077 */
4078 if (src != TEMP_SOURCE_VIRTUAL) {
d1bb2186 4079 if (mask & BIT(src))
7ce4190c 4080 continue;
d1bb2186 4081 mask |= BIT(src);
7ce4190c 4082 }
d1a284b7
GR		 4083
4084 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4085 if (src <= data->temp_fixed_num) {
d1bb2186 4086 if (data->have_temp & BIT(src - 1))
d1a284b7 4087 continue;
d1bb2186
GR		 4088 data->have_temp |= BIT(src - 1);
4089 data->have_temp_fixed |= BIT(src - 1);
d1a284b7
GR		 4090 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4091 data->temp_src[src - 1] = src;
4092 continue;
4093 }
4094
4095 if (s >= NUM_TEMP)
4096 continue;
4097
4098 /* Use dynamic index for other sources */
d1bb2186 4099 data->have_temp |= BIT(s);
d1a284b7
GR		 4100 data->reg_temp[0][s] = reg_temp_mon[i];
4101 data->temp_src[s] = src;
4102 s++;
4103 }
4104
aa136e5d
GR		 4105#ifdef USE_ALTERNATE
4106 /*
4107 * Go through the list of alternate temp registers and enable
4108 * if possible.
4109 * The temperature is already monitored if the respective bit in <mask>
4110 * is set.
4111 */
cc66b303
GR		 4112 for (i = 0; i < 32; i++) {
4113 if (!(data->temp_mask & BIT(i + 1)))
4114 continue;
aa136e5d
GR		 4115 if (!reg_temp_alternate[i])
4116 continue;
d1bb2186 4117 if (mask & BIT(i + 1))
aa136e5d
GR		 4118 continue;
4119 if (i < data->temp_fixed_num) {
d1bb2186 4120 if (data->have_temp & BIT(i))
aa136e5d 4121 continue;
d1bb2186
GR		 4122 data->have_temp |= BIT(i);
4123 data->have_temp_fixed |= BIT(i);
aa136e5d 4124 data->reg_temp[0][i] = reg_temp_alternate[i];
169c05cd
GR		 4125 if (i < num_reg_temp) {
4126 data->reg_temp[1][i] = reg_temp_over[i];
4127 data->reg_temp[2][i] = reg_temp_hyst[i];
4128 }
aa136e5d
GR		 4129 data->temp_src[i] = i + 1;
4130 continue;
4131 }
4132
4133 if (s >= NUM_TEMP) /* Abort if no more space */
4134 break;
4135
d1bb2186 4136 data->have_temp |= BIT(s);
aa136e5d
GR		 4137 data->reg_temp[0][s] = reg_temp_alternate[i];
4138 data->temp_src[s] = i + 1;
4139 s++;
4140 }
4141#endif /* USE_ALTERNATE */
4142
9de2e2e8
GR		 4143 /* Initialize the chip */
4144 nct6775_init_device(data);
4145
9de2e2e8
GR		 4146 err = superio_enter(sio_data->sioreg);
4147 if (err)
4148 return err;
4149
0fc1f8fc
GR		 4150 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4151 switch (data->kind) {
4152 case nct6775:
f73cf632 4153 data->have_vid = (cr2a & 0x40);
0fc1f8fc
GR		 4154 break;
4155 case nct6776:
f73cf632 4156 data->have_vid = (cr2a & 0x60) == 0x40;
0fc1f8fc 4157 break;
6c009501 4158 case nct6106:
0fc1f8fc 4159 case nct6779:
578ab5f0 4160 case nct6791:
8aefb93f 4161 case nct6792:
cd1faefa 4162 case nct6793:
419220dc 4163 case nct6795:
0fc1f8fc
GR		 4164 break;
4165 }
4166
9de2e2e8
GR		 4167 /*
4168 * Read VID value
4169 * We can get the VID input values directly at logical device D 0xe3.
4170 */
f73cf632 4171 if (data->have_vid) {
0fc1f8fc
GR		 4172 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4173 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4174 data->vrm = vid_which_vrm();
4175 }
47ece964
GR		 4176
4177 if (fan_debounce) {
4178 u8 tmp;
4179
4180 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4181 tmp = superio_inb(sio_data->sioreg,
4182 NCT6775_REG_CR_FAN_DEBOUNCE);
4183 switch (data->kind) {
6c009501
GR		 4184 case nct6106:
4185 tmp |= 0xe0;
4186 break;
47ece964
GR		 4187 case nct6775:
4188 tmp |= 0x1e;
4189 break;
4190 case nct6776:
4191 case nct6779:
4192 tmp |= 0x3e;
4193 break;
578ab5f0 4194 case nct6791:
8aefb93f 4195 case nct6792:
cd1faefa 4196 case nct6793:
419220dc 4197 case nct6795:
578ab5f0
DB		 4198 tmp |= 0x7e;
4199 break;
47ece964
GR		 4200 }
4201 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4202 tmp);
4203 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4204 data->name);
4205 }
4206
df612d5f 4207 nct6775_check_fan_inputs(data);
9de2e2e8 4208
f73cf632 4209 superio_exit(sio_data->sioreg);
1c65dc36
GR		 4210
4211 /* Read fan clock dividers immediately */
4212 nct6775_init_fan_common(dev, data);
4213
77eb5b37 4214 /* Register sysfs hooks */
f73cf632
GR		 4215 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4216 data->pwm_num);
615fc8cb
GR		 4217 if (IS_ERR(group))
4218 return PTR_ERR(group);
4219
55bdee69 4220 data->groups[num_attr_groups++] = group;
9de2e2e8 4221
f73cf632
GR		 4222 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4223 fls(data->have_in));
615fc8cb
GR		 4224 if (IS_ERR(group))
4225 return PTR_ERR(group);
4226
55bdee69 4227 data->groups[num_attr_groups++] = group;
1c65dc36 4228
f73cf632
GR		 4229 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4230 fls(data->has_fan));
615fc8cb
GR		 4231 if (IS_ERR(group))
4232 return PTR_ERR(group);
4233
55bdee69 4234 data->groups[num_attr_groups++] = group;
aa136e5d 4235
f73cf632
GR		 4236 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4237 fls(data->have_temp));
615fc8cb
GR		 4238 if (IS_ERR(group))
4239 return PTR_ERR(group);
a6bd5878 4240
55bdee69
AL		 4241 data->groups[num_attr_groups++] = group;
4242 data->groups[num_attr_groups++] = &nct6775_group_other;
9de2e2e8 4243
a150d95b
GR		 4244 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4245 data, data->groups);
9c09bd8d 4246 return PTR_ERR_OR_ZERO(hwmon_dev);
9de2e2e8
GR		 4247}
4248
f5776cc3
GR		 4249static void nct6791_enable_io_mapping(int sioaddr)
4250{
4251 int val;
4252
4253 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4254 if (val & 0x10) {
4255 pr_info("Enabling hardware monitor logical device mappings.\n");
4256 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4257 val & ~0x10);
4258 }
4259}
4260
48e93182 4261static int __maybe_unused nct6775_suspend(struct device *dev)
84d19d92
GR		 4262{
4263 struct nct6775_data *data = nct6775_update_device(dev);
84d19d92
GR		 4264
4265 mutex_lock(&data->update_lock);
4266 data->vbat = nct6775_read_value(data, data->REG_VBAT);
df612d5f 4267 if (data->kind == nct6775) {
84d19d92
GR		 4268 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4269 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4270 }
4271 mutex_unlock(&data->update_lock);
4272
4273 return 0;
4274}
4275
48e93182 4276static int __maybe_unused nct6775_resume(struct device *dev)
84d19d92
GR		 4277{
4278 struct nct6775_data *data = dev_get_drvdata(dev);
d2a14ea5 4279 int sioreg = data->sioreg;
f5776cc3 4280 int i, j, err = 0;
d2a14ea5 4281 u8 reg;
84d19d92
GR		 4282
4283 mutex_lock(&data->update_lock);
4284 data->bank = 0xff; /* Force initial bank selection */
4285
d2a14ea5
GR		 4286 err = superio_enter(sioreg);
4287 if (err)
4288 goto abort;
f5776cc3 4289
d2a14ea5
GR		 4290 superio_select(sioreg, NCT6775_LD_HWM);
4291 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4292 if (reg != data->sio_reg_enable)
4293 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4294
cd1faefa 4295 if (data->kind == nct6791 || data->kind == nct6792 ||
419220dc 4296 data->kind == nct6793 || data->kind == nct6795)
d2a14ea5
GR		 4297 nct6791_enable_io_mapping(sioreg);
4298
4299 superio_exit(sioreg);
f5776cc3 4300
84d19d92
GR		 4301 /* Restore limits */
4302 for (i = 0; i < data->in_num; i++) {
d1bb2186 4303 if (!(data->have_in & BIT(i)))
84d19d92
GR		 4304 continue;
4305
4306 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4307 data->in[i][1]);
4308 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4309 data->in[i][2]);
4310 }
4311
c409fd43 4312 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
d1bb2186 4313 if (!(data->has_fan_min & BIT(i)))
84d19d92
GR		 4314 continue;
4315
4316 nct6775_write_value(data, data->REG_FAN_MIN[i],
4317 data->fan_min[i]);
4318 }
4319
4320 for (i = 0; i < NUM_TEMP; i++) {
d1bb2186 4321 if (!(data->have_temp & BIT(i)))
84d19d92
GR		 4322 continue;
4323
c409fd43 4324 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
84d19d92
GR		 4325 if (data->reg_temp[j][i])
4326 nct6775_write_temp(data, data->reg_temp[j][i],
4327 data->temp[j][i]);
4328 }
4329
4330 /* Restore other settings */
4331 nct6775_write_value(data, data->REG_VBAT, data->vbat);
df612d5f 4332 if (data->kind == nct6775) {
84d19d92
GR		 4333 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4334 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4335 }
4336
f5776cc3 4337abort:
84d19d92
GR		 4338 /* Force re-reading all values */
4339 data->valid = false;
4340 mutex_unlock(&data->update_lock);
4341
f5776cc3 4342 return err;
84d19d92
GR		 4343}
4344
48e93182 4345static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
84d19d92 4346
9de2e2e8
GR		 4347static struct platform_driver nct6775_driver = {
4348 .driver = {
9de2e2e8 4349 .name = DRVNAME,
48e93182 4350 .pm = &nct6775_dev_pm_ops,
9de2e2e8
GR		 4351 },
4352 .probe = nct6775_probe,
9de2e2e8
GR		 4353};
4354
4355/* nct6775_find() looks for a '627 in the Super-I/O config space */
698a7c24 4356static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
9de2e2e8 4357{
9de2e2e8 4358 u16 val;
9de2e2e8 4359 int err;
698a7c24 4360 int addr;
9de2e2e8
GR		 4361
4362 err = superio_enter(sioaddr);
4363 if (err)
4364 return err;
4365
fc72af3a
GR		 4366 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4367 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4368 if (force_id && val != 0xffff)
9de2e2e8 4369 val = force_id;
fc72af3a 4370
9de2e2e8 4371 switch (val & SIO_ID_MASK) {
6c009501
GR		 4372 case SIO_NCT6106_ID:
4373 sio_data->kind = nct6106;
4374 break;
9de2e2e8
GR		 4375 case SIO_NCT6775_ID:
4376 sio_data->kind = nct6775;
9de2e2e8
GR		 4377 break;
4378 case SIO_NCT6776_ID:
4379 sio_data->kind = nct6776;
9de2e2e8
GR		 4380 break;
4381 case SIO_NCT6779_ID:
4382 sio_data->kind = nct6779;
9de2e2e8 4383 break;
578ab5f0
DB		 4384 case SIO_NCT6791_ID:
4385 sio_data->kind = nct6791;
4386 break;
8aefb93f
GR		 4387 case SIO_NCT6792_ID:
4388 sio_data->kind = nct6792;
4389 break;
cd1faefa
GR		 4390 case SIO_NCT6793_ID:
4391 sio_data->kind = nct6793;
4392 break;
419220dc
GR		 4393 case SIO_NCT6795_ID:
4394 sio_data->kind = nct6795;
4395 break;
9de2e2e8
GR		 4396 default:
4397 if (val != 0xffff)
4398 pr_debug("unsupported chip ID: 0x%04x\n", val);
4399 superio_exit(sioaddr);
4400 return -ENODEV;
4401 }
4402
4403 /* We have a known chip, find the HWM I/O address */
4404 superio_select(sioaddr, NCT6775_LD_HWM);
4405 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4406 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
698a7c24
GR		 4407 addr = val & IOREGION_ALIGNMENT;
4408 if (addr == 0) {
9de2e2e8
GR		 4409 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4410 superio_exit(sioaddr);
4411 return -ENODEV;
4412 }
4413
4414 /* Activate logical device if needed */
4415 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4416 if (!(val & 0x01)) {
4417 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4418 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4419 }
f5776cc3 4420
cd1faefa 4421 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
419220dc 4422 sio_data->kind == nct6793 || sio_data->kind == nct6795)
f5776cc3 4423 nct6791_enable_io_mapping(sioaddr);
9de2e2e8
GR		 4424
4425 superio_exit(sioaddr);
698a7c24
GR		 4426 pr_info("Found %s or compatible chip at %#x:%#x\n",
4427 nct6775_sio_names[sio_data->kind], sioaddr, addr);
9de2e2e8
GR		 4428 sio_data->sioreg = sioaddr;
4429
698a7c24 4430 return addr;
9de2e2e8
GR		 4431}
4432
4433/*
4434 * when Super-I/O functions move to a separate file, the Super-I/O
4435 * bus will manage the lifetime of the device and this module will only keep
615fc8cb 4436 * track of the nct6775 driver. But since we use platform_device_alloc(), we
9de2e2e8
GR		 4437 * must keep track of the device
4438 */
698a7c24 4439static struct platform_device *pdev[2];
9de2e2e8
GR		 4440
4441static int __init sensors_nct6775_init(void)
4442{
698a7c24
GR		 4443 int i, err;
4444 bool found = false;
4445 int address;
9de2e2e8
GR		 4446 struct resource res;
4447 struct nct6775_sio_data sio_data;
698a7c24
GR		 4448 int sioaddr[2] = { 0x2e, 0x4e };
4449
4450 err = platform_driver_register(&nct6775_driver);
4451 if (err)
4452 return err;
9de2e2e8
GR		 4453
4454 /*
4455 * initialize sio_data->kind and sio_data->sioreg.
4456 *
4457 * when Super-I/O functions move to a separate file, the Super-I/O
4458 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4459 * nct6775 hardware monitor, and call probe()
4460 */
698a7c24
GR		 4461 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4462 address = nct6775_find(sioaddr[i], &sio_data);
4463 if (address <= 0)
4464 continue;
9de2e2e8 4465
698a7c24 4466 found = true;
9de2e2e8 4467
698a7c24
GR		 4468 pdev[i] = platform_device_alloc(DRVNAME, address);
4469 if (!pdev[i]) {
4470 err = -ENOMEM;
9d311edd 4471 goto exit_device_unregister;
698a7c24 4472 }
9de2e2e8 4473
698a7c24
GR		 4474 err = platform_device_add_data(pdev[i], &sio_data,
4475 sizeof(struct nct6775_sio_data));
4476 if (err)
4477 goto exit_device_put;
4478
4479 memset(&res, 0, sizeof(res));
4480 res.name = DRVNAME;
4481 res.start = address + IOREGION_OFFSET;
4482 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4483 res.flags = IORESOURCE_IO;
4484
4485 err = acpi_check_resource_conflict(&res);
4486 if (err) {
4487 platform_device_put(pdev[i]);
4488 pdev[i] = NULL;
4489 continue;
4490 }
9de2e2e8 4491
698a7c24
GR		 4492 err = platform_device_add_resources(pdev[i], &res, 1);
4493 if (err)
4494 goto exit_device_put;
9de2e2e8 4495
698a7c24
GR		 4496 /* platform_device_add calls probe() */
4497 err = platform_device_add(pdev[i]);
4498 if (err)
4499 goto exit_device_put;
9de2e2e8 4500 }
698a7c24
GR		 4501 if (!found) {
4502 err = -ENODEV;
4503 goto exit_unregister;
9de2e2e8
GR		 4504 }
4505
4506 return 0;
4507
4508exit_device_put:
9d311edd
AL		 4509 platform_device_put(pdev[i]);
4510exit_device_unregister:
4511 while (--i >= 0) {
698a7c24 4512 if (pdev[i])
9d311edd 4513 platform_device_unregister(pdev[i]);
698a7c24 4514 }
9de2e2e8
GR		 4515exit_unregister:
4516 platform_driver_unregister(&nct6775_driver);
9de2e2e8
GR		 4517 return err;
4518}
4519
4520static void __exit sensors_nct6775_exit(void)
4521{
698a7c24
GR		 4522 int i;
4523
4524 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4525 if (pdev[i])
4526 platform_device_unregister(pdev[i]);
4527 }
9de2e2e8
GR		 4528 platform_driver_unregister(&nct6775_driver);
4529}
4530
4531MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
cd1faefa 4532MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
9de2e2e8
GR		 4533MODULE_LICENSE("GPL");
4534
4535module_init(sensors_nct6775_init);
4536module_exit(sensors_nct6775_exit);
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